Power supply communication system and method of programmable gate array communication daughter board and related device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-09
- Publication Date
- 2026-03-31
Smart Images
Figure CN121770931A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic system design, and in particular to a power supply and communication system, method and related apparatus for a programmable gate array communication sub-board. Background Technology
[0002] With the rapid development of industrial automation, intelligent communication and other fields, programmable gate array communication daughterboards are widely used in various data transmission scenarios due to their flexible programmability. The combination architecture of master control board and slave daughterboard has become the mainstream design solution.
[0003] However, the traditional FPGA communication daughterboard power supply communication mode can hardly meet the high requirements of modern systems for compatibility, power supply security and communication stability. The system urgently needs to achieve precise matching between master and slave, orderly power supply timing control, and flexible and reliable power supply guarantee to avoid hardware damage and ensure smooth data transmission.
[0004] Currently, to achieve power supply and communication between the main control board and the slave board, traditional designs often use fixed input / output level configurations and unified communication protocols, without dynamically adapting to the core parameters of slave boards of different specifications. This can easily lead to communication failures due to level mismatches. In addition, traditional solutions often use a design where the main board and slave board are powered on synchronously, lacking timing control logic for "main board power-on first," which may cause power backflow from the slave board to the main board's core chip, resulting in hardware failure. Summary of the Invention
[0005] This application proposes a power supply and communication system, method, and related apparatus for a programmable gate array (FPGA) communication daughterboard. The aim is to achieve communication between the FPGA master control board and the slave daughterboard via their read-only memory (ROM), accurately read I / O levels and hardware version information, and configure them accordingly, avoiding communication failures and FPGA damage caused by level or protocol mismatches. Utilizing the "master board first, daughter board last" timing rule and the anti-backflow design of the power supply control circuit, current peaks are dispersed, and voltage fluctuation stress is reduced. Thus, this power supply and communication system can solve the problems of equipment damage and communication anomalies caused by blindly controlling the slave power supply in traditional technologies, improving system stability and service life, and reducing the risk of failure.
[0006] In a first aspect, embodiments of this application provide a power supply and communication system for a programmable gate array (PGA) communication daughterboard, comprising: a master control board and a slave daughterboard, wherein the slave daughterboard includes a communication module, a power on / off control circuit, a power regulation module, and a read-only memory; and, The power supply output terminals of the main control board are connected to the power supply input terminals of the power on / off control circuit and the read-only memory, respectively. The power supply output terminal of the power on / off control circuit is connected to the power supply input terminal of the power regulation module, and the power supply output terminal of the power regulation module is connected to the power supply input terminal of the communication module. Furthermore, the communication terminals of the main control board are interconnected with the communication terminals of the read-only memory and the communication module, respectively. The communication terminal of the power on / off control circuit is connected to the communication terminal of the main control board. The main control board is used for priority power-on, power supply to the power on / off control circuit and read-only memory, and data interaction with the read-only memory to read the configuration information corresponding to the slave board; Read-only memory is used to pre-store the configuration information of the slave board and to perform data interaction operations with the main control board to transmit the configuration information to the main control board; The main control board is also used to perform adaptation operations based on configuration information; and after completing the adaptation operation, it sends an on / off control signal to the power on / off control circuit, which is used to indicate the working status of the power on / off control circuit. The power on / off control circuit is used to receive and respond to the on / off control signal sent by the main control board, and control the on / off of the power supply path of the power regulation module to control the power supply to the power regulation module. The power conditioning module is used to receive and regulate the electrical energy delivered by the power on / off control circuit when the power supply path is connected to the power supply control circuit, so as to deliver the regulated electrical energy to the communication module. The current and voltage parameters corresponding to the regulated electrical energy are determined by the power supply requirements of the communication module. The communication module is used to, after acquiring regulated electrical energy, receive first communication data transmitted by the main control board based on the configuration information adapted to the main control board, and convert the first communication data into a transmission signal conforming to the communication protocol of the external device to output the transmission signal to the external device; and to receive a reception signal from the external device and convert the reception signal into second communication data conforming to the communication protocol of the main control board to output the second communication data to the main control board.
[0007] Secondly, embodiments of this application provide a power supply timing control method for a programmable gate array (PGA) communication sub-board, applicable to a power supply communication system for any PGA communication sub-board as described in the first aspect; the method includes: Start the system power supply to prioritize powering on the main control board; After the main control board is powered on, it supplies power to the read-only memory and power on / off control circuit of the slave board. The main control board establishes a data connection with the read-only memory to read the configuration information pre-stored in the read-only memory; The main control board performs an adaptation operation based on the read configuration information, and sends an on / off control signal to the power on / off control circuit after the adaptation operation is performed. The power on / off control circuit responds to the on / off control signal and controls the on / off of the power supply path of the power regulation module. After the power supply path is turned on, the power conditioning module regulates the received electrical energy and transmits it to the communication module. The communication module realizes bidirectional data interaction with the main control board and external devices based on the configuration information.
[0008] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform the method as described in any of the second aspects.
[0009] Fourthly, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement some or all of the steps described in any of the second aspects of embodiments of this application.
[0010] In this embodiment, the power supply and communication system of the programmable gate array (PGA) communication daughterboard prioritizes power-on via the main control board, supplying power to the read-only memory and power on / off control circuit. It uses the communication connection to read and accurately match the daughterboard's input / output level specifications and hardware version number, avoiding communication failures and PGA damage caused by level mismatches or unknown daughterboard information. The power on / off control circuit includes a reverse current protection design to prevent current backflow from damaging the main board chips. Following the principle of "main board first, daughterboard last," the daughterboard is started in stages, dispersing instantaneous current peaks, reducing voltage fluctuations and current surge stress, and extending the daughterboard's lifespan. The power regulation module adapts to power supply requirements, ensuring stable power supply, achieving precise control of power supply timing, reducing equipment failure risks, and ensuring stable system operation. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a schematic diagram of the structure of a power supply and communication system provided in this application; Figure 2 This is a schematic diagram of the structure of a power supply on / off control circuit provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a power supply timing control method for a programmable gate array communication sub-board provided in an embodiment of this application. Figure 4 This is a flowchart illustrating another power supply timing control method for a programmable gate array communication sub-board provided in this application embodiment. Detailed Implementation
[0013] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0014] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0015] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0016] In the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone; A and B exist simultaneously; B exists alone. Among them, A and B can be singular or plural.
[0017] In this embodiment, the symbol " / " can indicate that the preceding and following objects are in an "or" relationship. Alternatively, the symbol " / " can also represent a division sign, i.e., performing a division operation. For example, A / B can mean A divided by B.
[0018] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.
[0019] In the embodiments of this application, "equal to" can be used with "greater than" and is applicable to technical solutions used when "greater than" is used; it can also be used with "less than" and is applicable to technical solutions used when "less than" is used. When "equal to" is used with "greater than", it is not used with "less than"; when "equal to" is used with "less than", it is not used with "greater than".
[0020] To better understand the solutions of the embodiments of this application, the terminal devices and related concepts that may be involved in the embodiments of this application will be introduced below.
[0021] FPGA (Field-Programmable Gate Array), also known as "Programmable Gate Array" in this application, is the core hardware carrier of the entire power supply and communication system. Specifically, it is the main control board in the system, which undertakes core functions such as priority power-on, data interaction, adaptation operation, and sending on / off control signals. Based on its programmable characteristics, it realizes the precise configuration of IO port levels and communication protocols.
[0022] IO BANK (Input / Output Bank), also known as the "input / output interface corresponding to the main control board" in this application, is a key hardware module of the FPGA main control board. It carries the signal interaction and data transmission between the main control board and the read-only memory, communication module, and power on / off control circuit. The main control board needs to configure the port level of the corresponding IO BANK based on the IO level specifications of the slave board to avoid communication failures or hardware damage caused by level mismatch.
[0023] EEPROM (Electrically Erasable Programmable Read-Only Memory), also known as "Read-Only Memory" in this application, is a hardware carrier that stores the core configuration information of the slave board. According to the actual data processing flow, it pre-stores the power supply voltage specifications and hardware version number of the slave board's IO interface through hexadecimal encoding. After the main control board is powered on, it completes data interaction and provides data basis for subsequent adaptation operations.
[0024] IIC (Inter-Integrated Circuit) (also often written as I²C) is a communication protocol that establishes a data connection between the main control board and the read-only memory. It is the technical foundation for ensuring data interaction between the two. The main control board uses the IIC protocol to complete operations such as EEPROM device address verification and configuration information reading, ensuring stable and reliable data transmission.
[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of a power supply and communication system provided in this application. Figure 1 As shown, the communication power supply system 100 includes a main control motherboard 110 and a slave board 120. The slave board 120 includes a communication module 121, a power on / off control circuit 122, a power regulation module 123, and a read-only memory 124. Figure 1 As shown, the connection relationships between the various sub-circuits in the power supply and communication system of the programmable gate array (PGA) communication sub-board are as follows: The power output terminal of the main control motherboard 110 is connected to the power input terminal of the power on / off control circuit 122 and the power input terminal of the read-only memory 124, respectively. The power output terminal of the power on / off control circuit 122 is connected to the power input terminal of the power regulation module 123, and the power output terminal of the power regulation module 123 is connected to the power input terminal of the communication module 121. The communication terminal of the main control motherboard 110 is connected to the communication terminal of the read-only memory 124 and the communication terminal of the communication module 121, respectively. The communication terminal of the power on / off control circuit 122 is connected to the communication terminal of the main control motherboard 110.
[0026] Furthermore, based on the above connection relationships, the specific functions implemented by each sub-circuit are described below: The main control board 110 is used to prioritize power-on, provide power supply to the power on / off control circuit 122 and the read-only memory 124, and perform data interaction operations with the read-only memory 124 to read the configuration information corresponding to the slave board 120. Read-only memory 124 is used to pre-store the configuration information of slave board 120 and to perform data interaction operations with master control board 110 to transmit the configuration information to master control board 110. The main control motherboard 110 is also used to perform adaptation operations according to configuration information; and after completing the adaptation operation, it sends an on / off control signal to the power on / off control circuit 122, the on / off control signal being used to indicate the working state of the power on / off control circuit 122. The power on / off control circuit 122 is used to receive and respond to the on / off control signal sent by the main control motherboard 110, and control the on / off of the power supply path of the power conditioning module 123, so as to control the power supply to the power conditioning module 123. The power conditioning module 123 is used to receive and adjust the electrical energy delivered by the power on / off control circuit 122 when the power supply path with the power on / off control circuit 122 is connected, so as to deliver the adjusted electrical energy to the communication module 121. The current parameters and voltage parameters corresponding to the adjusted electrical energy are determined by the power supply requirements of the communication module 121. The communication module 121 is used to, after acquiring regulated electrical energy, receive first communication data transmitted by the main control motherboard 110 based on the configuration information adapted to the main control motherboard 110, and convert the first communication data into a transmission signal conforming to the communication protocol of the external device, so as to output the transmission signal to the external device; and to receive a reception signal from the external device, and convert the reception signal into second communication data conforming to the communication protocol of the main control motherboard 110, so as to output the second communication data to the main control motherboard 110.
[0027] As can be seen, in this embodiment, the communication power supply system constructs a "master control motherboard + slave daughterboard" architecture, clearly defining the power supply and communication connection relationship of each module. Relying on the master control motherboard's priority power-on design and data interaction mechanism with the read-only memory, it achieves accurate acquisition and adaptation of slave daughterboard configuration information, avoiding communication failures or hardware damage caused by blindly supplying power due to unknown daughterboard information. At the same time, through the on / off control circuit, it achieves orderly management of daughterboard power supply, cooperating with each module to ensure accurate power supply timing and stable communication links, laying a foundation for the safe and reliable operation of the system from the architectural level, and effectively avoiding risks such as current backflow and level mismatch.
[0028] To illustrate in more detail the design of the power on / off control circuit added to the communication power supply system provided in this application compared to the traditional system architecture, please refer to [link / reference needed]. Figure 2 , Figure 2 This is a schematic diagram of a power supply on / off control circuit provided in an embodiment of this application.
[0029] Specifically, such as Figure 2 As shown, the power on / off control circuit 122 includes a first resistor R1, a second resistor R2, a third resistor R3, a MOSFET Q2, a transistor Q1, and an inductor L. The first end of the first resistor R1 serves as the communication terminal of the power on / off control circuit 122 and is connected to the communication terminal of the main control motherboard 110. The second end of the first resistor R1 is connected to the base of the transistor Q1. The emitter of the transistor Q1 is grounded. The collector of the transistor Q1 is connected to the first end of the second resistor R2 and the gate of the MOSFET Q2. The second end of the second resistor R2 is connected to the first end of the third resistor R3 and the source of the MOSFET Q2. The drain of the MOSFET Q2 is connected to the first end of the inductor L. The second end of the inductor L is connected to the power supply input terminal of the power adjustment module 123. The second end of the third resistor R3 serves as the power supply input terminal of the power on / off control circuit 122 and is connected to the power supply output terminal of the main control motherboard 110.
[0030] The control logic of the power on / off control circuit 122 is as follows: When the on / off control signal is high, the conduction current flows out from the communication terminal of the main control motherboard 110, passes through the first resistor R1, the base of transistor Q1, and the emitter of transistor Q1 in sequence, and flows into the common ground terminal, so that transistor Q1 is turned on; and after transistor Q1 is turned on, the gate of MOSFET Q2 is electrically connected to the common ground terminal through transistor Q1, and the source of MOSFET Q2 is electrically connected to the power supply output terminal of the main control motherboard 110 through the second resistor R2 and the third resistor R3, so that MOSFET Q2 is turned on; and the power supply path is... When the main control board 110 is in operation, the power supply current output from the main control board 110 passes through the third resistor R3, the second resistor R2, the MOSFET Q2, and the inductor L in sequence, and is output to the power supply input terminal of the power regulation module to supply power to the power regulation module. When the on / off control signal is low, the communication terminal of the main control board 110 does not output the conduction current, so that the transistor Q1 is in the off state. Also, the gate of the MOSFET is electrically connected to the power supply output terminal of the main control board 110 through the second resistor R2, the third resistor R3, and the second resistor R2, so that the MOSFET Q2 is turned off and the power supply path is disconnected.
[0031] In this circuit, Q1 is an NPN transistor, Q2 is a P-channel MOS field-effect transistor, R1 / R2 / R3 are current-limiting / voltage-dividing resistors, and L is an inductor; PRSNT is the on / off control signal output from the main control board. The circuit input is connected to the main control board power supply output, and the output (via L) is connected to the power regulation module of the slave board.
[0032] Furthermore, based on Figure 2The circuit structure of the power on / off control circuit 122 shown is based on the level of the control signal to determine its operating state. Specifically, when PRSNT is high, the control signal PRSNT is transmitted to the base of Q1 (NPN transistor) through R1, causing Q1 to receive a conduction current. The emitter (grounded) and collector of Q1 are connected, and the collector potential of Q1 is pulled to ground. The gate of Q2 (P-channel MOSFET) is connected to the collector of Q1, so the gate potential is pulled low. The source of Q2 is connected to the power supply output of the main control board (through R3), and a negative voltage difference is formed between the gate and the source, which satisfies the conduction condition of the P-channel MOSFET, and Q2 is turned on. The power supply current of the main control board is delivered to the power regulation module through R3, R2, Q2 (source to drain), and inductor L to power the subsequent modules of the slave board. When PRSNT is low, there is no effective current driving the base of Q1, and Q1 is in the off state; the gate of Q2 is connected to the source (power output of the main control board) through R2, and the gate and source potentials are the same, which does not meet the conduction condition of the P-channel MOSFET, so Q2 is off; the power supply path is disconnected, and no current flows from the main control board to the power regulation module of the slave board.
[0033] As can be seen, in this example, the power on / off control circuit receives the PRSNT signal from the main control board to achieve power supply timing control of "main board power-on first → read daughter board configuration → trigger power supply after adaptation," avoiding level mismatch and hardware damage caused by blind power supply. Furthermore, through component selection, relying on the unidirectional conduction characteristic of the P-channel MOSFET, reverse current from the slave board is blocked from flowing back to the main control board, protecting the FPGA core chip of the main control board. Additionally, by using inductor L to filter current fluctuations in the power supply path, the stable power supplied to the power regulation module is ensured, laying a power foundation for the reliable operation of the communication module.
[0034] In one possible embodiment, the configuration information includes the power supply voltage specifications and hardware version number of the input / output interfaces of the slave board; the read-only memory is also used to store the power supply voltage specifications and hardware version number of the input / output interfaces in hexadecimal data encoding into the configuration information before the main control board is powered on first.
[0035] The hexadecimal data encoding corresponding to the power supply voltage specifications of the input / output interfaces conforms to preset rules. Different hexadecimal encoding values correspond to different power supply voltage standards. The hardware version number is also stored in the form of hexadecimal data, and this encoding information is pre-written into the read-only memory before the slave board leaves the factory.
[0036] The read-only memory maintains its storage state when the main control board is not powered on. After the main control board is powered on and supplies power to it, the main control board establishes a connection with the read-only memory through a communication link, reads the hexadecimal encoded information stored in it, and then parses it to obtain the corresponding input / output interface power supply voltage specifications and hardware version number.
[0037] As can be seen in this example, by pre-storing the configuration information in hexadecimal encoding in the read-only memory, the main control board can quickly and accurately obtain the core configuration parameters of the slave board, providing a reliable data basis for subsequent adaptation operations, while avoiding confusion or errors in the configuration information during transmission.
[0038] In one possible embodiment, the read-only memory is also used to determine the device address via pin configuration operations before the main control board is powered on first.
[0039] The pin configuration operation includes determining the low-order pins, and when the pin is grounded, the value at the corresponding address position is a first value, and when the pin is connected to power, the value at the corresponding address position is a second value; the device address is determined based on the first or second value corresponding to each pin and the fixed bits corresponding to the pre-stored read-only memory.
[0040] For example, the device address configuration of an EEPROM relies on its lower-order A0, A1, and A2 pins. When a pin is grounded (GND), the corresponding address bit value is "0"; when a pin is connected to power, the corresponding address bit value is "1". Different combinations of pin connections enable differentiated device address configurations. Furthermore, the device address of the EEPROM consists of fixed bits and programmable bits. The value of the fixed bits is "1010", and the programmable bits are the address bits corresponding to the A0, A1, and A2 pins. Through different configurations of the programmable bits, each EEPROM has a unique device address.
[0041] As can be seen, in this example, the method of determining the EEPROM device address through pin configuration, combined with the address structure of fixed bits and programmable bits, can support up to 8 IIC devices to communicate with the main control board at the same time. This not only ensures the uniqueness of each EEPROM device address and avoids communication conflicts, but also improves the system's compatibility with multiple slave boards, providing a reliable communication foundation for the accurate reading, writing and verification of subsequent configuration information.
[0042] In one possible embodiment, the adaptation operation includes configuring the port level of the corresponding input / output interface of the main control board based on the power supply voltage specification of the input / output interface, and configuring the corresponding communication protocol based on the hardware version number.
[0043] The input / output interfaces of the main control board and the input / output interfaces of the slave board are the corresponding ports for communication. Different input / output interface power supply voltage specifications correspond to different port level configuration standards on the main control board, and different hardware version numbers correspond to different communication protocol parameters, including communication address, data transmission rate, etc.
[0044] For example, the power supply voltage specifications of the input / output interface are stored in read-only memory in hexadecimal code form. Different codes correspond to preset power supply voltage standards. Specifically, hexadecimal code 0X00 corresponds to a 1.2V power supply voltage specification, 0X01 corresponds to a 1.35V power supply voltage specification, and 0X02 corresponds to a 1.8V power supply voltage specification.
[0045] The main control board reads the configuration information from the read-only memory via IIC communication, first decoding the hexadecimal encoded data to obtain the input / output interface power supply voltage specifications and hardware version number of the slave board. Then, it calls its pre-stored adaptation model. If the decoded configuration information matches the adaptation model, the main control board adjusts the port level of the corresponding input / output interface to the standard consistent with the slave board's power supply voltage specifications, and completes the communication protocol matching configuration according to the parameters corresponding to the hardware version number. If the configuration information does not match the adaptation model, the main control board outputs a prompt message through the hardware debugging module, and performs the above configuration operation again after the adaptation model is updated.
[0046] As can be seen in this example, by performing an adaptation operation based on the configuration information of the slave board, the input / output interface levels of the master control board and the slave board can be kept consistent, and the corresponding communication protocols can be matched. This effectively avoids hardware damage caused by level mismatch and communication failure caused by communication protocol incompatibility.
[0047] In one possible embodiment, the power regulation module consists of a linear regulator and a switching regulator. The topology of the power regulation module is selected from one or more of the following: boost topology, buck topology, and buck-boost topology. After the power regulation module receives the power supplied by the power on / off control circuit, it adjusts the voltage and current parameters of the power supply according to the power supply voltage specifications of the input / output interface and the power supply requirements corresponding to the hardware version number, so as to obtain and output the regulated power to the communication module.
[0048] Among them, linear regulators are used to achieve precise voltage regulation of electrical energy, while switching regulators are responsible for voltage conversion of electrical energy based on the selected topology. Boost topology, buck topology, and buck-boost topology are suitable for different input-output voltage difference scenarios.
[0049] When the power supply path of the power on / off control circuit is turned on, the power regulation module receives the power from the circuit. Based on the power supply requirements corresponding to the slave board configuration information, it selects the corresponding topology and adjusts the voltage and current parameters of the power through the coordinated work of the linear regulator and the switching regulator, so that the output power meets the working requirements of the communication module.
[0050] As can be seen in this example, the power regulation module, by combining different types of voltage regulators and topologies, can flexibly adjust the power parameters according to the configuration information of the slave board, ensuring that the power supplied to the communication module is stable and adaptable to its power supply requirements, thus providing power guarantee for the reliable operation of the communication module.
[0051] In one possible embodiment, the power supply communication system of the programmable gate array communication daughterboard also includes an external power supply. The power supply of the read-only memory is taken from the main control motherboard. The power supply input of the power on / off control circuit includes the power supply output of the main control motherboard and the power supply output of the external power supply. When the power on / off control circuit selects the power supply output of the external power supply, the maximum output current of the external power supply is greater than a preset multiple of the maximum current consumed by the slave daughterboard during normal operation.
[0052] The power supply input of the power on / off control circuit adopts a selective access method, which can switch between the power supply output of the main control board and the power supply output of the external power supply. The read-only memory is powered only by the main control board and is not connected to an external power supply.
[0053] When the power on / off control circuit selects the external power supply output, the external power supply, relying on its larger maximum output current capability, provides power support for the operation of the slave board. Its output current can cover the maximum current consumption of the slave board during normal operation, while reserving sufficient margin.
[0054] Furthermore, in practical application scenarios, in the FPGA communication daughterboard power supply system of this application, the external input current margin needs to be 1.5-2 times greater than the actual current of the daughterboard. The core purpose is to ensure the stable and reliable operation of the system. Specifically, this current margin can not only cope with the load current peaks generated by the sudden high-bandwidth data interaction of the communication module, avoiding voltage drops, communication interruptions, or FPGA internal logic disorders, but also compensate for the conduction and switching losses of the power regulation module during the topology conversion process of boost, buck, or buck-boost, ensuring that the power supplied to the communication module meets its normal operating requirements. At the same time, it can also avoid the risk of overheating, component aging, and power disconnection triggered by overload protection caused by the long-term full-load operation of the power module, and prevent current backflow from damaging the FPGA core chip of the main control board. In addition, it can also be adapted to the expansion scenario of a single main control board with multiple slave daughterboards, improving the flexibility and compatibility of the system.
[0055] As can be seen, in this example, by introducing an external power supply as an optional power input and requiring its maximum output current to be greater than the maximum current consumed by the slave board during normal operation, problems such as voltage fluctuations and overheating of the power supply module caused by insufficient power supply current can be avoided, thereby improving the flexibility and reliability of the system power supply.
[0056] In one possible embodiment, LC filter circuits are arranged at the input and output terminals of the power on / off control circuit and the input and output terminals of the power regulation module, and an LED power-on indicator module is added to the output terminal of the power regulation module.
[0057] The LC filter circuit consists of a combination of inductors and capacitors, which are connected in parallel or series in the power on / off control circuit and the input / output link of the power regulation module, respectively, to specifically filter out power noise in different frequency bands; the power supply of the LED power-on indicator module is taken from the output terminal of the power regulation module, and its on / off state is bound to the power supply output state of the power regulation module.
[0058] When the power supply path of the power on / off control circuit is open and electrical energy is delivered to the power conditioning module, the LC filter circuit at the input and output terminals of the power on / off control circuit first performs preliminary noise filtering on the input electrical energy. The electrical energy after being regulated by the power conditioning module then undergoes secondary noise reduction through the LC filter circuit at its output terminal. At the same time, after the power conditioning module outputs electrical energy, the LED power-on indicator module is powered on and illuminates, providing direct feedback that the power supply path of the slave board is normally open. If the power supply path is not open or a fault occurs, resulting in no power output, the LED power-on indicator module remains off.
[0059] As can be seen, in this example, by deploying an LC filter circuit on the critical link, noise and spurious noise in the power transmission process can be effectively filtered out, ensuring that the power supplied to the communication module is stable and pure, and avoiding noise interference with the normal operation of the communication module; the added LED power-on indicator module can intuitively reflect the power supply status, making it easy for staff to quickly determine whether the slave board is in a normal power supply state, reducing the difficulty of troubleshooting, and further improving the system's ease of maintenance and operational reliability.
[0060] As can be seen, in the process of this application embodiment, the power supply and communication system of the programmable gate array communication daughterboard shown in this application adopts a "master control motherboard + slave daughterboard" architecture design. The read-only memory, power on / off control circuit, and communication module of the master control motherboard and slave daughterboard form a bidirectional communication link. At the same time, a hierarchical power supply link is established from the master control motherboard to the power on / off control circuit and read-only memory, from the power on / off control circuit to the power regulation module, and from the power regulation module to the communication module. Optional external power supplies are used to expand the power supply source, forming a complete architecture of "communication-power supply" coordinated management. This architecture prioritizes power-on of the master control motherboard and reads the read-only memory. The system stores configuration information and performs adaptation operations, effectively avoiding communication failures and hardware damage caused by level mismatch. It relies on the on / off logic of the power supply control circuit to achieve precise control of power supply timing and has anti-current backflow function. The power conditioning module flexibly adjusts power parameters in combination with the topology structure. The LC filter circuit at the input and output ends filters out power supply noise. The LED indicator module at the output end provides intuitive feedback on the power supply status. The current margin design of the external power supply further ensures power supply stability. The system achieves safe and reliable operation of power supply and communication, improves the system's compatibility with different specifications of slave boards, and reduces the risk of hardware failure and maintenance difficulty.
[0061] Furthermore, this application also provides a power supply timing control method for a programmable gate array (PGA) communication sub-board, including a power supply communication system employing the PGA communication sub-board as described in the above embodiments.
[0062] Please see Figure 3 , Figure 3 This is a flowchart illustrating a power supply timing control method for a programmable gate array (PGA) communication daughterboard according to an embodiment of this application, applicable to any of the above-mentioned PGA communication daughterboard power supply communication systems; the method includes: Step S301: Start the system power supply to control the main control board to be powered on first.
[0063] Step S302: After the main control board is powered on, power is supplied to the read-only memory and power on / off control circuit of the slave board through the main control board.
[0064] In step S303, the main control board establishes a data connection with the read-only memory to read the configuration information pre-stored in the read-only memory.
[0065] In one possible embodiment, the main control board establishes a data connection with the read-only memory (ROM) to read the configuration information pre-stored in the ROM, including: the main control board establishing a data connection with the ROM via an integrated circuit bus; after the data connection is established, obtaining the device address of the ROM; performing a validity verification operation on the device address to obtain a verification result, the verification result being used to characterize whether the device address is valid; if the verification result is positive, the main control board reads the configuration information of the slave board via the data connection.
[0066] The device address of the read-only memory can be composed of fixed bits and programmable bits. The value of the fixed bits is "1010". The programmable bits correspond to the A0, A1 and A2 pins of the EEPROM. When the pin is grounded, the corresponding address bit is "0" and when the pin is connected to the power supply, the corresponding address bit is "1". Different configuration of device address can be achieved by different connection methods of the pins. Up to 8 EEPROM devices with different addresses can work at the same time on the same integrated circuit bus.
[0067] In this example, the interaction process between the main control board and the read-only memory specifically includes: the main control board sends an address frame to the read-only memory through the integrated circuit bus, compares the obtained device address with a preset legal address range, and thus completes the validity verification of the device address; if the device address is within the legal range, the verification result is determined to be "yes", and the main control board then initiates a data read command; if the device address exceeds the legal range, the verification result is determined to be "no", and the main control board stops subsequent read operations.
[0068] As can be seen, in this example, by establishing a communication connection between the main control board and the read-only memory through the integrated circuit bus, combined with the device address validity verification mechanism, it can be ensured that the main control board accurately identifies the target read-only memory, avoiding configuration information reading errors caused by device address conflicts or illegal device access, and providing accurate and reliable data support for subsequent adaptation operations.
[0069] In step S304, the main control board performs an adaptation operation based on the read configuration information, and sends an on / off control signal to the power on / off control circuit after the adaptation operation is performed.
[0070] In one possible embodiment, the main control board further includes a hardware debugging module; the main control board performs an adaptation operation based on the read configuration information, and sends an on / off control signal to the power on / off control circuit after the adaptation operation is performed, including: the main control board decodes the configuration information according to hexadecimal encoding to obtain the power supply voltage specifications and hardware version number of the slave board's input / output interface; if the decoded configuration information matches the pre-established adaptation model stored on the main control board, the main control board configures the port level of the corresponding input / output interface based on the power supply voltage specifications of the input / output interface, and configures the corresponding communication protocol based on the hardware version number; if the decoded configuration information does not match the adaptation model, the main control board prints a prompt message through the hardware debugging module, the prompt message being used to indicate the adaptation model update operation; after the adaptation model is updated, the port level and communication protocol configuration operation is performed.
[0071] The input / output interface power supply voltage specifications in the configuration information are stored in hexadecimal encoding. The encoding 0X00 corresponds to a 1.2V voltage specification, 0X01 corresponds to a 1.35V voltage specification, and 0X02 corresponds to a 1.8V voltage specification. The hexadecimal encoding of the hardware version number corresponds one-to-one with the preset communication protocol parameters, which include core information such as communication address and data transmission rate.
[0072] The main control board decodes the specific configuration parameters of the slave board and then calls the internally stored adaptation model for matching and verification. The core of the matching and verification is to compare whether the configurable port level range and communication protocol type of the main control board are compatible with the configuration parameters of the slave board. If they are compatible, the port level and communication protocol configuration is completed directly. If they are incompatible, the hardware debugging module outputs a model update prompt. After the staff completes the adaptation model update, the configuration operation is re-executed. After the configuration is completed, the main control board sends an on / off control signal to the power on / off control circuit.
[0073] As can be seen in this example, by decoding the configuration information and matching and verifying the adaptation model, accurate adaptation between the main control board and the slave board can be achieved, avoiding hardware damage caused by level mismatch and communication failure caused by protocol incompatibility. The prompting function of the hardware debugging module improves the convenience of system operation and maintenance, and ensures that the adaptation operation is efficient and completed smoothly.
[0074] In step S305, the power on / off control circuit responds to the on / off control signal and controls the power supply path of the power regulation module to be on or off.
[0075] In step S306, after the power supply path is turned on, the power conditioning module adjusts the received electrical energy and transmits it to the communication module.
[0076] The communication module enables bidirectional data interaction with the main control board and external devices based on configuration information.
[0077] As can be seen, in this embodiment, a complete power supply timing control logic is constructed through the orderly steps of "powering on the main control board first, supplying power to the read-only memory and power on / off control circuit, reading configuration information to perform adaptation operations, controlling the power supply path on / off, and adjusting and transmitting power". This realizes the coordinated management and control of power supply and communication, which not only avoids the hardware risks caused by blind power supply, but also ensures the stable operation of the slave board communication module. At the same time, it improves the system's compatibility with slave boards of different specifications, and enhances the overall reliability and practicality of the programmable gate array communication slave board power supply communication system.
[0078] The power supply timing control method provided for the power supply and communication system of the programmable gate array communication sub-board mentioned in this embodiment also includes a power-off timing process. The core design concept is "communication termination priority, power supply cut-off step by step, and status confirmation in stages," which corresponds in reverse order to the power-on timing process of "main control power-on priority, power supply and communication start after adaptation." This will be explained in detail with reference to the diagram: Please see Figure 4 , Figure 4 This is a flowchart illustrating another power supply timing control method for a programmable gate array (PGA) communication daughterboard provided in this application embodiment, applicable to any of the above-mentioned PGA communication daughterboard power supply communication systems; the method further includes: In step S401, when the main control board receives a system power-off command or detects an abnormal operating state that requires an emergency power-off, it first sends a communication termination signal to the communication module of the slave board.
[0079] The power outage triggering conditions are divided into two categories: active triggering and passive triggering. Active triggering occurs when the system receives a manually issued power outage command, while passive triggering occurs when the system detects fault states such as overcurrent, overvoltage, or communication anomalies, requiring emergency power-off protection hardware. Regardless of the triggering method, the main control board first sends a communication termination signal to the communication module. This signal carries dual instructions: data transmission termination and buffered data saving. Upon receiving this signal, the communication module immediately stops receiving and sending data, writing any untransmitted buffered data to the local storage unit to ensure data integrity and prevent data loss due to sudden power outages.
[0080] In step S402, the communication module responds to the communication termination signal, stops bidirectional data interaction with external devices and the main control board, and completes data caching and cleanup.
[0081] The communication termination signal includes a data transmission termination instruction and a cached data saving instruction, ensuring that the communication module will not experience data loss or transmission abnormalities before ceasing interaction.
[0082] In step S403, after the communication module completes its final processing, the main control board sends a low-level on / off control signal to the power on / off control circuit.
[0083] In step S404, the power on / off control circuit responds to the low-level on / off control signal, cuts off the power supply path to the power regulation module, the power regulation module stops supplying power to the communication module, and the LED power-on indicator module at the output of the power regulation module goes out.
[0084] If the system is powered by an external power source, in step S404, the power supply on / off control circuit simultaneously disconnects the power supply connection with the external power source.
[0085] After the communication module completes data buffering and processing, it sends a "communication ready, power off" signal to the main control board. Upon receiving this feedback, the main control board sends a low-level on / off control signal to the power on / off control circuit. Specifically, based on the hardware structure of the power on / off control circuit described above, the low-level signal will turn off the NPN transistor, and the P-channel MOSFET will also turn off because its gate and source potentials are aligned, thus cutting off the power supply path to the power regulation module. After the power regulation module loses its input power, it stops supplying power to the communication module, and its output LED power-on indicator module turns off due to the power failure, providing direct feedback that the power supply path has been disconnected.
[0086] Step S405: After the power regulation module completely stops supplying power, the main control board stops supplying power to the read-only memory and power on / off control circuit of the slave board.
[0087] In step S406, the main control motherboard completes the power-off process for its core modules and finally stops supplying power to itself.
[0088] The main control board detects the output voltage signal of the power regulation module. Once it confirms that the voltage has dropped to a safe threshold, it stops supplying power to the read-only memory and power on / off control circuit of the slave board. Since the read-only memory has already completed reading and using the configuration information, stopping the power supply at this time will not affect the system data security; after the power on / off control circuit loses power, it further ensures that there is no residual reverse current. The main control board completes the power-off process for its own core modules, including turning off the internal clock and releasing I / O port resources, before stopping its own power supply, thus ending the entire power-off process. Throughout the process, the main control board strictly controls the execution order of each step by collecting the status feedback signals of each module in real time, avoiding the chaotic situation of "power-off first, then completion".
[0089] In the power-off sequence process, the main control board determines whether each step is completed by real-time detection of the communication module's closing status feedback signal and the power on / off control circuit's path status signal. Only after the previous step is confirmed to be completed will the next power-off operation be triggered, thus avoiding current backflow or hardware damage caused by a disordered power-off sequence.
[0090] As can be seen, in this example, by designing a reverse power-off timing sequence, first terminating the communication interaction and then cutting off the power supply path, data loss caused by interruption during data transmission can be avoided. The logic of confirming the power-off state step by step can effectively block the backflow of current from the slave board to the main control board, protect the FPGA core chip of the main control board and each module of the slave board, and at the same time ensure that each module completes the final processing in an orderly manner, thereby improving the safety and reliability of the system power-off process.
[0091] This application also provides a computer storage medium storing a computer program / instructions thereon, which, when executed by a processor, implements some or all of the steps of any of the methods described in the above method embodiments.
[0092] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments.
[0093] It should be understood that any solutions and products implemented based on the power supply and communication system of the aforementioned programmable gate array communication sub-board should fall within the protection scope of this application.
[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0095] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A power supply communication system for a programmable gate array communication daughter board, characterized by, The application relates to a master control motherboard and a slave sub-board, wherein the slave sub-board comprises a communication module, a power on-off control circuit, a power supply regulating module and a read-only memory. The power supply output end of the master control motherboard is connected with the power supply input end of the power on-off control circuit and the power supply input end of the read-only memory, the power supply output end of the power on-off control circuit is connected with the power supply input end of the power supply regulating module, and the power supply output end of the power supply regulating module is connected with the power supply input end of the communication module. The communication end of the master control motherboard is connected with the communication end of the read-only memory and the communication end of the communication module, and the communication end of the power on-off control circuit is connected with the communication end of the master control motherboard. The master control motherboard is used for preferentially powering on and supplying power to the power on-off control circuit and the read-only memory, and performing data interaction operation with the read-only memory to read the configuration information corresponding to the slave sub-board. The read-only memory is used for pre-storing the configuration information of the slave sub-board and performing the data interaction operation with the master control motherboard to transmit the configuration information to the master control motherboard. The master control motherboard is further used for performing adaptation operation according to the configuration information, and sending an on-off control signal to the power on-off control circuit after the adaptation operation is completed, wherein the on-off control signal is used for indicating the working state of the power on-off control circuit. The power on-off control circuit is used for receiving and responding to the on-off control signal sent by the master control motherboard, controlling the on-off of the power supply path of the power supply regulating module to control the power supply of the power supply regulating module. The power supply regulating module is used for receiving and regulating the electric energy delivered by the power on-off control circuit when the power supply path of the power on-off control circuit is turned on, delivering the regulated electric energy to the communication module, and the current parameter and voltage parameter corresponding to the regulated electric energy are determined by the power supply demand of the communication module. The communication module is used for receiving the first communication data transmitted by the master control motherboard based on the configuration information adapted by the master control motherboard after the regulated electric energy is obtained, converting the first communication data into a transmission signal conforming to the communication protocol of an external device, outputting the transmission signal to the external device, receiving a receiving signal from the external device, and converting the receiving signal into second communication data conforming to the communication protocol of the master control motherboard to output the second communication data to the master control motherboard. 2. The power supply communication system of a programmable gate array communication daughter board according to claim 1, wherein, The power on-off control circuit comprises a first resistor, a second resistor, a third resistor, a MOS tube, a triode and an inductor, a first end of the first resistor is connected with a communication end of the master control motherboard as a communication end of the power on-off control circuit, a second end of the first resistor is connected with a base of the triode, an emitter of the triode is grounded, a collector of the triode is connected with a first end of the second resistor and a gate of the MOS tube, a second end of the second resistor is connected with a first end of the third resistor and a source of the MOS tube, a drain of the MOS tube is connected with a first end of the inductor, a second end of the inductor is connected with a power supply input end of the power supply regulating module, and a second end of the third resistor is connected with a power supply output end of the master control motherboard as a power supply input end of the power on-off control circuit; wherein, when the on-off control signal is high, a conduction current flows out from the communication end of the master control motherboard, sequentially passes through the first resistor, the base of the triode, the emitter of the triode and flows into a common ground end, so as to make the triode conduct; and after the triode is turned on, the gate of the MOS tube is electrically connected with the common ground end through the triode, and the source of the MOS tube is electrically connected with the power supply output end of the master control motherboard through the second resistor and the third resistor, so as to make the MOS tube conduct; and the power supply path is turned on, and the power supply current output by the master control motherboard sequentially passes through the third resistor, the second resistor, the MOS tube and the inductor, so as to be output to the power supply input end of the power supply regulating module and supply power to the power supply regulating module; when the on-off control signal is low, the communication end of the master control motherboard does not output the conduction current, so as to make the triode in an off state; and the gate of the MOS tube is electrically connected with the power supply output end of the master control motherboard through the second resistor and the third resistor, so as to make the MOS tube off and the power supply path disconnected.
3. The power supply communication system of a programmable gate array communication daughter board according to claim 1, wherein, The configuration information comprises a power supply voltage specification and a hardware version number of an input / output interface of the slave sub-board; The read-only memory is further configured to store the power supply voltage specification and the hardware version number of the input / output interface into the configuration information through hexadecimal data coding respectively before the master control motherboard is powered on preferentially.
4. The power supply communication system of a programmable gate array communication daughter board according to claim 3, wherein, The adaptation operation comprises configuring a port level of an input / output interface corresponding to the master control motherboard based on the power supply voltage specification of the input / output interface, and configuring a corresponding communication protocol based on the hardware version number.
5. The power supply communication system of a programmable gate array communication daughter board according to claim 4, wherein, The power supply regulating module is composed of a linear voltage stabilizer and a switching voltage stabilizer, and a topology structure of the power supply regulating module is selected from one or more of a boost topology, a buck topology and a buck-boost topology. When the power supply adjustment module receives the power supplied by the power on-off control circuit, the voltage parameter and the current parameter of the power are adjusted according to the power supply voltage specification of the input / output interface and the power supply requirement corresponding to the hardware version number, so that the adjusted power is obtained and output to the communication module.
6. The power supply communication system of a programmable gate array communication daughter board according to any one of claims 1-5, wherein, The power supply communication system of the programmable gate array communication daughter board further comprises an external power supply, the power supply of the read-only memory is taken from the master control motherboard, and the power supply input of the power on-off control circuit comprises power supply output of the master control motherboard and power supply output of the external power supply. When the power on-off control circuit selects the power supply output of the external power supply, the maximum output current of the external power supply is greater than a preset multiple of the maximum consumption current of the slave daughter board in normal operation.
7. A power supply timing control method of a programmable gate array communication daughter board, characterized by, The application is applied to the power supply communication system of the programmable gate array communication daughter board in any one of claims 1-6; the method comprises: starting system power supply to control the master control motherboard to be powered on preferentially; after the master control motherboard is powered on, the read-only memory and the power on-off control circuit of the slave daughter board are powered by the master control motherboard; the master control motherboard establishes data connection with the read-only memory to read the configuration information pre-stored in the read-only memory; the master control motherboard performs adaptation operation according to the read configuration information, and sends on-off control signal to the power on-off control circuit after the adaptation operation is performed; the power on-off control circuit controls the power supply path of the power supply adjustment module to be on or off in response to the on-off control signal; after the power supply path is turned on, the power supply adjustment module adjusts the received power and supplies it to the communication module, and the communication module realizes bidirectional data interaction with the master control motherboard and external equipment based on the configuration information.
8. The method of claim 7, wherein, The master control motherboard establishes data connection with the read-only memory to read the configuration information pre-stored in the read-only memory, which comprises: the master control motherboard establishes data connection with the read-only memory through an integrated circuit bus; after the data connection is established, the device address of the read-only memory is obtained; validity verification operation is performed on the device address to obtain a verification result, which is used to represent whether the device address is valid; if the verification result represents yes, the master control motherboard reads the configuration information of the slave daughter board through the data connection.
9. The method of claim 8, wherein, The master control motherboard further comprises a hardware debugging module; the master control motherboard performs adaptation operation according to the read configuration information, and sends on-off control signal to the power on-off control circuit after the adaptation operation is performed, which comprises: the master control motherboard decodes the configuration information according to hexadecimal coding to obtain the power supply voltage specification of the input / output interface of the slave daughter board and the hardware version number; if the decoded configuration information matches the pre-established adaptation model stored in the master control motherboard, the master control motherboard configures the port level of the corresponding input / output interface of the master control motherboard based on the power supply voltage specification of the input / output interface, and configures the corresponding communication protocol based on the hardware version number. If the decoded configuration information does not match the adaptation model, the host motherboard prints prompt information through the hardware debugging module, and the prompt information is used to indicate an update operation of the adaptation model. After the adaptation model is updated, a configuration operation of the port level and the communication protocol is performed.
10. A computer-readable storage medium, characterized in that, A computer program for electronic data interchange is stored, wherein the computer program causes a computer to perform the method of any one of claims 7-9.