Artificial intelligence chip matching device compatible test method and system

Abstract

The application discloses an artificial intelligence chip matching device compatible test method and system, and relates to the field of artificial intelligence chip testing. First, the original hardware scanning information is acquired by using a hardware abstraction layer, and a device capability mapping diagram is constructed. Then, a measurement vector set containing a frequency gradient is generated, and the state switching of an AI chip is forced to be executed in a stress injection process. Subsequently, by calculating an electrical quality variation stability index, complex physical layer signal drift is converted into a measurable stability score matrix. This process establishes a dynamic mapping relationship between power fluctuations and bit error rate, signal integrity parameters, and makes up for the defects of the lack of linkage mechanism in traditional black box testing. Finally, the critical region of parameter mismatch is locked through failure boundary analysis, thereby providing accurate compatibility data support for the stable operation of high-performance AI systems under dynamic load.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip testing, and more specifically, to a method and system for testing the compatibility of artificial intelligence chip supporting devices. Background Technology

[0002] With the rapid development of artificial intelligence technology, large-scale model training and inference tasks place extremely high demands on the collaborative capabilities of high-performance AI chips and their supporting devices (such as PCIe switches, retimers, DPUs, and storage devices). In complex heterogeneous computing systems, the compatibility between AI chips and supporting hardware not only affects basic connectivity but also directly determines the overall performance and stability of the system under extreme loads. Due to the high transient volatility of AI workloads, AI chips must perform millisecond-level dynamic voltage-frequency adjustment (DVFS) according to task requirements. This highly dynamic operating environment makes it crucial to build a compatibility testing scheme that can deeply cover the hardware interaction layer.

[0003] However, existing compatibility testing schemes often suffer from significant lag and limitations. Traditional testing methods mostly treat AI chips and supporting devices as isolated black boxes, focusing on functional verification under static conditions. During the link initialization phase, existing technologies can often only negotiate a set of fixed pre-emphasis and de-emphasis parameters based on the chip's steady-state design. This static configuration approach is ill-suited to handle sudden situations during dynamic operation: when the AI ​​chip is performing DVFS conversion, its transmitting end's drive impedance and signal amplitude drift due to a sudden voltage drop, and the adaptive equalization algorithm at the receiving end of the supporting device often fails to match the convergence speed of such microsecond-level changes, leading to link negotiation failure or signal integrity damage. Furthermore, existing methods lack a time-domain state synchronization mechanism. During testing, it is impossible to force the AI ​​chip to traverse all electrical states and simultaneously perform high-frequency sampling of the underlying physical layer registers of the supporting device. Due to the failure to establish a dynamic mapping relationship between the AI ​​chip's power state and the supporting device's physical layer bit error rate, the testing process cannot accurately quantify the stability of electrical qualitative changes and is also unable to identify the precise boundaries of compatibility failures. This lack of multi-dimensional indicator collection and end-to-end collaborative testing capabilities makes it difficult for R&D personnel to quickly locate the root cause of faults and carry out targeted optimizations when faced with link instability issues.

[0004] Therefore, there is an urgent need for an automated testing method that can combine hardware capability mapping, synchronous pressure injection, and failure boundary analysis to solve the compatibility problem of high-performance AI systems under dynamic loads. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this application provides a compatibility testing method for artificial intelligence chip supporting devices, which includes: Obtain raw hardware scan information; Based on the original hardware scan information, construct a device capability mapping map; Generate a set of measurement vectors based on the device capability mapping map; Perform synchronous state switching and pressure injection on the measurement vector set to obtain the raw telemetry data stream; Electrical quality change stability index is calculated for the raw telemetry data stream to obtain the stability score matrix; Compatibility failure boundary analysis was performed on the stability score matrix to obtain failure boundary analysis data.

[0006] This application also provides a compatibility testing system for artificial intelligence chip supporting devices, which includes: The raw hardware scan information acquisition module is used to acquire raw hardware scan information; The device capability mapping construction module is used to construct a device capability mapping based on the original hardware scan information. The measurement vector set generation module is used to generate measurement vector sets based on the device capability mapping map; The telemetry data generation module is used to perform synchronous state switching and pressure injection on the measurement vector set to obtain the raw telemetry data stream; The stability scoring module is used to calculate the electrical quality change stability index of the raw telemetry data stream to obtain the stability scoring matrix. The compatibility failure boundary analysis module is used to perform compatibility failure boundary analysis on the stability score matrix to obtain failure boundary analysis data.

[0007] Compared with existing technologies, this application provides a compatibility testing method and system for AI chip components, aiming to solve the link failure problem between AI chips and supporting components during DVFS transition transients. First, it utilizes a hardware abstraction layer to obtain raw hardware scan information and construct a device capability mapping map, thereby achieving standardized quantification of heterogeneous hardware physical specifications. Addressing the bottlenecks of static configuration and transient response lag in existing technologies, it generates a measurement vector set containing frequency gradients and forces the AI ​​chip's state switching during pressure injection, ensuring precise synchronization of the AI ​​chip's power state and the supporting component's physical layer telemetry data in the time domain. Subsequently, by calculating the electrical quality change stability index, the complex physical layer signal drift is transformed into a measurable stability scoring matrix. This process establishes a dynamic mapping relationship between power fluctuations and bit error rate and signal integrity parameters, compensating for the lack of a linkage mechanism in traditional black-box testing. Finally, failure boundary analysis identifies the critical region of parameter mismatch, thus providing accurate compatibility data support for the stable operation of high-performance AI systems under dynamic loads. Attached Figure Description

[0008] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings.

[0009] Figure 1 This is a flowchart of a compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application.

[0010] Figure 2 This is a flowchart of step 2 in the compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application.

[0011] Figure 3 This is a schematic diagram of the data flow in step 6 of the compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application.

[0012] Figure 4 This is a block diagram of an artificial intelligence chip accessory compatibility testing system according to an embodiment of this application. Detailed Implementation

[0013] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0014] In view of the shortcomings in the above-mentioned technical fields, this application proposes a compatibility testing method for supporting devices of artificial intelligence chips. Figure 1 This is a flowchart illustrating a compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application. Figure 1As shown, the compatibility testing method for artificial intelligence chip supporting devices according to an embodiment of this application includes: Step 1, acquiring original hardware scan information; Step 2, constructing a device capability mapping map based on the original hardware scan information; Step 3, generating a measurement vector set based on the device capability mapping map; Step 4, performing synchronous state switching and pressure injection on the measurement vector set to obtain the original telemetry data stream; Step 5, calculating the electrical quality change stability index of the original telemetry data stream to obtain a stability scoring matrix; Step 6, performing compatibility failure boundary analysis on the stability scoring matrix to obtain failure boundary analysis data.

[0015] In step 1, raw hardware scan information is acquired. It should be understood that in the heterogeneous architecture of high-performance AI computing clusters, AI chips often need to interconnect at high speed with supporting devices (such as PCIe Switches, Retimers, and DPUs) from different manufacturers and possessing different physical characteristics. These hardware devices differ significantly in their underlying protocol implementations, electrical parameter specifications, and register configurations, and exhibit complex topologies in their physical connections. To ensure that subsequent compatibility testing can accurately apply dynamic loads and monitor signal integrity on specific physical links, the test framework first breaks through the black-box state and performs a comprehensive digital reconstruction of the current physical environment. Acquiring raw hardware scan information is the cornerstone of this digital reconstruction. Through standardized bus traversal and register reading mechanisms, the hardware connections in the physical world are transformed into raw data streams that can be recognized by the computer, thereby identifying the identity, bus address, and basic link status of heterogeneous hardware, providing a unique and authentic data source for subsequently constructing an accurate device capability mapping map.

[0016] In one embodiment of step 1, the specific processing is as follows: The specific implementation process of obtaining the original hardware scan information mainly relies on the collaboration between the Hardware Abstraction Layer (HAL) and the Hardware Topology Auto-Discovery Module in the test framework. During the initialization phase of the test task, the Hardware Topology Auto-Discovery Module is activated first. This module does not directly operate on the underlying registers, but instead uses the standardized adaptation interface provided by the HAL to shield the differences in underlying instructions between different hardware (such as CPU, DPU, NVMe, and switches). The HAL sends bus scan instructions to the underlying operating system or baseboard management controller. For PCIe bus devices, the implementation process combines in-band and out-of-band management. At the in-band management level, the underlying tools provided by the operating system (such as the LSPCI instruction set) are used to perform a deep traversal of the PCIe configuration space. This traversal process starts from the root complex of the PCIe bus and searches downwards level by level until all endpoint devices are reached. During the scan, the system reads the configuration space register header information of each detected physical node. Specifically, the system reads the register at offset 0x00 to obtain the vendor identifier, i.e., the vendor ID. For example, reading the hexadecimal value 0x10DE represents a specific GPU manufacturer, or 0x19E5 represents a specific network chip manufacturer. It reads the register at offset 0x02 to obtain the device identifier, i.e., the device ID, which is used to distinguish the specific chip model. At the same time, it reads the command register and the status register to confirm the current enabled status of the device.

[0017] In addition to basic identification, fundamental link status information is captured by reading link capability registers and link status registers. For example, during implementation, the currently negotiated link width, such as x16, x8, or x4, and the current link rate, such as 16GT / s (Gen4) or 32GT / s (Gen5), are extracted. For low-level physical layer devices that cannot be directly accessed through the operating system, such as PCIe Retimers or certain special switch chips, the implementation calls the SMBus (System Management Bus) interface for out-of-band data acquisition. Through the SMBus protocol, the test host directly sends read commands to the target device address mounted on the I2C bus to obtain unstructured data stored in its internal registers, such as firmware version number, physical channel mapping relationship, and temperature sensor readings.

[0018] For inter-chip interconnect buses that may exist in heterogeneous computing scenarios, the hardware topology auto-discovery module performs specific scans based on predefined private protocol signatures to identify the private bus connection methods between the CPU and AI chips or between AI chips. During this process, all PCIe layer data obtained through LSPCI scanning, physical device status data acquired through SMBus, and C2C bus data are aggregated in real time. This data is not yet cleaned and appears as a mixed data stream containing bus numbers, function numbers, vendor identifiers, device identifiers, and raw hexadecimal register values. For example, the scan result might contain a record like "03:00.0 Vendor:10DE Device:2330 Link: Gen5x16 Status: Active," indicating that a device with vendor identifier 10DE and device identifier 2330 was identified at PCI bus address 03:00.0, and its physical link is currently active in PCIe Gen5 x16 specifications—raw hardware scan information.

[0019] In step 2, a device capability mapping map is constructed based on the original hardware scan information. Correspondingly, while the original hardware scan information obtained in the previous stage provides proof of device existence at the bus level, it is essentially still discrete, unstructured, and shallow data. This data can only inform the test framework which devices exist on the bus, but cannot reveal the electrical characteristics and dynamic adjustment capabilities of these devices. For example, the vendor ID and device ID in the original data are only static identifiers and cannot directly reflect the voltage-frequency scaling curve (DVFS curve) of the AI ​​chip under millisecond-level load changes, nor can it reflect the equalizer (EQ) adjustment range of the matching PCIe Retimer device under different signal attenuations. Since the core objective of this test scheme is to solve the link negotiation failure problem under DVFS transients, this requires the test to be based on a deep understanding of the physical capabilities of the tested object. Without a digital mapping of the device's electrical capabilities, the subsequent measurement vector generation will fall into a state of blind randomness, failing to construct a stress scenario that accurately covers the failure boundary. Therefore, this application further performs deep cleaning, specification association, and topology reconstruction on the original scan information to construct a device capability mapping map that includes both physical connection relationships and dynamic electrical attributes.

[0020] Figure 2 This is a flowchart of step 2 in the compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application. Figure 2As shown, in one embodiment of step 2, a device capability mapping graph is constructed based on the original hardware scanning information, including: step 21, cleaning the original heterogeneous data and instantiating the nodes of the original hardware scanning information to obtain a list of basic hardware nodes; step 22, enhancing the electrical parameter association of each basic hardware node in the list of basic hardware nodes based on the specification library to obtain a list of enhanced hardware attributes; step 23, constructing a device capability mapping graph based on the list of enhanced hardware attributes.

[0021] In the above implementation, step 2 is specifically processed as follows: First stage: Step 21, raw heterogeneous data cleaning and node instantiation. The input to this step is the raw hardware scan information stream obtained through the Hardware Abstraction Layer (HAL) in the previous stage. This information exists in the form of a text stream or byte stream, containing a large number of redundant format characters and invalid entries that may be generated due to bus transient errors. For example, the input data may contain strings like 03:00.0 Vendor:10DE Device:2330Link: Gen5x16 Status: Active, as well as some invalid data of all F (0xFFFF) returned due to read timeout or non-existent device. First, the noise reduction engine of the bus protocol layer is started, which adopts filtering rules based on the PCIe protocol specification. For the raw data stream, the engine will scan and verify the Vendor ID field line by line. In the PCIe bus scanning mechanism, when the controller attempts to read a non-existent device configuration space, the bus will return 0xFFFF by default. Therefore, any record with a Vendor ID of 0xFFFF will be marked as a ghost device and directly removed from the data stream, ensuring that subsequent processing only targets real physical entities. Subsequently, a pre-defined regular expression parser is used to extract fields from the cleaned, valid data. The parser precisely captures the bus number, device number, and function number according to the standard format definition of PCIe BDF, such as ^([0-9a-f]{2}):([0-9a-f]{2})\.([0-9a-f]), while extracting the hexadecimal values ​​of the Vendor ID and Device ID. Taking the input data 03:00.0 Vendor:10DE Device:2330 as an example, the parser breaks it down into Bus:0x03, Device:0x00, Function:0x00, VID:0x10DE, DID:0x2330. After completing the field extraction, the object factory method is called to instantiate the node. The system defines a base class named BasicHardwareNode, which contains member variables such as UUID (unique identifier), location_id (physical location identifier), vendor_id (vendor identifier), device_id (device identifier), and link_status (link status). For each set of extracted data, a corresponding BasicHardwareNode object instance is created in memory. During this process, the PCIe link status is initially standardized, resolving Gen5x16 into numerical attributes of bandwidth 32GT / s and channel width 16 lanes. Finally, this stage outputs a list of basic hardware nodes.This is a linear container structure that stores several instantiated hardware objects. Each object contains only the device's identity and location information, for example: [Node_A(ID:10DE:2330,Loc:03:00.0),Node_B(ID:15B3:101E,Loc:04:00.0)]. This list does not yet contain any high-level electrical parameters about voltage, frequency, or equalizers; it only completes the digital registration of the physical entities.

[0022] Phase Two: Step 22, Enhanced Electrical Parameter Association Based on the Specification Library. This phase introduces a pre-built hardware specification database. This database is a pre-built localized or cloud-based knowledge base, with an architecture comprising an index layer, a data layer, and a version management layer. The data layer stores detailed electrical specification parameters for chips from major manufacturers (such as NVIDIA, AMD, Intel, Mellanox, etc.), derived from the chip's datasheet and register programming manual. The database employs a high-efficiency key-value pair storage structure, with the primary key composed of the Vendor ID and Device ID, for example, 10DE_2330. During implementation, the iterator sequentially reads each node object in the basic hardware node list. For each node, its VID and DID combination is extracted as the query key, initiating a retrieval request to the hardware specification database. For AI chip nodes (e.g., VID:10DE, DID:2330, corresponding to the NVIDIA H100 PCIe accelerator card), the database returns its dedicated Dynamic Voltage Frequency Scaling State Set (DVFS P-States). This is a list structure containing multiple tuples, each defining a specific performance state. For example, the returned data might be [{P0:(1.0V,1800MHz,MaxPower)},{P1:(0.95V,1500MHz,HighPower)},...,{P8:(0.7V,200MHz,Idle)}]. This data includes not only the core frequency and voltage, but also the maximum power consumption threshold and switching latency for that state. For the corresponding device node (e.g., VID:15B3, DID:101E, corresponding to the ConnectX-7 DPU or its integrated PCIe Retimer), the database will return the equalizer preset range. For PCIe Gen5 devices, this typically includes the standard coefficient set from Preset0 to Preset10 for the transmitter Tx, and the adjustable range of DC gain and high-frequency peak gain for the continuous-time linear equalizer (CTLE) of the receiver Rx. For example, the returned data might contain Tx_Presets:[P0(-6dB,0dB),P1(-3.5dB,0dB)...] and Rx_CTLE_Index:[0..15]. After obtaining these detailed parameters, the attribute injection operation is performed. The base node object is expanded into EnhancedHardwareNode, i.e., an enhanced hardware node, and the original object structure is supplemented with an electrical_capabilities field. The iterator deeply copies the DVFS table or EQ range table returned by the database to this field. At this point, the list of enhanced hardware attributes in memory is no longer a simple device list, but a parameter set rich in electrical characteristics.Each node in the table not only knows that it is an H100 graphics card, but also knows that it supports 9 voltage and frequency combinations from P0 to P8; it not only knows that it is a Retimer chip, but also knows that it supports weighted adjustment from -6dB to -12dB.

[0023] Phase 3: Step 23, Constructing the Device Capability Map. After acquiring enhanced hardware nodes with rich attributes, the final task is to reconstruct the physical topology connections between them and formalize it into a mathematical model. This step is primarily achieved by parsing the enumeration logic of the PCIe bus. According to the PCIe tree enumeration rules, each non-root device is mounted under a parent bus. The BDF address of each node in the enhanced hardware attribute list is parsed. For example, the root complex is typically located at 00:00.0, while the connected Switch uplink port might be located at 01:00.0. If the Switch's downlink port is configured with bus numbers 02 to 03, then the AI ​​chip with address 03:00.0 is clearly a child node of that Switch downlink port. The algorithm traverses the BDF of all nodes, matching the relationship between subordinate and secondary bus numbers to accurately reconstruct the parent-child connection pairs. These connections are mapped to a directed acyclic graph (DAG) structure. In this graph, enhanced hardware nodes are defined as vertices, and physical links are defined as directed edges. The edge attributes include the current width and speed of the link. To support subsequent mathematical analysis and compatibility boundary calculations, this step introduces set theory to formally define the mapping graph. The generated device capability mapping graph model is represented by the formula: ,in, This represents the set of vertices, that is, all the identified hardware device nodes. , This refers to the collection of auxiliary hardware nodes in the topology other than the AI ​​chip and the device under test, such as the root complex of the PCIe bus, CPU nodes, or passive adapter cards in the middle of the link. The set of edges represents the physical interconnections between devices. Indicates equipment and There are direct links between them. It is defined in the AI ​​chip node set The attribute mapping function on the chip node. For any AI chip node , Mapped to the complete set of DVFS states supported by this chip: ,here, Representing the Each performance state includes a specific voltage. and frequency . It is defined in the set of supporting device nodes. The attribute mapping function. For any matching device. , Mapped to the set of signal integrity conditioning parameters supported by the device: , and This involves defining the adjustable electrical parameters of the physical layer for the supporting devices, specifically the minimum and maximum boundary values ​​for equalizer (EQ) or signal integrity parameters. The final output device capability map is a memory object that encapsulates the aforementioned topology and mathematical definitions. It not only visually demonstrates the architecture of the CPU connecting four AI chips via a switch, but more importantly, it binds the mathematical boundaries of dynamic adjustment capabilities to each node. For example, the AI ​​chip node in the diagram defines its legal domain for voltage fluctuations, and the Retimer node defines its adjustment domain for signal shaping.

[0024] In step 3, a measurement vector set is generated based on the device capability map. It's understandable that while the device capability map successfully digitized the heterogeneous hardware topology and its static electrical boundaries into a graph structure model in the previous stage, this model remains static in the time dimension. However, real-world high-performance AI computing scenarios are highly dynamic. When AI chips perform large model inference or training, their operating voltage and frequency fluctuate drastically with load changes. This millisecond-level DVFS adjustment poses a severe challenge to the physical layer adaptability of the supporting devices. Testing based solely on a static capability map cannot simulate real transient impacts, nor can it capture link layer errors caused by clock data recovery lockouts or adaptive equalization convergence lags. Therefore, it is necessary to transform the spatial capability mapping into a temporal execution sequence. By accurately calculating state dwell times and introducing differentiated stress loads, a measurement vector set that covers all electrical states and provides a sufficient response window for the physical layer can be constructed.

[0025] In one embodiment of step 3, a measurement vector set is generated based on the equipment capability mapping diagram, including: step 31, performing DVFS state extraction and dwell time sequence calculation on the equipment capability mapping diagram to obtain a time-seriesd state sequence object; step 32, instantiating the time-seriesd state sequence object with the differentiated load mode of the matching device to obtain the complete set of state loads to be combined; step 33, generating a measurement vector set based on the complete set of state loads to be combined.

[0026] In the above implementation, step 3 is specifically processed as follows: First stage: Step 31, DVFS state extraction and dwell time sequence calculation. First, the vertex set in the device capability mapping graph is located to the node object marked as an AI accelerator, such as a high-performance chip like NVIDIA H100 or AMD MI300. This is done by reading the attribute set bound to the node. Extract all supported dynamic voltage frequency scaling states and construct the original state set. In this set, each element They all represent a specific work point, for example This likely corresponds to the full-speed performance mode (Boost Clock, 1.0V, 1800MHz), while This may correspond to a deep power-saving mode (Idle, 0.7V, 200MHz). After acquiring the initial state, the key challenge is determining how long each state should be maintained during the test. This duration cannot be an arbitrary fixed value. If the dwell time is too short, the supporting devices, such as the physical layer receiver of the PCIe Retimer, may not have completed locking onto the new frequency signal, or its internal decision feedback equalizer coefficients may not have converged. In this case, the acquired bit error data will be mixed with a large amount of invalid noise, leading to false alarms. Conversely, if the dwell time is too long, it will significantly reduce test efficiency. Therefore, this embodiment introduces a frequency span factor and uses mathematical modeling to dynamically calculate the optimal dwell time. The calculation engine calculates the first state according to the following formula. Dwell time of each state : In this formula: This represents the baseline statistical window time. It's a preset baseline value used to ensure that the PCIe Advanced Error Reporting (AER) mechanism has sufficient time to accumulate reliable bit error counts under steady-state conditions. In real-world high-performance computing scenarios, this value is typically set to 50ms to capture sparse bit errors. This represents the frequency span factor, which physically represents the voltage regulator (VRM) settling time compensation required per unit frequency change. Because the power supply unit of the AI ​​chip has a slope limitation during voltage rise and fall, the larger the frequency span, the longer the voltage takes to stabilize. In this embodiment, based on empirical data, this coefficient can be set to 0.05 ms / MHz. Indicates the current state Core frequency and previous state The absolute value of the difference in core frequencies. For example, switching from 200MHz to 1800MHz, this value is 1600. This represents the worst-case time required for the clock data recovery circuitry of the supporting device to relock. For PCIe Gen5 links, this value is typically set to 100μs to 1ms, taking into account the signal forwarding delay of the retimer. To illustrate with a specific numerical example: if the test sequence is switching from P8 state (200MHz) to P0 state (1800MHz), i.e. =1600MHz. Preset =50ms =0.05 ms / MHz, =1ms. Therefore, the dwell time of state P0 is calculated as follows: =50 + 0.05 × 1600 + 1 = 131 ms. This means that when the test reaches this high-frequency state, it must be forced to remain in this state for at least 131 milliseconds, with the first 81 milliseconds used to wait for electrical stabilization and physical layer locking, and the last 50 milliseconds used to acquire valid data. After the calculation engine completes the time parameter calculations for all states, The data is encapsulated into binary tuples and arranged according to a predetermined traversal order (such as linear upsampling, linear downsampling, or random jumps), ultimately outputting a time-series state sequence object. This object not only contains a set of timestamped voltage and frequency parameters but also retains metadata about the matching device types from the original mapping diagram.

[0027] Phase Two: Step 32, Instantiation of Differentiated Load Modes for Supporting Devices. After establishing the timing baseline at the AI ​​chip level, the next step is to address the load issues at the supporting device level. Simply changing the AI ​​chip's frequency won't necessarily translate signal integrity issues (such as eye diagram closure) into detectable CRC check errors or packet loss if there's no data traffic on the PCIe link. Specific traffic pressure must be applied to the link to trigger potential faults. First, the supporting device type information stored in the timing state sequence object is read. For example, if the identified supporting device is a PCIe Switch chip supporting the PCIe Gen5 protocol, a pre-built standard load library is invoked for this specific device type. This library stores various abstractly defined traffic models, which will be instantiated based on the physical characteristics of the current hardware (e.g., maximum supported bandwidth 32GT / sx16). In this embodiment, the set of instantiated load modes... The main types include the following three typical types: 1. Lsaturation (Saturation Bandwidth Mode) Instantiation: This mode aims to test the stability of the power supply system and the thermal drift characteristics of the chip under high current. The direct memory access engine sets the payload size of the transport layer data packets to the maximum allowed value (MPS) of the PCIe protocol, typically 4096 bytes (4KB). Simultaneously, the number of concurrent requests is increased to the upper limit supported by the device, such as 256 tags. In this mode, the link bandwidth utilization will approach the theoretical limit, such as 128GB / s bidirectional, forcing both the AI ​​chip and the Switch's transceiver to operate at full power, effectively exposing voltage drop issues caused by insufficient power integrity. 2. Lrandom (Random Fragmentation Mode) Instantiation: This mode aims to test the internal arbiter, flow control logic, and small packet processing capabilities of the device. The payload size is set to a minimum value, such as 64 bytes, and random packet intervals are enabled. This fragmented, small-packet traffic leads to a significant increase in the control character overhead on the PCIe link, greatly increasing the toggle rate of the internal scheduling logic of the associated switch. This mode is particularly effective for detecting Crossbar logic errors within the switch chip and signal jitter in the Retimer chip under frequent polarity reversals. 3. Lburst (Burst Oscillation Mode) Instantiation: This mode is designed to test the exit latency and wake-up reliability of the power management state (ASPM). Configure the traffic generator to operate intermittently: first send a full-speed traffic, then stop sending and force the link into an L1 low-power state, hold for a few milliseconds, and then instantly resume full-speed transmission. This intermittent traffic waveform forces the physical layer of the associated device to frequently perform sleep-wake operations. If the AI ​​chip experiences a DVFS frequency jump at the moment of wake-up, this double transient impact can easily lead to link training failure. The above-instantiated load set... The sequential state sequence object generated in step 31 is logically packaged and encapsulated. Note that at this stage, Cartesian product combination has not yet been performed; instead, a resource pool containing all dimensions is formed, namely the complete set of state loads to be combined. The data structure of this complete set can be viewed as a container containing two main dimensions: Dimension A is the AI ​​chip P-State sequence with precise dwell time, such as {(P0, 131ms), (P8, 60ms)}, and Dimension B is the set of stress loads customized for the supporting devices, such as... The generation of this complete set signifies that all the stimulus sources (DVFS states) and load sources (traffic patterns) required for the test are ready and have been parameterized to suit the physical characteristics of the hardware under test.

[0028] In one embodiment of step 33, a measurement vector set is generated based on the complete set of states and loads to be combined, including: step 331, performing column Cartesian product operation on the states of each AI chip and the loads of the supporting devices in the complete set of states and loads to be combined to obtain an original orthogonal pairing list; step 332, performing time-domain parameter fusion and atomic vector encapsulation on the original orthogonal pairing list to obtain an unordered vector list; step 333, performing frequency gradient sorting on the unordered vector list to obtain the measurement vector set.

[0029] Step 331 forms the foundation for constructing the full-coverage test space, and its input data directly inherits from the complete set of state loads to be combined output in step 32. This complete set is represented in memory as two independent collection objects: one is a set of AI chip states containing N elements. The other is a set of supporting device loads containing M elements. Here, the collection Each element in It's not just a simple frequency value, but an object that encapsulates complete electrical properties. For example, consider a high-performance GPU (such as the NVIDIA H100 PCIe). This likely represents the full-speed performance state P0, whose internal attributes include a core voltage of 1.0V, a core frequency of 1800MHz, and the corresponding PCIe link power management strategy. This likely represents a P8 in a deep power-saving state, corresponding to a core voltage of 0.7V and a frequency of 200MHz. (Collection) elements in This represents a specific flow pressure model, for example... For saturated bandwidth mode, a maximum transmission unit of 4KB and 256 concurrent tags are defined; For the random fragmentation mode, a 64-byte small packet random access logic is defined. First, a linear container of capacity N×M is initialized to store the pairing results to be generated. Then, the algorithm initiates a double loop traversal logic, executing the Cartesian product operation S×L from set theory. The outer loop traverses the state set. The inner loop iterates through the load set. In each iteration, the algorithm will select the currently chosen AI state object. With load pattern object Perform a deep copy and logical binding to generate an independent state-load tuple. The generation of this binary tuple has important physical significance: it represents a specific test condition point. For example, the generated binary tuple... This means that when the AI ​​chip is running at its highest frequency and under full voltage, the supporting devices simultaneously bear the greatest data throughput pressure; while the binary... This means that when the AI ​​chip is in a low-voltage, low-frequency energy-saving mode, the supporting devices handle random small packet traffic of high-frequency fragments. Through this Cartesian product operation with full permutations, the orthogonal completeness of the test scenario can be ensured, meaning no voltage-frequency-load combination is omitted. After all loop iterations are completed, the original orthogonal pairing list is output. This is an intermediate list structure containing N×M elements. At this point, although each element in the list clearly describes what is being measured, i.e., the physical condition, they do not yet contain the time dimension information of how long the measurement lasts, and the arrangement order is based on the natural order of set traversal (usually P0-L1, P0-L2...), without considering the smoothness of physical execution.

[0030] After obtaining the pairing list covering all operating conditions, step 332 involves injecting a time dimension into each static operating condition to make it executable. The input to this step includes the original orthogonal pairing list generated in the previous step, and the time-series state sequence object pre-calculated and stored in step 31. In step 31, a unique dwell time has been calculated for each P-State based on the PLL lock time, frequency span factor, and bit error statistics window. For example, for the P0 state with a large frequency range, the calculated... It takes 131 milliseconds; while for the intermediate state P4, its The time is 80 milliseconds. Iterate through each pair in the original orthogonal pairing list. For the currently processed pair, extract its state component. A unique identifier, such as the P-State ID, is used as an index to retrieve the corresponding residence time parameter from the time-series data structure output in step 31. This process, known as attribute fusion, essentially re-associates separated time attributes with specific operating condition descriptions. After obtaining the time parameters, the module calls the vector constructor to transfer the state... ,load and time It is encapsulated as a standardized triplet structure. This structure is defined as an atomic vector unit, denoted as... Its construction logic follows the formula below: This is called an atomic vector because it is the smallest indivisible unit in the test execution process. An atomic vector completely defines all the elements of a micro-level test behavior: who is running, by... The defined electrical state of the AI ​​chip and the load it is connected to are determined by... The defined pressure mode of the supporting components and the running time are determined by... The defined duration. For example, a generated atomic vector might look like this: The test execution layer of the instruction framework sets the AI ​​chip to full-speed P0 (1.0V / 1800MHz), while applying a 4KB packet-length saturation bandwidth stress load to the supporting devices and forcing this condition to be maintained for 131 milliseconds to verify the stability of the physical link under specific electrical conditions. This step is processed cyclically until all pairs in the list have completed the splicing of time parameters. The final output is an unordered vector list. At this point, the elements in the list have all the content required for execution, but their arrangement is still based on the generation order of the previous steps (possibly all load combinations of P0 immediately following all load combinations of P1). This arrangement is physically random or hash-distributed and has not yet been optimized for hardware characteristics.

[0031] Step 333 aims to transform the unordered vector list into an ordered instruction stream that conforms to the physical hardware characteristics. In a real semiconductor physical environment, the voltage rise and fall rate of a voltage regulator is finite, and the phase-locked loop (PLL) inside the chip requires a long lock-in time when the frequency jumps sharply. If the test sequence controls the chip to jump from P8 (200MHz) to P0 (1800MHz) instantaneously in a very short time, and then jumps back to P8, this violent oscillation may not only trigger overcurrent protection (OCP), but may also cause the signal eye diagram to be sampled before it has stabilized, resulting in a large amount of false alarm data. Therefore, a frequency gradient sorting algorithm is applied to rearrange the unordered vector list. The algorithm first parses the state object contained in each atomic vector in the list. Extract its core frequency attributes Subsequently, based on a preset sorting strategy, the vectors are reorganized into linear ascending or linear descending order. The specific implementation of the sorting logic is as follows: the system sorts all vectors from low to high frequency, such as... The vectors are sorted. For multiple vectors with the same frequency (i.e., the same P-State corresponding to different load modes), their relative order is maintained or they are sorted in a secondary order according to load intensity. This sorting strategy simulates the chip's thermal preheating process, making voltage and temperature exhibit smooth gradient changes, maximizing the simulation of real physical thermal expansion and contraction effects, and giving the physical layer equalizer (EQ) sufficient adaptive convergence time to avoid unexpected physical layer oscillations. After sorting, each vector in the queue is assigned a globally unique execution ID (VectorID). This is a monotonically increasing integer sequence (e.g., 001, 002, ..., K) used to accurately locate a specific test operation in subsequent logging and error tracking. For example, when the test system reports Vector ID 053 failed, developers can immediately find that the specific operating condition corresponding to that vector is a random load test in the P2 state. In addition, metadata for the entire vector set is calculated, including the total number of vectors, i.e., N×M, and the total estimated test duration (for all vectors). (The summation of the data). This metadata is added to the head of the list and finally encapsulated into a measurement vector set. This is an ordered, indexed instruction sequence object containing complete timing and load definitions. This object will be passed as the core input to the test execution layer. The system under test will strictly control the AI ​​chip to execute DVFS state switching in this order and synchronously trigger the load injection of supporting devices, thereby reproducing the most realistic dynamic compatibility stress scenario at the physical link level.

[0032] In step 4, a synchronous state switch and pressure injection are performed on the measurement vector set to obtain the raw telemetry data stream. It should be understood that in existing high-performance heterogeneous computing environments, AI chips typically adjust voltage and frequency autonomously based on their internal power management algorithms. This black-box automatic adjustment mechanism makes it difficult for testers to accurately capture the physical layer behavior of the link at specific moments. If only passive observation is relied upon, the testing process cannot guarantee sampling at the coincidence of the two critical stress points of voltage transient drops and maximum service load, resulting in a large number of potential signal integrity vulnerabilities being masked by random normal operating conditions. To deterministically reproduce communication faults that only trigger under extreme physical boundaries, the static measurement vectors generated in the preceding steps need to be transformed into mandatory control commands for the underlying hardware. By actively intervening in the chip's power management strategy and synchronously injecting differentiated pressure flows, the test framework can construct a rigorous and precisely controllable physical experimental environment within a millisecond-level time window, thereby acquiring raw data streams containing real electrical response characteristics, providing the sole objective basis for subsequent stability quantitative analysis.

[0033] In one embodiment of step 4, the specific processing is as follows: it mainly relies on the collaboration between the test execution layer and the hardware abstraction layer. This process transforms the instruction sequence at the logic planning level into electrical signal interactions at the physical circuit level, which is an automated operation process with extremely high requirements for timing synchronization accuracy.

[0034] First, the measurement vector set generated in the previous stage is loaded. This is an instruction queue containing thousands of ordered atomic vectors. The scheduler initializes a high-precision global clock and sequentially extracts the k-th atomic vector. ,Right now yes The results after sorting. For example, the currently extracted vector ID is 1024, which contains the following instructions: force the AI ​​chip to lock in performance state P0 (core voltage 1.0V, frequency 1800MHz), and at the same time require the supporting devices to perform saturated bandwidth load. The dwell time is 131 milliseconds. After parsing the instruction, the scheduler first sends an out-of-band management instruction to the AI ​​chip's power management unit (PMU) through the hardware abstraction layer (HAL). This instruction not only requires the chip to switch to the target voltage and frequency, but more importantly, it writes the automatic DVFS disable register bit to shield the chip's internal self-regulation logic and prevent it from automatically downclocking due to temperature increases or load changes. The controller continuously polls the chip's status register until the P-State Stable flag is set, confirming that the voltage has stabilized at 1.0V and the clock frequency is locked at 1800MHz. This process ensures that the physical state of the excitation source strictly conforms to the definition of the test vector.

[0035] Within a microsecond-level delay of confirming the AI ​​chip's electrical state lock, the execution logic immediately enters the second stage, namely, pressure injection from the supporting device. At this time, the test controller sends a trigger signal via the PCIe bus to the flow generation engine built into the supporting device (such as a switch or retimer) or the connected DMA controller. Based on the vector... Defined as follows: if the current load mode is saturated bandwidth mode, the controller will configure a DMA descriptor to initiate bidirectional data throughput of up to 128GB / s (for PCIeGen5 x16 links). To maximize power supply noise, the start time of traffic injection is strictly controlled in the early steady-state phase after voltage establishment, when the sharp current step (di / dt) will induce the maximum voltage ripple on the power distribution network (PDN). This synchronization mechanism ensures precise time-domain alignment between the worst electrical environment and the maximum data pressure, thereby effectively exposing potential physical layer link defects. With the start of the stressed load, [the following text appears to be incomplete and requires further context: "begins in..."] High-frequency telemetry is performed within a defined 131-millisecond dwell window. The acquisition system operates two data channels in parallel: the first is an in-band PCIe Advanced Error Reporting (AER) polling channel. It reads the correctable and uncorrectable error status registers in the PCIe configuration space at 1-millisecond sampling intervals. It focuses on the increments of the Receiver Error and Bad TLP counters, as these metrics directly reflect packet corruption caused by physical layer signal distortion. The second channel is a physical layer signal quality monitoring channel based on out-of-band or private registers. For devices with adaptive equalization capabilities, such as PCIe Retimers, it directly accesses their physical layer (PHY) registers to read the current eye opening parameters. For example, it acquires real-time values ​​of vertical eye height and horizontal eye width. For instance, it acquires normalized eye height data at 50 milliseconds. A drop to 50mV usually means that the current equalizer parameters cannot compensate for the impedance mismatch caused by DVFS.

[0036] In addition, telemetry data from the AI ​​chip is synchronously read via the SMBus bus on the motherboard, including the real-time waveform value of the core voltage (sampling rate is usually above 1kHz) and junction temperature. All acquired data is timestamped in nanoseconds synchronized with the global clock. For example, a complete sampling record may contain: Timestamp: 100234ms, V_core: 0.98V, Temp: 85C, AER_Err: 2, Eye_H: 45mV, which intuitively reflects the real-time status of the physical layer signal quality (eye height 45mV) and data link reliability (2 AER errors) of the AI ​​chip under a voltage of 0.98V and a high temperature of 85°C when the test runs up to 100234 milliseconds. When the 131-millisecond dwell time expires, or a fatal link error is detected causing the connection to be interrupted, the scheduler will immediately send a stop command, terminate the traffic injection and release the P-State lock on the AI ​​chip, allowing it to briefly return to an idle state to release heat, and then immediately prepare to execute the next vector. After the entire vector set has been executed, all time-series data temporarily stored in the memory buffer are aggregated and serialized to finally generate the raw telemetry data stream. This is a massive multi-dimensional time-series dataset that faithfully records the physical health status of the measured link under each specific voltage-frequency-load combination impact.

[0037] In step 5, an electrical quality change stability index is calculated on the original telemetry data stream to obtain a stability score matrix. Correspondingly, after the synchronization state switching and pressure injection in the preceding steps, although the test system successfully acquired the original telemetry data stream containing massive amounts of physical layer information, this data is essentially an unstructured time series consisting of discrete timestamps, fluctuating voltage values, transient eye diagram sampling points, and accumulated link error counts. Simply observing a voltage drop at a certain moment or an eye diagram closure at a certain instant often makes it difficult to directly determine whether the compatibility under that operating condition meets the standard, because the physical layer protocol itself has certain fault tolerance and error correction mechanisms. A simple binary judgment of whether there are errors or not cannot quantify the robustness margin of the system, nor can it distinguish the essential difference between critical collapse caused by extremely poor power integrity and occasional errors caused by signal attenuation. To transform this multi-dimensional, transient physical layer response into a measurable, comparable, and analyzable standardized indicator, this application performs in-depth mathematical processing on the original data stream. By introducing the calculation of electrical quality change stability index, the test framework aims to establish a comprehensive evaluation system that can integrate protocol layer robustness, physical layer signal quality and power integrity characteristics, and map complex time-domain waveforms into an intuitive two-dimensional stability scoring matrix, thereby providing an accurate mathematical basis for subsequent identification of compatibility failure boundaries.

[0038] In one embodiment of step 5, the electrical quality change stability index is calculated on the original telemetry data stream to obtain a stability score matrix, including: step 51, multi-dimensional time-series data slicing and alignment of the original telemetry data stream to obtain aligned vector data segments; step 52, key electrical feature parameters are extracted and differentially calculated on the aligned vector data segments to obtain a set of vector feature parameters; step 53, stability index weighted calculation and matrix generation are performed on the set of vector feature parameters to obtain a stability score matrix.

[0039] In the above implementation, step 5 is specifically processed as follows: First stage: Step 51, multi-dimensional time series data slicing and alignment. The input data for this step includes two parts: one part is the massive raw telemetry data stream generated in step 4, which is usually stored in a high-performance time series database or memory ring buffer, containing voltage waveforms (sampling rate 10kHz-100kHz), temperature change curves, PCIe link AER error counts (sampling rate approximately 1kHz), and physical layer eye diagram data from the start to the end of the test; the other part is the test vector ID execution log of the test controller, which accurately records the start timestamp of the actual execution of each measurement vector in the physical world. With end timestamp First, the timing slicing program is started. The engine reads the execution log, and for the k-th test vector, such as VectorID:053, which corresponds to the AI ​​chip P2 state superimposed with the random small packet load of the matching Switch, its absolute time window is extracted. This time window is used as a high-pass filter to precisely extract all data frames falling within this time period from millions of records in the original telemetry data stream. After slicing, the main challenge is the frequency asynchrony of heterogeneous data sources. In actual hardware telemetry, the motherboard voltage sensor may report data every 100 microseconds (10kHz), while the PCIe Retimer eye diagram data may only be updated every 50 milliseconds (20Hz), and the AER error counter's polling cycle may be 1 millisecond. This huge difference in sampling frequency results in uneven data across different dimensions in the data segment on the time axis. To address this, the engine performs time axis alignment operations for heterogeneous data sources. During implementation, a unified reference time axis in nanoseconds (ns) is first established, with the granularity determined by the data source with the highest sampling rate. Subsequently, different interpolation strategies are used for low-frequency data sources: 1. For voltage and temperature data, due to the continuous nature of their physical changes, the engine uses a linear interpolation algorithm. For example, in At that moment, the voltage was 0.98V. If the voltage is 0.96V, then at any time in between... The voltage value was calculated as This fills in the gaps between sampling points, restoring the continuous trend of voltage fluctuations. 2. For AER error counts and eye diagram data, since they are discrete events or state snapshots, the engine adopts a zero-order hold strategy, that is, holding the previous valid sample value until the next new sample value appears. This avoids artificially introducing non-existent bit errors. After slicing and alignment, the aligned vector data segment is output. This is a standardized list of data structures, where the k-th element is a multidimensional array containing a synchronous snapshot of all physical parameters on a unified time axis during the k-th test execution. For example, this data segment clearly shows how the core voltage fluctuated at the 35th millisecond of the execution, and whether the PCIe link recorded an error at the same time.

[0040] Phase Two: Step 52, Key Electrical Feature Parameter Extraction and Differential Calculation. Traverse each data segment in the list, and for the k-th segment, extract key indicators from three dimensions: protocol layer, physical layer, and power domain. First Dimension: Protocol Layer Error Statistical Feature Extraction, parsing the Advanced Error Reporting (AER) data stream in the data segment. The AER mechanism is a core means in the PCIe protocol for monitoring link reliability, and it is divided into correctable errors... Such as Replay TimerTimeout, Receiver Error, and Uncorrectable Errors Examples include Poisoned TLP and Data Link Protocol Error. The processing logic accumulates the increments of the error counters for all types within this time window. Specifically, the calculation formula is:

[0041] Typically, to simplify calculations, the weights of all errors are set to be consistent, i.e. =1 directly yields the total accumulated error count. For example, if the link triggers 5 receiver errors (RxErr) and 1 replay within a 131-millisecond test window, then =6. This feature directly reflects the bit error rate level of the link under the current operating conditions. The second dimension: physical layer signal quality margin calculation, extracting eye diagram sampling data from the data segment. The eye diagram is the most intuitive tool for evaluating the quality of high-speed serial signals. During testing, the receiver deserializer of supporting devices such as the Retimer periodically scans the voltage-time window of the signal. The engine reads the vertical eye height data recorded within this time period. To eliminate differences in signal amplitude standards between different devices, such as PCIe Gen4 vs Gen5, the engine performs normalization processing. The theoretical maximum signal swing or target reference value of the device is set to... For example, the typical eye opening under the PCIe Gen5 standard is 100mV, and the measured average eye height is... The normalized eye height margin is then calculated as follows: ,like A value close to 1.0 indicates good eye opening and a high signal-to-noise ratio; a value close to 0 or even negative indicates eye closure and severely compromised signal integrity. For example, if the measured eye height is 50mV and the reference value is 200mV, then... =0.25. The third dimension: power integrity noise differential calculation, which is a key step in this scheme to capture the transient effects of DVFS. Extracting the time-domain waveform array of the power rail voltage. At the moment when the AI ​​chip performs a P-state switch or experiences a sudden load change, the current changes drastically ( This will induce a voltage on the parasitic inductance of the power distribution network (PDN). This manifests as voltage noise. The absolute value of the voltage (e.g., 0.9V) alone cannot fully reflect the destructive power of this high-frequency interference, because high-frequency voltage jumps are the primary cause of clock jitter. Therefore, discrete differentiation is performed on the voltage waveform. For each point in the time series, its rate of change, i.e., the noise attenuation factor, is calculated: Subsequently, the engine takes the maximum value of the rate of change magnitude within the test window as the power supply noise feature of the vector:

[0042] For example, during a sudden load surge, the voltage drops from 1.0V to 0.95V within 10 microseconds, a rate of change of 0.05V / 10µs = 5000V / s. The larger this value, the more unstable the power rail, and the stronger the interference to the phase-locked loop (PLL). After completing the above calculations, the three eigenvalues ​​are encapsulated into a vector feature parameter set: .

[0043] Phase 3: Step 53, Stability Index Weighted Calculation and Matrix Generation. After obtaining the physical features, the final step is to convert them into a business-understandable score. This process relies on a comprehensive evaluation model that introduces weighting coefficients to adapt to different testing scenarios. In one embodiment of Step 53, stability index weighted calculation and matrix generation are performed on the vector feature parameter set to obtain a stability score matrix, including: performing stability index weighted calculation on the vector feature parameter set using the following formula:

[0044] in, The electrical quality change stability index corresponding to the k-th test vector. For protocol layer error robustness weight coefficients, For physical layer signal quality weighting coefficients, This is the power integrity penalty factor. This represents the cumulative total number of link-layer errors captured by the PCIE Advanced Error Reporting mechanism within the execution window of the k-th test vector. This refers to the normalized eye diagram vertical opening height margin measured by the deserializer at the receiver of the supporting device during the execution of the k-th test vector. This represents the maximum absolute value of the rate of change of the power supply noise voltage over time within the test window.

[0045] First, the engine loads the preset weight coefficient configuration. These coefficients are set based on the business sensitivity profile of the system under test. Protocol layer error robustness weights define the system's tolerance to bit errors. For financial trading or core training tasks, data accuracy is crucial; any bit error can lead to computational interruption. It will be set to a higher value, such as =60); however, for streaming inference tasks, a small amount of packet loss is acceptable. It can be appropriately reduced. Physical layer signal quality weights: These define the required signal margin. For long-distance transmission or aging tests, a higher physical margin is needed to resist environmental degradation. The value is set too high, such as =30. Power integrity penalty factor: Used to define sensitivity to power supply noise. If the PLL of the AI ​​chip is extremely sensitive to voltage ripple, then... It needs to be set to a large value, such as =20, to significantly penalize operating conditions with unstable power supply. These weights are typically derived from regression analysis of empirical data from historical projects, or distributed by the system architect via a JSON configuration file during the test configuration phase. Next, the engine substitutes the data from the feature parameter set into the electrical quality change stability equation, calculating the values ​​for each test vector one by one. The score. First item. This is a non-linear decay function. When the link is error-free ( When =0), the term takes its maximum value. With the number of errors As the denominator increases, the score rapidly decays and approaches zero. This design conforms to the zero-error principle, meaning that the stability score should drop significantly as soon as errors occur. (Second term) This is a linear gain term. (Normalized eye height) The larger the eye (the wider the eye diagram), the higher the score, reflecting the positive contribution of physical layer signal quality to stability. (Third item) This is a linear penalty term. The greater the rate of voltage change, the more points are deducted. This reflects the destructive effect of power supply noise on system stability.

[0046] Specifically, for vector k (P0 state, fully loaded), the measured... =0, =0.8, =0.5, the normalized unit value. Let the weights be configured as follows: =50, =40, =10. Therefore, the stability index is... =77 points. For example, for vector j (P8 state, burst load), the measured... =9, =0.5, =1.0. Then =15 points. This shows that even though the physical layer still has some limitations, the occurrence of errors at the protocol layer directly lowered the overall score, accurately reflecting the high risk of this operating condition. Finally, perform a matrix generation operation. Create a two-dimensional matrix structure, where row indices correspond to the AI ​​chip's state set (e.g., P0, P1...P8), and column indices correspond to the load mode set of the supporting devices (e.g., L1, L2...Lm). Read the coordinate information from the definition of each test vector. The calculated scalar score Fill in the corresponding cells in the matrix. The final output stability score matrix is ​​a data table similar to a heatmap. In this matrix, high-scoring areas represent extremely stable system operation under these conditions, while low-scoring areas directly expose compatibility risks. For example, if the lower right corner of the matrix (low voltage + high load area) generally scores extremely low, developers can quickly determine that the system's power integrity design under low power consumption conditions has defects, thus achieving a leap from massive amounts of raw data to precise fault location.

[0047] Specifically, in the results analysis layer, the multidimensional attributable stability assessment aims to address the limitations of the aforementioned linear weighted model in testing complex heterogeneous hardware. Although the preceding steps have obtained aligned data segments containing voltage waveforms, eye diagrams, and link errors, simple linear superposition cannot reflect the cascading causal relationships between various factors in the physical world. That is, severe power supply noise is often the trigger, directly causing the deterioration of the physical layer eye diagram margin, which in turn leads to protocol layer errors. Furthermore, traditional models struggle to distinguish the qualitative differences in errors, fail to reflect the devastating impact of uncorrectable errors on the system, and often neglect the transient physical impact of state switching during Dynamic Voltage Frequency Scaling (DVFS) on the phase-locked loop and clock recovery circuit. Therefore, this step is performed to construct a nonlinear assessment model that can deeply reconstruct the physical causal chain, accurately distinguish the severity of errors, and directly consider the risks of dynamic processes, transforming post-event statistical data into a forward-looking health indicator with fault prediction and attribution capabilities.

[0048] In a preferred embodiment of step 5, the electrical quality change stability index is calculated on the original telemetry data stream to obtain a stability score matrix, including: step 5-1, multi-dimensional time-series data slicing and alignment of the original telemetry data stream to obtain aligned vector data segments; step 5-2, multi-dimensional electrical feature parameter extraction is performed on the aligned vector data segments to obtain a vector feature parameter set, including: normalized eye height margin, noise attenuation factor, error severity index penalty, and state transition penalty; step 5-3, attributable stability assessment and matrix generation are performed on the vector feature parameter set to obtain a stability score matrix. Specifically, step 5-1 is the same as step 51 in the above embodiment, and therefore will not be described further. Here, the implementation of steps 5-2 and 5-3 will be described in detail.

[0049] Specifically, step 5-2 aims to transform the raw physical sampling data into intermediate factors with physical evaluation significance. It iterates through the aligned data segments corresponding to each test vector k, calculating the core parameters across the four dimensions. First, the normalized eye height margin is extracted. This parameter directly reflects the physical layer signal quality and serves as the foundation for evaluation. Its calculation method is the same as described above, so it will not be explained further. Next, the noise attenuation factor is calculated. This parameter no longer treats noise as an independent deduction factor, but rather models it as a direct attenuation coefficient of the eye diagram margin. Its calculation formula is:

[0050] in, This represents the maximum absolute value of the rate of change of the power supply noise voltage within the k-th test vector window. The preset noise sensitivity coefficient is set based on the operational sensitivity profile of the system under test (such as tolerance to power integrity) combined with regression analysis of historical production line experience data; for example, it is set to 0.001. This formula utilizes the characteristics of an exponential function, causing the factor to approach 1 (without attenuation) when the power supply noise is low, while rapidly approaching 0 as the noise slope increases, simulating the physical phenomenon of power supply jitter causing the effective eye diagram to close abruptly. Third, the error severity index penalty is calculated. This parameter is designed to implement differentiated penalty strategies for correctable and uncorrectable errors, and is calculated using the following formula:

[0051] in, and These represent the number of correctable and uncorrectable AER errors recorded in the window, respectively. To smooth out the effect, a penalty coefficient, such as 0.1, The lethal penalty coefficient, such as 10.0, is set based on the business sensitivity of the system under test (e.g., data accuracy requirements) and regression analysis of historical failure data, or preset by the system architect during the test configuration phase using a configuration file. The first part of the formula smoothly decreases for correctable errors, while the second part exponentially decays for uncorrectable errors, ensuring that the stability score suffers a devastating blow immediately upon the occurrence of a fatal error. Finally, the state transition penalty is calculated. This parameter is used to quantify the dynamic risks during DVFS switching, and the calculation formula is as follows:

[0052] in, and These represent the frequency and voltage of the current state, respectively. This is the previous state. and The corresponding switching weighting coefficients are determined based on the physical response characteristics of the phase-locked loop (PLL) and voltage regulation module to dynamic changes or regression analysis of historical fault data, such as the frequency switching weighting coefficient. It can be set to 0.005, meaning that 1 point is deducted from the stability score for every 200MHz frequency jump. It can be set to 20, meaning 2 points are deducted for every 0.1V voltage jump. This item directly quantifies the impact cost on circuit stability when there is a sharp jump from low frequency to high frequency.

[0053] Step 5-3: After obtaining the above feature parameters, this step applies an improved nonlinear model to calculate the final score and generate a matrix. The calculation formula is as follows:

[0054] This formula embodies a rigorous, progressive logic: the original eye diagram quality of the physical layer. Firstly affected by power supply noise The modulation and attenuation, forming an effective physical margin, are then processed by the protocol layer in case of errors. The weighted confirmation is then subtracted from the value due to the state switch. The inherent risk cost is used to obtain the final stability index of the k-th vector. .

[0055] To illustrate this process, consider a specific numerical example: Test vector k corresponds to the instant the AI ​​chip switches from P8 (low power) to P0 (high performance), under a high load. 1. Feature Extraction: Measured normalized eye height. =0.8 (Good physics foundation). The power supply noise is severe, with an extremely high maximum rate of change, calculated as follows: =0.5 (noise halved the effective eye height). One uncorrectable error occurred during this period ( =1), preset =5, then If the error is not corrected, then The frequency jump amplitude is large, resulting in a calculated state transition penalty. =5.0. 2. Stability assessment: When normalized to a 0-100 scale, it is truncated to 0. That is, although the original eye diagram height (0.8) is acceptable, a fatal error has occurred. The term causes the product term to approach zero directly, and the huge state-switching penalty further lowers the score. This accurately reflects that the system has already collapsed under this transient condition. In contrast, if there were only noise and no errors, the score might be much higher. The coefficient needs to be adjusted to the order of magnitude. If there is no noise, no errors, and static dwell, the score will be close to... That is, 80 points. Finally, all the calculated... Fill the data into a two-dimensional matrix with state S as the rows and load L as the columns. This attributable evaluation mechanism allows R&D personnel to quickly pinpoint the root cause based on the individual item values ​​when they see a low score: if... A low value indicates a power integrity issue. A low value indicates a problem with the protocol layer or hardware. The reason for the high number of deductions is that the dynamic clock management strategy needs to be optimized, and in-depth diagnosis of heterogeneous hardware compatibility has been achieved.

[0056] In step 6, a compatibility failure boundary analysis is performed on the stability scoring matrix to obtain failure boundary analysis data. That is, in the previous stage's electrical quality change stability index calculation, although the test framework successfully generated a stability scoring matrix that visually represents the system's robustness under all operating conditions, this matrix is ​​essentially still a static numerical heatmap. While the numerous low-scoring cells in the matrix indicate the coordinates of potential failures, they cannot directly reveal the physical root causes of these failures. For hardware developers, knowing that a score of 45 under P8 state with L2 load is merely a phenomenological description, not an executable optimization instruction. To transform these discrete, superficial numerical scores into specific, low-level physical layer parameter adjustment suggestions, a deep topological analysis and logical deduction are performed on the scoring matrix. This process aims to identify the distribution pattern of failure points on a two-dimensional plane, abstracting them into physically meaningful failure mode feature clusters, and using a reverse mapping mechanism to pinpoint the electrical parameter bottlenecks leading to these modes, thereby providing precise failure boundary navigation for subsequent hardware design iterations or firmware parameter fine-tuning.

[0057] Figure 3 This is a schematic diagram of the data flow in step 6 of the compatibility testing method for artificial intelligence chip accessories according to an embodiment of this application. Figure 3 As shown, in one embodiment of step 6, compatibility failure boundary analysis is performed on the stability score matrix to obtain failure boundary analysis data, including: step 61, based on an empirical threshold, threshold segmentation and anomaly coordinate extraction are performed on the stability score matrix to obtain a failure vector coordinate set; step 62, failure region clustering and distribution feature calculation are performed on the failure vector coordinate set to obtain a failure mode feature cluster; step 63, physical boundary inverse deduction and parameter locking are performed on the failure mode feature cluster to obtain failure boundary analysis data.

[0058] In the above implementation, step 6 is specifically processed as follows: First stage: Step 61, threshold segmentation and anomaly coordinate extraction. First, it is necessary to establish a scientific empirical threshold, denoted as . This threshold is obtained based on a dual benchmarking of historical production line yield data and industry protocol specification margins. Specifically, it retrieves the field failure rate (RMA) data of similar AI chips and supporting device combinations after large-scale deployment in historical projects. Regression analysis reveals that when the stability score in the laboratory environment falls below a certain critical value, the probability of black screens, card drops, or CRC check errors in the field increases exponentially. For example, statistical calculations determine that 85.0 is a safety baseline, meaning that links with a score higher than 85.0 have sufficient signal integrity margin to withstand equipment aging over the next 3-5 years; while links with a score lower than 85.0, even if no fatal errors occur in the current test, are considered to have long-term operational risks. In addition, this threshold can be dynamically adjusted according to the severity of the business scenario. For financial-grade high-frequency trading scenarios, this threshold may be increased to 95.0. After establishing the threshold, the matrix traversal program is started. The input data is the N×M dimension stability score matrix output in step 5, where row index i corresponds to the N voltage frequency states (P-State) of the AI ​​chip, and column index j corresponds to the M load modes of the supporting devices. The engine reads the stability index of each cell row by row and column by column. For each read score, perform a binarization filtering operation. The judgment logic is extremely straightforward: if... If 45.0 < 85.0, the operating point is judged as failed or high-risk; otherwise, it is marked as qualified. For all cells judged as failed, their corresponding row and column indices are extracted, i.e., the specific P-State index i and load mode index j. To preserve physical semantics, the original physical descriptions corresponding to these indices (such as 0.7V, 200MHz, and Burst Load) are retrieved simultaneously and constructed into discrete failure point tuples. Finally, these tuples are aggregated into a mathematical set, i.e., the failure vector coordinate set, denoted as . Its mathematical expression is as follows: In this set, each element Each represents a specific location where a failure occurred. For example, a set might contain... At this point, it is clear where the problem lies, but these points are still logically isolated. It has not yet been revealed whether there is any inherent physical connection between them, nor has it been answered why they failed here.

[0059] Phase Two: Step 62, Failure Region Clustering and Distribution Characteristic Calculation. To reveal the physical patterns from discrete fault points, these points need to be mapped onto a two-dimensional plane for topological analysis. In semiconductor physics, failures caused by the same physical mechanism (such as excessive power supply ripple) will exhibit a continuous distribution within a specific voltage or load range, rather than random isolated points. Therefore, this step aims to identify these continuous regions using clustering algorithms. During implementation, the first step is to... The dataset is mapped back to a state-load two-dimensional planar coordinate system. In this coordinate system, the X-axis represents the voltage / frequency variation of the AI ​​chip (from low voltage P8 to high voltage P0), and the Y-axis represents the load type variation of the supporting devices. Subsequently, a density clustering algorithm or a connected component labeling algorithm is applied. The algorithm sets the neighborhood radius. Minimum number of points contained within a 1-cell distance. The algorithm iterates through all failure points, grouping those with adjacent geometric locations (e.g., adjacent voltage or similar load types) into the same cluster. For example, if... and Since both are failure points, and P8 and P7 are adjacent in the voltmeter, the algorithm will determine that they belong to the same fault domain. Through this process, scattered failure points are merged into several independent failure clusters, denoted as... Next, for each identified... Geometric feature calculations are performed, focusing on extracting the geometric centroid and distribution span, and classifying them accordingly: 1. Voltage-sensitive feature identification: Calculate the coverage of clusters on the X-axis (voltage axis). If a cluster contains multiple consecutive low-voltage states such as {P8, P7, P6, P5} and covers multiple loads on the Y-axis, it indicates that the fault is strongly correlated with a specific voltage range and is not sensitive to load type. The engine calculates its centroid location; if the centroid is located in the region V < 0.75V, the cluster is labeled as low-voltage sensitive. 2. Transient response insufficiency feature identification: Calculate the distribution of clusters on the Y-axis (load axis). If a cluster is mainly concentrated in... (Sudden oscillation pattern) and similar transient load regions, while The (steady-state saturation mode) region behaves normally and spans multiple frequency points on the X-axis. This indicates that the failure was triggered by drastic load changes, rather than a static voltage issue. The engine labels this cluster as having insufficient transient response. Finally, this step outputs the failure mode feature cluster. This is a list of objects containing high-level semantics. For example, an element in the list might be described as: Cluster_A: Type=Low Voltage Sensitive, Range=[0.65V-0.75V], Coverage Load=[ALL], Severity=High.

[0060] Phase 3: Step 63, Physical Boundary Reverse Deduction and Parameter Locking. This is the most intelligent part of the entire analysis process, essentially mapping the extracted geometric features to the underlying circuit parameters. To achieve this mapping, the analysis engine has a built-in core knowledge base, the Physical Fault Dictionary. The Physical Fault Dictionary is an expert system rule base built on Signal Integrity (SI) and Power Integrity (PI) theories. The dictionary's architecture includes the mapping relationship between phenomenon features (Key) and physical root causes (Value), and its data sources include chip manufacturer datasheets, PCIe physical layer protocol specifications, and debugging experience accumulated by senior hardware engineers. During implementation, the analysis engine traverses each feature cluster output in Step 62, using its feature parameters as query keys to match and deduce in the Physical Fault Dictionary. The following are two typical examples of deduction logic: Example 1: Deduction in the low voltage range. When the input feature cluster is low voltage sensitive and covers a voltage range V < 0.7V, the engine queries the dictionary. The dictionary rules state that at low core voltages, the transconductance of the driving transistor at the AI ​​chip's transmitter (Tx) decreases, leading to a reduced swing in the output signal. If the receiver (Rx) of the accompanying device is improperly configured, it may be unable to amplify such a weak signal. The deduction concludes that the continuous-time linear equalizer (CTLE) at the Rx end of the accompanying device has insufficient DC gain in the low-frequency band, or its decision feedback equalizer (DFE)'s Tap1 coefficient is not adapted to the low swing. Parameter locking: It is recommended to adjust the physical layer registers of the accompanying device, increasing Rx_CTLE_Gain or decreasing Rx_Sensitivity_Threshold. Example 2: Deduction of high-frequency switching and transient load, when the input feature cluster is of the transient response insufficiency type and is located in the high-frequency switching range (e.g., When this occurs, the dictionary rules indicate that such faults typically originate from signal crosstalk or power supply noise. At high frequencies, signal edges are extremely steep; if the pre-emphasis at the transmitting end is too strong, severe overshoot can occur, leading to near-end crosstalk. The deduction concludes that the Pre-shoot or De-emphasis settings in the Finite Impulse Response (FIR) filter coefficients at the Tx end of the supporting device are too high, exceeding the compensation requirements for link loss. Parameter locking: It is recommended to adjust the Tx_FIR_Coefficients of the AI ​​chip or supporting device, specifically by reducing the difference between the Cursor and Pre-cursor. Based on these deductions, the incompatible physical parameter boundary set... Formal definitions are then performed. This set describes the logical constraints that the physical parameters must satisfy in order for the system to regain stability. The final boundary model description formula is constructed as follows:

[0061] Formula meaning explanation: For each failed cluster If specific characteristic conditions are met (If the voltage is below 0.7V), then derive the corresponding physical parameters. (e.g., CTLE gain) must meet specific constraints. (e.g., >6dB). This formula transforms vague fault phenomena into precise mathematical inequalities. Ultimately, the above physical conclusions are packaged into a highly readable failure boundary analysis data report. This report is no longer just a bunch of cold, hard data; it directly tells R&D personnel that when the AI ​​chip voltage is below 0.7V, the Rx CTLE gain of the matching switch needs to be increased by at least two levels, or when performing a burst write operation, the AI ​​chip's power supply ripple needs to be controlled within 30mV. This data provides concrete targets for automated parameter optimization or manual hardware debugging.

[0062] In summary, the compatibility testing method for AI chip supporting devices based on the embodiments of this application is explained, aiming to solve the link failure problem between AI chip and supporting devices during DVFS transition transients. First, the original hardware scan information is obtained using a hardware abstraction layer, and a device capability mapping map is constructed, thereby achieving standardized quantification of heterogeneous hardware physical specifications. Addressing the bottlenecks of static configuration and transient response lag in existing technologies, a measurement vector set containing frequency gradients is generated, and the state switching of the AI ​​chip is forcibly executed during pressure injection, ensuring precise synchronization of the AI ​​chip power state and the physical layer telemetry data of the supporting devices in the time domain. Subsequently, by calculating the electrical quality change stability index, the complex physical layer signal drift is transformed into a measurable stability scoring matrix. This process establishes a dynamic mapping relationship between power fluctuations and bit error rate and signal integrity parameters, compensating for the lack of a linkage mechanism in traditional black-box testing. Finally, failure boundary analysis is used to pinpoint the critical region of parameter mismatch, thereby providing accurate compatibility data support for the stable operation of high-performance AI systems under dynamic loads.

[0063] Figure 4 This is a block diagram of a compatibility testing system for artificial intelligence chip accessories according to an embodiment of this application. Figure 4As shown, the AI ​​chip supporting device compatibility testing system 100 according to an embodiment of this application includes: a raw hardware scan information acquisition module 110, used to acquire raw hardware scan information; a device capability mapping map construction module 120, used to construct a device capability mapping map based on the raw hardware scan information; a measurement vector set generation module 130, used to generate a measurement vector set based on the device capability mapping map; a telemetry data generation module 140, used to perform synchronous state switching and pressure injection on the measurement vector set to obtain a raw telemetry data stream; a stability scoring module 150, used to calculate the electrical quality change stability index on the raw telemetry data stream to obtain a stability scoring matrix; and a compatibility failure boundary analysis module 160, used to perform compatibility failure boundary analysis on the stability scoring matrix to obtain failure boundary analysis data.

[0064] Here, those skilled in the art will understand that the specific operations of each step in the above-mentioned AI chip and supporting device compatibility testing system have been referenced above. Figures 1 to 3 The description of the compatibility testing method for AI chip components is detailed here, and therefore, its repeated description will be omitted.

Claims

1. An artificial intelligence chip package device compatible test method, characterized in that, include: Obtain raw hardware scan information; Based on the original hardware scan information, construct a device capability mapping map; Generate a set of measurement vectors based on the device capability mapping map; Perform synchronous state switching and pressure injection on the measurement vector set to obtain the raw telemetry data stream; The process of calculating the electrical quality change stability index of the original telemetry data stream to obtain a stability score matrix includes: multi-dimensional time-series data slicing and alignment of the original telemetry data stream to obtain aligned vector data segments; extraction and differential calculation of key electrical feature parameters of the aligned vector data segments to obtain a vector feature parameter set; and weighted calculation of the stability index and matrix generation of the vector feature parameter set to obtain a stability score matrix, including: weighted calculation of the stability index of the vector feature parameter set using the following formula: in, The electrical quality change stability index corresponds to the k-th test vector. For protocol layer error robustness weight coefficients, For physical layer signal quality weighting coefficients, This is the power integrity penalty factor. This represents the cumulative total number of link-layer errors captured by the PCIE Advanced Error Reporting mechanism within the execution window of the k-th test vector. This refers to the normalized eye diagram vertical opening height margin measured by the deserializer at the receiver of the supporting device during the execution of the k-th test vector. The maximum absolute value of the rate of change of power supply noise voltage over time within the test window is defined as the value of the power supply noise voltage. Compatibility failure boundary analysis is performed on the stability score matrix to obtain failure boundary analysis data. 2.The artificial intelligence chip system-on-chip (SoC) compatibility test method of claim 1, wherein, Based on the original hardware scan information, a device capability mapping map is constructed, including: The raw hardware scan information is cleaned and instantiated to obtain a list of basic hardware nodes. The electrical parameter association enhancement based on the specification library is performed on each basic hardware node in the basic hardware node list to obtain the enhanced hardware attribute list; A device capability mapping graph is constructed based on the enhanced hardware attribute list. 3.The artificial intelligence chip package device compatible test method of claim 1, wherein, Based on the device capability mapping map, a measurement vector set is generated, including: DVFS state extraction and dwell time calculation are performed on the device capability mapping map to obtain a time-seriesd state sequence object; Instantiate the time-series state sequence object with the corresponding device-differentiated load mode to obtain the complete set of state loads to be combined; A set of measurement vectors is generated based on the complete set of load states to be combined. 4.The artificial intelligence chip system-on-chip (SoC) compatibility test method according to claim 3, wherein, Based on the complete set of load states to be combined, a set of measurement vectors is generated, including: Perform column Cartesian product operation on the state of each AI chip and the load of its associated devices in the complete set of combined state loads to obtain the original orthogonal pairing list; The original orthogonal pairing list is subjected to temporal parameter fusion and atomic vector encapsulation to obtain an unordered vector list; The unordered list of vectors is sorted by frequency gradient to obtain the measurement vector set. 5.The artificial intelligence chip package device compatible test method of claim 1, wherein, Compatibility failure boundary analysis was performed on the stability score matrix to obtain failure boundary analysis data, including: Based on empirical thresholds, threshold segmentation and anomaly coordinate extraction are performed on the stability scoring matrix to obtain the failure vector coordinate set. Failure mode feature clusters are obtained by clustering failure regions and calculating distribution characteristics of the failure vector coordinate set. Physical boundary inverse deduction and parameter locking are performed on the failure mode feature clusters to obtain failure boundary analysis data.

6. An artificial intelligence chip system-on-chip device compatibility test system, characterized in that, include: The raw hardware scan information acquisition module is used to acquire raw hardware scan information; The device capability mapping construction module is used to construct a device capability mapping based on the original hardware scan information. The measurement vector set generation module is used to generate measurement vector sets based on the device capability mapping map; The telemetry data generation module is used to perform synchronous state switching and pressure injection on the measurement vector set to obtain the raw telemetry data stream; The stability scoring module is used to calculate the electrical quality change stability index of the original telemetry data stream to obtain a stability scoring matrix. This includes: slicing and aligning the original telemetry data stream into multi-dimensional time-series data segments to obtain aligned vector data segments; extracting and differentiating key electrical feature parameters from the aligned vector data segments to obtain a set of vector feature parameters; and performing stability index weighted calculation and matrix generation on the vector feature parameter set to obtain the stability scoring matrix. This includes: performing stability index weighted calculation on the vector feature parameter set using the following formula: in, The electrical quality change stability index corresponds to the k-th test vector. For protocol layer error robustness weight coefficients, For physical layer signal quality weighting coefficients, This is the power integrity penalty factor. This represents the cumulative total number of link-layer errors captured by the PCIE Advanced Error Reporting mechanism within the execution window of the k-th test vector. This refers to the normalized eye diagram vertical opening height margin measured by the deserializer at the receiver of the supporting device during the execution of the k-th test vector. This represents the maximum absolute value of the rate of change of the power supply noise voltage over time within the test window. The compatibility failure boundary analysis module is used to perform compatibility failure boundary analysis on the stability score matrix to obtain failure boundary analysis data.

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