Multi-core parallel computing method and system for layered butterfly transformation
The multi-core parallel computing method using hierarchical butterfly transformation solves the problems of high computational complexity and insufficient memory in traditional algorithms for large-scale data processing, achieving efficient data processing, improving computational efficiency and parallelism, and is suitable for multi-core platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-03
AI Technical Summary
Traditional FFT, NTT, and ANF algorithms suffer from high computational complexity, insufficient memory on a single processor, and difficulty in fully utilizing the advantages of multi-core platforms when processing large-scale data, resulting in low computational efficiency.
A multi-core parallel computing method using hierarchical butterfly transformation is adopted. By dividing the data matrix into rows and distributing it to a multi-core processor cluster, and utilizing a row-first distributed storage architecture, a two-stage butterfly transformation and data matrix transposition are performed to achieve the separation and optimization of computation and communication.
It significantly reduces cross-core communication overhead, improves computational parallelism and efficiency, can process large-scale data, fully utilizes the hardware advantages of multi-core and many-core processors, and is suitable for cryptography, signal processing, and scientific computing.
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Figure CN121786468A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital signal processing technology, and in particular to a multi-core parallel computing method and system for hierarchical butterfly transform. Background Technology
[0002] With the development of digital signal processing technology, algorithms such as Fast Fourier Transform (FFT), Number Theory Transform (NTT), or Boolean Algebraic Normal Form (ANF) transformation have been widely used in image processing, communication systems, cryptography, and data analysis. However, as the scale of problems continues to expand, traditional FFT, NTT, and ANF algorithms suffer from significant computational complexity issues when processing data transformations, making it difficult to meet real-time processing requirements.
[0003] To address the computational speed issues of FFT, NTT, and ANF transforms, researchers have proposed various optimization strategies. Among these, iterative computation using a hierarchical butterfly structure is an important and commonly used technique that can reduce the computational complexity of these three transforms from O(T²) to O(Tlog₂T), significantly improving computational efficiency. However, existing transform computation methods still have some limitations in practical applications, especially when processing large-scale data. Often, it is necessary to wait for the results of the previous stage to be written back before proceeding to the next stage, and the problem of insufficient memory on a single processor remains unresolved. Furthermore, on multi-core and many-core processor platforms, traditional serial algorithms cannot fully leverage the advantages of multi-core platforms. Therefore, developing an efficient transform computation method that can adapt to large-scale data processing and utilize the parallel capabilities of multi-core hardware is of great significance for improving the overall performance of digital signal processing. Summary of the Invention
[0004] The purpose of this invention is to solve at least one technical problem in the background art and to provide a multi-core parallel computing method and system with hierarchical butterfly transformation.
[0005] To achieve the above objectives, this invention provides a multi-core parallel computing method for hierarchical butterfly transformation, comprising: S1. Determine the transformation type: Determine whether the transformation type is Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Form Transform; S2. Data matrix rearrangement: The input data is segmented and stored in the memory area of each processor; S3. First-stage butterfly transformation: Each processor performs the first-stage butterfly transformation on the locally stored data; S4. Data Matrix Transpose: Data transmission and interaction between processors are performed in a matrix transpose manner; S5. Second-stage butterfly transformation: Each processor performs a second-stage butterfly transformation on the local storage data; S6. Post-processing of results: Restore the index corresponding to the result data, and write the output data into the corresponding array position according to the index; S7. Run steps S1 to S6 sequentially to complete the Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normalization.
[0006] According to one aspect of the invention, determining the transformation type includes: When the transformation type is Fast Fourier Transform, the data computation type is complex number operation and the data transmission type is complex number. When the transformation type is number theory transformation, the data computation type is modular multiplication and modular addition, and the data transmission type is integer over the domain; When the transformation type is a Boolean function algebraic normal form transformation, the data calculation type is a Boolean XOR operation, and the data transmission type is binary data.
[0007] According to one aspect of the invention, the data matrix rearrangement includes: Number of input data Number of processors The processors are numbered 0, 1, ... Number of data items stored per processor ,in, ; Input data Evenly distributed Each paragraph contains One data point; Arrange 0 to... in order The segment data are stored in locations numbered 0 to On the processor; use Indicates the first On the processor Data, using Indicates the first Stored on each processor One data point, , .
[0008] According to one aspect of the invention, the first stage butterfly transformation includes Layer transformation, including: Each processor processes the locally stored data. Perform a butterfly transformation at level 0, with a data span of... ; Each processor performs a Level 1 butterfly transform on the local result data from the previous step, with a data span of [missing value]. ; And so on, until... Each processor performs the second step on the local result data from the previous step. Layered butterfly transformation, data span is ; use This represents the final total result data. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , .
[0009] According to one aspect of the present invention, the data transmission and interaction between the processors in a matrix transpose-like manner is as follows: ; in, This represents the total result data obtained by transposing the data matrix. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , , , express Round down to the nearest integer.
[0010] According to one aspect of the invention, the second-stage butterfly transformation includes Layer transformation, including: Each processor processes the locally stored data. Evenly divided into Blocks, each block contains There are 1 data points, and then a level 0 butterfly transform is performed on each block, with a data span of 1. ; Each processor evenly distributes the local result data from the previous step. Perform a level 1 butterfly transformation on the block, with a data span of... ; And so on, until... Each processor evenly distributes the local result data from the previous step. Do the first block Layered butterfly transformation, data span is ; use This represents the final total result data. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , .
[0011] According to one aspect of the invention, the result post-processing includes: The index calculation method involves assigning three numbers to each result data: n bits for the processor number, s bits for the data block number within the processor, and n bits for the relative position number within the data block. These three number values are expanded and concatenated in binary bits according to the order of relative position number within the block, processor number, and block number. The concatenated binary bit string is t bits, which is then converted back to a decimal index value.
[0012] According to one aspect of the present invention, the first-stage butterfly transformation and the second-stage butterfly transformation are multimodal butterfly operations; Based on the determined transformation type as Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Form Transform, dynamically switch between complex multiplication and addition operations, modular multiplication and addition operations over a field, or Boolean XOR operations, including: When transforming to Fast Fourier Transform or Number Theory Transform, the specific calculation process of the butterfly transform is as follows: ; in, The rotation factor is determined based on the number of layers and the transformed data. It varies depending on the location; When transforming to a Boolean function algebraic normal form transformation, the specific calculation process of the butterfly transform is as follows: ; Each layer of the butterfly transformation in the first-stage and second-stage butterfly transformations involves internal memory operations. One data point, M data points based on span Divided into M / 2 pairs, This refers to the layer number of each butterfly transformation. The specific calculations for each pair of data undergoing a butterfly transformation are as follows: This indicates the first data item in each pair of data. This indicates the data that appears later in the sort order. and This indicates that the transformed data, in its sorting position among the M data points, is respectively related to... and The same.
[0013] To achieve the above objectives, the present invention also provides a multi-core parallel computing system with hierarchical butterfly transformation, comprising: The transformation type determination module determines whether the transformation type is Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Transform. The data matrix rearrangement module divides the input data into segments and stores them in the storage area of each processor; In the first stage butterfly transformation module, each processor performs the first stage butterfly transformation on the locally stored data. The data matrix transpose module enables data transmission and interaction between processors in a matrix transpose manner. In the second stage butterfly transformation module, each processor performs a second-stage butterfly transformation on the locally stored data. The result post-processing module restores the index corresponding to the result data and writes the output data into the corresponding array position according to the index; The transformation calculation completion module runs sequentially through the transformation type determination module to the result post-processing module, completing the Fast Fourier Transform, number theory transformation, or Boolean function algebraic normal form conversion.
[0014] To achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the multi-core parallel computing method of the hierarchical butterfly transformation as described above.
[0015] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the multi-core parallel computing method of hierarchical butterfly transformation as described above.
[0016] According to the present invention, a parallel butterfly transformation architecture based on row-first distributed storage is proposed. By dividing the data matrix into rows and distributing it to a multi-core processor cluster, a parallel computing mode with locality optimization is achieved, which significantly reduces cross-core communication overhead. This invention designs a two-stage heterogeneous computing process of "row processing - data matrix transpose - row processing (corresponding to multiple columns of the original matrix)". By using the intermediate data matrix transpose operation, the transformation between processors is decoupled into parallel transformation operations between processors and within the processor, thereby realizing the separation of computation and communication and breaking through the technical bottleneck of excessive synchronization barriers in the traditional butterfly algorithm. This invention constructs a generalized hierarchical butterfly computing architecture, creatively unifies the parallel implementation paths of Fast Fourier Transform (FFT), Number Theory Transform (NTT), and Boolean Algebra Normal Form Transform (ANF), and achieves for the first time efficient collaborative optimization of the three types of algorithms under a distributed storage architecture; This invention fully utilizes the hardware advantages of multi-core and many-core processors, enabling it to directly process large-scale butterfly transformations and drive the upgrading of core algorithms in fields such as cryptography, signal processing, and scientific computing. This invention solves the problem of insufficient memory in a single processor by using block storage, and reduces communication overhead and control complexity by combining a two-stage butterfly transformation with data matrix transpose. It achieves overlapping optimization of computation and communication, and improves the computational parallelism and efficiency of trillion-point Fast Fourier Transform (FFT), Number Theory Transform (NTT), and Boolean function algebraic normal form (ANF) transformation. It is applicable to cryptography, signal processing, and scientific computing. Attached Figure Description
[0017] Figure 1 A flowchart illustrating a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention; Figure 2 This schematic diagram illustrates the principle of a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention. Figure 3 This diagram illustrates the data matrix transpose flowchart in a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention. Figure 4 This schematic diagram illustrates an FFT / NTT butterfly computation diagram according to an embodiment of the present invention. Figure 5 A schematic diagram illustrating an ANF butterfly calculation according to an embodiment of the present invention; Figure 6 This diagram schematically illustrates a data matrix arrangement according to an embodiment of the present invention. Figure 7 This schematic diagram illustrates the first-stage butterfly transformation according to an embodiment of the present invention. Figure 8 This schematic diagram illustrates a data class matrix transpose according to an embodiment of the present invention. Figure 9 The diagram schematically illustrates the second-stage butterfly transformation according to an embodiment of the present invention. Detailed Implementation
[0018] The invention will now be discussed with reference to exemplary embodiments. It should be understood that the described embodiments are merely intended to enable those skilled in the art to better understand and thus implement the invention, and are not intended to imply any limitation on the scope of the invention.
[0019] As used herein, the term "comprising" and its variations are to be interpreted as open-ended terms meaning "including but not limited to". The term "based on" is to be interpreted as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be interpreted as "at least one embodiment".
[0020] Figure 1 A flowchart illustrating a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention; Figure 2 This schematic diagram illustrates the principle of a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention. Figure 3 This diagram illustrates the data matrix transpose flowchart in a multi-core parallel computing method for hierarchical butterfly transformation according to an embodiment of the present invention. Figures 1-3 As shown, in this embodiment, the multi-core parallel computing method for hierarchical butterfly transformation includes: S1. Determine the transformation type: Determine the transformation type as one of FFT, NTT, or ANF. The transformation type determines the data type and calculation type in steps S2 to S6. When the transformation type is FFT, the data calculation type is complex number operation and the data transmission type is complex number. When the transformation type is NTT, the data calculation type is modular multiplication and modular addition and the data transmission type is integer over the domain. When the transformation type is ANF, the data calculation type is Boolean XOR operation and the data transmission type is binary data. When transforming to FFT / NTT, such as Figure 4 As shown, the specific calculation process of the butterfly transformation is as follows: (This is the rotation factor, and its value varies depending on the steps involved). ; When converting to ANF, such as Figure 5 As shown, the specific calculation process of the butterfly transformation is as follows: ; Each layer of the butterfly transformation in the first-stage and second-stage butterfly transformations involves internal memory operations. One data point, M data points based on span Divided into M / 2 pairs, This refers to the layer number of each butterfly transformation. The specific calculations for each pair of data undergoing a butterfly transformation are as follows: This indicates the first data item in each pair of data. This indicates the data that appears later in the sort order. and This indicates that the transformed data, in its sorting position among the M data points, is respectively related to... and The same.
[0021] S2. Data matrix rearrangement: such as Figure 6 As shown, the input data is segmented and stored in the memory area of each processor. The specific process is as follows: S21: Number of input data Number of processors The processors are numbered 0, 1, ... Number of data items stored per processor ,Require ; S22: Input data Evenly distributed Paragraphs, each containing One data point; S23: Sequentially fill in 0 to... The segment data are stored in locations numbered 0 to On the processor; use Indicates the first On the processor Data, using Indicates the first Stored on each processor One data point, , ; S3. First-stage butterfly transformation: as follows Figure 7 As shown, each processor performs a first-stage butterfly transformation on the locally stored data, which includes... Layer transformation, the specific process is as follows: S31: Each processor processes the locally stored data. Perform a butterfly transformation at level 0, with a data span of... ; S32: Each processor performs a first-level butterfly transformation on the local result data from step S31 above, with a data span of... ; ... S3m: Each processor performs the first step on the local result data of step S3(m-1) above. Layered butterfly transformation, data span is ; use This represents the total result data obtained from step S3m. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , ; S4. Transpose of a data matrix: such as Figure 8 As shown, data transmission and interaction between processors are performed in a manner similar to matrix transpose: ; in, This represents the total result data obtained from this step. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , , ; S5. Second stage butterfly transformation: as follows Figure 9 As shown, each processor performs a second-stage butterfly transformation on the locally stored data, which includes... Layer transformation, the specific process is as follows: S51: Each processor processes the locally stored data. Evenly divided into Blocks, each block contains There are 1 data points, and then a level 0 butterfly transform is performed on each block, with a data span of 1. ; S52: Each processor evenly distributes the local result data from step S51 above. Perform a level 1 butterfly transformation on the block, with a data span of... ; ... S5n: Each processor evenly distributes the local result data from step S5(n-1) above. Do the first block Layered butterfly transformation, data span is ; use This represents the total result data obtained from step S5n. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , ; S6. Post-processing of results: Restore the index corresponding to the result data, and write the output data to the corresponding array position according to the index. The index calculation method is as follows: each result data corresponds to 3 numbers, namely the processor number (n bits), the data block number in the processor (s bits), and the relative position number in the data block (n bits). Expand and concatenate the 3 number values in binary bits according to the order of relative position number within the block, processor number, and block number. The concatenated binary bit string is t bits, which is then restored to a decimal index value.
[0022] S7. By sequentially running steps S1 to S6, a large-scale FFT / NTT / ANF transformation is completed.
[0023] According to the above-described scheme of the present invention, the present invention proposes a parallel butterfly transformation architecture based on row-first distributed storage. By dividing the data matrix into rows and distributing it to a multi-core processor cluster, a parallel computing mode with locality optimization is achieved, which significantly reduces cross-core communication overhead. This invention designs a two-stage heterogeneous computing process of "row processing - data matrix transpose - row processing (corresponding to multiple columns of the original matrix)". By using the intermediate data matrix transpose operation, the transformation between processors is decoupled into parallel transformation operations between processors and within the processor, thereby realizing the separation of computation and communication and breaking through the technical bottleneck of excessive synchronization barriers in the traditional butterfly algorithm. This invention constructs a generalized hierarchical butterfly computing architecture, creatively unifies the parallel implementation paths of Fast Fourier Transform (FFT), Number Theory Transform (NTT), and Boolean Algebra Normal Form Transform (ANF), and achieves for the first time efficient collaborative optimization of the three types of algorithms under a distributed storage architecture; This invention fully utilizes the hardware advantages of multi-core and many-core processors, enabling it to directly handle large-scale butterfly transformations and drive the upgrading of core algorithms in fields such as cryptography, signal processing, and scientific computing.
[0024] Furthermore, to achieve the above objectives, the present invention also provides a multi-core parallel computing system with hierarchical butterfly transformation, comprising: The transformation type determination module determines whether the transformation type is Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Transform. The data matrix rearrangement module divides the input data into segments and stores them in the storage area of each processor; In the first stage butterfly transformation module, each processor performs the first stage butterfly transformation on the locally stored data. The data matrix transpose module enables data transmission and interaction between processors in a matrix transpose manner. In the second stage butterfly transformation module, each processor performs a second-stage butterfly transformation on the locally stored data. The result post-processing module restores the index corresponding to the result data and writes the output data into the corresponding array position according to the index; The transformation calculation completion module runs sequentially through the transformation type determination module to the result post-processing module, completing the Fast Fourier Transform, number theory transformation, or Boolean function algebraic normal form conversion.
[0025] The multi-core parallel computing system of the hierarchical butterfly transformation according to the present invention can realize the multi-core parallel computing method of the hierarchical butterfly transformation. The specific process steps are as described above and will not be repeated here.
[0026] Furthermore, to achieve the above objectives, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the multi-core parallel computing method of the hierarchical butterfly transformation as described above.
[0027] Furthermore, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the multi-core parallel computing method of the hierarchical butterfly transformation as described above.
[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely one preferred embodiment of the invention and are only used to explain the invention. They do not limit the scope of protection of the invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0029] Example 1 This embodiment provides a multi-core parallel computing method for hierarchical butterfly transformation, including the following steps: S1. Determine the transformation type: In this embodiment, the transformation type is determined to be NTT number theory transformation among FFT, NTT, and ANF. The NTT transformation determines that the data calculation type in the subsequent steps is modular multiplication and modular addition, and the data transmission type is integer over the domain.
[0030] S2. The specific process of data matrix rearrangement is as follows: S21. Number of input data Number of processors The processors are numbered 0, 1, and 2. Number of data items stored per processor ; S22. Input data The data is evenly divided into 4 segments, each containing 8 data points; S23. Store the data segments 0, 1, 2, and 3 in sequence on processors numbered 0, 1, 2, and 3 respectively. Indicates the first On the processor Data, using Indicates the first Eight data points stored on each processor. , .
[0031] S3. The first stage of the butterfly transformation includes three transformation layers, and the specific process is as follows: The S31's four processors each handle locally stored data. ( Perform a butterfly transformation at level 0, with a data span of... The calculation formula is: ; ; S32. The four processors process the local result data from step S31 respectively. ( Perform the first-level butterfly transformation, with a data span of... The calculation formula is: ; ; S33. The four processors process the local result data from step S32 respectively. ( Perform a second-level butterfly transformation with a data span of [value missing]. The calculation formula is: ; ; Rotation factor required for butterfly transformation Each processor calculates and generates the data as needed. The final data is obtained after step 3. , Indicates the first On the processor One data point, Indicates the first Eight data items are stored on each processor, of which , .
[0032] S4. Data Matrix Transpose: Processors exchange data in a manner similar to matrix transpose, meaning that each row of the resulting matrix d consists of two columns from the original matrix c, as shown below: ; Transformed through data transmission and interaction ; ; The calculation formula is: ; in .
[0033] S5. The second stage of butterfly transformation, the specific process is as follows: The S51's four processors each handle local data. ( Evenly divided into Each block contains 4 data points. From matrix d, this means dividing each row into two blocks, then performing a level 0 butterfly transformation on each block. The data span is... The calculation formula is: ; ; Each of the four S52 processors performs a Level 1 butterfly transform on the local S51 result data, dividing it into two equal blocks with a data span of [missing information]. The calculation formula is: ; ; Rotation factor required for butterfly transformation Each processor calculates and generates the data as needed. The final data is obtained after step 5. , Indicates the first On the processor One data point, Indicates the first Eight data items are stored on each processor, of which , .
[0034] S6. Result output processing: Restore the index corresponding to the result data, and write the output data to the corresponding array position according to the index. Index calculation method, for example... Corresponding to 3 numbers, the processor number is 2, expanded to the width The binary bit is '10', and the data block number in processor 2 is... Expand to width The binary bit is '1', and its relative position in the data block is numbered as follows: Expand to width The binary bits are '01'. The width is obtained by concatenating the three bit strings in the order of their relative positions within the block, processor number, and block number. Given the bit string '01101', its decimal index is 13. The position within the final array. The final result array is: .
[0035] S7. Complete the NTT conversion by running steps 1 to 6 in sequence.
[0036] Those skilled in the art will recognize that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0037] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and equipment can be referred to the corresponding process in the foregoing method implementation, and will not be repeated here.
[0038] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.
[0039] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the objectives of the embodiments of the present invention, depending on actual needs.
[0040] In addition, the functional modules in the embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.
[0041] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the sending / receiving methods of various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.
[0042] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.
[0043] It should be understood that the sequence number of each step in the invention and its embodiments does not absolutely imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
Claims
1. A multi-core parallel computing method for hierarchical butterfly transform, characterized in that, include: S1. Determine the transformation type: Determine whether the transformation type is Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Form Transform; S2. Data matrix rearrangement: The input data is segmented and stored in the memory area of each processor; S3. First-stage butterfly transformation: Each processor performs the first-stage butterfly transformation on the data stored locally; S4. Data Matrix Transpose: Data transmission and interaction between processors are performed in a matrix transpose manner; S5. Second-stage butterfly transformation: Each processor performs a second-stage butterfly transformation on the local storage data; S6. Post-processing of results: Restore the index corresponding to the result data, and write the output data into the corresponding array position according to the index; S7. Run steps S1 to S6 sequentially to complete the Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normalization.
2. The multi-core parallel computing method for hierarchical butterfly transformation according to claim 1, characterized in that, The determination of the transformation type includes: When the transformation type is Fast Fourier Transform, the data computation type is complex number operation and the data transmission type is complex number. When the transformation type is number theory transformation, the data computation type is modular multiplication and modular addition, and the data transmission type is integer over the domain; When the transformation type is a Boolean function algebraic normal form transformation, the data calculation type is a Boolean XOR operation, and the data transmission type is binary data.
3. The multi-core parallel computing method for hierarchical butterfly transform according to claim 1, characterized in that, The data matrix rearrangement includes: Number of input data Number of processors The processors are numbered 0, 1, ... Number of data items stored per processor ,in, ; Input data Evenly distributed Each paragraph contains One data point; Arrange 0 to... in order The segment data are stored in locations numbered 0 to On the processor; use Indicates the first On the processor Data, using Indicates the first Stored on each processor One data point, , .
4. The multi-core parallel computing method for hierarchical butterfly transform according to claim 1, characterized in that, The first stage butterfly transformation includes Layer transformation, including: Each processor processes the locally stored data. Perform a butterfly transformation at level 0, with a data span of... ; Each processor performs a Level 1 butterfly transform on the local result data from the previous step, with a data span of [missing value]. ; And so on, until... Each processor performs the second step on the local result data from the previous step. Layered butterfly transformation, data span is ; use This represents the final total result data. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , .
5. The multi-core parallel computing method for hierarchical butterfly transform according to claim 1, characterized in that, The data transmission and interaction between processors, performed in a matrix transpose-like manner, is as follows: ； in, This represents the total result data obtained by transposing the data matrix. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , , , express Round down to the nearest integer.
6. The multi-core parallel computing method for hierarchical butterfly transformation according to claim 1, characterized in that, The second stage butterfly transformation includes Layer transformation, including: Each processor processes the locally stored data. Evenly divided into Blocks, each block contains There are 1 data points, and then a level 0 butterfly transform is performed on each block, with a data span of 1. ; Each processor evenly distributes the local result data from the previous step. Perform a level 1 butterfly transformation on the block, with a data span of... ; And so on, until... Each processor evenly distributes the local result data from the previous step. Do the first block Layered butterfly transformation, data span is ; use This represents the final total result data. Indicates the first On the processor One data point, Indicates the first Stored on each processor Data, of which , .
7. The multi-core parallel computing method for hierarchical butterfly transformation according to claim 1, characterized in that, The post-processing of the results includes: The index calculation method involves assigning three numbers to each result data: n bits for the processor number, s bits for the data block number within the processor, and n bits for the relative position number within the data block. These three number values are expanded and concatenated in binary bits according to the order of relative position number within the block, processor number, and block number. The concatenated binary bit string is t bits, which is then converted back to a decimal index value.
8. The multi-core parallel computing method for hierarchical butterfly transformation according to claim 1, characterized in that, The first-stage butterfly transformation and the second-stage butterfly transformation are multimodal butterfly operations; Based on the determined transformation type as Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Form Transform, dynamically switch between complex multiplication and addition operations, modular multiplication and addition operations over a field, or Boolean XOR operations, including: When transforming to Fast Fourier Transform or Number Theory Transform, the specific calculation process of the butterfly transform is as follows: ； in, The rotation factor is determined based on the number of layers and the transformed data. It varies depending on the location; When transforming to a Boolean function algebraic normal form transformation, the specific calculation process of the butterfly transform is as follows: ； Each layer of the butterfly transformation in the first-stage and second-stage butterfly transformations involves internal memory operations. One data point, Data based on span Divided into / 2 pairs, This refers to the layer number of each butterfly transformation. The specific calculations for each pair of data undergoing a butterfly transformation are as follows: This indicates the first data item in each pair of data. This indicates the data that appears later in the sort order. and This indicates that the transformed data, in its sorting position among the M data points, is respectively related to... and The same.
9. A multi-core parallel computing system with hierarchical butterfly transformation, characterized in that, include: The transformation type determination module determines whether the transformation type is Fast Fourier Transform, Number Theory Transform, or Boolean Function Algebraic Normal Transform. The data matrix rearrangement module divides the input data into segments and stores them in the storage area of each processor; In the first stage butterfly transformation module, each processor performs the first stage butterfly transformation on the locally stored data. The data matrix transpose module enables data transmission and interaction between processors in a matrix transpose manner. In the second stage butterfly transformation module, each processor performs a second-stage butterfly transformation on the locally stored data. The result post-processing module restores the index corresponding to the result data and writes the output data into the corresponding array position according to the index; The transformation calculation completion module runs sequentially through the transformation type determination module to the result post-processing module, completing the Fast Fourier Transform, number theory transformation, or Boolean function algebraic normal form conversion.
10. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the multi-core parallel computing method of the hierarchical butterfly transformation as described in any one of claims 1-8.
11. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when executed by a processor, the computer program implements the multi-core parallel computing method of the hierarchical butterfly transformation as described in any one of claims 1-8.