Neural network processor and method

CN121787488APending Publication Date: 2026-04-03NXP BV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-25
Publication Date
2026-04-03

AI Technical Summary

Technical Problem

The architecture of existing neural network processing units (NPUs) struggles to strike a balance between scalability, utilization, and programming efficiency, resulting in limited computational performance.

Method used

It employs an architecture that combines multiple processing elements (PEs) with a switching network, processes neural network layers through lockstep cycles, and exclusively stores input data, weights, and results in each memory region. It utilizes a data transporter for efficient data transfer, avoiding cache copying.

Benefits of technology

It achieves high-performance neural network processing, supports flexible expansion and efficient utilization, reduces programming overhead, and ensures that computational efficiency is not affected.

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Abstract

A neural network processor processes layers of a neural network with a plurality of processing elements (PEs) configured to operate in a lockstep form, and has the same number of memory regions. During a lockstep cycle, within each memory region, a first set of region memories is configured to store neural network layer input data, a second set of region memories is configured to store neural network layer weights, and a third set of region memories is configured to store neural network layer results. The processing element is capable of exclusively accessing (i) the first set of region memories, (ii) the second set of region memories, and (iii) the third set of region memories. The plurality of sets of region memories may be in the same or different regions during a lockstep cycle. The data carrier is capable of exclusively accessing a fourth set of region memories in each of the memory regions.
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