A texture mapping system and mapping method based on tensor core acceleration
By introducing Tensor Cores to accelerate the texture mapping system in the GPU, the graphics computing core and the Tensor Core work together to solve the problem of low texture mapping efficiency, achieving efficient texture filtering and rendering effects, and adapting to complex and high-resolution graphics displays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN LINGJIU MICROELECTRONICS CO LTD
- Filing Date
- 2026-03-09
- Publication Date
- 2026-07-21
Smart Images
Figure CN121788693B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of texture mapping technology, and more specifically, to a texture mapping system and method based on tensor core acceleration. Background Technology
[0002] Texture mapping maps a 2D texture image onto the surface of a 3D model. Using texture coordinates at the model's vertices as a bridge, the texture image is sampled and filtered, ultimately applying the texture image to complex 3D geometry, making the model appear realistic and detailed. It can also be combined with techniques such as lighting calculations and alpha blending to create even more realistic graphics. However, the texture sampling and filtering processes in texture mapping are computationally intensive, and relying on traditional ALUs (Arithmetic Logic Units) is relatively inefficient. Especially for complex geometries at high resolutions and super-resolutions, texture mapping struggles to meet the performance requirements of real-time GPU rendering. Therefore, the latest GPU designs introduce tensor cores to overcome the bottlenecks of traditional texture processing methods and adapt to increasingly complex and realistic graphics display needs.
[0003] When rendering shading requires texture sampling, a texture request containing texture coordinates is issued. The Texture Sampling Unit calculates the memory address based on the texture UV coordinates and reads the specified texel. After texture filtering (such as bilinear filtering or trilinear filtering), the calculated color value is returned. Although the GPU has a large number of processor cores processing in parallel, this process is fragment-by-fragment, each request is independent, and the number of texture sampling units is limited. In complex filtering operations (such as anisotropic filtering or custom convolution kernels) and rendering in high-resolution / super-resolution scenes, texture mapping can easily become a performance bottleneck. How to utilize the extremely high throughput of tensor cores for texture mapping acceleration is a core issue considered in the design of the latest GPU architecture. Summary of the Invention
[0004] This invention addresses the technical problems existing in the prior art by providing a texture mapping system and method based on tensor core acceleration, overcoming the shortcomings of low efficiency in existing texture mapping.
[0005] According to a first aspect of the present invention, a texture mapping system based on tensor core acceleration is provided, including an external bus interface, a command processor, a task allocator and a graphics rendering engine array, wherein the graphics rendering engine array includes multiple fully mirrored graphics rendering engines.
[0006] The command processor is used to read the command stream and vertex index generated by the upper-layer software stack through an external bus interface. The command stream contains state configuration information and graphics processing command information.
[0007] The task allocator is used to organize and package the command stream and vertex index into tasks, and allocate the tasks to the corresponding graphics rendering engines for execution.
[0008] Each of the graphics rendering engines includes programmable components and fixed-function components. The programmable components include a graphics computing core (Render Core) and a coprocessor. The coprocessor includes a tensor core. The graphics computing core (Render Core) is used to perform various graphics shading tasks according to the task. The tensor core (Tensor Core) is used to perform matrix operations in texture mapping.
[0009] Based on the above technical solution, the present invention can be further improved as follows.
[0010] Optionally, the graphics computing core (Render Core) includes a controller, memory access, and an ALU computing array, wherein the ALU computing array includes multiple ALU computing cores;
[0011] The controller is configured to generate multiple coloring tasks based on the tasks issued by the task allocator, and to assign each coloring task to the ALU computing array to complete the corresponding calculations.
[0012] Each of the ALU computing cores is used to perform corresponding calculations according to the coloring task, including integer calculations, floating-point calculations, and transcendental function calculations;
[0013] When the Render Core needs to perform texture mapping during fragment shading, it sends texture configuration parameters and texture operation requests to the coprocessor, which then performs texture sampling and texture interpolation filtering. The Tensor Core performs the texture interpolation filtering.
[0014] Optionally, the coprocessor further includes a texture unit; the texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and a read request;
[0015] The texture unit is used to calculate the texture address based on each texture UV coordinate and texture mipmap detail level information, and based on the texture address, sample on each feature texture image through texture data cache to obtain multiple sampled feature values, organize the multiple sampled feature values into a texture feature vector, organize the multiple texture feature vectors into a texture feature vector matrix, and store the texture feature vector matrix in on-chip storage.
[0016] The Tensor Core reads the texture feature vector matrix and weight matrix from on-chip storage, performs operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result, and writes the texture interpolation filtering result back to the Render Core to complete the fragment shading.
[0017] Optionally, it also includes a server, on which a neural network is deployed to complete texture image training, wherein:
[0018] The texture image is trained based on a neural network to learn the mapping from a "low-resolution + blurry" texture image to a "high-resolution + sharp" texture feature image. After training, the weight matrix and feature texture image of the neural network are generated and stored so that the texture unit can read each feature texture image through the texture data cache.
[0019] According to a second aspect of the present invention, a texture mapping method based on tensor core acceleration is provided, comprising:
[0020] The command stream and vertex index generated by the upper-layer software stack are read through the external bus interface. The command stream contains state configuration information and graphics processing command information.
[0021] The command stream and vertex index are organized and packaged into tasks, and the tasks are assigned to the corresponding graphics rendering engines for execution. The graphics rendering engines include a graphics computing core (Render Core) and a tensor core (Tensor Core).
[0022] The Render Core performs various graphics shading tasks according to the task, and the Tensor Core is used to perform matrix operations in texture mapping.
[0023] Optionally, the graphics rendering core, which shades various graphics according to the task, further includes:
[0024] When the graphics computing core Render Core needs to perform texture mapping during the shading process, it sends texture configuration parameters and texture operation requests to the coprocessor. The coprocessor then performs texture sampling and texture interpolation filtering, with the Tensor Core performing the texture interpolation filtering.
[0025] Optionally, the texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and read request;
[0026] The texture address is calculated based on the UV coordinates of each texture and the texture mipmap detail level information. Based on the texture address, multiple sampled feature values are obtained by sampling on each feature texture image through the texture data cache. The multiple sampled feature values are organized into a texture feature vector. The multiple texture feature vectors are organized into a texture feature vector matrix, and the texture feature vector matrix is stored in on-chip memory.
[0027] The Tensor Core reads the texture feature vector matrix and weight matrix from on-chip storage, performs operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result, and writes the texture interpolation filtering result back to the Render Core to complete the fragment shading.
[0028] Optional, also includes:
[0029] The neural network is used to train the texture image to learn the mapping from "low resolution + blurry" texture image to "high resolution + sharp" texture feature image. After training, the weight matrix and feature texture image of the neural network are generated and stored so that the texture unit can read each feature texture image through the texture data cache.
[0030] According to a third aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the processor is configured to implement a texture mapping method based on tensor kernel acceleration when executing a computer management program stored in the memory.
[0031] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer management class program is stored, wherein the computer management class program, when executed by a processor, implements the steps of a texture mapping method based on tensor core acceleration.
[0032] This invention provides a texture mapping system and method based on tensor core acceleration. By simultaneously designing a Render Core and a Tensor Core within the graphics rendering engine, the Render Core is primarily responsible for graphics rendering and shading, while the Tensor Core mainly performs matrix operations. This invention leverages the advantages of the Tensor Core in matrix operations to accelerate texture mapping calculations. Attached Figure Description
[0033] Figure 1 This is a diagram illustrating the overall architecture of a GPU after introducing a tensor core in one embodiment of the present invention.
[0034] Figure 2A structural block diagram of a texture mapping system based on tensor core acceleration provided in one embodiment of the present invention;
[0035] Figure 3 This is a schematic diagram of the structure of a graphics rendering engine according to an embodiment of the present invention;
[0036] Figure 4 A flowchart illustrating a texture mapping method based on tensor core acceleration, as provided in one embodiment of the present invention;
[0037] Figure 5 This is a flowchart of texture operations based on Tensor Core;
[0038] Figure 6 A schematic diagram of the hardware structure of a possible electronic device provided by the present invention;
[0039] Figure 7 This is a schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0041] Traditional texture mapping is memory-intensive and bandwidth-intensive, with significant latency overhead for per-fragment texture requests. Furthermore, it is prone to various problems such as aliasing, moiré patterns, and texture blurring during texture stretching or compression, which become more pronounced in high-resolution / super-resolution rendering. While anisotropic filtering can solve texture perspective distortion, it requires multiple samplings along the principal direction and is a very expensive post-processing remedial measure.
[0042] Addressing the inefficiency of existing texture mapping, this invention aims to break the boundaries of traditional graphics pipelines. Texture units continue to handle their strengths in address calculation and memory access, while computationally intensive filtering / interpolation tasks are delegated to the higher-throughput tensor cores. This enables dynamic resource allocation and collaborative acceleration between different processing functions, signifying that GPU architecture is evolving towards greater integration. Tensor cores are no longer exclusive to AI but are also powerful and versatile computing units within GPUs.
[0043] The architecture that integrates the graphics computing core and the tensor core is the core design for modern high-performance GPUs to achieve graphics rendering and AI acceleration. Based on the traditional SIMT architecture for graphics rendering, it integrates a tensor core optimized for matrix operations, forming a collaborative computing hierarchy. The graphics computing core excels at handling logically complex, high-branch tasks (such as vertex shading and fragment shading), while the tensor core specializes in executing large-scale deep learning training and inference tasks that can be decomposed into matrix multiplication and addition operations. Both share a unified memory and cache system, achieving orders-of-magnitude performance and energy efficiency improvements through deep hardware and software collaboration, while maintaining perfect compatibility with traditional graphics. This allows the GPU to evolve from a pure graphics processor into a heterogeneous computing platform integrating graphics rendering, scientific computing, and AI acceleration. Its overall architecture is as follows: Figure 1 As shown.
[0044] The heterogeneous computing platform mainly includes a PCIe controller, bus, DDR, VAG display controller and GPU core. The GPU core mainly includes the Render Core and Tensor Core. All modules are connected and communicate with each other through a data bus.
[0045] PCIe (Peripheral Component Interconnect Express) control is the core mechanism for high-speed I / O management in modern computer systems, responsible for coordinating reliable and efficient communication between the CPU and various peripherals (such as GPU, NVMe SSD, network card, etc.).
[0046] The trained texture feature image data is stored in DDR, the GPU core performs graphics rendering and shading, and the rendered pixel data is also stored in DDR, and finally displayed on VGA.
[0047] In one embodiment of the present invention, the provided texture mapping system based on tensor core acceleration includes an external bus interface, a command processor, a task allocator, and a graphics rendering engine array, wherein the graphics rendering engine array includes multiple fully mirrored graphics rendering engines.
[0048] The command processor is used to read the command stream and vertex index generated by the upper-layer software stack through an external bus interface. The command stream contains state configuration information and graphics processing command information.
[0049] The task allocator is used to organize and package the command stream and vertex index into a graphics rendering task, and to allocate the graphics rendering task to the corresponding graphics rendering engine for execution.
[0050] Each of the graphics rendering engines includes programmable components and fixed-function components. The programmable components include a graphics computing core (Render Core) and a coprocessor. The coprocessor includes a tensor core. The graphics computing core (Render Core) is used to perform various graphics shading tasks according to the task. The tensor core (Tensor Core) is used to perform matrix operations in texture mapping.
[0051] Understandably, see Figure 2 One embodiment of the present invention provides a texture mapping system based on tensor core acceleration, deployed in a GPU. The GPU mainly consists of four functional components: an external bus interface, a command processor, a task allocator, and a graphics rendering engine array. The external bus interface is responsible for exchanging data with external modules via an AXI bus. The external bus interface can be appropriately expanded according to the number of graphics rendering engines in the graphics rendering engine array; N graphics rendering engines correspond to N external bus interfaces. The command processor reads the command stream and vertex indexes generated by the upper-layer software stack through the external bus interface. The command stream contains state setting information and graphics processing command information. The task allocator is responsible for organizing and packaging graphics rendering tasks and assigning them to specific graphics rendering engines in the graphics rendering engine array for execution. The graphics rendering engine array consists of multiple fully mirrored graphics rendering engines, each containing programmable components and fixed-function components. The programmable components consist of a Render Core and a Tensor Core. The Render Core is mainly responsible for various graphics shading (vertex shading, fragment shading, tessellation shading, and geometry shading, etc.), while the Tensor Core is mainly responsible for matrix operations. Fixed-function components are specific dedicated circuits, mainly used to accelerate operations with fixed functions that cannot be computed in parallel, such as primitive assembly, rasterization, texture mapping, fragment operations, etc.
[0052] Aside from fixed acceleration units, the core design of a graphics rendering engine consists of programmable components comprised of Render Cores and Tensor Cores, sharing a unified memory and cache architecture. Texture address calculation and memory access remain consistent with traditional graphics processors, still handled by texture units, while computationally intensive texture filtering is offloaded to the higher-throughput Tensor Cores. Tensor Cores do not simply replace traditional texture filtering hardware; rather, they act as co-acceleration units to enhance the traditional filtering pipeline, performing lightweight neural network inference on batch sampling points. A single Tensor Core can process N FP16 / BF16 matrix multiplications in parallel within one clock cycle. This means it can simultaneously compute filters for texture sampling requests from hundreds or thousands of fragments, forming a "single instruction, multiple data" super-parallel filtering approach. This enables higher quality, more complex, or more efficient filtering effects in high-resolution / super-resolution, detail reconstruction, and intelligent denoising scenarios, thus breaking through the visual quality bottleneck of traditional texture filtering. The graphics rendering engine processor architecture is as follows: Figure 3 As shown.
[0053] See Figure 3 Each graphics rendering engine includes a Render Core and a coprocessor. The coprocessor includes a Tensor Core, which is used to perform various graphics shading tasks according to the task, and a Tensor Core, which is used to perform matrix operations.
[0054] The graphics computing core, Render Core, includes a controller, memory access, and an ALU computing array, wherein the ALU computing array includes multiple ALU computing cores.
[0055] The controller is used to generate multiple coloring tasks according to the tasks issued by the task allocator, and to assign each coloring task to the ALU computing array to complete the corresponding calculation.
[0056] Each of the ALU computing cores is used to perform corresponding calculations according to the coloring task, including integer calculations, floating-point calculations, and transcendental function calculations;
[0057] In fragment shading, when the Render Core needs to perform texture mapping, it sends texture configuration parameters and texture operation requests to the coprocessor, which then performs texture sampling and texture interpolation filtering. The Tensor Core performs texture interpolation filtering.
[0058] The texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and read request.
[0059] The coprocessors in a graphics rendering engine include not only Tensor Cores,
[0060] It also includes a texture unit, which is used to calculate the texture address based on the UV coordinates of each texture and the texture mipmap detail level information, and based on the texture address, sample on each feature texture image through the texture data cache to obtain multiple sampled feature values, organize the multiple sampled feature values into a texture feature vector; organize the multiple texture feature vectors into a texture feature vector matrix, and store the texture feature vector matrix in on-chip storage.
[0061] The Tensor Core reads the texture feature vector matrix and weight matrix from on-chip storage, performs operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result, and writes the texture interpolation filtering result back to the Render Core to complete the fragment shading.
[0062] It should be noted that the neural network is deployed on an external server, where:
[0063] The texture image is trained based on a neural network to learn the mapping from a "low-resolution + blurry" texture image to a "high-resolution + sharp" texture feature image. After training, the weight matrix of the neural network and the feature texture image are generated and stored so that the texture unit can read each feature texture image through the texture data cache.
[0064] Neural network training involves learning from a large number of low-resolution, blurry texture images that require texture sampling and filtering within the neural network to obtain high-resolution, sharp, and clear feature texture images, which are then stored.
[0065] Traditional GPUs, when performing texture mapping, first send the texture configuration parameters to the texture unit, then send the texture UV coordinates and texture request to the texture unit. The texture unit then performs texture sampling and interpolation filtering based on the texture configuration information. However, for high-fidelity graphics rendering, the computational load of texture sampling and interpolation filtering increases rapidly. Therefore, this invention uses Tensor Cores to accelerate texture mapping, not simply making the "texture unit" run faster, but fundamentally changing the way texture filtering is calculated. First, a large number of texture images are trained to learn the mapping from "low resolution + blurry" to "high resolution + sharp," generating and storing the weight matrix of the neural network and the high-information-density feature texture images optimized by the neural network. When the Render Core needs to perform texture mapping, it also first sends the texture configuration parameters to the texture unit, then sends the texture coordinates and texture request to the texture unit. The texture unit samples each feature texture image using a high-speed texture data cache based on the given texture coordinates, obtaining multiple feature values, and then organizes these feature values into a feature vector. Since the GPU processes multiple sampling points in batches (such as a tile of size 8×8), it organizes the texture feature vectors of these sampling points into a texture feature vector matrix and stores it in storage. The texture feature vector matrix and the weight matrix are the inputs of the TensorCore. The TensorCore performs the operation on the vector matrix and the weight matrix to obtain the interpolation filtering result. The interpolation filtering result is written back to the RenderCore register file for subsequent calculations.
[0066] This invention organizes feature vectors sampled from multiple sampled texture coordinates on a feature texture image into a texture feature vector matrix, and leverages the advantages of Tensor Core for matrix multiplication and addition operations to accelerate texture mapping operations.
[0067] See Figure 4 One embodiment of the present invention provides a texture mapping method based on tensor kernel acceleration, applied to the aforementioned texture mapping system based on tensor kernel acceleration. The method mainly includes the following steps:
[0068] Step 1: Read the command stream and vertex index generated by the upper-layer software stack through the external bus interface. The command stream contains state configuration information and graphics processing command information.
[0069] Step 2: Organize and package the command stream and vertex index into a task, and assign the task to the corresponding graphics rendering engine for execution. The graphics rendering engine includes a graphics computing core (Render Core) and a tensor core (TensorCore).
[0070] Step 3: The Render Core performs various graphics shading tasks according to the task, and the Tensor Core is used to perform matrix operations in texture mapping.
[0071] During the shading process, when the Render Core needs to perform texture mapping, it sends texture configuration parameters and texture operation requests to the coprocessor. The coprocessor then performs texture sampling and texture interpolation filtering, with the Tensor Core performing the texture interpolation filtering.
[0072] Texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and read request;
[0073] The texture address is calculated based on the UV coordinates of each texture and the texture mipmap detail level information. Based on the texture address, multiple sampled feature values are obtained by sampling on each feature texture image through the texture data cache. The multiple sampled feature values are organized into a texture sampled feature vector. The multiple texture sampled feature vectors are organized into a texture feature vector matrix, and the texture feature vector matrix is stored in on-chip memory.
[0074] The Tensor Core reads the texture feature vector matrix from on-chip storage, performs operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result, and writes the texture interpolation filtering result back to the Render Core to complete the fragment shading.
[0075] A flowchart for texture operations based on Tensor Cores can be found here. Figure 5 First, the texture image is trained on the neural network to generate the weight matrix and feature texture image of the neural network. When the graphics computing core RenderCore needs texture mapping during the shading process, it sends texture configuration parameters and texture operation requests to the texture unit. The texture configuration parameters include texture mipmap detail level information, and the texture operation requests include each texture UV coordinate and read request.
[0076] The texture unit calculates the texture address based on each texture UV coordinate and texture mipmap detail information. Based on this address, it samples each feature texture image using the texture data cache, i.e., it reads the feature values of each feature texture image to obtain multiple sampled feature values, which are then organized into a texture feature vector. These multiple feature vectors are then organized into a texture feature vector matrix. The Tensor Core performs operations on the texture feature vector matrix and the neural network weight matrix to obtain the texture interpolation filtering result. This result is then written back to the Render Core register file for subsequent calculations.
[0077] Tensor Core does not replace but enhances the traditional filtering pipeline. It transforms texture from "static image data" into "executable small algorithms (neural networks) + optimized data (feature textures)," thereby leveraging the Tensor Core's powerful computing capabilities to overcome storage and bandwidth bottlenecks.
[0078] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 6 As shown, an embodiment of the present invention provides an electronic device 600, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor 620. When the processor 620 executes the computer program 611, it implements the steps of a texture mapping method based on tensor core acceleration.
[0079] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 7 As shown, this embodiment provides a computer-readable storage medium 700 on which a computer program 711 is stored. When the computer program 711 is executed by a processor, it implements the steps of a texture mapping method based on tensor core acceleration.
[0080] This invention provides a texture mapping system and method based on tensor core acceleration, whose core advantage lies in its innovative architecture. This GPU architecture fully combines the advantages of both the graphics rendering core and the tensor core. Texture address calculation and storage access are still handled by texture units, while the complex texture filtering process (especially anisotropic filtering and trilinear filtering) is transformed into an efficient neural inference process directly executed by the tensor core, fully leveraging the high throughput capability of the tensor core. Secondly, the feature textures and neural network weights are typically much smaller than the original texture data, significantly saving data storage and effectively reducing storage and bandwidth pressure.
[0081] The texture mapping design and implementation based on tensor core acceleration has a clear and easy-to-implement circuit structure. Hardware resources such as data cache can be reused, reducing circuit area and power consumption, making it very suitable for graphics processing applications.
[0082] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0083] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0084] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0085] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0086] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0087] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0088] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A texture mapping system based on tensor kernel acceleration, characterized in that, It includes an external bus interface, a command processor, a task allocator, and a graphics rendering engine array, wherein the graphics rendering engine array includes multiple fully mirrored graphics rendering engines. The command processor is used to read the command stream and vertex index generated by the upper-layer software stack through an external bus interface. The command stream contains state configuration information and graphics processing command information. The task allocator is used to organize and package the command stream and vertex index into tasks, and allocate the tasks to the corresponding graphics rendering engines for execution. Each of the graphics rendering engines includes programmable components and fixed-function components. The programmable components include a graphics computing core (Render Core) and a coprocessor. The coprocessor includes a tensor core. The graphics computing core (Render Core) is used to perform various graphics shading tasks according to the task. The tensor core (Tensor Core) is used to perform matrix operations in texture mapping. When the Render Core needs to perform texture mapping during fragment shading, the Render Core sends texture configuration parameters and texture operation requests to the coprocessor, which then performs texture sampling and texture interpolation filtering. The Tensor Core performs texture interpolation filtering. The coprocessor also includes a texture unit; the texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and a read request; The texture unit is used to calculate the texture address based on each texture UV coordinate and texture mipmap detail level information, and based on the texture address, sample on each feature texture image through texture data cache to obtain multiple sampled feature values, organize the multiple sampled feature values into a texture feature vector, organize the multiple texture feature vectors into a texture feature vector matrix, and store the texture feature vector matrix in on-chip storage. The Tensor Core is used to read the texture feature vector matrix and weight matrix from on-chip storage; to perform operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result; and to write the texture interpolation filtering result back to the Render Core to complete fragment shading.
2. The texture mapping system based on tensor kernel acceleration according to claim 1, characterized in that, The graphics computing core (Render Core) includes a controller, memory access, and an ALU computing array, wherein the ALU computing array includes multiple ALU computing cores. The controller is configured to generate multiple coloring tasks based on the tasks issued by the task allocator, and to assign each coloring task to the ALU computing array to complete the corresponding calculations. Each of the ALU computing cores is used to perform corresponding calculations according to the coloring task, including integer calculations, floating-point calculations, and transcendental function calculations.
3. The texture mapping system based on tensor kernel acceleration according to claim 1, characterized in that, It also includes a server, on which a neural network is deployed to complete texture image training, wherein: The texture image is trained based on a neural network to learn the mapping from low-resolution and blurry texture images to high-resolution and sharp texture feature images. After training, the weight matrix and feature texture images of the neural network are generated and stored so that the texture unit can read each feature texture image through the texture data cache.
4. A texture mapping method based on tensor core acceleration, applied to the texture mapping system based on tensor core acceleration as described in claim 1, characterized in that, include: The command stream and vertex index generated by the upper-layer software stack are read through the external bus interface. The command stream contains state configuration information and graphics processing command information. The command stream and vertex index are organized and packaged into tasks, and the tasks are assigned to the corresponding graphics rendering engines for execution. The graphics rendering engines include a graphics computing core (Render Core) and a tensor core (Tensor Core). The graphics computing core Render Core performs various graphics shading according to the task, and the tensor core is used to perform matrix operations in texture mapping. When the graphics computing core Render Core needs to perform texture mapping during fragment shading, it sends texture configuration parameters and texture operation requests to the coprocessor. The coprocessor then performs texture sampling and texture interpolation filtering, with the Tensor Core performing the texture interpolation filtering. The texture configuration parameters include texture mipmap detail level information, and the texture operation request includes each texture UV coordinate and read request; The texture address is calculated based on the UV coordinates of each texture and the texture mipmap detail level information. Based on the texture address, multiple sampled feature values are obtained by sampling on each feature texture image through the texture data cache. The multiple sampled feature values are organized into a texture feature vector. The multiple texture feature vectors are organized into a texture feature vector matrix, and the texture feature vector matrix is stored in on-chip memory. The Tensor Core reads the texture feature vector matrix and weight matrix from on-chip storage, performs operations on the texture feature vector matrix and weight matrix to obtain the texture interpolation filtering result, and writes the texture interpolation filtering result back to the Render Core to complete the fragment shading.
5. The texture mapping method based on tensor kernel acceleration according to claim 4, characterized in that, Also includes: The neural network is used to train texture images to learn the mapping from low-resolution and blurry texture images to high-resolution and sharp texture feature images. After training, the weight matrix and feature texture images of the neural network are generated and stored so that the texture unit can read each feature texture image through the texture data cache.