Analog-to-digital converter non-ideality calibration system

Abstract

An analog-to-digital converter (ADC) non-ideal calibration system includes: a gain and offset detection module, a calibration control module, and a gain and offset correction module connected in sequence. This invention utilizes the data and error signals generated by the data / error generation module in the feedforward equalizer and Miller-Muller phase detector within the clock data recovery (CDR) system as the source of mismatch information between ADC channels. This allows for accurate detection of offset voltage and conversion gain mismatch in each channel without requiring separate design and introduction of additional high-speed detection hardware circuitry for the calibration function. This enables the detection and calibration of voltage offset and gain mismatch non-ideals in high-speed multi-channel time-interleaved ADCs.

Description

Technical Field

[0001] This invention relates to a technology in the field of wired communication, specifically a non-ideal calibration system for analog-to-digital converters based on an analog-to-digital converter-digital processor architecture. Background Technology

[0002] In the field of wired communication receivers, multi-channel time-interleaved analog-to-digital converters (ADCs) are one of the key modules in receivers based on an analog-to-digital converter-digital processor architecture. Existing time-interleaved ADC mismatch calibration methods mostly employ fully digital back-end calibration, relying on complex digital calculations and incurring high resource and power consumption overhead; or they use front-end calibration, requiring high-precision training signals and unable to track environmental changes. Existing solutions all rely on additional dedicated detection circuits. When applied to wired communication receivers, the existing error generation hardware in the clock data recovery loop cannot be reused, leading to significant additional resource and power consumption overhead and reduced overall energy efficiency. Summary of the Invention

[0003] This invention addresses the shortcomings of existing calibration technologies in terms of power consumption, real-time performance, and system complexity by proposing a non-ideal calibration system for analog-to-digital converters (ADCs). It utilizes the data and error signals generated by the data / error generation modules in the feedforward equalizer and Miller-Muller phase detector within the clock data recovery (CDR) system as a source for detecting mismatch information between ADC channels. This eliminates the need for designing and introducing additional high-speed detection hardware circuitry for the calibration function, enabling accurate detection of offset voltage and conversion gain mismatch in each channel. This allows for the detection and calibration of voltage offset and gain mismatch non-ideals in high-speed, multi-channel time-interleaved ADCs.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a non-ideal calibration system for analog-to-digital converters (ADCs), comprising: a gain and offset detection module, a calibration control module, and a gain and offset correction module connected in sequence. The gain and offset detection module estimates the offset voltage error and conversion gain mismatch of each channel based on the phase error signal output from the data / error generation module in the CDR system and the output data of each channel's ADC. The result is then processed by moving average or digital low-pass filtering to obtain a calibration control word. The calibration control module defines and controls the initialization, adjustment, and locking states and their switching conditions through logic control, and generates digital gain correction coefficients and offset correction values ​​for each channel based on the calibration control word. The gain and offset correction module performs real-time compensation on the digital outputs of each channel's ADC in the CDR system based on the digital gain correction coefficients and the offset correction values ​​for each channel, and then outputs the compensation to the feedforward equalizer of the CDR system, ensuring that the multi-channel outputs maintain consistency in amplitude and DC level.

[0006] The CDR system includes, but is not limited to: a feedforward equalizer, a data / error generation module, a phase error generation module, a voter, a digital filter, and a phase interpolator.

[0007] The estimation mentioned above refers to the following: the gain and offset detection module directly uses the data and error signals generated by the data / error generation module when the CDR system is working normally as the source of mismatch information between analog-to-digital converter channels. After performing logical judgment and estimation for each channel, it generates an original offset error signal to characterize the magnitude of the offset voltage deviation of the channel itself and an original gain error signal to characterize the degree of mismatch of the conversion gain of the channel relative to the ideal value.

[0008] The aforementioned logic control defines and controls the initialization, adjustment, and locking states and their transition conditions, which are implemented through a predetermined logic truth table.

[0009] The aforementioned analog-to-digital converter non-ideal calibration system is preferably embedded in the clock data recovery path that includes the CDR system and reuses the CDR system, thereby avoiding the introduction of additional hardware, improving system integration and reducing overall power consumption.

[0010] Technical effect

[0011] This invention uses data and error signals generated during normal operation of the CDR system as the information source for mismatch detection, achieving real-time background monitoring and compensation for multi-channel offset and gain mismatch without introducing additional high-speed detection hardware. Compared with existing technologies, this invention significantly reduces the complexity and power consumption of the digital calibration module. Furthermore, through an embedded closed-loop correction mechanism, it can continuously track and suppress mismatch drift caused by process deviations, temperature fluctuations, and voltage variations, thereby achieving excellent system energy efficiency and integration while ensuring high-precision calibration. Attached Figure Description

[0012] Figure 1 This is a schematic diagram illustrating an application scenario for an example.

[0013] Figure 2 This is a schematic diagram illustrating the principle of offset and gain mismatch detection.

[0014] In the figure: a is a schematic diagram of the gain and offset detection structure; b is the principle of offset voltage detection between multiple channels; c is the principle of gain mismatch detection between multiple channels.

[0015] Figure 3 The following is a screenshot showing the effect of implementing the example. Detailed Implementation

[0016] like Figure 1The diagram illustrates the application scenario of this embodiment, including: a feedforward equalizer, a data / error generation module, a phase error generation module, a voter, a digital filter and a phase interpolator, as well as a gain and offset detection module, an averaging filter, a calibration control module, and a gain and offset correction module. Specifically: the feedforward equalizer performs equalization processing on the digitally quantized data sequence output by the gain and offset correction module to obtain an equalized data signal with effectively suppressed inter-symbol interference; the Miller-Muller phase detector performs phase comparison and extraction processing based on the transition edge timing information of the equalized data signal to obtain an error signal characterizing the sampling phase error; the gain and offset detection module recovers the equalized data signal and corresponding error signal in the clock data recovery path based on the output data of each channel's analog-to-digital converter. The system performs decision and estimation based on a predetermined logic truth table to obtain the original offset error signal and original gain error signal for each channel. The averaging filter performs moving average or digital low-pass filtering based on the offset voltage error and conversion gain mismatch output by the gain and offset detection module to obtain a smooth and stable digital calibration control word. The calibration control module performs decoding, mapping, and state machine management based on the calibration control word output by the averaging filter to generate digital gain correction coefficients and offset correction values ​​for each channel for actual calibration. The gain and offset correction module performs digital multiplication and addition operations based on the digital output of each channel's analog-to-digital converter and the calibration parameters provided by the calibration control module to obtain consistent calibration output data between channels after real-time compensation.

[0017] like Figure 2 As shown, the predetermined logic truth tables include: an offset detection logic truth table as shown in Table 1 and a gain detection logic truth table as shown in Table 2, which are respectively based on the equalized and decided data in the path of the CDR system. and error signal Set the corresponding offset and gain.

[0018] Table 1

[0019] Table 2

[0020] The feedforward equalizer utilizes a multi-stage data feedforward architecture to achieve inter-symbol interference cancellation, ensuring that the data signal input to the subsequent Miller-Muller phase detector and gain and mismatch detection module has effectively suppressed inter-symbol interference, thereby providing a high-quality data foundation for mismatch detection.

[0021] The gain and offset detection module includes: a data pattern recognition and triggering unit, an offset error detection unit, a gain error detection unit, and an error signal output unit, wherein: the data pattern recognition and triggering unit generates the equalized data signal output by the data / error generation module. and its adjacent positions The information is processed by identifying and matching specific data patterns (such as

[100] or

[011] ) to obtain the enable control signal result for triggering offset and gain error detection operations; under the enable control of the data pattern recognition and triggering unit, the offset error detection unit, based on the phase error signal... and data signals The information is processed by referring to a predefined truth table for offset error detection logic, performing logical decision and polarity determination to obtain the original offset error signal representing the direction of DC level deviation for the corresponding channel; similarly, the gain error detection unit, under the enable control of the data pattern recognition and triggering unit, determines the offset error signal based on the phase error signal. The statistical distribution characteristics of the data under a specific data pattern are statistically analyzed and the direction is determined by referring to the predefined truth table of the gain error detection logic. This results in the original gain error signal that represents the direction of the gain mismatch (too large or too small) of the corresponding channel conversion gain. The error signal output unit performs signal synchronization and format integration processing based on the original offset error signal output by the offset error detection unit and the original gain error signal output by the gain error detection unit. This results in the original offset and gain error signal stream organized by channel and available for subsequent filtering.

[0022] The Miller-Muller phase detector, based on the equalized data signal, generates and outputs a signal characterizing the data sequence and transition edge information through digital logic (such as flip-flops, delay units, etc.). It then processes the equalized data through a specific algorithm (e.g., based on the relationship between the current and adjacent data symbols and sampling points) to generate an error signal characterizing the phase deviation of the current sampling clock.

[0023] The average filter smooths the offset voltage error and conversion gain mismatch output by the gain and offset detection module to filter out high-frequency noise and data-dependent disturbances, and outputs a stable calibration control word.

[0024] The calibration control module includes a parameter decoding and loop control unit and a parameter update and state holding unit. The parameter decoding and loop control unit decodes, maps, and performs loop state decision processing based on the digital calibration control word information output by the averaging filter, obtaining preliminary mapping results of the digital gain correction coefficients and offset correction values ​​for each channel, as well as control signals for the loop operating state (initialization / adjustment / locking). The parameter update and state holding unit, based on the calibration parameter mapping results and loop state control signals, performs dynamic parameter updates and integral accumulation processing in the adjustment state, or parameter locking and output holding processing in the locked state, ultimately obtaining stable final gain and offset correction values ​​suitable for real-time compensation, and outputting them to the gain and offset correction module. This module is implemented based on conventional design methods using digital logic and finite state machines, without any special modifications to its fundamental principles.

[0025] The gain and offset correction module includes an offset correction unit and a gain correction unit. The offset correction unit performs digital subtraction based on the original digital output of each channel's analog-to-digital converter and the offset correction value information of the corresponding channel provided by the calibration control module to obtain intermediate data of each channel with DC deviation eliminated. The gain correction unit performs digital multiplication based on the intermediate data with corrected offset output by the offset correction unit and the digital gain correction coefficient information provided by the calibration control module to obtain the final standard digital output with consistent amplitude across all channels after gain compensation.

[0026] The digital subtraction and multiplication operations are implemented based on general digital signal processing or arithmetic logic units.

[0027] This embodiment is based on the calibration method of the above system, specifically including:

[0028] Step 1: In the feedforward equalization and phase detection logic module of the CDR system, the input data undergoes adaptive equalization by the feedforward equalizer to suppress inter-symbol interference. The Miller-Muller phase detector then extracts the phase error based on the data transition edge information and outputs the data sequence. Sum of error signals .

[0029] Step 2: The gain and offset detection module receives the digital output data of each channel ADC and the error signal generated by the Miller-Muller phase detector. For offset voltage detection, the module uses the error signal and data sequence under a specific data pattern. The correlation between them is determined through logical decision-making using a predefined truth table, generating the original offset error signal E. offset For gain mismatch detection, the statistical distribution characteristics of the error signal are analyzed under the same data mode, and the direction of gain mismatch is determined based on the gain error detection truth table, outputting the original gain error signal E.gain During the detection process, operating parameters, including the data sampling rate and error extraction threshold, can be adjusted according to system requirements.

[0030] Step 3: The averaging filter smooths the offset voltage error and conversion gain mismatch to suppress noise and data-dependent disturbances. This module uses a moving average algorithm or a first-order IIR low-pass filter. The filter window size N is configurable (typically 4-16 sampling periods), and the cutoff frequency is set much lower than the signal bandwidth to ensure effective filtering of high-frequency noise while maintaining response speed. The smoothed error signal is converted into a digital calibration control word and output to the calibration control module.

[0031] Step 4: The calibration control module receives the averaged calibration control word and manages the calibration loop through its built-in state machine. The state machine contains three operating states: an initialization state, used to set initial calibration parameters (such as the gain correction coefficient G). corr The initial value is 1, and the offset correction value is 0. corr Initial value is 0); Adjustment state: dynamically adjusts the correction parameters based on the error signal, using an accumulator for integral control, with configurable adjustment step size; Locked state: maintains the current calibration parameters when the error is below a preset threshold to ensure system stability. The calibration control module outputs a digital gain correction coefficient G. corr and the offset correction value O for each channel corr .

[0032] Step 5: The gain and offset correction module receives the raw output D of each channel ADC. ADC_raw And apply the correction formula for real-time compensation: D ADC_corrected = (D ADC_raw - O corr ) ×G corr The corrected data is used for subsequent digital processing to eliminate channel mismatches and non-ideals.

[0033] The entire calibration process runs continuously in the background without the need for external training signals or interruption of normal data sampling, achieving high integration and low power consumption in real-time mismatch compensation.

[0034] like Figure 2 As shown, during offset voltage detection, without loss of generality, when the data mode is

[100] , if the current detection channel (corresponding data bit) The presence of offset voltage will cause the sampled value to deviate from the ideal level, which will be reflected in the error signal output by the Miller-Muller phase detector. In the CDR system, the data obtained from equalization and decision processes are in the path. and error signal ,pass Figure 2The logic truth table shown in the lower left corner is used for decision-making to generate the corresponding offset error indication signal. This truth table fully defines the correspondence between offset voltage polarity determination and error quantity extraction under different data transition combinations.

[0035] Based on the completed offset calibration, the gain mismatch detection employs the same timing analysis mechanism. When the data mode is

[100] , if a positive gain mismatch exists, the sampling point amplitude will exceed the expected range, causing the Miller-Muller phase detector error signal to exhibit specific statistical characteristics. The system analyzes the correlation between the equalized data and the error signal, and accurately determines the gain mismatch direction of each channel based on the gain error detection truth table. This detection logic fully utilizes the phase information output by the existing Miller-Muller phase detector, achieving gain error extraction without introducing additional detection circuitry.

[0036] Through practical application experiments, a receiver chip circuit prototype based on 22nm CMOS technology and integrating the aforementioned non-ideal calibration system for analog-to-digital converters was tested at full speed in real time. For a 32-channel time-interleaved analog-to-digital converter with a sampling rate of 1 GS / s per channel and a resolution of 7 bits, under the condition of a full-amplitude sine wave test signal at an input frequency of 12 GHz, the key performance indicators before and after enabling the system calibration function were compared as follows: Before and after calibration, standard test signals (such as full-amplitude sine waves) were input to multiple TIADCs, and the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) of the simulated output spectrum were measured. Before calibration, with a random gain and offset mismatch of ±4% between the analog channels, the measured output signal SNR was 30.3 dB and the SFDR was 35.1 dB. After enabling the calibration system described in this invention, the residual mismatch between channels was suppressed to within ±0.1%, and the measured output signal SNR increased to 44.0 dB and the SFDR increased to 58.9 dB.

[0037] Compared with existing technologies, the present invention can continuously monitor error characteristics under specific data modes during normal data communication, realize real-time background detection of offset and gain mismatch, and provide accurate error input for subsequent calibration.

[0038] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A non-ideal calibration system for an analog-to-digital converter, characterized in that, include: The gain and offset detection module, calibration control module, and gain and offset correction module are connected in sequence. Specifically: the gain and offset detection module estimates the offset voltage error and conversion gain mismatch of each channel based on the phase error signal output from the data / error generation module in the CDR system and the output data of each channel's analog-to-digital converter. After passing the result through moving average or digital low-pass filtering, a calibration control word is obtained. The calibration control module defines and controls the initialization, adjustment, and locking states and their switching conditions through logic control. Based on the calibration control word, it generates digital gain correction coefficients and offset correction values ​​for each channel. The gain and offset correction module performs real-time compensation on the digital outputs of each channel's analog-to-digital converter in the CDR system based on the digital gain correction coefficients and offset correction values ​​for each channel, and then outputs the compensation to the feedforward equalizer of the CDR system, ensuring that the multi-channel outputs maintain consistency in amplitude and DC level. The gain and offset detection module includes: a data pattern recognition and triggering unit, an offset error detection unit, a gain error detection unit, and an error signal output unit, wherein: the data pattern recognition and triggering unit generates the equalized data signal output by the data / error generation module. and its adjacent positions The information is processed to identify and match specific data patterns, resulting in an enable control signal for triggering offset and gain error detection operations. Under the enable control of the data pattern recognition and triggering unit, the offset error detection unit, based on the phase error signal... and data signals The information is processed by referring to a predefined truth table for offset error detection logic, performing logical decision and polarity determination to obtain the original offset error signal representing the direction of DC level deviation for the corresponding channel; similarly, the gain error detection unit, under the enable control of the data pattern recognition and triggering unit, determines the offset error signal based on the phase error signal. The statistical distribution characteristics of the data under a specific data pattern are statistically analyzed and the direction is determined by referring to the predefined truth table of the gain error detection logic. This results in the original gain error signal that represents the direction of gain mismatch in the corresponding channel. The error signal output unit performs signal synchronization and format integration processing based on the original offset error signal output by the offset error detection unit and the original gain error signal output by the gain error detection unit. This results in the original offset and gain error signal stream organized by channel and available for subsequent filtering.

2. The analog-to-digital converter non-ideal calibration system according to claim 1, characterized in that, The estimation mentioned above refers to the following: the gain and offset detection module directly uses the data and error signals generated by the data / error generation module when the CDR system is working normally as the source of mismatch information between analog-to-digital converter channels. After performing logical judgment and estimation for each channel, it generates an original offset error signal to characterize the magnitude of the offset voltage deviation of the channel itself and an original gain error signal to characterize the degree of mismatch of the conversion gain of the channel relative to the ideal value.

3. The analog-to-digital converter non-ideal calibration system according to claim 1, characterized in that, The aforementioned logic control defines and controls the initialization, adjustment, and locking states and their transition conditions, implemented through predetermined logic truth tables, including: an offset detection logic truth table and a gain detection logic truth table, which are respectively based on the equalized and decision data obtained in the CDR system's path. and error signal Set the corresponding offset and gain.

4. The analog-to-digital converter non-ideal calibration system according to claim 1, characterized in that, the average... The filter smooths the offset voltage error and conversion gain mismatch output by the gain and offset detection module to remove high-frequency noise and data-dependent disturbances, and outputs a stable calibration control word.

5. The analog-to-digital converter non-ideal calibration system according to claim 1 or 3, characterized in that, The calibration control module includes a parameter decoding and loop control unit and a parameter update and state holding unit. The parameter decoding and loop control unit decodes, maps, and performs loop state decision processing based on the digital calibration control word information output by the average filter, obtaining preliminary mapping results of the digital gain correction coefficients and offset correction values ​​for each channel, as well as control signals for loop operation state initialization / adjustment / locking. The parameter update and state holding unit performs dynamic parameter updates and integral accumulation processing in the adjustment state, or parameter locking and output holding processing in the locked state, based on the calibration parameter mapping results and loop state control signal information, ultimately obtaining stable final gain and offset correction values ​​suitable for real-time compensation, and outputting them to the gain and offset correction module. This module is implemented based on conventional design methods of digital logic and finite state machines, without any special modifications to its fundamental principles.

6. The analog-to-digital converter non-ideal calibration system according to claim 1, characterized in that, The gain and offset correction module includes an offset correction unit and a gain correction unit. The offset correction unit performs digital subtraction based on the original digital output of each channel's analog-to-digital converter and the offset correction value information of the corresponding channel provided by the calibration control module to obtain intermediate data of each channel with DC deviation eliminated. The gain correction unit performs digital multiplication based on the intermediate data with corrected offset output by the offset correction unit and the digital gain correction coefficient information provided by the calibration control module to obtain the final standard digital output with consistent amplitude across all channels after gain compensation.

7. The analog-to-digital converter non-ideal calibration system according to any one of claims 1-3, characterized in that, The aforementioned analog-to-digital converter non-ideal calibration system is embedded in the clock data recovery path containing the CDR system and reuses the CDR system, thereby avoiding the introduction of additional hardware, improving system integration and reducing overall power consumption.

8. A calibration method for a non-ideal calibration system for an analog-to-digital converter according to any one of claims 1-7, characterized in that, include: Step 1: In the feedforward equalization and phase detection logic module of the CDR system, the input data undergoes adaptive equalization by the feedforward equalizer to suppress inter-symbol interference. The Miller-Muller phase detector then extracts the phase error based on the data transition edge information and outputs the data sequence. Sum of error signals ; Step 2: The gain and offset detection module receives the digital output data of each channel ADC and the error signal generated by the Miller-Muller phase detector. For offset voltage detection, the module uses the error signal and data sequence under a specific data pattern. The correlation between them is determined through logical decision-making using a predefined truth table, generating the original offset error signal E. offset For gain mismatch detection, the statistical distribution characteristics of the error signal are analyzed under the same data mode, and the direction of gain mismatch is determined according to the gain error detection truth table, and the original gain error signal E is output. gain During the detection process, the operating parameters, including the data sampling rate and the error extraction threshold, can be adjusted according to system requirements. Step 3: The average filter smooths the offset voltage error and conversion gain mismatch to suppress noise and data-dependent disturbances. This module uses a moving average algorithm or a first-order IIR low-pass filter. The filter window size N is configurable, and the cutoff frequency is set to be much lower than the signal bandwidth to ensure that high-frequency noise is effectively filtered out while maintaining response speed. The smoothed error signal is converted into a digital calibration control word and output to the calibration control module. Step 4: The calibration control module receives the averaged calibration control word and manages the calibration loop through the built-in state machine. The state machine contains three working states: initialization state, which is used to set the initial calibration parameters. In adjustment mode, the calibration parameters are dynamically adjusted based on the error signal, using an accumulator for integral control, and the adjustment step size is configurable. In lock mode, the current calibration parameters are maintained when the error is below a preset threshold to ensure system stability. The calibration control module outputs a digital gain correction coefficient G. corr and the offset correction value O for each channel corr ; Step 5: The gain and offset correction module receives the raw output D of each channel ADC. ADC_raw And apply the correction formula for real-time compensation: D ADC_corrected =(D ADC_raw -O corr )×G corr The corrected data is used for subsequent digital processing to eliminate the non-idealities of mismatch between channels.

Images