Semiconductor device

Abstract

According to some embodiments, a device is provided. The device includes a transistor having a gate electrode, a first gate pad connected to the gate electrode, a second gate pad connected to the gate electrode, and a first gate ring connecting the first gate pad and the second gate pad.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, for example, to silicon carbide (SiC) semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices include doped regions formed by ion implantation. A semiconductor die containing the semiconductor device is mounted in a device package having external contact pads for accessing the semiconductor device within the die. Summary of the Invention

[0003] The choice of concepts provided to introduce a simplified form of the present invention will be further described in the following detailed description. The present invention is not intended to identify key elements or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a device is provided. The device includes: a transistor including a gate electrode; a first gate pad connected to the gate electrode; a second gate pad connected to the gate electrode; and a first gate ring connecting the first gate pad and the second gate pad.

[0005] According to some embodiments, a circuit board assembly is provided. The circuit board assembly includes a first semiconductor package including a first semiconductor die, the first semiconductor die including a first gate pad, a second gate pad, and a first gate ring connecting the first gate pad to the second gate pad. The circuit board assembly also includes a second semiconductor package including a second semiconductor die, the second semiconductor die including a third gate pad, a fourth gate pad, and a second gate ring connecting the third gate pad to the fourth gate pad. The circuit board assembly includes gate pins and gate interconnects connecting the gate pins to the first gate pad and the third gate pad.

[0006] According to some embodiments, a method is provided. The method includes mounting a first semiconductor die in a first semiconductor package, the first semiconductor die including a first gate pad, a second gate pad, and a first gate ring connecting the first gate pad to the second gate pad. The method also includes mounting a second semiconductor die in a second semiconductor package, the second semiconductor die including a third gate pad, a fourth gate pad, and a second gate ring connecting the third gate pad to the fourth gate pad. Finally, the method includes connecting gate pins to the first gate pad and the third gate pad.

[0007] According to some embodiments, a system is provided. The system includes means for mounting a first semiconductor die in a first semiconductor package, the first semiconductor die including a first gate pad, a second gate pad, and a first gate ring connecting the first gate pad to the second gate pad. The system includes means for mounting a second semiconductor die in a second semiconductor package, the second semiconductor die including a third gate pad, a fourth gate pad, and a second gate ring connecting the third gate pad to the fourth gate pad. The system includes means for connecting gate pins to the first gate pad and the third gate pad.

[0008] To achieve the foregoing and related objectives, the following description and accompanying drawings illustrate certain illustrative aspects and embodiments. These indicate only a few of the various ways in which one or more aspects can be employed. Other aspects, advantages, and novel features of this disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 It is a plan view of a semiconductor device according to some embodiments.

[0010] Figure 2 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0011] Figures 3 to 11 It is a plan view of an arrangement for interconnecting a semiconductor package comprising one or more semiconductor devices, according to some embodiments. Detailed Implementation

[0012] The claimed subject matter will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent, however, that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0013] It should be understood that the following description of the embodiments should not be considered limiting. The scope of this disclosure is not intended to be limited to the embodiments described below or by means of the accompanying drawings, which are merely illustrative. The drawings are intended to be schematic, and the elements shown in the drawings are not necessarily shown to scale. Rather, various elements are represented such that their function and general purpose will become apparent to those skilled in the art.

[0014] All numerical values ​​in the specific embodiments and claims herein are modified in such a way that they are “approximately” or “approximately” to the indicated values, taking into account experimental errors and variations that would be expected by one of ordinary skill in the art.

[0015] The terms “above” and / or “over” should not be interpreted as simply meaning “directly above” and / or “in direct contact with”. Rather, if one element is “above” and / or “over” another element (e.g., one region over another region), then the other element (e.g., another region) can be located between the two elements (e.g., if the first region is “above” and / or “over” the second region, then the other region can be located between the first and second regions). Furthermore, if the first element is “above” and / or “over” the second element, then at least some of the first element can be perpendicularly coincident with the second element, such that a vertical line can intersect the first and second elements.

[0016] The semiconductor substrate or body may extend along a main extension plane. The term "horizontal" as used herein is intended to describe an orientation substantially parallel to the main extension plane. A first or main horizontal side of the semiconductor substrate or body may extend substantially parallel to the horizontal direction, or may have a surface portion at an angle of up to 8° (or up to 6° or up to 4°) to the main extension plane. The first or main horizontal side may be, for example, the surface of a wafer or die. Sometimes, the horizontal direction is also referred to as the lateral direction.

[0017] As used herein, the term "vertical" is intended to describe an orientation that is substantially perpendicular to a horizontal orientation (e.g., a normal direction parallel to a first side of a semiconductor substrate or body, or a normal direction parallel to a surface portion of a first side of a semiconductor substrate or body).

[0018] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the dopant conductivity type "n" or "p". For example, "n-" indicates a dopant concentration lower than that of an "n" doped region, while an "n+" doped region has a higher dopant concentration than an "n" doped region. Doped regions with the same relative dopant concentration do not necessarily have the same absolute dopant concentration. For example, two different "n" doped regions may have the same or different absolute dopant concentrations. In some embodiments, the n-type dopant (or impurity) may include at least one of phosphorus, arsenic, or other suitable n-type dopant, and the p-type dopant (or impurity) may include at least one of boron, BF3, or other suitable p-type dopant.

[0019] According to this disclosure, a semiconductor device and a method for manufacturing the semiconductor device are provided. The embodiments described herein can be combined in any manner.

[0020] Figure 1 This is a plan view of a semiconductor device 100 provided according to some embodiments. In some embodiments, the semiconductor device 100 is a superjunction transistor device, which includes a source pad 102 having a lower source semiconductor structure, a gate pad 104 having a lower gate semiconductor structure, and a gate ring 106 in an edge termination region of the semiconductor device 100. The gate ring 106 interconnects the gate pad 104. In some embodiments, a drain pad for contacting the drain of the transistor is on the back side of the semiconductor device 100. The semiconductor device 100 may be a semiconductor die. The number and arrangement of the gate pads 104 may vary.

[0021] Figure 2 This is a cross-sectional view of a portion of a semiconductor device 100 according to some embodiments, showing a gate pad 104 and a gate ring 106. The semiconductor device 100 includes highly doped n-pillars 110 and highly doped p-pillars 112 in a semiconductor body 114. In some embodiments, the semiconductor body 114 comprises a crystalline semiconductor material, such as silicon carbide (SiC) and / or other semiconductor compounds.

[0022] P-doped semiconductor layers 116 and 118 and n-doped semiconductor layer 120 are formed on pillars 110 and 112 to control the electric field and facilitate carrier recombination during commutation events. A gate dielectric layer 122, such as silicon dioxide, is formed on the n-doped semiconductor layer 120, and a gate electrode layer 124, such as polysilicon, is formed on the gate dielectric layer 122. In some embodiments, the gate electrode layer 124 includes a gate electrode pad portion 124P and a gate electrode ring portion 124R, the gate electrode pad portion 124P being below the gate pad 104 and having the same overall shape as the gate pad 104, and the gate electrode ring portion 124R being below the gate ring 106 and having the same overall shape as the gate ring 106. A dielectric layer 126 is formed on the gate electrode layer 124. Conductive vias 128 connect gate pads 104 to gate electrode pad portions 124P of gate electrode layer 124, and conductive vias 130 connect gate rings 106 to gate electrode ring portions 124R of gate electrode layer 124. The conductive vias 128 and 130 may be positioned around the outer periphery of semiconductor device 100 such that each gate pad 104 has a corresponding underlying gate electrode pad portion 124P and a plurality of conductive vias 128. Similarly, gate ring 106 may have an underlying gate electrode ring portion 124R with a plurality of connecting vias 130. In some embodiments, a protective layer 132, such as a polyimide layer, is formed on semiconductor device 100 and patterned to form openings on gate pads 104 while covering gate ring 106. In some embodiments, vias 128 and 130 comprise tungsten or some other conductive material. Gate pads 104 and gate rings may comprise multiple layers, such as a tungsten layer including vias 128 and 130 and one or more additional layers, such as aluminum-copper layers. In some embodiments, the protective layer covers some portions of the source pad 102, while other portions of the source pad 102 are exposed to allow connection thereto.

[0023] Figures 3 to 11 This is a plan view of the arrangement of a circuit board assembly for interconnecting a semiconductor package including a semiconductor device 100, according to some embodiments. Figures 3 to 11 The view is simplified because the protective layer 132, which has the openings exposing the source pad 102 and the openings exposing the gate pad 104, is omitted. Figures 3-11 The view also includes a semiconductor package that may have an additional protective layer (not shown) with patterned openings to facilitate the interconnects shown.

[0024] refer to Figure 3 The circuit board assembly 300 includes semiconductor packages 150A and 150B, each semiconductor package 150A and 150B including instances of semiconductor devices 100 mating with gate pins 152A and 152B and source pins 154A and 154B. Figure 3 In some embodiments, the semiconductor device 100 includes four gate pads 104 connected by a gate ring 106. In some embodiments, gate interconnects 156A, 156B connect gate pins 152A, 152B to selected gate pads 104 of the semiconductor device 100, and gate interconnects 158A, 158B interconnect two or more of the gate pads 104. The interconnects may be conductive traces, bonding wires, flowable conductive materials, plates, or some other type of conductive interconnect. Providing gate interconnects 158A, 158B reduces the signal propagation time of the gate signal and improves signal distribution. In some embodiments, source interconnects 159A, 159B connect source pins 154A, 154B to corresponding source pads 102 of the semiconductor device 100. Providing gate pads 104 at different locations on the semiconductor device 100 provides flexibility regarding contact location to maintain compliance with manufacturability and design rules. For example, gate interconnect 156A is on the opposite side of semiconductor package 150A, compared to gate interconnect 156B on semiconductor package 150B.

[0025] refer to Figure 4 The circuit board assembly 400 includes semiconductor packages 160A and 160B, each including an example of a semiconductor device 100 mating with gate pins 162A and 162B and source pins 164A and 164B. Figure 4 In one embodiment, the semiconductor device 100 includes two gate pads 104 connected by a gate ring 106. Note that the semiconductor package 160B is rotated 180° relative to the semiconductor package 160A to provide contact flexibility. To reduce gate signal propagation delay by providing earlier activation of the gate ring 106, different gate interconnects 166A, 167A connect gate pin 162A to the gate pad 104 of the semiconductor device 100 in the semiconductor package 160A, and different gate interconnects 166B, 167B connect gate pin 162B to the gate pad 104 of the semiconductor device 100 in the semiconductor package 160B. In some embodiments, source interconnects 169A, 169B connect source pins 164A, 164B to corresponding source pads 102 of the semiconductor device 100.

[0026] refer to Figure 5 The circuit board assembly 500 includes a semiconductor package 170, which includes an instance of a semiconductor device 100 that interfaces with a gate pin 172, a source pin 174, and a temperature sensing (TS) pin 175. Figure 5In one embodiment, the semiconductor device 100 includes two gate pads 104 and a temperature sensing pad 107 connected by a gate ring 106 to facilitate temperature measurement of the semiconductor package 170. One or more gate interconnects 176A, 177A connect a gate pin 172A to the gate pad 104 of the semiconductor device 100 in the semiconductor package 160A, and a TS interconnect 177 connects a temperature sensing pin 175 to the TS pad 107 of the semiconductor device 100 in the semiconductor package 170. In some embodiments, a source interconnect 179 connects a source pin 174 to the source pad 102 of the semiconductor device 100.

[0027] refer to Figure 6 The circuit board assembly 600 includes a semiconductor package 180, which includes an example of a semiconductor device 100 that interfaces with a gate pin 182, a source pin 184, and a plurality of temperature sensing pins 185A, 185B. Figure 6 In one embodiment, the semiconductor device 100 includes two gate pads 104 and two temperature sensing pads 107A, 107B connected by a gate ring 106 to facilitate temperature measurement of the semiconductor package 180 at different locations. Note that one of the gate pads 104 is located at the center of the semiconductor device 100 rather than at a corner. A gate interconnect 186 connects a gate pin 182 to the gate pad 104 of the semiconductor device 100 in the semiconductor package 180, and TS interconnects 187A, 187B connect temperature sensing pins 185A, 185B to the TS pads 107A, 107B of the semiconductor device 100 in the semiconductor package 180. In some embodiments, a source interconnect 189 connects a source pin 184 to the source pad 102 of the semiconductor device 100.

[0028] refer to Figure 7 The circuit board assembly 700 includes semiconductor packages 190A and 190B, each including instances of semiconductor devices 100 mating with gate pins 192 and source pins 194, such that the semiconductor devices 100 in the semiconductor packages 190A and 190B are interconnected and operate in parallel. Figure 7In some embodiments, each semiconductor device 100 includes two gate pads 104 connected by a gate ring 106. A gate interconnect 196 connects a gate pin 192 to a gate pad 104 of the semiconductor device 100 in semiconductor package 190B, and a gate interconnect 197 connects a gate pad 104 of the semiconductor device 100 in semiconductor package 190B to an adjacent gate pad 104 of the semiconductor device 100 in semiconductor package 190A. In some embodiments, source interconnects 198A, 198B connect source pins 194 to corresponding source pads 102 of the semiconductor devices 100 in semiconductor packages 190A, 190B. In some embodiments, an additional source interconnect 199 directly connects to corresponding source pads 102 of the semiconductor devices 100 in semiconductor packages 190A, 190B to reduce asymmetric source junctions with ground.

[0029] refer to Figure 8 The circuit board assembly 800 is shown, in which Figure 7 The source interconnects 198A, 198B, 199 shown are replaced by source interconnect clips 198C that contact and interconnect the corresponding source pads 102 of the semiconductor devices 100 in the semiconductor packages 190A, 190B. In some embodiments, clips 198C may include a conductive material, such as copper, aluminum, a metal alloy, or some other conductive material. Clips 198C may be plated with a solderable material.

[0030] refer to Figure 9 The circuit board assembly 900 includes semiconductor packages 210A and 210B, each including instances of semiconductor devices 100 mating with gate pins 212 and source pins 214A and 214B, such that the semiconductor devices 100 in the semiconductor packages 210A and 210B are interconnected and operate in parallel. Figure 9 In some embodiments, each semiconductor device 100 includes two gate pads 104 connected by a gate ring 106. Gate interconnects 216A, 216B connect gate pins 212 to the gate pads 104 of the semiconductor device 100 in semiconductor packages 210A, 210B. In some embodiments, source interconnects 218A, 218B connect source pins 214A, 214B to corresponding source pads 102 of the semiconductor device 100 in semiconductor packages 210A, 210B. In some embodiments, an additional source interconnect 219 is directly connected to the corresponding source pads 102 of the semiconductor device 100 in semiconductor packages 210A, 210B.

[0031] refer to Figure 10 In circuit board assembly 1000, Figure 9The source interconnects 218A, 218B, and 219 shown are replaced by source interconnect clips 218P, which contact and interconnect the corresponding source pads 102 of the semiconductor devices 100 in the semiconductor packages 210A and 210B.

[0032] refer to Figure 11 The circuit board assembly 1100 includes semiconductor packages 220A and 220B. Semiconductor packages 220A and 220B include instances of semiconductor devices 100 that interface with gate pins 222, source pins 223A and 223B, TS pins 224A and 224B, and Kelvin sensing (KS) pins 225A and 225B, such that the semiconductor devices 100 in semiconductor packages 220A and 220B are interconnected and operate in parallel. Figure 11 In each embodiment, the semiconductor device 100 includes two gate pads 104, a TS pad 107, and a KS pad 109 connected by a gate ring 106. Gate interconnects 226A and 226B connect gate pins 222 to the gate pads 104 of the semiconductor device 100 in semiconductor packages 220A and 220B. In some embodiments, source clips 227 connect source pins 223A and 223B to the corresponding source pads 102 of the semiconductor device 100 in semiconductor packages 220A and 220B. TS interconnects connect TS pins 224A and 224B to the corresponding TS pads 107 of the semiconductor device 100 in semiconductor packages 220A and 220B. KS interconnects connect KS pins 225A and 225B to the corresponding KS pads 109 of the semiconductor device 100 in semiconductor packages 220A and 220B. The number of gate pads 104 on the semiconductor device 100 can vary. The number or location of TS pads 107 or KS pads 109 can be varied, or one or more can be omitted. Source clips 227 can be used for interconnections between source pads 102 and source pins, as well as interconnections between source pads 102 (e.g., ...). Figure 9 (As shown) instead. The shape of the source clip 227 can vary. For example, if only one source pin 223A, 223B is provided, the source clip 227 can have a shape similar to Figure 8 The shape of the source clip 198C is shown.

[0033] Providing flexibility for multi-chip products by offering multiple gate pads 104 interconnected by gate ring 106 allows for changes in package orientation, selection of the shortest signal path, provision of multiple signal paths or package-to-package interconnects to reduce propagation delay, reduction of parasitic effects of gate ring 106, reduction of asymmetric source junction with ground, and provides flexibility to meet manufacturability and design rules, among other benefits.

[0034] According to some embodiments, a device is provided. The device includes: a transistor including a gate electrode; a first gate pad connected to the gate electrode; a second gate pad connected to the gate electrode; and a first gate ring connecting the first gate pad and the second gate pad.

[0035] According to some embodiments, the first gate ring and the gate electrode comprise polysilicon.

[0036] According to some embodiments, the device includes a second gate ring located above a first gate ring, wherein the first gate ring is connected to the second gate ring, the first gate ring and a gate electrode are formed in a first layer, and the second gate ring, the first gate pad and the second gate pad are formed in a second layer above the first layer.

[0037] According to some embodiments, the device includes a dielectric layer located between a first gate ring and a second gate ring.

[0038] According to some embodiments, the device includes: a first conductive via in a dielectric layer, the first conductive via connecting a gate electrode to a first gate pad; and a second conductive via in a dielectric layer, the second conductive via connecting a first gate ring to a second gate ring.

[0039] According to some embodiments, the device includes a protective layer located above the gate ring.

[0040] According to some embodiments, the device includes a gate interconnect formed over a protective layer and connecting a first gate pad and a second gate pad.

[0041] According to some embodiments, the device includes a third gate pad connected to a first gate ring and a gate electrode, and a fourth gate pad connected to the first gate ring and the gate electrode.

[0042] According to some embodiments, the device includes a circuit board assembly, the circuit board assembly including a gate pin, a first gate interconnect connecting a first gate pad and the gate pin, and a second gate interconnect connecting a second gate pad and the gate pin.

[0043] According to some embodiments, the device includes a temperature sensing pad and a circuit board assembly, the circuit board assembly including a temperature sensing pin and a temperature sensing interconnect connecting the temperature sensing pad and the temperature sensing pin.

[0044] According to some embodiments, a circuit board assembly is provided. The circuit board assembly includes a first semiconductor package including a first semiconductor die, the first semiconductor die including a first gate pad, a second gate pad, and a first gate ring connecting the first gate pad to the second gate pad. The circuit board assembly also includes a second semiconductor package including a second semiconductor die, the second semiconductor die including a third gate pad, a fourth gate pad, and a second gate ring connecting the third gate pad to the fourth gate pad. The circuit board assembly includes gate pins and gate interconnects connecting the gate pins to the first gate pad and the third gate pad.

[0045] According to some embodiments, the gate interconnect includes a first interconnect that connects a gate pin to a first gate pad, and a second interconnect that connects a gate pin to a third gate pad.

[0046] According to some embodiments, the gate interconnect includes a first interconnect that connects a gate pin to a first gate pad, and a second interconnect that connects the first gate pad to a third gate pad.

[0047] According to some embodiments, a first semiconductor die includes a first source pad, a second semiconductor die includes a second source pad, and the circuit board assembly includes a first source pin and a source interconnect that connects the first source pin to the first source pad and the second source pad.

[0048] According to some embodiments, the source interconnect includes a first interconnect that connects a first source pin to a first source pad, and a second interconnect that connects the first source pin to a second source pad.

[0049] According to some embodiments, the source interconnect includes a first interconnect that connects a first source pin to a first source pad, and a second interconnect that connects the first source pad to a second source pad.

[0050] According to some embodiments, the source interconnect includes a clamp that connects a first source pin to a first source pad and connects the first source pad to a second source pad.

[0051] According to some embodiments, the circuit board assembly includes a second source pin, wherein the source interconnect includes a clamp connecting the first source pin to a first source pad, connecting the first source pad to a second source pad, and connecting the second source pad to the second source pin.

[0052] According to some embodiments, a first semiconductor die includes a first sensing pad, a second semiconductor die includes a second sensing pad, and the circuit board assembly includes a first sensing pin, a second sensing pin, a first sensing interconnect connecting the first sensing pin to the first sensing pad, and a second sensing interconnect connecting the second sensing pin to the second sensing pad.

[0053] According to some embodiments, a method is provided. The method includes mounting a first semiconductor die in a first semiconductor package, the first semiconductor die including a first gate pad, a second gate pad, and a first gate ring connecting the first gate pad to the second gate pad. The method also includes mounting a second semiconductor die in a second semiconductor package, the second semiconductor die including a third gate pad, a fourth gate pad, and a second gate ring connecting the third gate pad to the fourth gate pad. Finally, the method includes connecting gate pins to the first gate pad and the third gate pad.

[0054] It is understood that combinations of one or more embodiments described herein (including combinations of embodiments described with respect to different figures) are considered herein.

[0055] Although the subject matter has been described using language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

[0056] Any aspect or design described herein as an "example" is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the word "example" is intended to illustrate one possible aspect and / or implementation of the technology presented herein. Such examples are not necessary for such technology or are intended to be limiting. Various embodiments of such technology may include such examples, alone or in combination with other features, and / or the examples shown may be modified and / or omitted.

[0057] As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or clearly seen from the context, “X adopts A or B” is intended to mean any natural inclusive arrangement. That is, “X adopts A or B” is satisfied in any of the foregoing instances if X adopts A; X adopts B; or X adopts both A and B. Additionally, the articles “a” and “an” as used herein and in the appended claims can generally be interpreted as meaning “one or more” unless otherwise stated or clearly pointed to from the context in the singular form. Furthermore, unless otherwise stated, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0058] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding of this specification and drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component performing the specified function of said component (e.g., functionally equivalent), even if the disclosed structure is not structurally equivalent to the function performed in the exemplary embodiments of this disclosure described herein. Additionally, while specific features of this disclosure may have been disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application. Furthermore, the use of the terms “comprising,” “containing,” “having,” “with,” and variations thereof in the Detailed Description or claims is intended to be inclusive in a manner similar to the term “comprising.”

[0059] Although the subject matter has been described with reference to illustrative embodiments, this specification is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, will be apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A device comprising: A transistor including a gate electrode; A first gate pad connected to the gate electrode; A second gate pad connected to the gate electrode; as well as A first gate ring connecting the first gate pad and the second gate pad.

2. The device according to claim 1, wherein: The first gate ring and the gate electrode comprise polysilicon.

3. The device according to claim 1, comprising: A second gate ring is located above the first gate ring, wherein: The first gate ring is connected to the second gate ring; The first gate ring and the gate electrode are formed in the first layer; and The second gate ring, the first gate pad, and the second gate pad are formed in a second layer above the first layer.

4. The device according to claim 3, comprising: A dielectric layer located between the first gate ring and the second gate ring.

5. The device according to claim 4, comprising: A first conductive via located in the dielectric layer, the first conductive via connecting the gate electrode to the first gate pad; as well as A second conductive via is located in the dielectric layer, the second conductive via connecting the first gate ring to the second gate ring.

6. The device according to claim 1, comprising: A protective layer located above the gate ring.

7. The device according to claim 6, comprising: A gate interconnect is formed on the protective layer and connects the first gate pad and the second gate pad.

8. The device according to claim 1, comprising: A third gate pad connected to the first gate ring and the gate electrode; as well as A fourth gate pad connected to the first gate ring and the gate electrode.

9. The device according to claim 1, comprising: Circuit board assembly, the circuit board assembly comprising: Gate pin; A first gate interconnect connecting the first gate pad and the gate pin; and A second gate interconnect connecting the second gate pad and the gate pin.

10. The device according to claim 1, comprising: Temperature sensing pads; as well as Circuit board assembly, the circuit board assembly comprising: Temperature sensing pin; as well as A temperature sensing interconnect connecting the temperature sensing pad and the temperature sensing pin.

11. A circuit board assembly, comprising: A first semiconductor package, the first semiconductor package including a first semiconductor die, the first semiconductor die including: First gate pad; The second gate pad; and Connect the first gate pad to the first gate ring of the second gate pad; A second semiconductor package, the second semiconductor package including a second semiconductor die, the second semiconductor die including: Third gate pad; Fourth gate pad; and Connect the third gate pad to the second gate ring of the fourth gate pad; Gate pin; and A gate interconnect that connects the gate pin to the first gate pad and the third gate pad.

12. The circuit board assembly of claim 11, wherein: The gate interconnect includes: Connect the gate pin to the first interconnect of the first gate pad; and The gate pin is connected to the second interconnect of the third gate pad.

13. The circuit board assembly of claim 11, wherein: The gate interconnect includes: Connect the gate pin to the first interconnect of the first gate pad; and The first gate pad is connected to the second interconnect of the third gate pad.

14. The circuit board assembly of claim 11, wherein: The first semiconductor die includes a first source pad; The second semiconductor die includes a second source pad; and The circuit board assembly includes: First source pin; as well as Connect the first source pin to the source interconnect of the first source pad and the second source pad.

15. The circuit board assembly of claim 14, wherein: The source interconnect includes: Connect the first source pin to the first interconnect of the first source pad; and Connect the first source pin to the second interconnect of the second source pad.

16. The circuit board assembly of claim 14, wherein: The source interconnect includes: Connect the first source pin to the first interconnect of the first source pad; and The first source pad is connected to the second source pad via a second interconnect.

17. The circuit board assembly of claim 14, wherein: The source interconnect includes: A clamp that connects the first source pin to the first source pad and connects the first source pad to the second source pad.

18. The circuit board assembly of claim 14, comprising: The second source pin, where The source interconnect includes: Connect the first source pin to the first source pad, connect the first source pad to the second source pad, and connect the second source pad to the clip of the second source pin.

19. The circuit board assembly of claim 11, wherein: The first semiconductor die includes a first sensing pad; The second semiconductor die includes a second sensing pad; and The circuit board assembly includes: First sensing pin; Second sensing pin; A first sensing interconnect connecting the first sensing pin to the first sensing pad; and The second sensing pin is connected to the second sensing pad via a second sensing interconnect.

20. A method comprising: A first semiconductor die is mounted in a first semiconductor package, the first semiconductor die comprising: First gate pad; The second gate pad; and Connect the first gate pad to the first gate ring of the second gate pad; A second semiconductor die is mounted in a second semiconductor package, the second semiconductor die comprising: Third gate pad; Fourth gate pad; and Connect the third gate pad to the second gate ring of the fourth gate pad; and Connect the gate pin to the first gate pad and the third gate pad.

Images