Manufacturing method of semiconductor device
By forming and etching dielectric layers during semiconductor device manufacturing, the process load effect caused by the height difference of hard mask layers is solved, achieving uniformity of film height and void-free dielectric layer filling.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-04-03
AI Technical Summary
In the semiconductor device manufacturing process, the process load effect caused by the height difference of the hard mask layer on top of the gate affects the uniformity of the film height in subsequent processes.
By forming and etching a first dielectric layer between the gates, followed by etching back the hard mask layer, and finally forming a covering second dielectric layer, height differences are eliminated and void formation is avoided.
It eliminates the process load effect caused by the height difference of the hard mask layer, ensures the flatness and consistency of subsequent film layers, and avoids the occurrence of voids in the dielectric layer.
Smart Images
Figure CN121793428A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for manufacturing a semiconductor device. Background Technology
[0002] In the manufacturing process of semiconductor devices, a hard mask layer is usually placed on top of the gate. However, when forming a germanium-silicon epitaxial layer in the substrate, the substrate usually needs to be etched first to form a germanium-silicon trench, and then the germanium-silicon epitaxial layer is formed through the germanium-silicon trench. However, during the formation of the germanium-silicon trench, the consumption of the hard mask layer on top of the gate in different areas has a loading effect, which leads to differences in the height of the hard mask layer on top of the gate in different areas. In subsequent processes, the height difference of the hard mask layer will cause differences in the height of the film layer in subsequent processes, etc. Therefore, it is necessary to eliminate this height difference. Summary of the Invention
[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor device to eliminate the process load effect caused by the height difference of the hard mask layer on top of the gate.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0005] A substrate is provided, wherein a first gate and a second gate are formed therebetween, a first hard mask layer is formed on both the first gate and the second gate, and the top surface of the first hard mask layer on the second gate is higher than the top surface of the first hard mask layer on the first gate.
[0006] A first dielectric layer is formed, which fills the space between the first gate and the second gate and extends to cover the first hard mask layer, wherein the top surface of the first dielectric layer on the second gate is higher than the top surface of the first dielectric layer on the first gate.
[0007] The first dielectric layer on the second gate is etched to remove the first dielectric layer on the second gate;
[0008] The first dielectric layer and the first hard mask layer are etched back to sequentially remove the first dielectric layer and the first hard mask layer on the first gate, and a portion of the thickness of the first dielectric layer between the first gate and the second gate is removed to expose the voids in the first dielectric layer.
[0009] A second dielectric layer is formed, which fills the voids and covers the first dielectric layer.
[0010] Optionally, in the method for manufacturing the semiconductor device, the method for forming the first dielectric layer includes:
[0011] A first etch stop layer is formed, which is located on the sidewalls of the first gate and the second gate, and extends to cover the first hard mask layer and the substrate;
[0012] The first dielectric layer is formed on the first etch stop layer using a high aspect ratio process.
[0013] Optionally, in the semiconductor device manufacturing method, the sidewalls of the first gate and the second gate are each formed with a first sidewall and a second sidewall, and the second sidewall covers the first sidewall.
[0014] Before forming the first etch stop layer, the second sidewall is removed to expose the first sidewall;
[0015] After the first etch stop layer is formed, the first etch stop layer covers the first sidewall.
[0016] Optionally, in the method for manufacturing the semiconductor device, the method for etching the first dielectric layer on the second gate includes:
[0017] A second etch stop layer is formed, which covers the surface of the first dielectric layer, wherein the material of the second etch stop layer is titanium nitride;
[0018] A patterned photoresist layer is formed on the second etch stop layer, the patterned photoresist layer exposing the second etch stop layer on the second gate;
[0019] Using the patterned photoresist layer as a mask, the exposed second etch stop layer is etched to expose a portion of the first dielectric layer;
[0020] Remove the patterned photoresist layer to expose the remaining second etch stop layer;
[0021] Using the remaining second etch stop layer as a mask, the exposed first dielectric layer is etched up to the top surface of the first etch stop layer.
[0022] Optionally, in the method for manufacturing the semiconductor device, the method for etching back the first dielectric layer and the first hard mask layer includes:
[0023] The remaining second etch stop layer is removed by a wet etching process to expose the remaining first dielectric layer;
[0024] The first dielectric layer, the first etch stop layer, and the first hard mask layer are etched using a dry etching process to remove a portion of the thickness of the first dielectric layer, and to remove the first etch stop layer and the first hard mask layer from the surface of the first hard mask layer.
[0025] Optionally, in the method for manufacturing the semiconductor device, the method for forming the second dielectric layer includes:
[0026] A second dielectric material layer is formed, which fills the voids and covers the first dielectric layer, the first gate, and the second gate.
[0027] A chemical mechanical polishing process is performed on the second dielectric material layer to form a second dielectric layer, the top surface of the second dielectric layer being flush with the top surface of the first gate and the top surface of the second gate.
[0028] Optionally, in the semiconductor device manufacturing method, the second dielectric material layer is formed by a high aspect ratio process.
[0029] Optionally, in the semiconductor device manufacturing method, a second hard mask layer is formed on the top surface of both the first gate and the top surface of the second gate, and the second hard mask layer is removed during the chemical mechanical polishing process.
[0030] Optionally, in the semiconductor device manufacturing method, the substrate includes a first region and a second region, the first gate is formed on the first region, and the second gate is formed on the second region.
[0031] Optionally, in the semiconductor device manufacturing method, a germanium-silicon epitaxial layer is formed in the first region on the first gate side, or a germanium-silicon epitaxial layer is formed in both the first region on the first gate side and the second region on the second gate side.
[0032] In the semiconductor device manufacturing method provided by this invention, a first dielectric layer is first formed, which fills the space between a first gate and a second gate and extends to cover a first hard mask layer. The top surface of the first dielectric layer on the second gate is higher than the top surface of the first dielectric layer on the first gate. Then, the first dielectric layer on the second gate is etched to remove it. Next, the first dielectric layer and the first hard mask layer are etched back to remove them, and a portion of the thickness of the first dielectric layer between the first gate and the second gate is removed to expose voids in the first dielectric layer. Afterward, a second dielectric layer is formed, which fills the voids and covers the first dielectric layer. This eliminates the process load effect caused by the height difference of the first hard mask layer at the top of the gate, avoids height differences on the surface of the subsequently formed second dielectric layer, and allows the second dielectric layer to fill the voids in the first dielectric layer, thereby preventing voids in the dielectric layer. Attached Figure Description
[0033] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0034] Figures 2 to 14 This is a schematic diagram of the structure formed in the manufacturing method of the semiconductor device according to an embodiment of the present invention;
[0035] The reference numerals in the attached figures are explained as follows:
[0036] 100 - Substrate; 100a - First region; 1001 - nFET region; 1002 - pFET region; 100b - Second region; 101 - Germanium-silicon epitaxial layer; 102 - First gate; 103 - Second gate; 104 - First sidewall; 105 - Second sidewall; 106 - First hard mask layer; 107 - Second hard mask layer;
[0037] 110 - First etch stop layer; 120 - First dielectric layer; 130 - Second etch stop layer; 140 - Photoresist layer; 140a - Patterned photoresist layer; 150 - Second dielectric material layer; 150a - Second dielectric layer. Detailed Implementation
[0038] The manufacturing method of the semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales.
[0039] Figure 1 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention. Figure 1 As shown, the semiconductor device manufacturing method provided in this embodiment includes:
[0040] Step S1: Provide a substrate, wherein a first gate and a second gate are formed on the substrate at intervals, a first hard mask layer is formed on both the first gate and the second gate, and the top surface of the first hard mask layer on the second gate is higher than the top surface of the first hard mask layer on the first gate.
[0041] Step S2: Form a first dielectric layer, which fills the space between the first gate and the second gate and extends to cover the first hard mask layer. The top surface of the first dielectric layer on the second gate is higher than the top surface of the first dielectric layer on the first gate.
[0042] Step S3: Etch the first dielectric layer on the second gate to remove the first dielectric layer on the second gate;
[0043] Step S4: Etch back the first dielectric layer and the first hard mask layer to sequentially remove the first dielectric layer and the first hard mask layer on the first gate, and remove a portion of the thickness of the first dielectric layer between the first gate and the second gate to expose the voids in the first dielectric layer.
[0044] Step S5: Form a second dielectric layer, which fills the voids and covers the first dielectric layer.
[0045] Figures 2-14 This is a schematic diagram of the structure formed in the manufacturing method of the semiconductor device provided in the embodiments of the present invention. The following will refer to the accompanying drawings. Figures 2-14 The manufacturing method of the semiconductor device provided in this embodiment will be described in more detail.
[0046] like Figure 2 As shown, in step S1, a substrate 100 is provided. The substrate 100 has a first gate 102 and a second gate 103 spaced apart. A first hard mask layer 106 is formed on both the first gate 102 and the second gate 103, and the top surface of the first hard mask layer 106 on the second gate 103 is higher than the top surface of the first hard mask layer 106 on the first gate 102. The substrate 100 can be made of silicon.
[0047] In this embodiment, the substrate 100 includes a first region 100a and a second region 100b, the first gate 102 is formed on the first region 100a, and the second gate 103 is formed on the second region 100b.
[0048] In some embodiments, both the first region 100a and the second region 100b are pMOS regions, meaning the first gate and the second gate are formed on different pMOS regions, which can form an SRAM (Dynamic Random Access Memory) device. The first gate and the second gate are used to form the pMOS device, and germanium-silicon epitaxial layers are formed in both the first region on the side of the first gate and the second region on the side of the second gate. The germanium-silicon epitaxial layers are obtained by forming germanium-silicon trenches in the substrate 100 of the first region 100a and the substrate 100 of the second region, and then filling the formed germanium-silicon trenches with germanium-silicon epitaxial material.
[0049] During the formation of the front-end germanium-silicon trench, the first hard mask layer 106 is consumed. Due to the load effect, the first hard mask layers on different gates have a height difference, that is, the top surface of the first hard mask layer 106 on the second gate 103 is higher than the top surface of the first hard mask layer 106 on the first gate 102.
[0050] In some embodiments, the first region 100a is a core region used to form core devices; the second region 100b is an input / output device region used to form input / output devices. In this embodiment, the first region 100a is used as the core region and the second region 100b as the input / output device region for illustration. The first region 100a includes an nFET region 1001 and a pFET region 1002.
[0051] like Figure 2 As shown, the first gate 102 is formed on the first region 100a, and a germanium-silicon epitaxial layer 101 is formed in the first region 100a on one side of the first gate 102. The germanium-silicon epitaxial layer 101 is obtained by forming a germanium-silicon trench in the substrate 100 of the first region 100a, and then filling the formed germanium-silicon trench with germanium-silicon epitaxial material.
[0052] Figure 2 The diagram shows two first gates 102 located in the first region 100a. One of the first gates 102 can be the gate of the nFET region 1001, and the other first gate 102 can be the gate of the pFET region 1002. A germanium-silicon epitaxial layer 101 is formed in the substrate on the side of the gate of the pFET region 1002 near the second region 100b, that is, the germanium-silicon epitaxial layer 101 is formed in the pFET region 1002.
[0053] The second gate 103 is formed on the second region 100b, and the width of the second gate 103 may be greater than the width of the first gate 102. Both the first gate 102 and the second gate 103 are made of polysilicon, and both the first gate 102 and the second gate 103 can be dummy gates. (Continue to refer to...) Figure 2 As shown, the sidewalls of the first gate 102 and the second gate 103 are each formed with a first sidewall 104 and a second sidewall 105, and the second sidewall 105 covers the first sidewall 104.
[0054] Furthermore, the first sidewall 104 may extend in the thickness direction to cover a portion of the sidewall of the first hard mask layer 106.
[0055] In this embodiment, the first hard mask layer 106 is made of silicon nitride. During the formation of the front-end germanium-silicon trench, the first hard mask layer 106 is consumed. Due to the loading effect, the consumption of the first hard mask layer 106 on the second gate 103 is greater than that on the first gate 102. That is, the consumption of the first hard mask layer 106 in the first region 100a is greater than that in the device region 100b, resulting in a difference in the height of the first hard mask layer. Therefore, the top surface of the first hard mask layer 106 on the second gate 103 is higher than that on the first gate 102.
[0056] Furthermore, since the germanium-silicon trench is formed in the pFET region 1002, during the formation of the germanium-silicon trench, due to the loading effect, there is a problem of one-sided consumption of the first hard mask layer. That is, the consumption of the first hard mask layer in the pFET region 1002 is greater than the consumption of the first hard mask layer in the nFET region 1001. Therefore, the thickness of the first hard mask layer in the pFET region 1002 is less than the thickness of the first hard mask layer in the nFET region 1001. As a result, the top surface of the first hard mask layer in the pFET region 1002 is lower than the top surface of the first hard mask layer in the nFET region 1001.
[0057] Optionally, a second hard mask layer 107 is formed on the top surface of the first gate 102 and the top surface of the second gate 103. The second hard mask layer 107 is made of silicon nitride, and the first hard mask layer 106 is located on the second hard mask layer 107.
[0058] Next, as Figure 5As shown, step S2 is performed to form a first dielectric layer 120. The first dielectric layer 120 fills the space between the first gate 102 and the second gate 103 and extends to cover the first hard mask layer 106. The top surface of the first dielectric layer 120 on the second gate 103 is higher than the top surface of the first dielectric layer 120 on the first gate 102.
[0059] Specifically, the method for forming the first dielectric layer 120 includes: firstly, as... Figure 3 As shown, the second sidewall 105 is removed to expose the first sidewall 104; wherein the second sidewall 105 is removed by a wet etching process, wherein the solution used in the wet etching process is phosphoric acid.
[0060] Then, as Figure 4 As shown, a first etch stop layer 110 is formed. The first etch stop layer 110 can be made of silicon nitride and is used as a film layer to stop the etching during subsequent etching of the first dielectric layer 120. The first etch stop layer 110 is located on the sidewall of the first gate 102 and the sidewall of the second gate 103, and extends to cover the first hard mask layer 106 and the substrate 100. That is, the first etch stop layer 110 covers the first sidewall 104, the first hard mask layer 106, and the exposed substrate 100. Furthermore, the first etch stop layer 110 also extends to cover the germanium-silicon epitaxial layer 101.
[0061] Next, as Figure 5 As shown, the first dielectric layer 120 is formed on the first etch stop layer 110 using a high aspect ratio process (HARP), meaning the first dielectric layer 120 covers the first etch stop layer 110, and the top surface of the first dielectric layer 120 is higher than the top surface of the first etch stop layer 110 on the first hard mask layer 106. Since the top surface of the first hard mask layer 106 on the second gate 103 is higher than the top surface of the first hard mask layer 106 on the first gate 102, the top surface of the first dielectric layer 120 on the second gate 103 is higher than the top surface of the first dielectric layer 120 on the first gate 102.
[0062] Next, as Figure 10 As shown, step S3 is performed to etch the first dielectric layer 120 on the second gate 103 to remove the first dielectric layer 120 on the second gate 103.
[0063] In this embodiment, the method for etching the first dielectric layer 120 on the second gate 103 includes:
[0064] Step 1, as follows Figure 6As shown, a second etch stop layer 130 is formed, which covers the surface of the first dielectric layer 120. The material of the second etch stop layer 130 is titanium nitride (TiN).
[0065] Step two, as Figure 8 As shown, a patterned photoresist layer 140a is formed on the second etch stop layer 130, and the patterned photoresist layer 140a exposes the second etch stop layer 130 on the second gate 103.
[0066] Specifically, the method for forming the patterned photoresist layer 140a includes: as follows Figure 7 As shown, a photoresist layer 140 is first formed on the second etch stop layer 130; as Figure 8 As shown, the photoresist layer 140 is sequentially exposed and developed to form a patterned photoresist layer 140a.
[0067] Next, as Figure 9 As shown, using the patterned photoresist layer 140a as a mask, a dry etching process is used to etch the exposed second etch stop layer 130 to expose part of the first dielectric layer 120, that is, to expose the first dielectric layer 120 on the second gate 103.
[0068] Next, the patterned photoresist layer 140a is removed, exposing the remaining second etch stop layer 130.
[0069] After that, as Figure 10 As shown, using the remaining second etch stop layer 130 as a mask, a dry etching process is used to etch the exposed first dielectric layer 120 until the first etch stop layer 110 is exposed. That is, the area with a higher top surface in the first dielectric layer 120 is etched, and the etching stops at the top surface of the first etch stop layer (CESL) 110. In other words, during the process of etching the exposed first dielectric layer 120 using a dry etching process, the dry etching stops at the top surface of the first etch stop layer 110. The first etch stop layer 110 serves as the stop layer for the dry etching process, thereby reducing the height of the top surface of the first dielectric layer 120 on the second gate and eliminating most of the loading effect.
[0070] Next, as Figure 12 As shown, step S4 is performed to etch back the first dielectric layer 120 and the first hard mask layer 106 to sequentially remove the first dielectric layer 120 and the first hard mask layer 106 on the first gate 102, and to remove a portion of the thickness of the first dielectric layer 120 between the first gate 102 and the second gate 103 to expose the voids in the first dielectric layer 120.
[0071] Specifically, the method for back etching of the first dielectric layer 120 and the first hard mask layer 106 includes: as follows Figure 11 As shown, the remaining second etch stop layer 130 is removed by a wet etching process to expose the remaining first dielectric layer 120.
[0072] After that, as Figure 12 As shown, the first dielectric layer 120, the first etch stop layer 110, and the first hard mask layer 106 are etched by a dry etching process to sequentially remove a portion of the thickness of the first dielectric layer 120, and to remove the first etch stop layer 110 and the first hard mask layer 106 from the surface of the first hard mask layer 106.
[0073] Next, as Figure 14 As shown, step S5 is performed to form a second dielectric layer 150a. The second dielectric layer 150a fills the voids and covers the first dielectric layer 120. This eliminates the process load effect caused by the height difference of the first hard mask layer 106, avoids height differences on the surface of the subsequently formed second dielectric layer 150a, and fills the voids in the first dielectric layer 120, thereby preventing voids in the dielectric layer.
[0074] In this embodiment, the method for forming the second dielectric layer 150a includes: firstly, as... Figure 13 As shown, a second dielectric material layer 150 is formed, which fills the voids and covers the first dielectric layer 120, the first gate 102, and the second gate 103; wherein, the second dielectric material layer 150 can be formed by a high aspect ratio process. The thickness of the second dielectric material layer can be 1500 angstroms to 2000 angstroms.
[0075] Then, as Figure 14 As shown, a chemical mechanical polishing process is performed on the second dielectric material layer 150 to form a second dielectric layer 150a, the top surface of the second dielectric layer 150a being flush with the top surface of the first gate 102 and the top surface of the second gate 103.
[0076] In addition, such as Figure 14 As shown, during the chemical mechanical polishing process, the second hard mask layer 107, a portion of the first sidewall 104, and a portion of the first etch stop layer 110 are also removed.
[0077] In summary, in the semiconductor device manufacturing method provided by the embodiments of the present invention, a first dielectric layer is formed, which fills the space between a first gate and a second gate and extends to cover a first hard mask layer. The top surface of the first dielectric layer on the second gate is higher than the top surface of the first dielectric layer on the first gate. Then, the first dielectric layer on the second gate is etched to remove it. The first dielectric layer and the first hard mask layer are etched back to remove them, and a portion of the thickness of the first dielectric layer between the first gate and the second gate is removed to expose voids in the first dielectric layer. A second dielectric layer is then formed, which fills the voids and covers the first dielectric layer. This eliminates the process load effect caused by the height difference of the first hard mask layer at the top of the gate, avoids a height difference on the surface of the subsequently formed second dielectric layer, and allows the second dielectric layer to fill the voids in the first dielectric layer, thereby preventing voids in the dielectric layer.
[0078] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0079] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein a first gate and a second gate are formed therebetween, a first hard mask layer is formed on both the first gate and the second gate, and the top surface of the first hard mask layer on the second gate is higher than the top surface of the first hard mask layer on the first gate. A first dielectric layer is formed, which fills the space between the first gate and the second gate and extends to cover the first hard mask layer, wherein the top surface of the first dielectric layer on the second gate is higher than the top surface of the first dielectric layer on the first gate. The first dielectric layer on the second gate is etched to remove the first dielectric layer on the second gate; The first dielectric layer and the first hard mask layer are etched back to sequentially remove the first dielectric layer and the first hard mask layer on the first gate, and a portion of the thickness of the first dielectric layer between the first gate and the second gate is removed to expose the voids in the first dielectric layer. A second dielectric layer is formed, which fills the voids and covers the first dielectric layer.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The method for forming the first dielectric layer includes: A first etch stop layer is formed, which is located on the sidewalls of the first gate and the second gate, and extends to cover the first hard mask layer and the substrate; The first dielectric layer is formed on the first etch stop layer using a high aspect ratio process.
3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, Both the sidewall of the first gate and the sidewall of the second gate are formed with a first sidewall and a second sidewall, and the second sidewall covers the first sidewall; Before forming the first etch stop layer, the second sidewall is removed to expose the first sidewall; After the first etch stop layer is formed, the first etch stop layer covers the first sidewall.
4. The method for manufacturing a semiconductor device as described in claim 3, characterized in that, The method for etching the first dielectric layer on the second gate includes: A second etch stop layer is formed, which covers the surface of the first dielectric layer, wherein the material of the second etch stop layer is titanium nitride; A patterned photoresist layer is formed on the second etch stop layer, the patterned photoresist layer exposing the second etch stop layer on the second gate; Using the patterned photoresist layer as a mask, the exposed second etch stop layer is etched to expose a portion of the first dielectric layer; Remove the patterned photoresist layer to expose the remaining second etch stop layer; Using the remaining second etch stop layer as a mask, the exposed first dielectric layer is etched up to the top surface of the first etch stop layer.
5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The method for etching back the first dielectric layer and the first hard mask layer includes: The remaining second etch stop layer is removed by a wet etching process to expose the remaining first dielectric layer; The first dielectric layer, the first etch stop layer, and the first hard mask layer are etched using a dry etching process to remove a portion of the thickness of the first dielectric layer, and to remove the first etch stop layer and the first hard mask layer from the surface of the first hard mask layer.
6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The method for forming the second dielectric layer includes: A second dielectric material layer is formed, which fills the voids and covers the first dielectric layer, the first gate, and the second gate. A chemical mechanical polishing process is performed on the second dielectric material layer to form a second dielectric layer, the top surface of the second dielectric layer being flush with the top surface of the first gate and the top surface of the second gate.
7. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The second dielectric material layer is formed using a high aspect ratio process.
8. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, A second hard mask layer is formed on the top surface of both the first gate and the second gate. The second hard mask layer is also removed during the chemical mechanical polishing process.
9. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The substrate includes a first region and a second region, wherein the first gate is formed on the first region and the second gate is formed on the second region.
10. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, A germanium-silicon epitaxial layer is formed in the first region on one side of the first gate, or a germanium-silicon epitaxial layer is formed in both the first region on one side of the first gate and the second region on one side of the second gate.