Array substrate and display panel

Abstract

The embodiment of the invention discloses an array substrate and a display panel, the array substrate comprises at least one pixel circuit, the pixel circuit comprises a driving transistor and at least one switching transistor, and the switching transistor comprises a first transistor; the array substrate further comprises a substrate and an active layer. The channel region of the driving transistor and the channel region of the first transistor are both located on the active layer. The first electrode of the first transistor is connected with the gate of the driving transistor; among all the switching transistors and the driving transistors of the same pixel circuit, the area of the channel region of the first transistor is the smallest. In all the transistors of the same pixel circuit, the area of the channel region of the first transistor connected with the grid electrode of the driving transistor is set to be minimum, so that the size of the first transistor is reduced, the voltage difference between the two ends of the first transistor is reduced, and the leakage current of the first transistor is reduced; therefore, the grid voltage of the driving transistor can be kept stable, the low-frequency flicker phenomenon can be improved, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the display performance of display panels.

[0003] Currently, the display panel suffers from poor display quality. Summary of the Invention

[0004] This invention provides an array substrate and a display panel to improve display performance.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate including at least one pixel circuit, the pixel circuit including a driving transistor and at least one switching transistor, the switching transistor including a first transistor; the array substrate further includes:

[0006] Substrate;

[0007] An active layer is located on one side of the substrate, and the channel regions of the driving transistor and the first transistor are both located in the active layer; the first electrode of the first transistor is connected to the gate of the driving transistor.

[0008] Among all the switching transistors and driving transistors in the same pixel circuit, the channel region of the first transistor has the smallest area.

[0009] Optionally, the channel region of the first transistor extends along a first direction, and the ratio of the size of the channel region of the first transistor in the second direction to the size of the channel region of the first transistor in the first direction is between 0.17 and 1.1; wherein the first direction intersects the second direction.

[0010] Optionally, the channel region of the first transistor has a size of 2 μm to 3 μm in the first direction and a size of 0.5 μm to 2.2 μm in the second direction;

[0011] Optionally, the dimension of the channel region of the first transistor in the first direction is larger than the dimension of the channel region of the first transistor in the second direction.

[0012] Optionally, the array substrate further includes a multilayer conductive layer stacked on the side of the active layer away from the substrate, the multilayer conductive layer including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate; at least one pixel circuit, the pixel circuit including a driving transistor and at least one switching transistor, the switching transistor including the first transistor; the array substrate further includes:

[0013] Substrate;

[0014] An active layer is located on one side of the substrate, and the channel regions of the driving transistor and the first transistor are both located in the active layer; the first electrode of the first transistor is connected to the gate of the driving transistor.

[0015] Among all the switching transistors and driving transistors in the same pixel circuit, the channel region of the first transistor has the smallest area.

[0016] The array substrate also includes a power line, and the pixel circuit also includes a first capacitor. The first plate of the first capacitor is located on the first conductive layer, and the second plate of the first capacitor is located on the second conductive layer. The first plate of the first capacitor is connected to the gate of the driving transistor, and the second plate of the first capacitor is connected to the power line.

[0017] Optionally, the first plate of the first capacitor is reused as the gate of the driving transistor;

[0018] Optionally, the second plate of the first capacitor extends along a second direction, and the orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

[0019] Optionally, the power cord includes a first sub-wire and a second sub-wire, the first sub-wire extending along a second direction and the second sub-wire extending along a first direction, and at the intersection of the first sub-wire and the second sub-wire, the second sub-wire is connected to the first sub-wire through a first via.

[0020] Optionally, at the intersection of the first sub-line and the second sub-line, at least two first vias are included;

[0021] Optionally, the multilayer conductive layer further includes a third conductive layer, which is located on the side of the second conductive layer away from the substrate, with the first sub-line located in the second conductive layer and the second sub-line located in the third conductive layer.

[0022] Optionally, the first sub-line is reused as the second plate of the first capacitor.

[0023] Optionally, the power line further includes a third sub-line extending along a first direction, the orthographic projection of the third sub-line on the substrate at least partially overlapping the orthographic projection of the second sub-line on the substrate, and at the overlapping position of the third sub-line and the second sub-line, the third sub-line is connected to the second sub-line through a second via.

[0024] Optionally, the orthogonal projection of the third sub-line onto the substrate covers the orthogonal projection of the channel region of the first transistor onto the substrate;

[0025] Optionally, the edge of the orthogonal projection of the third sub-line onto the substrate extends at least 2 μm beyond the edge of the orthogonal projection of the channel region of the first transistor onto the substrate;

[0026] Optionally, the multilayer conductive layer further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate, and the third sub-line is located in the fourth conductive layer;

[0027] Optionally, the orthographic projection of the second sub-line onto the substrate is separated from the orthographic projection of the channel region of the first transistor onto the substrate.

[0028] Optionally, the array substrate further includes a reference voltage signal line, and the pixel circuit further includes a second capacitor, the first plate of the second capacitor being connected to the reference voltage signal line, and the second plate of the second capacitor being connected to the second electrode of the first transistor.

[0029] Optionally, the first plate of the second capacitor is located in the second conductive layer, and the second plate of the second capacitor is located in the active layer.

[0030] Optionally, the reference voltage signal line extends along a second direction;

[0031] Optionally, the reference voltage signal line is multiplexed as the first plate of the second capacitor;

[0032] Optionally, at the intersection of the reference voltage signal line and the active layer, the size of the active layer extending at least partially along the second direction in the first direction is larger than the size of the channel region of the first transistor in the second direction.

[0033] Optionally, the array substrate further includes a first gate signal line extending along a second direction, the channel region of the first transistor being located at the first overlap position of the active layer and the first gate signal line, and the first electrode of the first transistor being connected to the gate of the driving transistor through a gate connection portion.

[0034] Optionally, the first electrode of the first transistor is connected to one end of the gate connection portion through a third via, and the gate of the driving transistor is connected to the other end of the gate connection portion through a fourth via.

[0035] Optionally, the array substrate further includes a second gate signal line and a first initialization signal line, and the switching transistor further includes a second transistor and a third transistor. The channel region of the second transistor is located at the second overlap position between the active layer and the first gate signal line, and the channel region of the third transistor is located at the overlap position between the active layer and the second gate signal line. The first electrode of the second transistor is connected to the second electrode of the first transistor, the second electrode of the second transistor is connected to the first electrode of the third transistor, and the second electrode of the third transistor is connected to the first initialization signal line through a first connection line.

[0036] Optionally, the second terminal of the third transistor is connected to one end of the first connection line through the fifth via, and the first initialization signal line is connected to the other end of the first connection line through the sixth via.

[0037] Optionally, the first initialization signal line extends along a first direction;

[0038] Optionally, the multilayer conductive layer further includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located on the side of the second conductive layer away from the substrate, the fourth conductive layer is located on the side of the third conductive layer away from the substrate, the first initialization signal line is located on the fourth conductive layer, and the first connection line is located on the third conductive layer.

[0039] Optionally, the orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the second gate signal line on the substrate.

[0040] Optionally, both the first gate signal line and the second gate signal line are located in the first conductive layer;

[0041] Optionally, the orthogonal projection of the second gate signal line on the substrate is located on the side where the orthogonal projection of the first gate signal line on the substrate is far away from the orthogonal projection of the gate of the driving transistor on the substrate.

[0042] Optionally, the first gate signal line includes a main body and a branch, the channel region of the first transistor is located at the orthographic projection position of the main body of the first gate signal line in the active layer, and the channel region of the second transistor is located at the orthographic projection position of the branch of the first gate signal line in the active layer.

[0043] Optionally, the channel region of the second transistor extends along the second direction;

[0044] Optionally, the second gate signal line includes a main body and a branch, and the channel region of the third transistor is located at the orthographic projection position of the branch of the second gate signal line onto the active layer.

[0045] Optionally, the channel region of the third transistor extends along the second direction;

[0046] Optionally, the branch of the first gate signal line extends towards the branch of the second gate signal line.

[0047] Optionally, at least one pixel circuit includes a first pixel circuit and a second pixel circuit that are adjacent and mirrored, wherein the orthographic projection of the first initialization signal line in the first pixel circuit onto the substrate and the orthographic projection of the first initialization signal line in the second pixel circuit onto the substrate do not overlap at least partially.

[0048] Optionally, at the connection position between the first connection line and the first initialization signal line, the first connection line in the first pixel circuit and the first connection line in the second pixel circuit share the same sixth via to connect to the corresponding first initialization signal line;

[0049] Optionally, the first initialization signal line includes a first sub-segment and a second sub-segment connected alternately in sequence. The orthographic projection of the first sub-segment of the first initialization signal line in the first pixel circuit on the substrate coincides with the orthographic projection of the first sub-segment of the first initialization signal line in the second pixel circuit on the substrate, and the orthographic projection of the second sub-segment of the first initialization signal line in the first pixel circuit on the substrate is separate from the orthographic projection of the second sub-segment of the first initialization signal line in the second pixel circuit on the substrate.

[0050] Optionally, the orthographic projection of the connection point between the first sub-segment and the second sub-segment on the substrate at least partially overlaps with the orthographic projection of the sixth via used by the first connection line to connect the first initialization signal line on the substrate;

[0051] Optionally, the orthogonal projection of the second segment onto the substrate at least partially covers the orthogonal projection of the active layer onto the substrate.

[0052] Optionally, the array substrate further includes a third gate signal line, and the switching transistor further includes a fourth transistor and a fifth transistor. The channel region of the fourth transistor is located at the third overlap position between the active layer and the first gate signal line, and the channel region of the fifth transistor is located at the first overlap position between the active layer and the third gate signal line. The first terminal of the fourth transistor is connected to the second terminal of the first transistor, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, and the second terminal of the fifth transistor is connected to the second terminal of the driving transistor.

[0053] Optionally, the channel regions of the fourth transistor and the fifth transistor both extend along the first direction and are on the same straight line;

[0054] Optionally, the orthographic projection of the first initialization signal line on the substrate at least partially covers the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the fifth transistor on the substrate.

[0055] Optionally, the orthogonal projection of the third gate signal line on the substrate is located between the orthogonal projection of the first gate signal line on the substrate and the orthogonal projection of the gate of the driving transistor on the substrate.

[0056] Optionally, the orthographic projection of the third gate signal line on the substrate and the orthographic projection of the first gate signal line on the substrate are located on the same side of the orthographic projection of the gate of the driving transistor on the substrate.

[0057] Optionally, the array substrate also includes a data line, and the switching transistor also includes a sixth transistor. The channel region of the sixth transistor is located at the second overlap position between the active layer and the third gate signal line. The first electrode of the sixth transistor is connected to the data line through a second connection line, and the second electrode of the sixth transistor is connected to the first electrode of the driving transistor.

[0058] Optionally, the first terminal of the sixth transistor is connected to one end of the second connection line through the seventh via, and the data line is connected to the other end of the second connection line through the eighth via.

[0059] Optionally, the data line is located on the fourth conductive layer;

[0060] Optionally, the data cable extends along the first direction;

[0061] Optionally, in the fourth conductive layer, the orthographic projection of the power line onto the substrate is located between the orthographic projection of the first initialization signal line onto the substrate and the orthographic projection of the data line onto the substrate.

[0062] Optionally, the array substrate further includes a fourth gate signal line, and the switching transistor further includes a seventh transistor and an eighth transistor. The channel region of the seventh transistor is located at the first overlap position between the active layer and the fourth gate signal line, and the channel region of the eighth transistor is located at the second overlap position between the active layer and the fourth gate signal line. The first electrode of the seventh transistor is connected to the power supply line, and the second electrode of the seventh transistor is connected to the first electrode of the driving transistor through a third connection line. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode of the eighth transistor is connected to the light-emitting element.

[0063] Optionally, the second terminal of the seventh transistor is connected to one end of the third connection line through the ninth via, and the first terminal of the driving transistor is connected to the other end of the third connection line through the tenth via.

[0064] Optionally, the fourth gate signal line includes a main body and a branch, the channel region of the seventh transistor is located at the intersection of the active layer and the main body of the fourth gate signal line, and the channel region of the eighth transistor is located at the intersection of the active layer and the branch of the fourth gate signal line.

[0065] Optionally, the orthographic projection of the third connection line on the substrate and the orthographic projection of the main body of the fourth gate signal line on the substrate are arranged to intersect;

[0066] Optionally, the third connection line is located in the third conductive layer, and the fourth gate signal line is located in the first conductive layer;

[0067] Optionally, the orthogonal projection of the fourth gate signal line on the substrate is located on the side where the orthogonal projection of the gate of the driving transistor on the substrate is far from the orthogonal projection of the first gate signal line on the substrate.

[0068] Optionally, the orthographic projection of the fourth gate signal line on the substrate and the orthographic projection of the first gate signal line on the substrate are located on different sides of the orthographic projection of the gate of the driving transistor on the substrate.

[0069] Optionally, the array substrate further includes a fifth gate signal line and a second initialization signal line, and the switching transistor further includes a ninth transistor. The channel region of the ninth transistor is located at the first overlap position between the active layer and the fifth gate signal line. The first electrode of the ninth transistor is connected to the second initialization signal line, and the second electrode of the ninth transistor is connected to the light-emitting element.

[0070] Optionally, the orthographic projection of the fifth gate signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate are located on the same side of the orthographic projection of the gate of the driving transistor on the substrate.

[0071] Optionally, the fifth gate signal line is located in the first conductive layer, and the second initialization signal line is located in the second conductive layer;

[0072] Optionally, both the fifth gate signal line and the second initialization signal line extend along the second direction;

[0073] Optionally, the orthographic projection of the first initialization signal line on the substrate intersects with the orthographic projection of the second initialization signal line on the substrate.

[0074] Optionally, the orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the fifth gate signal line on the substrate and the orthographic projection of the fourth gate signal line on the substrate.

[0075] Optionally, the orthographic projection of the second initialization signal line on the substrate is separated from the orthographic projection of the fifth gate signal line on the substrate;

[0076] Optionally, the first terminal of the ninth transistor is connected to the second initialization signal line via the fourth connection line;

[0077] Optionally, the first terminal of the ninth transistor is connected to one end of the fourth connection line through the eleventh via, and the second initialization signal line is connected to the other end of the fourth connection line through the twelfth via.

[0078] Optionally, the orthographic projection of the fourth connection line on the substrate intersects with the orthographic projection of the fifth gate signal line on the substrate.

[0079] Optionally, at least one pixel circuit includes a first pixel circuit and a second pixel circuit that are adjacent and mirror-arranged, wherein the first terminal of the ninth transistor in the first pixel circuit is connected to the first terminal of the ninth transistor in the second pixel circuit, and the first pixel circuit and the second pixel circuit share the same fourth connection line.

[0080] Optionally, the array substrate further includes a reference voltage signal line, and the switching transistor further includes a tenth transistor. The channel region of the tenth transistor is located at the second overlap position of the active layer and the fifth gate signal line. The first terminal of the tenth transistor is connected to the reference voltage signal line of the next row of pixel circuits, and the second terminal of the tenth transistor is connected to the first terminal of the driving transistor of the current row of pixel circuits.

[0081] Optionally, the first terminal of the tenth transistor is connected to the reference voltage signal line via the fifth connection line, and the second terminal of the tenth transistor is connected to the first terminal of the driving transistor via the third connection line.

[0082] Optionally, the first terminal of the tenth transistor is connected to one end of the fifth connection line through the thirteenth via, and the reference voltage signal line is connected to the other end of the fifth connection line through the fourteenth via.

[0083] Optionally, the channel region of the tenth transistor is on the same layer as the channel region of the ninth transistor and is not connected.

[0084] Optionally, the fifth gate signal line includes a main body and a branch. The overlapping position of the active layer and the main body of the fifth gate signal line forms the channel region of the ninth and tenth transistors of the pixel circuit in this row, and the overlapping position of the active layer and the branch of the fifth gate signal line forms the channel region of the third transistor of the next row pixel circuit.

[0085] Optionally, the array substrate further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, and the fourth insulating layer is located between the third conductive layer and the fourth conductive layer.

[0086] According to another aspect of the present invention, a display panel is provided, the display panel including the array substrate provided in any embodiment of the present invention.

[0087] The technical solution provided in this embodiment minimizes the area of ​​the channel region of the first transistor connected to the gate of the driving transistor among all transistors in the same pixel circuit. This reduces the size of the first transistor, which helps to reduce the voltage difference across the first transistor, thereby reducing the leakage current of the first transistor. This, in turn, helps to maintain the stability of the gate voltage of the driving transistor, which helps to improve the low-frequency flicker phenomenon and enhance the display effect.

[0088] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0089] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0090] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0091] Figure 2 This is a top view of an array substrate provided in an embodiment of the present invention;

[0092] Figure 3 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0093] Figure 4 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0094] Figure 5 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0095] Figure 6 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0096] Figure 7 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0097] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0098] Figure 9 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0099] Figure 10 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0100] Figure 11 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0101] Figure 12 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0102] Figure 13 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0103] Figure 14 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0104] Figure 15 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0105] Figure 16 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0106] Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0107] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0108] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0109] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, wherein, Figure 1 Only a portion of the pixel circuit structure is shown. Figure 2 This is a top view schematic diagram of an array substrate provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 2 The array substrate provided in this embodiment includes at least one pixel circuit, the pixel circuit includes a driving transistor M0 and at least one switching transistor, the switching transistor includes a first transistor M1, and the array substrate further includes:

[0110] Substrate (not shown in the figure);

[0111] The active layer 10 is located on one side of the substrate, and the channel regions of the driving transistor M0 and the first transistor M1 are both located in the active layer 10; the first electrode of the first transistor M1 is connected to the gate of the driving transistor M0.

[0112] Among all the switching transistors and driving transistors M0 in the same pixel circuit, the channel region of the first transistor M1 has the smallest area.

[0113] The channel region of the driving transistor M0 is located at the intersection of the gate G0 of the driving transistor M0 and the active layer 10, and the channel region of the first transistor M1 is located at the intersection of the first gate signal line 11 and the active layer 10.

[0114] Specifically, the driving transistor M0 is used to generate a driving current in response to its own gate voltage when the connection path between the first power supply voltage VDD and the second power supply voltage VSS is turned on, so as to drive the light-emitting element D1 to emit light. Since the first transistor M1 is connected to the gate G0 of the driving transistor M0, when the first transistor M1 is turned off, the gate G0 of the driving transistor M0 will leak current through the first transistor M1, which will cause the gate voltage of the driving transistor M0 to be unstable, thereby affecting the change of the driving current and affecting the display effect.

[0115] The technical solution provided in this embodiment minimizes the area of ​​the channel region of the first transistor M1, which is connected to the gate of the driving transistor M0, among all transistors in the same pixel circuit. This reduces the size of the first transistor M1, which in turn reduces the voltage difference across the first transistor M1, thereby reducing the leakage current of the first transistor M1. This, in turn, maintains the stability of the gate voltage of the driving transistor M0, which helps to improve low-frequency flicker and enhance the display effect.

[0116] Figure 3 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, specifically... Figure 2 An enlarged schematic diagram of the structure within the red dashed box in the array substrate shown, for reference. Figure 2 and Figure 3 The channel region of the first transistor M1 extends along the first direction Y, and the ratio of the dimension d2 of the channel region of the first transistor M1 in the second direction X to the dimension d1 of the channel region of the first transistor M1 in the first direction Y is between 0.17 and 1.1; wherein the first direction Y intersects the second direction X.

[0117] Where d1 is the length of the channel region of the first transistor M1, and d2 is the width of the channel region of the first transistor M1. While meeting the functional requirements of the first transistor M1, the size of the first transistor M1 can be set by adjusting the width-to-length ratio (d2 / d1), thereby minimizing the area of ​​the channel region of the first transistor M1.

[0118] Optionally, the channel region of the first transistor M1 has a dimension d1 of 2 μm to 3 μm in the first direction Y, and the channel region of the first transistor M1 has a dimension d2 of 0.5 μm to 2.2 μm in the second direction X.

[0119] In one optional embodiment provided in this example, the dimension d1 of the channel region of the first transistor M1 in the first direction Y is greater than the dimension d2 of the channel region of the first transistor M1 in the second direction X, so that the aspect ratio of the first transistor M1 is less than 1, thereby enabling the first transistor M1 to have a lower leakage current, thereby improving the ability to maintain the gate voltage of the driving transistor M0.

[0120] Continue to refer to Figure 1 The pixel circuit also includes a first capacitor C1, which is used to store the gate voltage of the driving transistor M0.

[0121] Figure 4 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 4 Optionally, based on the above embodiments, the array substrate further includes multiple conductive layers stacked on the side of the active layer 10 away from the substrate. The multiple conductive layers include a first conductive layer and a second conductive layer, with the second conductive layer located on the side of the first conductive layer away from the substrate. The first electrode 22 of the first capacitor C1 is located on the first conductive layer, and the second electrode 21 of the first capacitor C1 is located on the second conductive layer. The first electrode 22 of the first capacitor C1 is connected to the gate G0 of the driving transistor M0, and the second electrode 21 of the first capacitor C1 is connected to the power supply line 30.

[0122] In this capacitor, the second plate 21 of the first capacitor C1 extends along the second direction X. The orthographic projection of the second plate 21 of the first capacitor C1 onto the substrate at least partially covers the orthographic projection of the channel region of the driving transistor M0 onto the substrate. The overlapping position of the second plate 21 of the first capacitor C1 and the gate G0 of the driving transistor M0 forms the first capacitor C1. The first plate 22 of the first capacitor C1 is disposed on the same layer as the gate G0 of the driving transistor M0. The first plate 22 of the first capacitor C1 can be reused as the gate G0 of the driving transistor M0, which helps to reduce the layout space occupied by the pixel circuit.

[0123] In this embodiment, the orthographic projection of the second plate 21 of the first capacitor C1 onto the substrate covers the orthographic projection of the gate G0 of the driving transistor M0 onto the substrate. An opening is provided on the second plate 21 of the first capacitor C1, exposing the gate of the driving transistor M0, so that the first electrode of the first transistor M1 can be connected to the gate G0 of the driving transistor M0. Here, the first electrode of the first transistor M1 can be connected to the gate G0 of the driving transistor M0 via the first connection line 101.

[0124] Optionally, the power line 30 includes a first sub-line 31 and a second sub-line 32. The first sub-line 31 extends along a second direction X, and the second sub-line 32 extends along a first direction Y. At the intersection of the first sub-line 31 and the second sub-line 32, the second sub-line 32 is connected to the first sub-line 31 through a first via K1. That is, the first sub-line 31 and the second sub-line 32 are connected to form a mesh structure, which helps to reduce the impedance of the power line 30, thereby reducing the voltage drop of the power line 30.

[0125] Optionally, at the intersection of the first sub-line 31 and the second sub-line 32, at least two first vias K1 are included, which helps to further reduce the impedance of the power line 30 to ensure the stability and accuracy of the transmitted voltage.

[0126] In this embodiment, the first sub-line 31 can be reused as the second electrode plate 21 of the first capacitor C1, thereby eliminating the connection line between the second electrode plate 21 of the first capacitor C1 and the power line 30. The connection between the second electrode plate 21 of the first capacitor C1 and the power line 30 can be achieved only through the first via K1, which is beneficial for saving wiring space and improving PPI.

[0127] Figure 5 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 5 Optionally, based on the above embodiments, the power line 30 further includes a third sub-line 33, which extends along the first direction Y. The orthographic projection of the third sub-line 33 on the substrate at least partially overlaps with the orthographic projection of the second sub-line 32 on the substrate. At the overlap position of the third sub-line 33 and the second sub-line 32, the third sub-line 33 is connected to the second sub-line 32 through the second via K2.

[0128] Specifically, Figure 6 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention, specifically... Figure 5 The cross-sectional structure of the array substrate shown is obtained along the cutting line AA', for reference. Figure 5 and Figure 6 The multilayer conductive layer also includes a third conductive layer, which is located on the side of the second conductive layer away from the substrate 101. The first sub-line 31 is located in the second conductive layer, and the second sub-line 32 is located in the third conductive layer. The multilayer conductive layer also includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate 101. The third sub-line 33 is located in the fourth conductive layer.

[0129] Optionally, the gate G0 of the driving transistor M0 is located in the first conductive layer.

[0130] In this design, a first insulating layer 102 is disposed between the active layer 10 and the first conductive layer; a second insulating layer 103 is disposed between the first conductive layer and the second conductive layer; a third insulating layer 104 is disposed between the second conductive layer and the third conductive layer; a fourth insulating layer 105 is disposed between the third conductive layer and the fourth conductive layer; and a fifth insulating layer 106 is disposed on the side of the fourth conductive layer away from the substrate 101. Here, the first via K1 is a via connecting the third conductive layer downwards to the second conductive layer, and the second via K2 is a via connecting the fourth conductive layer downwards to the third conductive layer. For example, the first via K1 penetrates the third insulating layer 104; and the second via K2 penetrates the fourth insulating layer 105.

[0131] Figure 7 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 5 The cross-sectional structure of the array substrate shown is obtained along the cutting line BB', for reference. Figure 5 and Figure 7 The orthographic projection of the third sub-line 33 on the substrate 101 covers the orthographic projection of the channel region of the first transistor M1 on the substrate 101. The fourth conductive layer is a metal layer, and the third sub-line 33 located on the fourth conductive layer can be used as a light-shielding layer for the first transistor M1, thereby reducing the influence of light on the channel region of the first transistor M1.

[0132] Optionally, the edge of the orthogonal projection of the third sub-line 33 onto the substrate 101 extends at least 2 μm beyond the edge of the orthogonal projection of the channel region of the first transistor M1 onto the substrate 101, i.e., a ≥ 2 μm and b ≥ 2 μm. This enables complete light shielding of the channel region of the first transistor M1, thereby reducing the photo-generated leakage current of the first transistor. Here, a and b can be the same or different.

[0133] Continue to refer to Figure 7 The orthographic projection of the second sub-line 32 on the substrate 101 is separated from the orthographic projection of the channel region of the first transistor M1 on the substrate 101, so as to avoid the generation of parasitic capacitance between the second sub-line 32 located in the third conductive layer and the first transistor M1, which would affect the normal operation of the first transistor M1.

[0134] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 9 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 8 and Figure 9The display panel also includes a reference voltage signal line 34, and the pixel circuit includes a second capacitor C2. The first plate 23 of the second capacitor C2 is connected to the reference voltage signal line 34, and the second plate 24 of the second capacitor C2 is connected to the second electrode of the first transistor M1. The reference voltage signal line 34 is used to transmit the reference voltage VEH, and the second capacitor C2 is used to store the voltage of the second electrode of the first transistor M1. The first plate 23 of the second capacitor C2 is located in the second conductive layer, and the second plate 24 of the second capacitor C2 is located in the active layer. In one embodiment, the reference voltage signal line 34 can be reused as the first plate 23 of the second capacitor C2, which can reduce the number of film layers and avoid the second sub-line 32 in the power line 30, facilitating the wiring of the power line 30 and saving layout space.

[0135] Optionally, the reference voltage signal line 34 extends along the second direction X, and the overlap position of the reference voltage signal line 34 with the active layer 10, at least partially extending along the second direction X, has a dimension in the first direction Y that is larger than the dimension of the channel region of the first transistor M1 in the second direction X. For example, combined with Figure 3 d3 > d2. That is to say, the width of the active layer 10 overlapping with the reference voltage signal line 34 is greater than the width of the channel region of the first transistor M1, so as to increase the overlap area between the reference voltage signal line 34 and the active layer 10, which facilitates the formation of a second capacitor C2 with a larger capacitance value.

[0136] In the above embodiments, the array substrate further includes a first gate signal line 11 extending along a second direction X. The channel region of the first transistor M1 is located at the first overlap position between the active layer 10 and the first gate signal line 11. The first electrode of the first transistor M1 is connected to the gate G0 of the driving transistor M0 through a gate connection portion 110. The first electrode of the first transistor M1 is connected to one end of the gate connection portion 110 through a third via K3, and the gate G0 of the driving transistor M0 is connected to the other end of the gate connection portion 110 through a fourth via K4. The third via K3 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102, while the fourth via K4 penetrates the third insulating layer 104 and the second insulating layer 103.

[0137] In this embodiment, among the multiple switching transistors in the pixel circuit, only the first transistor M1 is directly connected to the gate G0 of the driving transistor M0. That is, the gate of the driving transistor M0 can only leak current through the first transistor M1, and there is only one leakage path for the gate of the driving transistor M0. Therefore, by setting the area of ​​the channel region of the first transistor M1 to the minimum value among all transistors, and using the third sub-line 33 in the power line 30 to shield the channel region of the first transistor M1 from light, the leakage current of the first transistor M1 can be reduced to a large extent, thereby improving the stability of the gate voltage of the driving transistor M0.

[0138] Figure 10 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 10 and Figure 8 Based on the above embodiments, optionally, the array substrate further includes a second gate signal line 12 and a first initialization signal line 41, and the switching transistor further includes a second transistor M2 and a third transistor M3. The channel region of the second transistor M2 is located at the second overlap position between the active layer 10 and the first gate signal line 11, and the channel region of the third transistor M3 is located at the overlap position between the active layer 10 and the second gate signal line 12. The first electrode of the second transistor M2 is connected to the second electrode of the first transistor M1, the second electrode of the second transistor M2 is connected to the first electrode of the third transistor M3, and the second electrode of the third transistor M3 is connected to the first initialization signal line 41 through a first connection line 51.

[0139] The second transistor M2 and the third transistor M3 are used to transmit the first initialization voltage Vref1 on the first initialization signal line 41 to the second terminal of the first transistor M1, and then to the gate G0 of the driving transistor M0 via the first transistor M1, so as to initialize the gate G0 of the driving transistor M0.

[0140] Figure 11 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 10 The cross-sectional structure of the array substrate shown is obtained along the cutting line CC', for reference. Figure 10 and Figure 11 The second terminal of the third transistor M3 is connected to one end of the first connection line 51 through the fifth via K1, and the first initialization signal line 41 is connected to the other end of the first connection line 51 through the sixth via K2. Here, the first initialization signal line 41 is located in the fourth conductive layer, and the first connection line 51 is located in the third conductive layer. The fifth via K5 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102, and the sixth via K6 penetrates the fourth insulating layer 105.

[0141] The first initialization signal line 41 extends along the first direction Y. The first initialization signal line 41 and the third sub-line 33 are set on the same layer, which is beneficial to optimize the layout space.

[0142] Optionally, both the first gate signal line 11 and the second gate signal line 12 are located in the first conductive layer. The orthographic projection of the second gate signal line 12 onto the substrate 101 is located on the side of the orthographic projection of the first gate signal line 11 onto the substrate 101 that is far from the orthographic projection of the gate G0 of the driving transistor M0 onto the substrate 101. The orthographic projection of the first connection line 51 onto the substrate 101 does not overlap with the orthographic projection of the second gate signal line 12 onto the substrate 101, and the orthographic projection of the first connection line 51 onto the substrate 101 is located between the orthographic projections of the second gate signal line 12 onto the substrate 101 and the first gate signal line 11 onto the substrate 101. This helps to reduce the length of the first connection line 51 along its own extension direction, thereby reducing the impedance of the first connection line 51.

[0143] The orthographic projection of the first connecting line 51 on the substrate 101 does not overlap with the orthographic projection of the second sub-line 32 on the substrate 101, thus avoiding a short circuit between the two.

[0144] In this embodiment, the first gate signal line 11 includes a main body and a branch. The channel region of the first transistor M1 is located at the orthographic projection position of the main body of the first gate signal line 11 onto the active layer 10, and the channel region of the second transistor M2 is located at the orthographic projection position of the branch of the first gate signal line 11 onto the active layer 10. The main body of the first gate signal line 11 extends along a second direction X, and the branch of the first gate signal line 11 extends along a first direction Y. The first transistor M1 and the second transistor M2 simultaneously respond to the first gate signal S1 transmitted on the first gate signal line 11.

[0145] Optionally, the channel region of the first transistor M1 extends along the first direction Y, and the channel region of the second transistor M2 extends along the second direction X, so that the first gate signal line 11 overlaps with the active layer 10 to form the first transistor M1 and the second transistor M2 respectively, which facilitates the layout space arrangement.

[0146] Continue to refer to Figure 10 The second gate signal line 12 includes a main body and a branch. The main body of the second gate signal line 12 extends along the second direction X, and the branch extends along the first direction Y. The channel region of the third transistor M3 is located at the orthographic projection position of the branch of the second gate signal line 12 on the active layer 10, so that the channel region of the third transistor M3 extends along the second direction X and is located between the main body of the second gate signal line 12 and the first gate signal line 11, preventing the first connection line 51 used to connect the third transistor M3 from overlapping with the second gate signal line 12.

[0147] Optionally, the branch of the first gate signal line 11 and the branch of the second gate signal line 12 extend towards each other to facilitate the connection between the second transistor M2 and the third transistor M3, optimize the layout, and improve the utilization of layout space.

[0148] Figure 12 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 12 Based on the above embodiments, optionally, at least one pixel circuit includes a first pixel circuit PX1 and a second pixel circuit PX2 that are adjacent and mirrored. The orthographic projection of the first initialization signal line 41 in the first pixel circuit PX1 onto the substrate 101 and the orthographic projection of the first initialization signal line 41 in the second pixel circuit PX2 onto the substrate 101 do not overlap at least partially, so that light can pass through in the area where the two do not overlap, thereby increasing the light transmittance of the panel.

[0149] Specifically, at the connection position between the first connecting line 51 and the first initialization signal line 41, the first connecting line 51 in the first pixel circuit PX1 and the first connecting line 51 in the second pixel circuit PX2 share the same sixth via K6 connected to the corresponding first initialization signal line 41.

[0150] Specifically, the first initialization signal line 41 includes a first sub-segment 401 and a second sub-segment 402 connected alternately in sequence. The orthographic projection of the first sub-segment 401 of the first initialization signal line 41 in the first pixel circuit PX1 onto the substrate 101 coincides with the orthographic projection of the first sub-segment 401 of the first initialization signal line 41 in the second pixel circuit PX2 onto the substrate 101. The orthographic projection of the second sub-segment 402 of the first initialization signal line 41 in the first pixel circuit PX1 onto the substrate 101 is separate from the orthographic projection of the second sub-segment 402 of the first initialization signal line 41 in the second pixel circuit PX2 onto the substrate 101. That is, the second sub-segment 402 in the first pixel circuit PX1 and the second sub-segment 402 in the second pixel circuit PX2 form a light-transmitting area to increase the light transmittance of the panel.

[0151] The orthographic projection of the connection point between the first sub-segment 401 and the second sub-segment 402 on the substrate 101 at least partially overlaps with the orthographic projection of the sixth via K6, used by the first connection line 51 to connect the first initialization signal line 41, on the substrate 101. For example, the connection point of the first sub-segment 401 and the second sub-segment 402 is located at the same location as the connection point of the first connection line 51 and the first initialization signal line 41, which is beneficial for optimizing the layout of the layout space.

[0152] Optionally, the orthographic projection of the second sub-segment 402 on the substrate 101 at least partially covers the orthographic projection of the active layer 10 on the substrate 101, which can be used for light shielding and improve the performance of the pixel circuit.

[0153] Figure 13 This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention, with reference to... Figure 8 and Figure 13 Based on the above embodiments, optionally, the array substrate further includes a third gate signal line 13, and the switching transistor further includes a fourth transistor M4 and a fifth transistor M5. The channel region of the fourth transistor M4 is located at the third overlap position between the active layer 10 and the first gate signal line 11, and the channel region of the fifth transistor M5 is located at the first overlap position between the active layer 10 and the third gate signal line 13. The first terminal of the fourth transistor M4 is connected to the second terminal of the first transistor M1, the second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5, and the second terminal of the fifth transistor M5 is connected to the second terminal of the driving transistor M0. The fourth transistor M4 and the fifth transistor M5 are used to implement threshold voltage compensation for the driving transistor M0.

[0154] In this configuration, the channel regions of the fourth transistor M4 and the fifth transistor M5 both extend along the first direction Y and are on the same straight line, which is beneficial for optimizing the layout space. The orthogonal projection of the second segment 402 in the first initialization signal line 41 onto the substrate 101 at least partially covers the orthogonal projections of the channel regions of the fourth transistor M4 and the fifth transistor M5 onto the substrate 101. For example, the orthogonal projection of the second segment 402 onto the substrate 101 completely covers the orthogonal projections of the channel regions of the fourth transistor M4 and the fifth transistor M5 onto the substrate 101, thereby shielding the channel regions of the fourth transistor M4 and the fifth transistor M5 from light, thus reducing the leakage current of the fourth transistor M4 and the fifth transistor M5 and improving the compensation effect of the threshold voltage of the driving transistor M0.

[0155] In this embodiment, the orthographic projection of the third gate signal line 13 on the substrate 101 is located between the orthographic projection of the first gate signal line 11 on the substrate and the orthographic projection of the gate G0 of the driving transistor M0 on the substrate 101; and the orthographic projection of the third gate signal line 13 on the substrate 101 and the orthographic projection of the first gate signal line 11 on the substrate 101 are located on the same side of the orthographic projection of the gate G0 of the driving transistor M0 on the substrate 101, so as to facilitate the connection between the first transistor M1, the fourth transistor M4, the fifth transistor M5 and the driving transistor M0.

[0156] Continue to refer to Figure 13The array substrate provided in this embodiment also includes a data line 43, and the switching transistor also includes a sixth transistor M6. The channel region of the sixth transistor M6 is located at the second overlap position of the active layer 10 and the third gate signal line 13. The first electrode of the sixth transistor M6 is connected to the data line 43 through the second connection line 52, and the second electrode of the sixth transistor M6 is connected to the first electrode of the driving transistor M0.

[0157] Specifically, the first terminal of the sixth transistor M6 is connected to one end of the second connection line 52 through the seventh via K7, and the data line 43 is connected to the other end of the second connection line 52 through the eighth via K8. The data line 43 and the first initialization signal line 41 are disposed on the same layer, for example, both are located in the fourth conductive layer. The data line 43 extends along the first direction Y to avoid short-circuiting with the third sub-line 33 of the power line 30 and the first initialization signal line 41. For example, in the fourth conductive layer, the orthographic projection of the power line 30 on the substrate 101 is located between the orthographic projection of the first initialization signal line 41 on the substrate 101 and the orthographic projection of the data line 43 on the substrate 101, which helps save layout space and allows the power line 40 to shield most of the transistor's channel region. The seventh via K7 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102, and the eighth via K8 penetrates the fourth insulating layer 105.

[0158] Continue to refer to Figure 13 The array substrate provided in this embodiment also includes a fourth gate signal line 14, and the switching transistors include a seventh transistor M7 and an eighth transistor M8. The channel region of the seventh transistor M7 is located at the first overlap position between the active layer 10 and the fourth gate signal line 14, and the channel region of the eighth transistor M8 is located at the second overlap position between the active layer 10 and the fourth gate signal line 14. The first terminal of the seventh transistor M7 is connected to the power supply line 30, and the second terminal of the seventh transistor M7 is connected to the first terminal of the driving transistor M0 through the third connection line 53. The first terminal of the eighth transistor M8 is connected to the second terminal of the driving transistor M0, and the second terminal of the eighth transistor M8 is connected to the light-emitting element. Here, both the seventh transistor M7 and the eighth transistor M8 are light-emitting control transistors, used to turn on or off in response to the light-emitting control signal EM transmitted on the fourth gate signal line 14.

[0159] The first terminal of the seventh transistor M7 can be connected to the second sub-line 32 of the power line 30 via a via.

[0160] Optionally, the fourth gate signal line 14 includes a main body and a branch. The main body of the fourth gate signal line 14 extends along the second direction X, and the branch extends along the first direction Y. The channel region of the seventh transistor M7 is located at the intersection of the active layer 10 and the main body of the fourth gate signal line 14, and the channel region of the eighth transistor M8 is located at the intersection of the active layer 10 and the branch of the fourth gate signal line 14. The orthographic projection of the third connection line 53 on the substrate 101 intersects with the orthographic projection of the main body of the fourth gate signal line 14 on the substrate 101, which facilitates the connection between the seventh transistor M7 and the driving transistor M0.

[0161] The orthographic projection of the fourth gate signal line 14 on the substrate 101 is located on the side away from the orthographic projection of the gate of the driving transistor M0 on the substrate 101; the orthographic projection of the fourth gate signal line 14 on the substrate 101 and the orthographic projection of the first gate signal line 11 on the substrate 101 are located on different sides of the orthographic projection of the gate G0 of the driving transistor M0 on the substrate 101.

[0162] Figure 14 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 13 The cross-sectional structure of the array substrate shown is obtained along the cutting line DD', for reference. Figure 13 and Figure 14 The fourth gate signal line 14 is located in the first conductive layer, the first electrode 21 of the first capacitor C1 is located in the second conductive layer, the third connection line 53 is located in the third conductive layer, and the data line 43 is located in the fourth conductive layer. The second electrode of the seventh transistor M7 is connected to one end of the third connection line 53 through the ninth via K9, and the first electrode of the driving transistor M0 is connected to the other end of the third connection line 53 through the tenth via K10. The ninth via K9 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102, and the tenth via K10 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102.

[0163] Figure 15 This is a cross-sectional view of another array substrate provided in an embodiment of the present invention, specifically... Figure 13 The cross-sectional structure of the array substrate shown is obtained along the cutting line EE', for reference. Figure 8 , Figure 13 and Figure 15The array substrate provided in this embodiment further includes a fifth gate signal line 15 and a second initialization signal line 42. The switching transistor further includes a ninth transistor M9. The channel region of the ninth transistor M9 is located at the first overlap position between the active layer 10 and the fifth gate signal line 15. The first electrode of the ninth transistor M9 is connected to the second initialization signal line 42, and the second electrode of the ninth transistor M9 is connected to the light-emitting element. The ninth transistor M9 is used to respond to the signal on the fifth gate signal line 15 to conduct, so as to transmit the second initialization voltage Vref2 on the second initialization signal line 42 to the first electrode of the light-emitting element to initialize the first electrode of the light-emitting element.

[0164] The orthographic projection of the fifth gate signal line 15 onto the substrate 101 and the orthographic projection of the second initialization signal line 42 onto the substrate are located on the same side of the orthographic projection of the gate G0 of the driving transistor M0 onto the substrate 101. Both the fifth gate signal line 15 and the second initialization signal line 42 extend along the second direction X, and the orthographic projection of the first initialization signal line 41 onto the substrate 101 intersects with the orthographic projection of the second initialization signal line 42 onto the substrate 101.

[0165] In this embodiment, the orthographic projection of the second initialization signal line 42 on the substrate 101 is separate from the orthographic projection of the fifth gate signal line 15 on the substrate 101 to avoid their overlap and the generation of parasitic capacitance. The channel region of the ninth transistor M9 extends along the first direction Y. The first terminal of the ninth transistor M9 is connected to the second initialization signal line 42 through the fourth connection line 54. For example, the first terminal of the ninth transistor M9 is connected to one end of the fourth connection line 54 through the eleventh via K11, and the second initialization signal line 42 is connected to the other end of the fourth connection line 54 through the twelfth via K12. Since the orthographic projection of the second initialization signal line 42 on the substrate 101 is located between the orthographic projections of the fifth gate signal line 15 and the fourth gate signal line 14 on the substrate 101, the fourth connection line 54 needs to cross the fifth gate signal line 15 before connecting to the second initialization signal line 42. That is, the orthographic projection of the fourth connection line 54 on the substrate 101 intersects with the orthographic projection of the fifth gate signal line 15 on the substrate 101, which is beneficial for optimizing the layout space. Among them, the eleventh via K11 penetrates the third insulating layer 104, the second insulating layer 103 and the first insulating layer 102, and the twelfth via K12 penetrates the third insulating layer 104.

[0166] Optionally, in the mirrored first pixel circuit PX1 and second pixel circuit PX2, the first terminal of the ninth transistor M9 in the first pixel circuit PX1 is connected to the first terminal of the ninth transistor M9 in the second pixel circuit PX2, and the first pixel circuit PX1 and the second pixel circuit PX2 share the same fourth connection line 54. In other words, the vias between the second initialization signal line 42 and the fourth connection line 54 corresponding to the mirrored first pixel circuit PX1 and the second pixel circuit PX2 are merged together. The via connecting the second initialization signal line 42 and the fourth connection line 54 in the first pixel circuit PX1 is the same via as the via connecting the second initialization signal line 42 and the fourth connection line 54 in the second pixel circuit PX2. This helps to reduce the number of vias and connections in the layout, thereby improving the integrity of the film layer and reducing the layout area.

[0167] Figure 16 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 13 and Figure 16 The array substrate provided in this embodiment also includes a reference voltage signal line, and the switching transistor includes a tenth transistor M10. The channel region of the tenth transistor M10 is located at the second overlap position between the active layer 10 and the fifth gate signal line 15. The first terminal of the tenth transistor M10 is connected to the reference voltage signal line 34 of the next row of pixel circuits, and the second terminal of the tenth transistor M10 is connected to the first terminal of the driving transistor M0 of the current row of pixel circuits. The tenth transistor M10 is used to transmit the reference voltage VEH on the reference voltage signal line 34 to the first or second terminal of the driving transistor M0 to apply a bias voltage to the first or second terminal of the driving transistor M0 to improve the threshold characteristics of the driving transistor M0.

[0168] In this configuration, the first terminal of the tenth transistor M10 is connected to the reference voltage signal line 34 via the fifth connection line 55, and the second terminal of the tenth transistor M10 is connected to the first terminal of the driving transistor M0 via the third connection line 53. Here, the reference voltage signal line 34 is located in the second conductive layer, and the fifth connection line 55 is located in the third conductive layer. For example, the first terminal of the tenth transistor M10 is connected to one end of the fifth connection line 55 via the thirteenth via K13, and the reference voltage signal line 34 is connected to the other end of the fifth connection line 55 via the fourteenth via K14. The thirteenth via K13 penetrates the third insulating layer 104, the second insulating layer 103, and the first insulating layer 102, and the fourteenth via K14 penetrates the third insulating layer 104.

[0169] Figure 16 The specific working principle of the pixel circuit shown can be found in the description in the relevant technology, and will not be repeated here.

[0170] In this embodiment, the channel region of the tenth transistor M10 is on the same layer as the channel region of the ninth transistor M9 and is not connected, while the channel region of the tenth transistor M10 is on the same layer as the channel region of the seventh transistor M7 and is connected, which is beneficial to optimizing the layout of the pixel circuit.

[0171] Optionally, in the same pixel circuit, the orthographic projection of the fifth gate signal line 15 onto the substrate 101 is located on the side where the orthographic projection of the second initialization signal line 42 onto the substrate 101 is far from the orthographic projection of the gate G0 of the driving transistor M0 onto the substrate 101. The fifth gate signal line 15 includes a main body and a branch. The main body of the fifth gate signal line 15 extends along the second direction X, and the branch extends along the first direction Y. The overlapping position of the active layer 10 and the main body of the fifth gate signal line 15 forms the channel region of the ninth transistor M9 and the tenth transistor M10 of the current row of pixel circuits. The overlapping position of the active layer 10 and the branch of the fifth gate signal line 15 forms the channel region of the third transistor M3 of the next row of pixel circuits, facilitating the connection of the tenth transistor M10 to the reference voltage signal line 34 in the next row of pixel circuits.

[0172] The technical solution provided in this invention places signal lines and connecting lines extending along the second direction X on the first and second conductive layers, and signal lines and connecting lines extending along the first direction Y on the third and fourth conductive layers. The signal lines and connecting lines extending along the second direction X and the first direction Y intersect each other, eliminating the need for bridging via bridge lines. This saves layout space, reduces trace resistance, and minimizes IR drop. The pixel circuit layout provided by this solution significantly improves layout space utilization while maintaining pixel circuit performance, thus contributing to increased PPI.

[0173] Optionally, embodiments of the present invention also provide a display panel. Figure 17 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 17 The display panel 200 includes the array substrate provided in any of the above embodiments, and therefore the display panel 200 also possesses the beneficial effects described in the above embodiments. The display panel 200 can be applied to mobile phones, and also to any electronic product with display functionality, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, and touch interactive terminals. The embodiments of the present invention do not impose any special limitations on these applications.

[0174] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0175] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, The array substrate includes at least one pixel circuit, the pixel circuit includes a driving transistor and at least one switching transistor, the switching transistor includes a first transistor; The array substrate further includes: Substrate; An active layer is located on one side of the substrate, and the channel regions of the driving transistor and the first transistor are both located in the active layer; the first electrode of the first transistor is connected to the gate of the driving transistor. Of all the switching transistors and driving transistors in the same pixel circuit, the channel region of the first transistor has the smallest area.

2. The array substrate according to claim 1, characterized in that, The channel region of the first transistor extends along a first direction, and the ratio of the size of the channel region of the first transistor in the second direction to the size of the channel region of the first transistor in the first direction is between 0.17 and 1.1; wherein the first direction intersects the second direction. Preferably, the channel region of the first transistor has a size of 2 μm to 3 μm in the first direction, and the channel region of the first transistor has a size of 0.5 μm to 2.2 μm in the second direction; Preferably, the dimension of the channel region of the first transistor in the first direction is greater than the dimension of the channel region of the first transistor in the second direction.

3. The array substrate according to claim 1, characterized in that, The array substrate further includes a multilayer conductive layer stacked on the side of the active layer away from the substrate, the multilayer conductive layer including a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate. The array substrate further includes a power line, and the pixel circuit further includes a first capacitor. The first plate of the first capacitor is located on the first conductive layer, and the second plate of the first capacitor is located on the second conductive layer. The first plate of the first capacitor is connected to the gate of the driving transistor, and the second plate of the first capacitor is connected to the power line. Preferably, the first plate of the first capacitor is reused as the gate of the driving transistor; Preferably, the second plate of the first capacitor extends along a second direction, and the orthographic projection of the second plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

4. The array substrate according to claim 3, characterized in that, The power cord includes a first sub-wire and a second sub-wire. The first sub-wire extends along the second direction, and the second sub-wire extends along the first direction. At the intersection of the first sub-wire and the second sub-wire, the second sub-wire is connected to the first sub-wire through a first via. Preferably, at the intersection of the first sub-line and the second sub-line, at least two first vias are included; Preferably, the multilayer conductive layer further includes a third conductive layer, which is located on the side of the second conductive layer away from the substrate, the first sub-line is located in the second conductive layer, and the second sub-line is located in the third conductive layer; Preferably, the first sub-line is reused as the second plate of the first capacitor.

5. The array substrate according to claim 4, characterized in that, The power line also includes a third sub-line, which extends along the first direction. The orthographic projection of the third sub-line on the substrate at least partially overlaps with the orthographic projection of the second sub-line on the substrate. At the overlap position of the third sub-line and the second sub-line, the third sub-line is connected to the second sub-line through a second via. Preferably, the orthographic projection of the third sub-line onto the substrate covers the orthographic projection of the channel region of the first transistor onto the substrate; Preferably, the edge of the orthogonal projection of the third sub-line onto the substrate extends at least 2 μm beyond the edge of the orthogonal projection of the channel region of the first transistor onto the substrate; Preferably, the multilayer conductive layer further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate, and the third sub-line is located in the fourth conductive layer; Preferably, the orthographic projection of the second sub-line on the substrate is separate from the orthographic projection of the channel region of the first transistor on the substrate.

6. The array substrate according to claim 3, characterized in that, The array substrate further includes a reference voltage signal line, and the pixel circuit further includes a second capacitor. The first plate of the second capacitor is connected to the reference voltage signal line, and the second plate of the second capacitor is connected to the second electrode of the first transistor. Preferably, the first electrode of the second capacitor is located in the second conductive layer, and the second electrode of the second capacitor is located in the active layer; Preferably, the reference voltage signal line extends along the second direction; Preferably, the reference voltage signal line is multiplexed as the first plate of the second capacitor; Preferably, at the point where the reference voltage signal line overlaps with the active layer, the dimension of the active layer extending at least partially along the second direction in the first direction is greater than the dimension of the channel region of the first transistor in the second direction.

7. The array substrate according to claim 3, characterized in that, The array substrate further includes a first gate signal line extending along the second direction, the channel region of the first transistor being located at the first overlap position between the active layer and the first gate signal line, and the first electrode of the first transistor being connected to the gate of the driving transistor through a gate connection portion. Preferably, the first electrode of the first transistor is connected to one end of the gate connection portion through a third via, and the gate of the driving transistor is connected to the other end of the gate connection portion through a fourth via. Preferably, the array substrate further includes a second gate signal line and a first initialization signal line, and the switching transistor further includes a second transistor and a third transistor. The channel region of the second transistor is located at the second overlap position between the active layer and the first gate signal line, and the channel region of the third transistor is located at the overlap position between the active layer and the second gate signal line. The first terminal of the second transistor is connected to the second terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the third transistor. The second terminal of the third transistor is connected to the first initialization signal line through a first connection line. Preferably, the second electrode of the third transistor is connected to one end of the first connection line through a fifth via, and the first initialization signal line is connected to the other end of the first connection line through a sixth via. Preferably, the first initialization signal line extends along a first direction; Preferably, the multilayer conductive layer further includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located on the side of the second conductive layer away from the substrate, the fourth conductive layer is located on the side of the third conductive layer away from the substrate, the first initialization signal line is located on the fourth conductive layer, and the first connection line is located on the third conductive layer; Preferably, the orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the second gate signal line on the substrate.

8. The array substrate according to claim 7, characterized in that, Both the first gate signal line and the second gate signal line are located in the first conductive layer; Preferably, the orthographic projection of the second gate signal line on the substrate is located on the side where the orthographic projection of the first gate signal line on the substrate is away from the orthographic projection of the gate of the driving transistor on the substrate; Preferably, the first gate signal line includes a main body portion and a branch portion, the channel region of the first transistor is located at the orthographic projection position of the main body portion of the first gate signal line on the active layer, and the channel region of the second transistor is located at the orthographic projection position of the branch portion of the first gate signal line on the active layer. Preferably, the channel region of the second transistor extends along the second direction; Preferably, the second gate signal line includes a main body and a branch, and the channel region of the third transistor is located at the orthographic projection position of the branch of the second gate signal line on the active layer; Preferably, the channel region of the third transistor extends along the second direction; Preferably, the branch of the first gate signal line extends toward the branch of the second gate signal line.

9. The array substrate according to claim 7, characterized in that, The at least one pixel circuit includes a first pixel circuit and a second pixel circuit that are adjacent and mirrored, wherein the orthographic projection of the first initialization signal line in the first pixel circuit on the substrate and the orthographic projection of the first initialization signal line in the second pixel circuit on the substrate do not overlap at least partially. Preferably, at the connection position between the first connecting line and the first initialization signal line, the first connecting line in the first pixel circuit and the first connecting line in the second pixel circuit share the same sixth via to connect to the corresponding first initialization signal line; Preferably, the first initialization signal line includes a first sub-segment and a second sub-segment connected alternately in sequence, the orthographic projection of the first sub-segment of the first initialization signal line in the first pixel circuit on the substrate coincides with the orthographic projection of the first sub-segment of the first initialization signal line in the second pixel circuit on the substrate, and the orthographic projection of the second sub-segment of the first initialization signal line in the first pixel circuit on the substrate is separate from the orthographic projection of the second sub-segment of the first initialization signal line in the second pixel circuit on the substrate. Preferably, the orthographic projection of the connection point between the first sub-segment and the second sub-segment on the substrate at least partially overlaps with the orthographic projection of the sixth via used by the first connecting line to connect the first initialization signal line on the substrate; Preferably, the orthographic projection of the second segment onto the substrate at least partially covers the orthographic projection of the active layer onto the substrate.

10. The array substrate according to claim 7, characterized in that, The array substrate further includes a third gate signal line, and the switching transistor further includes a fourth transistor and a fifth transistor. The channel region of the fourth transistor is located at the third overlap position between the active layer and the first gate signal line, and the channel region of the fifth transistor is located at the first overlap position between the active layer and the third gate signal line. The first terminal of the fourth transistor is connected to the second terminal of the first transistor, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, and the second terminal of the fifth transistor is connected to the second terminal of the driving transistor. Preferably, the channel regions of the fourth transistor and the fifth transistor both extend along the first direction and are on the same straight line; Preferably, the orthographic projection of the first initialization signal line on the substrate at least partially covers the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the fifth transistor on the substrate; Preferably, the orthographic projection of the third gate signal line on the substrate is located between the orthographic projection of the first gate signal line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate; Preferably, the orthographic projection of the third gate signal line on the substrate and the orthographic projection of the first gate signal line on the substrate are located on the same side of the orthographic projection of the gate of the driving transistor on the substrate.

11. The array substrate according to claim 10, characterized in that, The array substrate further includes a data line, and the switching transistor further includes a sixth transistor. The channel region of the sixth transistor is located at the second overlap position of the active layer and the third gate signal line. The first electrode of the sixth transistor is connected to the data line through a second connection line, and the second electrode of the sixth transistor is connected to the first electrode of the driving transistor. Preferably, the first electrode of the sixth transistor is connected to one end of the second connection line through a seventh via, and the data line is connected to the other end of the second connection line through an eighth via; Preferably, the data line is located in the fourth conductive layer; Preferably, the data line extends along the first direction; Preferably, in the fourth conductive layer, the orthographic projection of the power line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the data line on the substrate.

12. The array substrate according to claim 7, characterized in that, The array substrate further includes a fourth gate signal line, and the switching transistor further includes a seventh transistor and an eighth transistor. The channel region of the seventh transistor is located at the first overlap position of the active layer and the fourth gate signal line, and the channel region of the eighth transistor is located at the second overlap position of the active layer and the fourth gate signal line. The first electrode of the seventh transistor is connected to the power supply line, and the second electrode of the seventh transistor is connected to the first electrode of the driving transistor through a third connection line. The first electrode of the eighth transistor is connected to the second electrode of the driving transistor, and the second electrode of the eighth transistor is connected to the light-emitting element. Preferably, the second terminal of the seventh transistor is connected to one end of the third connection line through a ninth via, and the first terminal of the driving transistor is connected to the other end of the third connection line through a tenth via. Preferably, the fourth gate signal line includes a main body and a branch, the channel region of the seventh transistor is located at the intersection of the active layer and the main body of the fourth gate signal line, and the channel region of the eighth transistor is located at the intersection of the active layer and the branch of the fourth gate signal line. Preferably, the orthographic projection of the third connecting line on the substrate intersects with the orthographic projection of the main body of the fourth gate signal line on the substrate; Preferably, the third connection line is located in the third conductive layer, and the fourth gate signal line is located in the first conductive layer; Preferably, the orthogonal projection of the fourth gate signal line on the substrate is located on the side where the orthogonal projection of the gate of the driving transistor on the substrate is away from the orthogonal projection of the first gate signal line on the substrate; Preferably, the orthographic projection of the fourth gate signal line on the substrate and the orthographic projection of the first gate signal line on the substrate are located on different sides of the orthographic projection of the gate of the driving transistor on the substrate.

13. The array substrate according to claim 12, characterized in that, The array substrate further includes a fifth gate signal line and a second initialization signal line. The switching transistor further includes a ninth transistor. The channel region of the ninth transistor is located at the first overlap position between the active layer and the fifth gate signal line. The first electrode of the ninth transistor is connected to the second initialization signal line, and the second electrode of the ninth transistor is connected to the light-emitting element. Preferably, the orthographic projection of the fifth gate signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate are located on the same side of the orthographic projection of the gate of the driving transistor on the substrate. Preferably, the fifth gate signal line is located in the first conductive layer, and the second initialization signal line is located in the second conductive layer; Preferably, both the fifth gate signal line and the second initialization signal line extend along the second direction; Preferably, the orthographic projection of the first initialization signal line on the substrate intersects with the orthographic projection of the second initialization signal line on the substrate.

14. The array substrate according to claim 13, characterized in that, The orthographic projection of the second initialization signal line on the substrate is located between the orthographic projections of the fifth gate signal line on the substrate and the orthographic projections of the fourth gate signal line on the substrate; Preferably, the orthographic projection of the second initialization signal line on the substrate is separate from the orthographic projection of the fifth gate signal line on the substrate; Preferably, the first electrode of the ninth transistor is connected to the second initialization signal line via a fourth connection line; Preferably, the first terminal of the ninth transistor is connected to one end of the fourth connection line through the eleventh via, and the second initialization signal line is connected to the other end of the fourth connection line through the twelfth via. Preferably, the orthographic projection of the fourth connection line on the substrate intersects the orthographic projection of the fifth gate signal line on the substrate.

15. The array substrate according to claim 14, characterized in that, The at least one pixel circuit includes a first pixel circuit and a second pixel circuit that are adjacent and mirrored. The first terminal of the ninth transistor in the first pixel circuit is connected to the first terminal of the ninth transistor in the second pixel circuit. The first pixel circuit and the second pixel circuit share the same fourth connection line.

16. The array substrate according to claim 13, characterized in that, The array substrate further includes a reference voltage signal line, and the switching transistor further includes a tenth transistor. The channel region of the tenth transistor is located at the second overlap position of the active layer and the fifth gate signal line. The first terminal of the tenth transistor is connected to the reference voltage signal line of the pixel circuit in the next row, and the second terminal of the tenth transistor is connected to the first terminal of the driving transistor of the pixel circuit in the same row. Preferably, the first terminal of the tenth transistor is connected to the reference voltage signal line via the fifth connection line, and the second terminal of the tenth transistor is connected to the first terminal of the driving transistor via the third connection line; Preferably, the first terminal of the tenth transistor is connected to one end of the fifth connection line through the thirteenth via, and the reference voltage signal line is connected to the other end of the fifth connection line through the fourteenth via.

17. The array substrate according to claim 16, characterized in that, The channel region of the tenth transistor is on the same layer as the channel region of the ninth transistor but is not connected.

18. The array substrate according to any one of claims 13-17, characterized in that, The fifth gate signal line includes a main body and a branch. The overlap between the active layer and the main body of the fifth gate signal line forms the channel regions of the ninth and tenth transistors of the pixel circuit in the current row. The overlap between the active layer and the branch of the fifth gate signal line forms the channel region of the third transistor of the pixel circuit in the next row.

19. The array substrate according to claim 7, characterized in that, The array substrate further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, and the fourth insulating layer is located between the third conductive layer and the fourth conductive layer.

20. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-19.

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