Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a solar cell, a preparation method thereof and a photovoltaic module, and the method comprises the steps: providing a silicon wafer after boron source diffusion, enabling the silicon wafer to form a first doped conductive region at a first surface after boron source diffusion, and enabling the first surface to be provided with a to-be-scribed region; processing the first doped conductive region in the to-be-scribed region by using laser, cleaning the first doped conductive region after laser processing, removing the first doped conductive region in the to-be-scribed region, and forming a first groove in the silicon wafer; forming a tunneling oxide layer and a doped conductive layer on the second surface of the silicon wafer, wherein the doping type of the doped conductive layer is different from that of the first doped conductive region; performing laser cutting on the silicon wafer along the first groove to obtain a plurality of fragmented batteries; and carrying out cleaning, passivation, electrode printing and test sorting on the plurality of fragmented batteries. According to the solar cell provided by the embodiment of the invention, at least the technical problem that the investment cost of solar cell preparation is relatively high can be solved.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and in particular to a solar cell, a method for its fabrication, and a photovoltaic module. Background Technology

[0002] A solar cell is a photoelectric semiconductor that generates electricity using sunlight. It typically uses silicon as the main semiconductor material. When a P-type doped semiconductor comes into contact with an N-type doped semiconductor, a PN junction structure is formed. When exposed to light, holes in the N-type region of the PN junction move to the P-type region, while electrons in the P-type region move to the N-type region, thus creating a current flowing from the N-type region to the P-type region. Summary of the Invention

[0003] This application provides a solar cell, its preparation method, and a photovoltaic module, which at least helps to improve the technical problem of high input costs in the preparation of solar cells.

[0004] According to some embodiments of this application, one aspect of this application provides a method for fabricating a solar cell, comprising: providing a silicon wafer after boron source diffusion, the silicon wafer having a first side and a second side opposite to each other, the silicon wafer forming a first doped conductive region on the first side after the boron source diffusion, the first side having a dicing region; laser processing the first doped conductive region in the dicing region, and cleaning the laser-processed first doped conductive region to remove the first doped conductive region located in the dicing region, forming a first groove in the silicon wafer; forming a tunneling oxide layer and a doped conductive layer on the second side of the silicon wafer, the doping type of the doped conductive layer being different from that of the first doped conductive region; laser cutting the silicon wafer along the first groove to obtain multiple diced cells; cleaning, passivating, printing electrodes, and testing and sorting the multiple diced cells to obtain solar cell wafers.

[0005] In some embodiments, the step of forming the first doped conductive region includes: providing a silicon wafer and texturing the silicon wafer; placing the silicon wafer in a diffusion furnace and performing the boron source diffusion on the silicon wafer to form the first doped conductive region on the first surface of the silicon wafer, wherein the boron source includes boron trichloride and the temperature during boron source diffusion is 850~920°C.

[0006] In some embodiments, the step of using a laser to process the first doped conductive region in the region to be diced includes: irradiating the first doped conductive region in the region to be diced with a laser, wherein the width of the laser irradiation is 400~800μm, and the laser includes a red picosecond laser with a wavelength of 1035~1060nm and a scanning rate of 500~800mm / s.

[0007] In some embodiments, the step of cleaning the first doped conductive region after laser treatment includes: performing a first wet etching process on the first doped conductive region, wherein the solution of the first wet etching process includes alkali and pure water, the volume percentage of the alkali and the pure water is (2~3):(97~98), the temperature of the first wet etching process is 65~72°C, and the time is 100~150s.

[0008] In some embodiments, the preparation method further includes: simultaneously cleaning the first doped conductive region after laser treatment, performing a second wet etching process on the first doped conductive region located on the second side of the silicon wafer, and polishing the second side after removal. The solution for the second wet etching process includes alkali, additives, and pure water, and the volume percentage of the alkali, the additives, and the pure water is (1~2):(0.6~0.8):(97.2~98.4). The temperature of the second wet etching process is 65~72℃, and the time is 350~500s.

[0009] In some embodiments, the steps of forming the tunneling oxide layer and the doped conductive layer include: forming a tunneling oxide layer on a second surface of the polished silicon wafer; forming an intrinsic amorphous silicon layer on the side of the tunneling oxide layer opposite to the silicon wafer and on the side of the first doped conductive region opposite to the silicon wafer; and performing phosphorus source diffusion on the intrinsic amorphous silicon layer located on the tunneling oxide layer to form the doped conductive layer, wherein the phosphorus source includes phosphorus oxychloride and the temperature during phosphorus source diffusion is 870~900°C.

[0010] In some embodiments, the step of laser cutting the silicon wafer includes: using a laser to perform laser scanning on the silicon wafer in the first groove of the area to be cut, wherein the width of the laser scan is 1.5~2μm, the wavelength is 1035~1060nm, and the scanning rate is 150~200mm / s; and during the laser scanning process, cooling treatment is performed on the area on the second surface of the silicon wafer corresponding to the area to be cut.

[0011] In some embodiments, while the intrinsic amorphous silicon layer located on the tunneling oxide layer forms the doped conductive layer, a polycrystalline silicon layer is formed on the side of the first doped conductive region opposite to the silicon wafer. The step of cleaning the multiple cell wafers includes: performing a third wet etching process on the multiple cell wafers to remove the polycrystalline silicon layer. The alkaline solution of the third wet etching process includes alkali, additives, and pure water, and the volume percentage of the alkali, the additives, and the pure water is (2.5~3.5). The process involves a four-stage wet etching process on multiple cell segments to remove the borosilicate glass layer on the surface of the first doped conductive region and the phosphosilicate glass layer on the surface of the doped conductive layer. The acidic solution for the four-stage wet etching process includes hydrofluoric acid and pure water, with a volume percentage of (4~5):(5~6). The temperature is 25~30℃, and the time is 100~300s.

[0012] In some embodiments, the step of passivating the plurality of cell wafers includes: forming a first passivation layer and a first antireflection layer on the side of the first doped conductive region away from the silicon wafer, wherein the thickness of the first passivation layer in a first direction is 3-4 nm, the thickness of the first antireflection layer is 75-80 nm, and the thickness of the first passivation layer deposited around to the cut surface of the cell wafer is 4-5 nm, and the first direction is perpendicular to the first surface; forming a second passivation layer on the side of the doped conductive layer away from the silicon wafer, wherein the total thickness of the first antireflection layer and the second passivation layer deposited around to the cut surface of the cell wafer in a second direction is 80-100 nm, and the second direction is perpendicular to the first direction.

[0013] In some embodiments, the step of printing electrodes on a plurality of the segmented cells includes: printing grid lines on the first antireflection layer and the second passivation layer; sintering the grid lines at a temperature of 740~780°C; and performing a secondary sintering of the grid lines using a laser-assisted sintering process, wherein the ratio of the laser output power to the maximum output power of the laser in the laser-assisted sintering process is 20~40%, and the bias voltage applied to the grid lines is 15~25V.

[0014] According to some embodiments of this application, another aspect of this application provides a solar cell prepared using the solar cell preparation method described above.

[0015] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, which is a plurality of solar cells prepared by the method described above, or a plurality of solar cells connected together as described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0016] The technical solution provided in this application has at least the following advantages:

[0017] The method for fabricating a solar cell proposed in this application first provides a silicon wafer after boron source diffusion. After boron source diffusion, a first doped conductive region is formed on the first surface of the silicon wafer, and a dicing area is located on the surface (first surface) of the first doped conductive region. The first doped conductive region in the dicing area is treated with a laser, and the laser-treated first doped conductive region is cleaned to remove the first doped conductive region located in the dicing area, forming a first groove in the silicon wafer. A tunneling oxide layer and a doped conductive layer are formed on the second surface of the silicon wafer. The doped conductive layer has a different doping type than the first doped conductive region. The silicon wafer is laser-cut along the first groove to obtain multiple segmented cells. By pre-processing the boron-expanded silicon wafer with laser at the location to be laser-scribed, the borosilicate glass and boron-rich layer formed after boron expansion can be modified. These layers are then removed to expose the silicon wafer in that area. Subsequent dicing of the wafer reduces high recombination rates caused by boron doping at the diced edges. After phosphorus expansion to form a doped conductive layer on the amorphous silicon layer of the second side of the wafer, it is cut to achieve wafer separation. Subsequent passivation processes (e.g., deposition of a first passivation layer) passivate the undoped cut edges of the silicon wafer, achieving passivation of the entire cut edge and reducing defects and recombination in the cell. This fabrication method can be completed using simpler equipment, saving production line space and reducing investment costs. This method improves the passivation effect and reduces investment costs, solving the problem of high investment costs in existing solar cell fabrication technologies. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic flowchart illustrating a method for fabricating a solar cell according to an embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the structure of a solar cell according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the structure of a photovoltaic module according to an embodiment of this application.

[0022] The above figures include the following reference numerals:

[0023] 01. Solar cell; 02. Encapsulating film; 03. Cover plate; 04. Conductive strip; 10. Silicon wafer; 20. First doped conductive region; 30. First passivation layer; 40. First antireflection layer; 50. First electrode; 60. Tunneling oxide layer; 70. Doped conductive layer; 80. Second passivation layer; 90. Second electrode. Detailed Implementation

[0024] This application provides a method for fabricating a solar cell, comprising: providing a silicon wafer after boron source diffusion, the silicon wafer having a first side and a second side opposite to each other; forming a first doped conductive region on the first side of the silicon wafer after boron source diffusion, and having a dicing region on the first side; processing the first doped conductive region in the dicing region with a laser, and cleaning the laser-processed first doped conductive region to remove the first doped conductive region located in the dicing region, forming a first groove in the silicon wafer; forming a tunneling oxide layer and a doped conductive layer on the second side of the silicon wafer, the doping type of the doped conductive layer being different from that of the first doped conductive region; laser cutting the silicon wafer along the first groove to obtain multiple diced cells; cleaning, passivating, printing electrodes, and testing and sorting the multiple diced cells to obtain solar cell wafers.

[0025] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0028] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0029] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0030] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0031] In the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0032] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0033] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the word "part" is also intended to include the plural form, unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This application proposes a method for preparing a solar cell, such as... Figure 1 As shown, it includes:

[0036] Step S1: Provide a silicon wafer after boron source diffusion. The silicon wafer has a first side and a second side opposite to each other. After the boron source diffusion, a first doped conductive region is formed on the first side of the silicon wafer, and a dicing area is formed on the first side.

[0037] Optionally, forming a first doped conductive region means that boron has diffused to the surface area of ​​the silicon wafer and formed a first doped conductive region that is opposite to the doping type of the silicon wafer; the above-mentioned area to be diced is an area defined artificially according to the actual situation, and is not an area with obvious boundaries on the cell or an area that is significantly different from other surrounding areas.

[0038] Step S2: The first doped conductive region in the area to be diced is treated with a laser, and the first doped conductive region after laser treatment is cleaned to remove the first doped conductive region located in the area to be diced, thereby forming a first groove in the silicon wafer.

[0039] Optionally, the first doped conductive region in the dicing area is first laser-treated to physically or chemically alter its material structure, thereby destroying its original doping distribution and conductivity. Subsequently, the laser-treated area is cleaned to remove the material from the laser-treated first doped conductive region through physical or chemical action, ultimately forming a groove structure (first groove) in the silicon wafer without the first doped conductive region. This groove is formed directly by the combined action of laser treatment and cleaning, and its boundary and position are defined by the division of the dicing area, with no components of the first doped conductive region remaining inside. The width of the first groove can be larger than the diameter of the laser spot used for subsequent laser dicing, allowing for a certain distance between the diced edge of the cell and the first doped conductive region, thus reducing recombination at the cell edge. After dicing, the cut surface of the silicon wafer is passivated.

[0040] Step S3: A tunneling oxide layer and a doped conductive layer are formed on the second side of the silicon wafer. The doped conductive layer has a different doping type than the first doped conductive region.

[0041] Optionally, the tunneling oxide layer can be generated by thermal oxidation or chemical vapor deposition. It is extremely thin and can achieve the quantum tunneling effect of charge carriers while not allowing majority charge carriers to pass through freely. This establishes electrical isolation and surface passivation between the silicon wafer and the doped conductive layer on the back side. Subsequently, a doped conductive layer is formed on the tunneling oxide layer. The doping type of this layer is opposite to that of the first doped conductive region. Its formation process can be achieved by doping diffusion or ion implantation. The doped conductive layer and the first doped conductive region form a complementary structure in terms of electrical polarity. This establishes a symmetrical or differentiated selective contact mechanism for charge carriers on both sides of the silicon wafer, providing a structural basis for the efficient charge separation and collection of the battery.

[0042] Step S4: Laser cut the silicon wafer along the first groove to obtain multiple segmented cells;

[0043] Step S5 involves cleaning, passivating, printing electrodes, and testing and sorting multiple cell segments to obtain solar cells.

[0044] Optionally, the silicon wafer is laser-cut along the centerline of the first groove to obtain multiple segmented cells. This process uses a laser to act on the pre-formed groove area on the silicon wafer, using concentrated laser energy to induce material fracture and achieve precise separation along the preset groove path. The multiple segmented cells are then cleaned to remove residual process contaminants on the cell surface, including acid and alkali residues, particulate matter, and metal ion impurities, ensuring a clean interface between the subsequent first passivation layer and the silicon substrate. Passivation reduces the recombination rate of charge carriers on the cell surface by forming a chemical or physical coating layer, improving charge collection efficiency. Electrodes are printed by depositing conductive paste in a specific pattern on the positive and negative electrode areas of the cell, establishing a metal path for current collection and transmission. Finally, the processed segmented cells are tested and sorted, and their efficiency, current, voltage, and other indicators are quantitatively evaluated based on electrical performance parameters. They are then classified according to performance level to provide consistent matching cell units for subsequent module packaging.

[0045] The aforementioned preparation method of this application pre-processes the boron-expanded silicon wafer with laser at the location to be laser-scribed. This modifies the borosilicate glass and boron-rich layer formed after boron expansion, which are then removed to expose the silicon wafer in that area. Subsequently, the silicon wafer is directly scribed, reducing high recombination caused by boron doping at the scribed edge. After phosphorus expansion to form a doped conductive layer on the amorphous silicon layer of the second side of the silicon wafer, it is cut to achieve wafer separation. Subsequent passivation processes (such as depositing a first passivation layer) are used to passivate the undoped cut edges of the silicon wafer, achieving passivation of the entire cut edge, which can reduce defects and recombination in the cell. In the above preparation method, simpler equipment can be used, which can save production line space and reduce investment costs. It can solve the problem of high investment costs in the preparation of solar cells in the prior art while improving the passivation effect.

[0046] In the above embodiments, the silicon wafer can be made of an elemental semiconductor material. Optionally, the elemental semiconductor material is composed of a single element, such as silicon. The elemental semiconductor material can be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0047] In the above embodiments, the silicon wafer can also be made of compound semiconductor materials. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen phosphate, perovskite, cadmium telluride, and copper indium selenide. The silicon wafer can also be a sapphire silicon wafer, a silicon-on-insulator (SOI) wafer, or a germanium-on-insulator (SOI) wafer.

[0048] In the above embodiments, the N-type silicon wafer is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type silicon wafer is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In). Optionally, the thickness of the N-type silicon wafer can be 100 μm to 210 μm, such as 130 μm, 170 μm, and 190 μm.

[0049] In the above embodiments, the doping type of the first doped conductive region is opposite to the doping type of the silicon wafer, and the doped conductive layer is opposite to the doping type of the first doped conductive region. For example, the doping type of the silicon wafer is N-type, the doping type of the first doped conductive region is P-type, and the doping type of the doped conductive layer is N-type; or the doping type of the silicon wafer is P-type, the doping type of the first doped conductive region is N-type, and the doping type of the doped conductive layer is P-type.

[0050] In the above embodiments, the first side of the silicon wafer is the front side, and the second side is the back side. That is, the solar cell is a single-sided cell. The front side can serve as the light-receiving surface to receive incident light, and the back side serves as the backlight surface. The first and second sides can be either flat or non-flat surfaces. In other words, the first and second sides can be either flat or non-flat surfaces, and they can be the same or different.

[0051] In the above embodiments, both the first and second surfaces are non-flat surfaces. Non-flat surfaces can increase internal reflection of incident light, thereby further improving the light utilization efficiency of the solar cell. More specifically, the cross-section of the non-flat surface along the first predetermined direction is a line segment. This line segment can include at least one of straight segments and curved segments; that is, the line segment can be composed of straight segments, curved segments, or a combination of both. In the case where only straight segments are used, the line segment is composed of multiple sequentially connected straight segments. The first predetermined direction is the thickness direction of the silicon wafer.

[0052] In the above embodiments, the first doped conductive region and the doped conductive layer can be a doped polycrystalline silicon layer, a silicon carbide layer, an amorphous silicon layer, or a composite layer of doped polycrystalline silicon and silicon carbide layers. For example, it can be only silicon carbide or only polycrystalline silicon, or a doped material of silicon carbide and polycrystalline silicon. When the doped conductive layer is doped polycrystalline silicon, it can serve as the first passivation layer, forming band bending on the silicon wafer surface to achieve selective carrier transport and reduce recombination losses. The thickness of the first doped conductive region and the doped conductive layer can be 80nm~100nm, such as 80nm and 95nm. The specific thickness and material are not limited in this application and can be selected according to the actual situation.

[0053] In some alternative implementations, the step of forming the first doped conductive region includes:

[0054] A silicon wafer is provided and texturized. The wafer is then placed in a diffusion furnace for boron source diffusion, forming a first doped conductive region on the first surface of the wafer. The boron source includes boron trichloride, and the diffusion temperature is 850–920°C. By texturizing the silicon wafer before boron source diffusion, using boron trichloride as the boron source, and controlling the diffusion temperature within the aforementioned specific range, the doping of the first doped conductive region formed on the first surface can be more uniform. This avoids localized areas with excessively high boron concentrations (boron-rich regions) or excessively low concentrations (underdoped regions). Boron-rich regions tend to form high recombination centers, increasing the probability of carrier (electron) recombination at the surface; underdoped regions, on the other hand, cannot effectively form a good pn junction electric field. A uniformly doped first doped conductive region reduces interface defects and recombination centers.

[0055] In some alternative implementations, the step of laser processing of the first doped conductive region in the area to be diced includes:

[0056] A red picosecond laser is used to irradiate the first doped conductive region of the dicing area. The irradiation width is 400-800 μm. The laser is a red picosecond laser with a wavelength of 1035-1060 nm and a scanning rate of 500-800 mm / s. Irradiating the first doped conductive region of the dicing area with a red picosecond laser modifies the borosilicate glass (BSG) and boron-rich layer on the surface of the first doped conductive region, facilitating subsequent cleaning. By limiting the laser wavelength to 1035-1060 nm, controlling the irradiation width to 400-800 μm, and using a specific scanning rate, the laser energy is precisely applied to the borosilicate glass layer and the boron-rich layer. Utilizing the high selective photothermal absorption characteristics of red picosecond lasers for boron compounds in this wavelength band, controllable removal and surface modification of the conductive region of the dicing area are achieved without damaging the silicon substrate. This ensures the integrity of the groove formation and clean edges after subsequent cleaning, better preventing recombination in the edge areas after dicing. At the same time, the limited irradiation width covers the entire path to be cut, and the scanning rate can improve the uniformity and efficiency of the modification process.

[0057] In some alternative embodiments, the step of cleaning the first doped conductive region after laser treatment includes:

[0058] The first doped conductive region undergoes a first wet etching process. The solution for the first wet etching process includes alkali and pure water, with a volume percentage of alkali to pure water of (2~3):(97~98). The temperature of the first wet etching process is 65~72℃, and the time is 100~150s. The volume percentage of alkali to pure water can be 2:98, 2.5:97.5, or 3:97. The advantage of using an etching solution including alkali and pure water is that the cleaning of the laser area is more thorough. The advantage of setting the volume percentage within the above range is that it ensures effective pre-removal of the boron-rich layer in the modified region and reduces the recombination of residual dead layers. This wet etching process acts on the first doped conductive region after laser modification, avoiding damage to the underlying silicon substrate. At the same time, it can ensure that the boron-rich residues are completely removed, thereby overcoming the problems of insufficient removal or over-etching caused by the lack of parameter control and laser modification in traditional cleaning methods. This ensures that the edge of the battery after subsequent laser cutting has a certain distance from the first doped conductive region, which can reduce the problem of edge recombination.

[0059] In some optional embodiments, the preparation method further includes:

[0060] While cleaning the first doped conductive region after laser treatment, a second wet etching process is performed on the first doped conductive region located on the second side of the silicon wafer. The second side is then polished after etching. The solution for the second wet etching process includes alkali, additives, and pure water, with a volume percentage of (1~2):(0.6~0.8):(97.2~98.4). The temperature for the second wet etching process is 65~72℃, and the time is 350~500s. The volume percentage of alkali, additives, and pure water can be 1:0.6:98.4, 1.5:0.7:97.8, or 2:0.8:97.2. Simultaneously with the formation of the first doped conductive region on the first side, a plating process occurs on other surfaces of the silicon wafer. The first doped conductive regions on these other surfaces need to be removed. The solution for the second wet etching process can be the same as or different from the solution for the first wet etching process. After removing the first doped conductive region on the second surface, the second surface can be polished, for example, by mechanical polishing or chemical polishing, in order to form structures such as the tunnel oxide layer. This can completely remove the first doped conductive region on the second surface, effectively eliminating carrier recombination centers caused by high-concentration boron doping on the second surface, significantly reducing the surface recombination rate, and providing a clean silicon substrate interface for the doped conductive layer formed by subsequent phosphorus diffusion. At the same time, thoroughly removing boron impurities can prevent them from diffusing into the tunnel oxide layer or the doped conductive layer during high-temperature processes, ensuring the integrity and stability of the passivation contact.

[0061] In some alternative embodiments, the steps of forming the tunneling oxide layer and the doped conductive layer include:

[0062] A tunneling oxide layer is formed on the second side of the polished silicon wafer. On the second side (back side) of the polished silicon wafer, an ultrathin (about 1~2nm) tunneling oxide layer (which can be SiO2) is formed by thermal oxidation or wet oxidation process. This layer has atomic-level flatness and high insulation, which can effectively prevent majority carriers (holes) from passing through, while allowing minority carriers (electrons) to be transported efficiently through quantum tunneling effect.

[0063] An intrinsic amorphous silicon layer is formed on the side of the tunneling oxide layer facing away from the silicon wafer and on the side of the first doped conductive region facing away from the silicon wafer. On top of the tunneling oxide layer, an intrinsic amorphous silicon layer (ia-Si:H) with a thickness of approximately 50-150 nm is deposited using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). This layer serves as a precursor for subsequent doping; its amorphous structure facilitates the uniform diffusion and crystallization of phosphorus atoms into polycrystalline silicon at high temperatures. Simultaneously, a wraparound plating process occurs on the first surface, forming another intrinsic amorphous silicon layer on the boron diffusion region of the first surface.

[0064] Phosphorus source diffusion is performed on the intrinsic amorphous silicon layer located on the tunneling oxide layer to form a doped conductive layer. The phosphorus source includes phosphorus oxychloride, and the diffusion temperature is 870~900℃. The silicon wafer is placed in a diffusion furnace, and phosphorus oxychloride (POCl3) is introduced as the phosphorus source. High-temperature diffusion is carried out in the temperature range of 870~900℃. Under these conditions, phosphorus atoms diffuse from the gas phase into the intrinsic amorphous silicon layer and diffuse to the interface with the tunneling oxide layer to form a doped polycrystalline silicon layer (i.e., a doped conductive layer). At the same time, the amorphous silicon crystallizes into polycrystalline silicon, forming a complete “n”. + The passivated contact structure is "poly / SiOx / n-Si". This structure not only has good surface passivation capability, but also provides low contact resistance, which can significantly improve the open-circuit voltage and fill factor of the battery.

[0065] In some alternative implementations, the step of laser cutting the silicon wafer includes:

[0066] A laser is used to scan the silicon wafer in the first groove of the dicing area. The laser scanning width is 1.5~2μm, the wavelength is 1035~1060nm, and the scanning rate is 150~200mm / s. During the laser scanning process, the area on the second side of the silicon wafer corresponding to the dicing area is cooled. In the above steps, by using a laser to scan the silicon wafer in the first groove of the dicing area with specific parameters, controlling the scanning width, wavelength, and scanning rate within the above range, and simultaneously cooling the area on the second side of the silicon wafer corresponding to the dicing area, the local thermal effect generated by the laser energy when it acts on the first groove for cutting has a large temperature difference with the temperature of the cooled area. The temperature difference is used to generate thermal stress in the silicon wafer in the area not affected by the laser, thus causing thermal cracking and achieving the cutting of the silicon wafer. In this way, by controlling the temperature difference between heating and cooling, non-destructive fracture can be achieved by "indirect cutting"—the laser only needs to provide a local heat source and does not need to completely penetrate the silicon wafer. It can induce spontaneous and neat fracture of the silicon material along the pre-etched weakened area (first groove) by relying on the difference in thermal expansion. This significantly reduces the laser energy requirement and avoids slag, microcracks, edge recasting layers, or thermal damage that are easily caused by traditional laser cutting, thus preserving the crystal integrity of the cut edge. At the same time, the cooling surface suppresses heat diffusion, concentrates stress in the grooving area, improves the controllability and consistency of crack direction, and ensures that the cut edge is flat, free of debris, and free of electrical defects.

[0067] While a doped conductive layer is formed on the intrinsic amorphous silicon layer located on the tunneling oxide layer, a polycrystalline silicon layer is formed on the side of the intrinsic amorphous silicon layer located away from the silicon wafer in the first doped conductive region. In some optional embodiments, the step of cleaning multiple cell wafers includes:

[0068] Multiple cell slabs are subjected to a third wet etching process to remove the polycrystalline silicon layer. The alkaline solution used in this process comprises alkali, additives, and pure water, with a volume percentage of alkali, additives, and pure water of (2.5~3.5):(0.5~1.0):(95.5~97). The temperature is 65~72℃, and the etching time is 350~800s. The volume percentages of alkali, additives, and pure water can be 2.5:0.5:97, 3:0.8:96.2, or 3.5:1:95.5. Using an alkaline solution comprising alkali, additives, and pure water, and setting the volume percentages within the aforementioned ranges, ensures more thorough cleaning of the polycrystalline silicon layer.

[0069] A fourth wet etching process is performed on multiple cell slabs to remove the borosilicate glass layer on the surface of the first doped conductive region and the phosphosilicate glass layer on the surface of the doped conductive layer. The acidic solution for the fourth wet etching process includes hydrofluoric acid and pure water, with a volume percentage of (4~5):(5~6), a temperature of 25~30℃, and a time of 100~300s. Specifically, the volume percentages of hydrofluoric acid and pure water are 4:6, 4.5:5.5, and 5:5. By using an acidic solution containing hydrofluoric acid and pure water and setting the volume percentages within the above ranges, the phosphosilicate glass layer can be completely removed.

[0070] By sequentially performing a third and fourth wet etching process on multiple cell slabs, using alkaline solutions with specific ratios and process parameters (alkali, additives, and pure water) to selectively remove the polycrystalline silicon layer formed from the intrinsic amorphous silicon layer deposited onto the first surface of the silicon wafer on the side opposite to the first doped conductive region, and simultaneously using hydrofluoric acid solution with specific ratios and process parameters to remove the borosilicate glass layer on the surface of the first doped conductive region and the phosphosilicate glass layer on the surface of the second doped conductive layer, the residues can be completely removed. This provides a clean interface for the subsequent uniform deposition of the first passivation layer and reliable contact of the electrodes, thereby avoiding risks such as increased surface recombination, passivation failure, and increased series resistance caused by glass layer or polycrystalline silicon residues, and improving cell efficiency and yield.

[0071] In some alternative implementations, the step of passivating multiple cell segments includes:

[0072] A first passivation layer and a first antireflection layer are formed on the side of the first doped conductive region away from the silicon wafer. The thickness of the first passivation layer in the first direction is 3-4 nm, and the thickness of the first antireflection layer is 75-80 nm. The thickness of the first passivation layer deposited around to the cut surface of the cell is 4-5 nm. The first direction is perpendicular to the first surface. The material of the first passivation layer can be a single layer or a composite layer such as aluminum oxide, silicon nitride, silicon oxide, and silicon oxynitride. The coverage thickness of the first passivation layer on the front side of the cell can be 3-4 nm. The first passivation layer is deposited around the silicon wafer during deposition, and the coverage thickness at the cut edge of the cell can be 4-5 nm. The material of the first antireflection layer can be silicon nitride, and it can be a single layer or a multilayer film.

[0073] A second passivation layer is formed on the side of the doped conductive layer facing away from the silicon wafer. The total thickness of the first antireflective layer and the second passivation layer, deposited around the cut edge of the cell, is 80-100 nm in a second direction, perpendicular to the first direction. The material of the second passivation layer can be silicon nitride. During the deposition of the first antireflective layer and the second passivation layer, a wrap-around deposition process is performed to ensure that the coverage thickness of both at the cell cut edge is 80-100 nm. The material of the second passivation layer can be a single layer or composite layer such as aluminum oxide, silicon nitride, silicon oxide, and silicon oxynitride, and can be the same as or different from the material of the first passivation layer. The wrap-around plating of the first passivation layer, the first antireflection layer, and the second passivation layer at the battery cutting edge can replace the passivation process in the traditional process. The equipment used is simpler, saving costs. It can also avoid the problem of defect passivation failure caused by the first passivation layer being too thin or the antireflection layer being unevenly covered at the edge. It improves the electrical stability of the cutting edge and solves the problems of uneven coverage of the first passivation layer, defect escape, and increased surface recombination caused by process fluctuations in the edge area. Ultimately, it achieves efficient, uniform, and highly reliable passivation and electrical optimization of the cutting edge without additional equipment investment.

[0074] In the above embodiments, the deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and can be reasonably selected according to the actual situation. This application does not make specific limitations.

[0075] In some alternative implementations, the step of printing electrodes on multiple cell wafers includes:

[0076] Grid lines are printed on the first anti-reflection layer and the second passivation layer; the formed fine grid can be used to collect current, and the main grid can be used to converge the current collected by the fine grid and provide sufficient tension between the main grid and the solder strip (or interconnect strip) to make the battery structure more stable.

[0077] The grid lines are sintered at a temperature of 740~780℃. The grid lines can be sintered in a high-temperature sintering furnace. Controlling the temperature within the above range can enable the metal grid lines to form a good ohmic contact with the cell structure.

[0078] A laser-assisted sintering (LAS) process is used for secondary sintering of the grid lines. The ratio of the laser output power to the maximum output power of the laser in this process is 20-40%, and the bias voltage applied to the grid lines is 15-25V. In this LAS process, high-intensity laser irradiation of the solar cell excites carrier migration and activates local defect regions, effectively repairing interface defects not completely eliminated during sintering, improving the ohmic contact quality between the grid lines and the silicon substrate, and thus significantly improving electrode conductivity.

[0079] Another embodiment of this application also proposes a solar cell, which is prepared using the solar cell preparation method described above. For example... Figure 2 As shown, the solar cell described above can be a TOPCon cell, including a silicon wafer 10, a first doped conductive region 20, a first passivation layer 30, a first antireflection layer 40, a first electrode 50, a tunneling oxide layer 60, a doped conductive layer 70, a second passivation layer 80, and a second electrode 90.

[0080] Another embodiment of this application also proposes a photovoltaic module, such as... Figure 3 As shown, it includes: a battery string, which is composed of multiple solar cells 01 prepared by the method described above, or a combination of multiple solar cells 01 as described above; an encapsulating film 02 for covering the surface of the battery string; and a cover plate 03 for covering the surface of the encapsulating film 02 facing away from the battery string. The solar cells 01 can be electrically connected to each other by conductive strips 04, which are welded to the electrodes on the solar cells 01.

[0081] The aforementioned encapsulating film can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, EPE film, or PVP film. Specifically, EP film refers to a co-extruded film composed of stacked EVA and POE films; EPE film refers to a co-extruded film formed by sequentially stacking EVA, POE, and EVA films; and PVP film refers to a co-extruded film formed by stacking POE, EVA, and POE films. The co-extruded film can be manufactured by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0082] The aforementioned cover plate can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate facing the encapsulating film can be an uneven surface or a textured surface containing multiple raised structures, which can increase the utilization rate of incident light.

[0083] The preparation method of the solar cell described above in this application will be specifically described below with reference to specific embodiments and comparative examples.

[0084] Example 1

[0085] Step 1: Provide an N-type silicon wafer with a thickness of 150μm, and texturize the silicon wafer;

[0086] Step 2: Place the silicon wafer in a diffusion furnace and perform boron source diffusion on the silicon wafer to form a first doped conductive region on the first side of the silicon wafer. The boron source includes boron trichloride, and the diffusion temperature is 910℃. The first doped conductive region is P-type doped with a doping concentration of 1.9E12cm⁻¹. -3 The junction depth is 80nm.

[0087] Step 3: Use a laser to irradiate the first doped conductive region of the area to be diced. The width of the laser irradiation is 400~800μm. The laser includes a red picosecond laser with a wavelength of 1035nm and a scanning rate of 650mm / s.

[0088] Step 4: Perform a first wet etching process on the first doped conductive region. The solution for the first wet etching process includes alkali and pure water, with a volume percentage of alkali to pure water of 2:98. The temperature of the first wet etching process is 67°C and the time is 100s. This removes the first doped conductive region located in the area to be diced, forming a first groove in the silicon wafer. While cleaning the first doped conductive region after laser treatment, perform a second wet etching process on the first doped conductive region located on the second side of the silicon wafer. Polish the second side after removal. The solution for the second wet etching process includes alkali, additives, and pure water, with a volume percentage of alkali, additives, and pure water of 1:0.6:98.4. The temperature of the second wet etching process is 67°C and the time is 430s.

[0089] Step 5: Form a tunneling oxide layer on the second surface of the polished silicon wafer. The tunneling oxide layer is silicon dioxide and has a thickness of 2nm.

[0090] Step 6: Form an intrinsic amorphous silicon layer on the side of the tunneling oxide layer facing away from the silicon wafer and on the side of the first doped conductive region facing away from the silicon wafer; perform phosphorus source diffusion on the intrinsic amorphous silicon layer located on the tunneling oxide layer to form a doped conductive layer. The phosphorus source includes phosphorus oxychloride, and the diffusion temperature is 890℃. The doped conductive layer is an N-type doped polycrystalline silicon layer with a doping concentration of 2.5E20cm⁻¹. -3 The thickness is 80nm; at the same time, the intrinsic amorphous silicon layer located on the side of the first doped conductive region away from the silicon wafer forms a polycrystalline silicon layer.

[0091] Step 7: Perform a third wet etching process on multiple cell slabs to remove the polysilicon layer. The alkaline solution for the third wet etching process includes alkali, additives, and pure water, with a volume percentage of 2.5:0.5:97. The temperature is 67°C and the time is 400s. Perform a fourth wet etching process on multiple cell slabs to remove the borosilicate glass layer on the surface of the first doped conductive region and the phosphosilicate glass layer on the surface of the doped conductive layer. The acidic solution for the fourth wet etching process includes hydrofluoric acid and pure water, with a volume percentage of 4:6. The temperature is 25°C and the time is 150s.

[0092] Step 8: Use a laser to perform laser scanning on the silicon wafer in the first groove of the dicing area. The laser scanning width is 1.7μm, the wavelength is 1035nm, and the scanning rate is 170mm / s. During the laser scanning process, the area on the second side of the silicon wafer corresponding to the dicing area is cooled.

[0093] Step 9: A first passivation layer and a first antireflection layer are formed on the side of the first doped conductive region away from the silicon wafer. The thickness of the first passivation layer in the first direction is 4 nm, the thickness of the first antireflection layer is 80 nm, and the thickness of the first passivation layer deposited around to the cut surface of the cell is 5 nm. The first direction is perpendicular to the first surface. The material of the first passivation layer is aluminum oxide, and the material of the first antireflection layer is silicon nitride.

[0094] Step 10: A second passivation layer is formed on the side of the doped conductive layer away from the silicon wafer. The total thickness of the first antireflection layer and the second passivation layer, which are deposited around the cut surface of the cell, is 90 nm in the second direction. The second direction is perpendicular to the first direction. The material of the second passivation layer is aluminum oxide.

[0095] Step 11: Print gate lines on the first antireflection layer and the second passivation layer. The gate lines are made of Ag and have a thickness of 12 μm.

[0096] Step 12: Sinter the grid lines at a temperature of 760℃;

[0097] Step 13: The grid lines are sintered a second time using a laser-assisted sintering process. The ratio of the laser output power to the maximum output power of the laser in the laser-assisted sintering process is 30%. The bias voltage applied to the grid lines is 20V. The cells are then divided into solar cells.

[0098] Comparative Example 1

[0099] The difference from Example 1 is that steps 3 and 8 are missing, and after step 13, the solar cell is subjected to conventional laser scribing, and after laser scribing, the solar cell is subjected to conventional edge passivation to obtain a solar cell.

[0100] One hundred solar cells were selected to test the solar cells prepared in Example 1 and Comparative Example 1 above. The average data from the tests are shown in the table below:

[0101] Table 1

[0102]

[0103] As can be seen from the above experimental data, compared with Comparative Example 1, Example 1 showed an improvement of 0.3% in passivation characterization parameter pFF, an improvement of 0.2mV in Voc, and an improvement of 0.21% in photoelectric conversion efficiency. This indicates that the solar cells prepared using the solar cell preparation method of this application have improved performance in all aspects.

[0104] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for preparing a solar cell, characterized in that, include: A silicon wafer is provided after diffusion of a boron source, the silicon wafer having a first side and a second side opposite to each other, a first doped conductive region is formed on the first side after diffusion of the boron source, and a dicing area is provided on the first side; A first doped conductive region in the area to be diced is treated with a laser, and the laser-treated first doped conductive region is cleaned to remove the first doped conductive region located in the area to be diced, thereby forming a first groove in the silicon wafer. A tunneling oxide layer and a doped conductive layer are formed on the second side of the silicon wafer, wherein the doped conductive layer has a different doping type than the first doped conductive region. The silicon wafer is laser-cut along the first groove to obtain multiple segmented cells; Multiple of the aforementioned cell segments are cleaned, passivated, have electrodes printed, and are tested and sorted to obtain solar cells.

2. The preparation method according to claim 1, characterized in that, The steps for forming the first doped conductive region include: A silicon wafer is provided, and the silicon wafer is texturized. The silicon wafer is placed in a diffusion furnace and diffused with the boron source to form the first doped conductive region on the first surface of the silicon wafer. The boron source includes boron trichloride, and the diffusion temperature of the boron source is 850~920℃.

3. The preparation method according to claim 1, characterized in that, The step of processing the first doped conductive region in the area to be diced using a laser includes: The first doped conductive region of the area to be diced is irradiated with a laser, the width of the laser irradiation is 400~800μm, and the laser includes a red picosecond laser with a wavelength of 1035~1060nm and a scanning rate of 500~800mm / s.

4. The preparation method according to claim 1, characterized in that, The step of cleaning the first doped conductive region after laser treatment includes: The first doped conductive region is subjected to a first wet etching process. The solution of the first wet etching process includes alkali and pure water, and the volume percentage of the alkali and the pure water is (2~3):(97~98). The temperature of the first wet etching process is 65~72℃ and the time is 100~150s.

5. The preparation method according to claim 4, characterized in that, The preparation method further includes: While cleaning the first doped conductive region after laser treatment, a second wet etching process is performed on the first doped conductive region located on the second side of the silicon wafer, and the second side after removal is polished. The solution for the second wet etching process includes alkali, additives and pure water, and the volume percentage of the alkali, the additives and the pure water is (1~2):(0.6~0.8):(97.2~98.4). The temperature of the second wet etching process is 65~72℃ and the time is 350~500s.

6. The preparation method according to claim 5, characterized in that, The steps of forming the tunneling oxide layer and the doped conductive layer include: A tunneling oxide layer is formed on the second surface of the polished silicon wafer; An intrinsic amorphous silicon layer is formed on the side of the tunneling oxide layer facing away from the silicon wafer and on the side of the first doped conductive region facing away from the silicon wafer. The intrinsic amorphous silicon layer located on the tunneling oxide layer is diffused with a phosphorus source to form the doped conductive layer. The phosphorus source includes phosphorus oxychloride, and the temperature during phosphorus source diffusion is 870~900℃.

7. The preparation method according to claim 1, characterized in that, The step of laser cutting the silicon wafer includes: A laser is used to perform laser scanning on the silicon wafer in the first groove of the area to be diced. The width of the laser scan is 1.5~2μm, the wavelength is 1035~1060nm, and the scanning rate is 150~200mm / s. During the laser scanning process, the area on the second surface of the silicon wafer corresponding to the area to be diced is cooled.

8. The preparation method according to claim 6, characterized in that, While the doped conductive layer is formed on the intrinsic amorphous silicon layer located on the tunneling oxide layer, a polycrystalline silicon layer is formed on the side of the intrinsic amorphous silicon layer located away from the silicon wafer in the first doped conductive region. The step of cleaning the multiple cell wafers includes: The multiple cell wafers are subjected to a third wet etching process to remove the polycrystalline silicon layer. The solution for the third wet etching process includes alkali, additives and pure water, and the volume percentage of alkali, additives and pure water is (2.5~3.5):(0.5~1.0):(95.5~97), the temperature is 65~72℃ and the time is 350-800s. A fourth wet etching process is performed on multiple of the said segmented cells to remove the borosilicate glass layer located on the surface of the first doped conductive region and the phosphosilicate glass layer located on the surface of the doped conductive layer. The acidic solution of the fourth wet etching process includes hydrofluoric acid and pure water, with the volume percentage of hydrofluoric acid and pure water being (4~5):(5~6), the temperature being 25~30℃, and the time being 100~300s.

9. The preparation method according to claim 1, characterized in that, The passivation step for the multiple said segmented cells includes: A first passivation layer and a first antireflection layer are formed on the side of the first doped conductive region away from the silicon wafer. The thickness of the first passivation layer in the first direction is 3-4 nm, and the thickness of the first antireflection layer is 75-80 nm. The thickness of the first passivation layer deposited around to the cut surface of the slab cell is 4-5 nm. The first direction is perpendicular to the first surface. A second passivation layer is formed on the side of the doped conductive layer away from the silicon wafer. The total thickness of the first antireflection layer and the second passivation layer, which are deposited around the cut surface of the slab cell, is 80~100nm in a second direction, and the second direction is perpendicular to the first direction.

10. The preparation method according to claim 9, characterized in that, The step of printing electrodes on multiple of the said slab cells includes: Print gate lines on the first antireflection layer and the second passivation layer; The grid lines are sintered at a temperature of 740~780℃. The gate wire is sintered a second time using a laser-assisted sintering process. The ratio of the laser output power to the maximum output power of the laser in the laser-assisted sintering process is 20-40%, and the bias voltage applied to the gate wire is 15-25V.

11. A solar cell, characterized in that, The solar cell is prepared using the method described in any one of claims 1 to 10.

12. A photovoltaic module, characterized in that, include: A battery string, consisting of multiple solar cells as described in claim 11 connected together; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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