2.5d interposer copper exposure preparation process and package structure

Abstract

The application provides a 2.5D interposer copper exposure preparation process and a packaging structure, and relates to the technical field of semiconductor packaging. The process comprises the following steps: providing a substrate with a conductive column; wherein the substrate comprises a first surface and a second surface arranged oppositely, and an end of the conductive column close to the first surface protrudes from the first surface of the substrate; the substrate has a module mounting area and a skeleton area. A protective layer is formed on the first surface, and the protective layer covers the first surface and the conductive column. A first opening is formed on the protective layer located in the module mounting area; an insulating layer is formed in the first opening; a first dielectric layer covering the insulating layer and the protective layer is formed. The first dielectric layer and the insulating layer are ground to expose the end surface of the conductive column; and a bump electrically connected with the conductive column is formed. The process is favorable for the protection of the conductive column, prevents the fracture of the conductive column, reduces the risk of delamination and hidden cracking of the insulating layer in the cutting process, and improves the product quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D exposed copper interposer fabrication process and packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet technology adopts a new design approach, packaging small chips with different functions together to form a heterogeneous integrated chip package structure. As the input and output density of chips increases and the number integrated into a single package increases significantly, various 2.5D and 3D packaging technologies, as multi-chip packaging solutions, connect the pad lines of adjacent chips within a single package through redistribution layers.

[0003] During the packaging process, the product needs to be cut and separated into individual products. During the cutting process, the cutting tool is likely to come into physical contact with the surface or interior of the material, which generates shear stress, tensile stress or compressive stress during the cutting process. This can cause problems such as microcracks or delamination in the insulating layer of the packaging structure, affecting product quality and performance. Summary of the Invention

[0004] The purpose of this invention is to provide a 2.5D exposed copper interposer fabrication process and packaging structure, which helps to protect the conductive pillars from breakage, reduce the risk of insulation layer delamination and microcracks during the cutting process, and improve product quality.

[0005] In a first aspect, the present invention provides a process for preparing a 2.5D exposed copper interposer, comprising: A substrate with conductive pillars is provided; wherein the substrate includes a first surface and a second surface disposed opposite to each other, and one end of the conductive pillar protrudes from the first surface of the substrate; the substrate has a module mounting area and a skeleton area; A protective layer is formed on the first surface, the protective layer covering the first surface and the conductive pillar; A first opening is formed on the protective layer located in the module mounting area; An insulating layer is formed within the first opening; A first dielectric layer is formed covering the insulating layer and the protective layer; Grind the first dielectric layer and the insulating layer to expose the end face of the conductive pillar; A protrusion is formed that is electrically connected to the conductive post.

[0006] In an optional implementation, in the step of forming a first opening in the protective layer located in the module mounting area: The depth of the first opening is equal to the thickness of the protective layer.

[0007] In an optional implementation, in the step of forming a first opening in the protective layer located in the module mounting area: The first opening is formed on the protective layer located in the module mounting area; A second opening is formed in the protective layer located in the skeleton region; The step of forming an insulating layer in the first opening includes forming the insulating layer in both the first opening and the second opening.

[0008] In an optional implementation, in the step of forming a second opening in the protective layer located in the skeleton region: the depth of the second opening is equal to the thickness of the protective layer.

[0009] In an optional embodiment, after the step of forming the insulating layer in the first opening and the second opening respectively, the method further includes: A third opening is made in the insulating layer within the second opening; In the step of forming a first dielectric layer covering the insulating layer and the protective layer, the first dielectric layer fills the third opening.

[0010] In an optional embodiment, the substrate has a plurality of spaced-apart module mounting areas, each of the module mounting areas being rectangular; The cross-sectional shape and size of each of the first openings are the same as the shape and size of the module mounting area; the second openings are distributed along the extension direction of the rectangular diagonal of the first opening.

[0011] In an optional embodiment, the thickness of the insulating layer is less than the depth of the first opening and the depth of the second opening, respectively; the remaining space in the first opening and the second opening is filled by the first dielectric layer.

[0012] In an optional implementation, in the step of forming an insulating layer within the first opening: the insulating layer covers the end face and sidewalls of the conductive post.

[0013] In an optional implementation, after the step of forming the bumps electrically connected to the conductive post, the method further includes: A connection terminal electrically connected to the conductive pillar is formed on the second surface of the substrate; Chips are mounted at the connection end and / or the bumps; The skeleton region is cut to separate it into individual products; wherein, the protective layer is removed.

[0014] In an optional implementation, prior to the step of forming a protective layer on the first surface, the method further includes: The edge of the second surface is cut in a ring shape to form a first annular groove; A first carrier is mounted on the second surface; a first debonding adhesive on the first carrier fills the first annular groove; Before forming the connection end electrically connected to the conductive pillar on the second surface of the substrate, the first carrier and the first debonding adhesive are removed; a second carrier is mounted on the side having the bump; the cross-section of the second carrier is larger than the cross-section of the first dielectric layer.

[0015] In an optional implementation, after the step of mounting the chip at the connection end and / or the bump, the following is included: molding the chip to form a molded body; The step of cutting the skeleton region to separate and form a single product includes: making a circumferential cut on the edge of the encapsulation body; Remove the second vehicle; The skeleton region is cut to separate and form individual products.

[0016] In an optional implementation, the step of forming a bump electrically connected to the conductive post includes: A second dielectric layer is formed on the first dielectric layer; A first window is formed on the second dielectric layer to expose the end face of the conductive pillar; The bump is formed by filling the first window with a first metal layer. Alternatively, a second window can be formed on the second dielectric layer to expose the end face of the conductive pillar; A second metal layer is filled into the second window to form a first wiring layer; A third dielectric layer is formed on the second dielectric layer; A third window is formed on the third dielectric layer to expose the first wiring layer; The bump is formed by filling the third window with a third metal layer.

[0017] Secondly, the present invention provides a packaging structure made using a 2.5D exposed copper interposer fabrication process as described in any of the foregoing embodiments.

[0018] In an optional implementation, it includes: Substrate, the substrate including a first surface and a second surface disposed opposite to each other; A conductive pillar is embedded in the substrate; one end of the conductive pillar protrudes from the first surface. An insulating layer is disposed on the first surface and covers the sidewalls of the conductive pillar; the insulating layer forms grooves between the sidewalls of the conductive pillar. A first dielectric layer, the first dielectric layer filling the groove; A second dielectric layer is disposed on the side of the first dielectric layer away from the substrate; The bump is electrically connected to the conductive post and protrudes from or is flush with the second dielectric layer.

[0019] In an optional embodiment, a first conductive layer is connected to one end of the conductive post near the first surface. The first conductive layer includes pads or wiring layers, and the first conductive layer and the conductive post are electrically connected.

[0020] In an optional embodiment, the first conductive layer is connected to a plurality of the conductive pillars.

[0021] In an optional embodiment, the second surface is provided with a second wiring layer and a connection terminal; the second wiring layer is electrically connected to the conductive post, and the connection terminal is electrically connected to the second wiring layer; The chip is mounted on one side of the bump, and / or the chip is mounted on one side of the connector; the chip is encapsulated in a molding compound.

[0022] The 2.5D exposed copper interposer fabrication process and packaging structure provided by this invention have the following beneficial effects: In the packaging process, protective and insulating layers are set up alternately. This helps reduce stress on the insulating layer during the cutting process, preventing problems such as delamination and microcracks in the insulating layer, thus improving product quality and performance. Forming an insulating layer in the module mounting area enhances insulation performance and prevents electrostatic discharge (ESD) from damaging the chip and wiring structure during the process. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 One of the process diagrams for the fabrication of exposed copper in a 2.5D interposer layer provided in an embodiment of the present invention; Figure 2 The second schematic diagram of the 2.5D exposed copper interposer fabrication process provided in this embodiment of the invention; Figure 3 A schematic diagram of the process for forming an insulating layer in the first opening during the 2.5D exposed copper interposer fabrication process provided in an embodiment of the present invention; Figure 4A schematic diagram showing the distribution of the insulating layer and protective layer in the skeleton region during the 2.5D exposed copper interposer fabrication process provided in this embodiment of the invention; Figure 5 A schematic diagram of a structure in which a third opening is made on the insulating layer in the skeleton region during the 2.5D exposed copper interposer fabrication process provided in this embodiment of the invention; Figure 6 This is a schematic diagram of the first process for forming bumps in the 2.5D exposed copper interposer fabrication process provided in this embodiment of the invention. Figure 7 This is a schematic diagram of a second process for forming bumps in the 2.5D exposed copper interposer fabrication process provided in an embodiment of the present invention. Figure 8 This is one of the process diagrams of the second surface side in the 2.5D exposed copper interposer fabrication process provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the structure in which a bump is formed on one side of the second surface during the 2.5D exposed copper interposer fabrication process provided in this embodiment of the invention. Figure 10 This is the second schematic diagram of the process for fabricating a 2.5D exposed copper interposer layer in an embodiment of the present invention, showing one side of the second surface. Figure 11 This is the third schematic diagram of the process for fabricating a 2.5D exposed copper interposer layer in an embodiment of the present invention, showing one side of the second surface. Figure 12 This is a schematic diagram of the process of selecting another second carrier on one side of the second surface in the 2.5D exposed copper interposer fabrication process provided in the embodiments of the present invention; Figure 13 A schematic diagram of the packaging structure prepared by the 2.5D exposed copper interposer process provided in this embodiment of the invention; Figure 14 This is a partial schematic diagram of another structure of the packaging structure prepared by the 2.5D exposed copper interposer process provided in the embodiment of the present invention; Figure 15 This is a schematic diagram illustrating an application scenario of the packaging structure prepared by the 2.5D exposed copper interposer process provided in this embodiment of the invention.

[0025] Icons: 100-Substrate; 101-First surface; 102-Second surface; 103-Conductive pillar; 104-First annular groove; 105-First carrier; 106-First debonding adhesive; 110-Protective layer; 111-First opening; 120-Insulating layer; 121-Groove; 112-Module mounting area; 113-Second opening; 114-Third opening; 131-First dielectric layer; 132-Second dielectric layer; 133-First window; 134-Bump; 135- Second window; 136-First conductive layer; 137-Third dielectric layer; 138-Third window; 139-Third conductive layer; 141-Second debonding adhesive; 142-Second carrier; 1421-Edge portion; 143-Fourth dielectric layer; 144-Fourth window; 145-Second wiring layer; 146-Fifth dielectric layer; 147-Fifth window; 148-Bump; 150-Chip; 160-Encapsulation; 210-Substrate; 220-Metal ring; 230-Component. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0031] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0032] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] The 2.5D exposed copper interposer fabrication process and packaging structure proposed in this invention are beneficial for protecting the conductive pillars, preventing their breakage, reducing the risk of insulation layer delamination and microcracks during the cutting process, and improving product quality.

[0034] This invention provides a process for fabricating a 2.5D exposed copper interposer, comprising: Please combine Figure 1 A substrate 100 with conductive pillars 103 is provided. The substrate 100 includes a first surface 101 and a second surface 102 disposed opposite to each other, and the conductive pillars 103 are embedded in the substrate 100. One end of the conductive pillar 103 protrudes from the first surface 101 of the substrate 100. The substrate 100 has a module mounting area 112 and a skeleton area. The module mounting area 112 refers to the area used for subsequent mounting of chips 150. The skeleton area is the non-mounting area, which can also be understood as the cutting area where the dicing track is located. The chips 150 can be mounted upright or flip-chip. The number and type of chips 150 are not limited. The number can be one or more, and the types include, but are not limited to, one or more of SOC chips, HBM chips, RF chips, CPUs, and GPUs. The material of the substrate 100 is silicon-based or germanium-based substrate material, or a substrate made of silicon oxide, phosphosilicate glass, fluorine-containing glass, or glass. The thickness of the substrate 100 is 600um to 1500um. The conductive post 103 can be pre-fabricated. The conductive post 103 can be fabricated using the TSV perforation process. The end face of the conductive post 103 near the second surface 102 is flush with the second surface 102.

[0035] Optionally, the edge of the second surface 102 is cut in a ring shape to form a first annular groove 104, i.e., a stepped structure is formed at the edge. This has a barrier effect when the first carrier 105 is attached, which can prevent the adhesive from overflowing and contaminating the first surface 101.

[0036] In this embodiment, a first carrier 105 is mounted on the second surface 102; a first debonding adhesive 106 on the first carrier 105 fills the first annular groove 104. The first carrier 105 can be made of metal or glass. The first debonding adhesive 106 is applied to the first carrier 105 or the second surface 102 to fix the substrate 100 to the first carrier 105. The first debonding adhesive 106 can be a self-crosslinking resin such as an aqueous acrylic emulsion or an aqueous styrene-acrylic emulsion, and the first carrier 105 and the substrate 100 can be separated later by laser debonding or ultraviolet debonding.

[0037] Optionally, the formation process of one end of the conductive post 103 protruding from the first surface 101 is roughly as follows: It should be noted that upon arrival, the end of the conductive post 103 near the first surface 101 is embedded within the substrate 100. The first surface 101 of the substrate 100 must first be ground so that the end face of the conductive post 103 near the first surface 101 is flush with the first surface 101. The grinding process can employ chemical polishing or diamond polishing. If chemical polishing is used, a chemical polishing fluid such as ammonia, HF acid, or citric acid can be used. Under the pressure of the polishing pad and the action of centrifugal force, the substrate 100 is ground to expose the end face of the conductive post 103.

[0038] Optionally, the substrate 100 can be thinned using methods such as dry etching, chemical etching, or laser grooving. If dry etching is used, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or hydrogen (H2) can be used to thin the substrate 100. If chemical etching is used, a mixture of hydrofluoric acid (HF), buffered oxide etching solution, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2) can be used to thin the substrate 100, thereby causing the end face of the conductive pillar 103 to protrude from the first surface 101 of the substrate 100. Optionally, the protrusion height of the conductive pillar 103 is from 2 micrometers to 60 micrometers.

[0039] Optionally, the bottom of the first annular groove 104 is flush with the end face of the conductive post 103. During grinding, when the end face of the conductive post 103 is exposed, the bottom of the first annular groove 104 is ground away, thus removing the step portion formed by the first annular groove 104. This arrangement helps to control the grinding accuracy and prevent over-grinding.

[0040] Please combine Figure 2Optionally, a protective layer 110 is formed on the first surface 101, covering the first surface 101 and the conductive pillars 103. The protective layer 110 covers the module mounting area 112 and the skeleton area of ​​the substrate 100. The material of the protective layer 110 can be any one or more of ABF film, polyimide, and benzocyclobutene. The protective layer 110 can be formed by processes such as spin coating or spray coating.

[0041] A first opening 111 is formed on the protective layer 110 located in the module mounting area 112. The first opening 111 can be formed using an exposure and development process.

[0042] Please combine Figure 3 An insulating layer 120 is formed within the first opening 111. Optionally, the insulating layer 120 is formed using vapor deposition methods such as PVCD, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The material of the insulating layer 120 can be any one or more of silicon oxide, silicon dioxide, silicon nitride, and silicon oxynitride. The insulating layer 120 uses an inorganic non-metallic material with silicon as its core, possessing high hardness, excellent insulation properties, and a resistivity greater than 10¹ at room temperature. 4 Ω cm, with a relatively high breakdown electric field strength; for example, the breakdown electric field strength of SiO2 is approximately 10. 6 The breakdown electric field strength of Si3N4 is approximately 10 V / cm. 6 ~10 7 With a strength of V / cm and no conductivity, the insulating layer 120 is suitable for electronic devices, improving insulation performance and preventing electrostatic discharge (ESD) ions from damaging the chip and wiring layers during the manufacturing process. The thickness of the insulating layer 120 is less than the depth of the first opening 111, facilitating better bonding between the subsequent first dielectric layer 131 and the insulating layer 120, and between the first dielectric layer 131 and the protective layer 110, preventing structural delamination or cracking. The insulating layer 120 covers the exposed sidewalls and heads of the conductive pillar 103, protecting it. The insulating layer 120 can be one or more layers.

[0043] Please combine Figure 4In some embodiments, when forming the first opening 111, a second opening 113 may also be formed on the protective layer 110 located in the skeleton region. The formation process of the second opening 113 is the same as that of the first opening 111, and can be completed simultaneously or in steps. Optionally, the depth of the first opening 111 and the depth of the second opening 113 are equal, and are respectively less than or equal to the thickness of the protective layer 110. In this embodiment, the depth of the first opening 111 and the depth of the second opening 113 are respectively equal to the thickness of the protective layer 110. In this way, the filled insulating layer 120 can directly contact the surface of the substrate 100, which can reduce the overall package height. Of course, in some embodiments, the depth of the first opening 111 and the depth of the second opening 113 can also be less than the thickness of the protective layer 110, which can play a better buffering role during polishing.

[0044] When the insulating layer 120 is filled into the first opening 111, the insulating layer 120 can also be filled into the second opening 113 simultaneously. Alternatively, the insulating layers 120 in the first opening 111 and the second opening 113 can be distributed. It can be understood that since the first opening 111 and the second opening 113 are respectively filled with the insulating layer 120, in the structure containing the protective layer 110, the module mounting area 112 is entirely filled with the insulating layer 120; in the skeleton area, the insulating layer 120 and the protective layer 110 are distributed in a grid pattern. This arrangement ensures the insulation performance of the module mounting area 112 while also allowing for the separation of the insulating layers 120 in the skeleton area and the module mounting area 112. Therefore, when cutting and separating individual products, the cutting stress will not act on the insulating layer 120 in the module mounting area 112, thus preventing microcracks, cracks, and delamination in the insulating layer 120 in the module mounting area 112, improving product performance and yield. The insulating layer 120 and the protective layer 110 in the skeleton area are distributed in an interlaced grid pattern. The protective layer 110 acts as a buffer to reduce the impact of cutting and tensile stress on the module mounting area 112 and improve the cutting quality.

[0045] Optionally, the insulating layer 120 and the protective layer 110 in the skeleton region are staggered in a grid pattern. The insulating layer 120 can prevent free electrostatic ions from breaking down the chip and wiring layer structure during the process, while the protective layer 110 acts as a buffer. It should be noted that if a continuous insulating layer structure is used, for example, if the insulating layer is SiO2, the poor thermal conductivity of the SiO2 film will hinder the conduction of heat generated during device operation to the substrate or heat dissipation structure, resulting in excessively high local temperatures. This can easily lead to warping, cracking, or even peeling due to the accumulation of thermal stress. In this embodiment, the insulating layer 120 and the protective layer 110 are staggered in a grid pattern. The small deformation of the grid can release thermal stress and quickly disperse the local concentrated load to the entire grid system. At the same time, the protective layer 110 in the porous structure of the grid helps to improve heat dissipation efficiency and reduce the risk of deformation, warping, cracking, or even peeling caused by temperature gradient stress.

[0046] It is understood that in wafer-level or panel-level packaging processes, a substrate 100 has multiple spaced-apart module mounting areas 112, each module mounting area 112 being approximately rectangular. The cross-sectional shape and size of each first opening 111 are the same as the shape and size of the module mounting area 112; second openings 113 are distributed along the extension of the rectangular diagonal of the first opening 111. The cross-sectional shape and size of the second opening 113 are the same as the cross-sectional shape and size of the first opening 111. Of course, in some other embodiments, the shape and size of the first opening 111 and the second opening 113 may be different. The number, position, and shape of the second openings 113 can be flexibly adjusted according to actual needs, and are not specifically limited here. For example, the cross-sectional shape of the second opening 113 can be any shape such as circular, triangular, quadrilateral, pentagonal, crescent-shaped, elliptical, annular, or wavy. In this way, the positional distribution of the insulating layer 120 and the protective layer 110 in the skeleton region can be flexibly designed.

[0047] It should be noted that in some implementation methods, please refer to... Figure 5 A third opening 114 is formed on the insulating layer 120 within the second opening 113; the third opening 114 is filled by the subsequent first dielectric layer 131. This allows for a greater interleaving density between the insulating layer 120 and the protective layer 110, improving buffering performance and the bonding between the protective layer 110 and the insulating layer 120, as well as the bonding between the protective layer 110 and the insulating layer 120 and the subsequently formed first dielectric layer 131. Furthermore, the third opening 114 serves a positioning function, which is beneficial in the coating process of the first dielectric layer 131, improving the positioning and recognition capabilities of the machine tool, and thus improving the accuracy of forming the first window 133 on the second dielectric layer 132.

[0048] Optionally, a first dielectric layer 131 is formed covering the insulating layer 120 and the protective layer 110. It is readily understood that since the thickness of the insulating layer 120 is less than the depth of the first opening 111, and the insulating layer 120 covers the sidewalls and end faces (heads) of the conductive pillars 103, i.e., the insulating layer 120 forms a groove 121 between the conductive pillars 103, the first dielectric layer 131 will fill the groove 121 or protrude from the opening of the groove 121. In this embodiment, the formed first dielectric layer 131 is flush with the surface of the protective layer 110. Optionally, the first dielectric layer 131 can be formed using spin coating or spray coating processes, and the material of the first dielectric layer 131 can be at least one of ABF film, polyimide, and benzocyclobutene.

[0049] The first dielectric layer 131 and the insulating layer 120 are ground to expose the end face of the conductive post 103. The grinding process is similar to that described above for grinding the first surface 101, and will not be repeated here. During the grinding process, the first dielectric layer 131 can protect the insulating layer 120, thereby preventing the insulating layer 120 from cracking due to grinding pressure and protecting the sidewalls of the conductive post 103.

[0050] Please combine Figure 6 A bump 134 electrically connected to the conductive pillar 103 is formed. Optionally, a second dielectric layer 132 is formed on the first dielectric layer 131 using spin coating or spray coating processes; a first window 133 exposing the end face of the conductive pillar 103 is formed on the second dielectric layer 132 using an exposure and development process; the bump 134 is formed by filling the first window 133 with a first metal layer. The formation of the first metal layer includes, but is not limited to, sputtering, chemical plating, or electroplating. The bump 134 includes a connected UBM seed layer and solder balls. A UBM seed layer can be formed first in the first window 133, and the material includes, but is not limited to, any one or more of copper, titanium, nickel, vanadium, chromium, gold, and silver. Then, solder balls are formed in the UBM seed layer by a ball-planting process, such as electroplating, printed ball-planting, or formic acid reflow, to complete the process. The material of the solder balls can be tin-silver, tin-silver-copper, or tin-bismuth, etc.

[0051] In some other embodiments, a first conductive layer 136 may be formed as needed before forming the bump 134. The first conductive layer 136 may be a pad or a wiring layer. If it is a wiring layer, the number of wiring layers is not limited; it may be one or more layers. The process is roughly as follows: Please combine Figure 7A second window 135 is formed on the second dielectric layer 132, exposing the end face of the conductive post 103. A second metal layer is filled in the second window 135 to form a first conductive layer 136. The second window 135 is opened according to the pattern design of the first conductive layer 136. A third dielectric layer 137 is formed on the second dielectric layer 132. A third window 138 is formed on the third dielectric layer 137, exposing the first conductive layer 136. A third metal layer is filled in the third window 138 to form a bump 134. It can be understood that the materials of the second dielectric layer 132 and the third dielectric layer 137 are the same as the material of the first dielectric layer 131. The opening method of the second window 135 and the third window 138 is similar to the opening method of the first window 133. The formation method of the second metal layer and the third metal layer is similar to the formation method of the first metal layer.

[0052] After the fabrication process of the first surface 101 of the substrate 100 is completed, the first carrier 105 and the first debonding adhesive 106 are removed.

[0053] Please combine Figure 8 , Figure 9 Take the second carrier 142, apply the second debonding adhesive 141 to the second carrier 142, and attach the side of the substrate 100 with the bumps 134 to the second carrier 142. At this time, the second surface 102 of the substrate 100 is located on the side away from the second carrier 142.

[0054] A connection terminal electrically connected to the conductive pillar 103 is formed on the second surface 102 of the substrate 100. Optionally, the connection terminal includes a second wiring layer 145 and a bump 148. Since the second surface 102 is flush with the end face of the conductive pillar 103 near the second surface 102, the fourth dielectric layer 143 can be directly spin-coated or spray-coated onto the second surface 102. A fourth window 144 is formed on the fourth dielectric layer 143 using an exposure and development process, and metal is electroplated within the fourth window 144 to form the second wiring layer 145. A fifth dielectric layer 146 is then coated, and a fifth window 147 is formed on the fifth dielectric layer 146 using an exposure and development process. Metal is electroplated within the fifth window 147 to form the bump 148. The fabrication process of the second wiring layer 145 is similar to that of the first wiring layer and is not specifically limited here. The formation process of the bump 148 is similar to that of the bump 134 described above and will not be repeated here. It is understood that in some embodiments, the number of layers of the second wiring layer 145 is not limited, or in some embodiments, the second wiring layer 145 may be omitted. The bump 148 may be a pad or a solder ball.

[0055] It should be noted that during the entire packaging process, the protective layer 110 can resolve the thermal and mechanical stresses in the process, playing a buffering role and thus protecting the insulating layer 120.

[0056] Please combine Figure 10Optionally, chip 150 is mounted at the connection end and / or bump 134. Chip 150 can be mounted on either side of the substrate 100, or on both sides. In this embodiment, chip 150 is mounted on one side of bump 148, that is, on the side closer to the second surface 102 of the substrate 100. Chip 150 can be mounted upright or flip-chip; in this embodiment, flip-chip mounting is used.

[0057] After mounting the chip 150, the chip 150 is encapsulated to form a protective encapsulation body 160. The encapsulation body 160 is then ground until its surface is flush with the surface of the chip 150 to improve heat dissipation. During this grinding process, the second carrier 142 on the back side and the protective layer 110 on one side of the first surface 101 act as a buffer. It should be noted that after the first annular cut, the edges of the subsequently formed protective layer 110, first dielectric layer 131, second dielectric layer 132, etc., extend beyond the edge of the substrate 100, forming a first step at the edge. This first step improves the bonding performance between the encapsulation body 160 and the substrate 100 during encapsulation.

[0058] Please combine Figure 11 The skeleton region is separated to form a single product; the protective layer 110 can be removed during the cutting process. Optionally, a second circumferential cut is performed on the edge of the molding compound 160. In this cutting process, the molding compound 160, protective layer 110, first dielectric layer 131, and second dielectric layer 132 outside the edge of the substrate 100 are cut away, while the second carrier 142 and the second debonding adhesive 141 are retained. After cutting, the edge portion 1421 of the second carrier 142 exposes the second debonding adhesive 141, which helps to increase the separation angle and facilitates the separation of the second carrier 142. It should be understood that when separating the second carrier 142, the second debonding adhesive 141 is also removed from the surface of the third dielectric layer 137. After removing the second carrier 142, the skeleton region is cut along the cutting path to separate and form a single product. It should be noted that when cutting the skeleton area, the width W2 of the cut should be equal to the width W1 of the protective layer 110 in the skeleton area, so that all the protective layer 110 can be cut and removed. It is easy to understand that after being cut and separated into individual products, the position of the individual product corresponds to the module mounting area 112 of the substrate 100, which includes the insulating layer 120, but does not have the protective layer 110.

[0059] Please combine Figure 12Optionally, in some embodiments, when mounting the second carrier 142, the cross-section of the second carrier 142 is selected to be larger than the cross-section of the first dielectric layer 131, so that the edges of the second carrier 142 and the first dielectric layer 131 form a second step. Thus, during the subsequent formation of the encapsulation 160, the action of the first and second steps can increase the bonding force between the encapsulation 160 and the substrate 100, and between the encapsulation 160 and the first dielectric layer 131, preventing structural delamination. Furthermore, the encapsulation 160 also serves as a sidewall protector, protecting the edges of the substrate 100, as well as the edges of the first dielectric layer 131, the second dielectric layer 132, and the third dielectric layer 137. In this embodiment, when the second annular cut is performed on the edge of the encapsulation 160, the portion outside the edge of the substrate 100 is also cut off and removed, namely the encapsulation 160 on the first and second steps, and the first dielectric layer 131 outside the edge of the substrate 100. It is easy to understand that during the cutting process, the encapsulated body 160 is connected to the protective layer 110, the medium layer, etc. The encapsulated body 160 can improve edge support, which is conducive to improving cutting efficiency and cutting quality, and reducing the risk of edge cracking and curling during the cutting process.

[0060] It should be noted that, during the packaging process on the second surface 102 side, the following steps can also be selectively performed: grinding or etching the second surface 102 of the substrate 100 to make the conductive pillar 103 protrude from the second surface 102; forming a protective layer 110 on the second surface 102; creating grooves in the protective layer 110; filling the grooves with an insulating layer 120; and covering the end face of the conductive pillar 103 with the insulating layer 120; followed by spin-coating the fourth dielectric layer 143. The second surface 102 of the substrate 100 also has a module mounting area 112 and a framework area. An insulating layer 120 is formed in the module mounting area 112, and a protective layer 110 or an interlaced mesh structure of the protective layer 110 and the insulating layer 120 is formed in the framework area. The above steps are similar to the fabrication process of the first surface 101 and will not be repeated here.

[0061] Please combine Figure 13This invention provides a packaging structure fabricated using a 2.5D exposed copper interposer fabrication process as described in any of the foregoing embodiments. The packaging structure includes a substrate 100, conductive pillars 103, an insulating layer 120, a first dielectric layer 131, a second dielectric layer 132, and bumps 134. The substrate 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the conductive pillars 103 are embedded within the substrate 100. One end of the conductive pillar 103 protrudes from the first surface 101, and the other end is flush with the second surface 102. In some embodiments, the end face of the conductive pillar 103 near the second surface 102 may also protrude from the second surface 102; this is not specifically limited here. The insulating layer 120 is disposed on the first surface 101 and covers the sidewalls of the conductive pillars 103, protecting the sidewalls and preventing breakage or microcracks in the conductive pillars during polishing. The insulating layer 120 forms grooves 121 between the sidewalls of the conductive pillars 103. The first dielectric layer 131 fills the groove 121, providing better buffering and improving bonding performance while preventing structural delamination. The second dielectric layer 132 is located on the side of the first dielectric layer 131 away from the substrate 100; bumps 134 are electrically connected to conductive pillars 103 and protrude from or are flush with the second dielectric layer 132. The insulating layer 120 improves electrical insulation performance, preventing free electrostatic ions from damaging the chip and wiring layers during the manufacturing process.

[0062] Optionally, a first conductive layer 136 is connected to one end of the conductive post 103 near the first surface 101. The first conductive layer 136 includes pads or wiring layers, and the first conductive layer 136 and the conductive post 103 are electrically connected.

[0063] Please combine Figure 14 The first conductive layer 136 connects to multiple conductive pillars 103. It can be understood that multiple first windows 133 are formed on the second dielectric layer 132, with at least one first window 133 simultaneously exposing the end faces of two or more conductive pillars 103. A first conductive layer 136 is formed within each first window 133. In this way, each first conductive layer 136 has a larger cross-section, allowing multiple conductive pillars 103 to be connected simultaneously, increasing the conductive contact area, and improving the structural connection reliability and conductivity.

[0064] Optionally, a third window 138 is formed on the third dielectric layer 137, and a third conductive layer 139 is disposed within the third window 138. The third conductive layer 139 is connected to the first conductive layer 136, and the bump 134 is connected to the third conductive layer 139. The bump 134 is designed as a solder ball structure. The third conductive layer 139 has one or more recesses, and multiple recesses can accommodate more solder ball material, increasing the contact area and improving the bonding force and reliability. By using a first conductive layer 136 with a larger cross-section and a solder ball structure with a larger cross-section, the connection is more reliable, the connection efficiency is higher, and the conductivity reliability is better.

[0065] Optionally, the second surface 102 is provided with a second wiring layer 145 and a connection terminal; the second wiring layer 145 is electrically connected to the conductive post 103, and the connection terminal is electrically connected to the second wiring layer 145. It should be noted that in some embodiments, the first wiring layer and the second wiring layer 145 may be omitted, or the number of layers of the first wiring layer and the second wiring layer 145 may be designed as one or more layers depending on the actual situation. The connection terminal may be a bump 148 or a pad.

[0066] Chip 150 is mounted on one side of bump 134, and / or chip 150 is mounted on one side of connector; molding compound 160 covers chip 150. Chip 150 can be mounted on one side of the first surface 101 or the second surface 102 of substrate 100, or chip 150 can be mounted on both sides respectively, without specific limitation.

[0067] Optional, combined Figure 15 The packaging structure also includes a substrate 210 and a metal ring 220. A bump 134 on the side of the substrate 100 away from the molding compound 160 is soldered to the substrate 210 and fixed and protected by an adhesive base. A metal ring 220 is disposed around the periphery of the substrate 100. The metal ring 220 and the substrate 210 are electrically connected, forming a shield and improving heat dissipation and preventing warping. Alternatively, the metal ring 220 can be bonded to the substrate 210 without electrical connection, serving the purpose of heat dissipation and preventing warping. Of course, components 230 can also be disposed on the substrate 210. In this embodiment, the components 230 are located between the metal ring 220 and the substrate 100, which is beneficial for improving the performance of the packaging structure.

[0068] In summary, the 2.5D exposed copper interposer fabrication process and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including: In the packaging process, a protective layer 110 and an insulating layer 120 are set, and the protective layer 110 and the insulating layer 120 are set alternately. This helps to reduce stress on the insulating layer 120 during the cutting process, prevents problems such as delamination and microcracks in the insulating layer 120, and improves product quality and performance. The insulating layer 120 is formed in the module mounting area 112 to improve insulation performance and prevent free electrostatic ions from breaking down the chip and wiring layer structure during the process.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A process for fabricating a 2.5D exposed copper interposer, characterized in that, include: A substrate with conductive pillars is provided; wherein the substrate includes a first surface and a second surface disposed opposite to each other, and one end of the conductive pillar protrudes from the first surface of the substrate; the substrate has a module mounting area and a skeleton area; A protective layer is formed on the first surface, the protective layer covering the first surface and the conductive pillar; wherein the thickness of the protective layer is greater than the height by which the conductive pillar protrudes from the substrate, and the side of the protective layer away from the substrate is planar; A first opening is formed on the protective layer located in the module mounting area. The depth of the first opening is equal to the thickness of the protective layer, that is, all the protective layer in the module mounting area is removed, and only the protective layer on the skeleton area is retained. An insulating layer is formed within the first opening, and the insulating layer is located in the module mounting area; wherein, the thickness of the insulating layer is less than the depth of the first opening, and the insulating layer covers the sidewalls and end faces of the conductive pillars, and the insulating layer forms grooves between adjacent conductive pillars; the insulating layer filling the first opening is in direct contact with the first surface of the substrate, that is, the protective layer in the skeleton area and the insulating layer in the mounting area are both in contact with the first surface; A second opening is formed on the protective layer located in the skeleton region; the insulating layer is formed within the second opening; the insulating layer and the protective layer in the skeleton region are distributed in an alternating grid pattern; A first dielectric layer is formed to cover the insulating layer and the protective layer; the first dielectric layer fills the groove and is flush with the surface of the protective layer; Grind the first dielectric layer and the insulating layer to expose the end face of the conductive pillar; A protrusion is formed that is electrically connected to the conductive post.

2. The 2.5D exposed copper interposer fabrication process according to claim 1, characterized in that, The step of forming an insulating layer in the first opening includes forming the insulating layer in both the first opening and the second opening.

3. The 2.5D exposed copper interposer fabrication process according to claim 1, characterized in that, In the step of forming a second opening on the protective layer located in the skeleton region: the depth of the second opening is equal to the thickness of the protective layer.

4. The 2.5D exposed copper interposer fabrication process according to claim 2, characterized in that, After the step of forming the insulating layer in the first opening and the second opening respectively, the method further includes: A third opening is made in the insulating layer within the second opening; In the step of forming a first dielectric layer covering the insulating layer and the protective layer, the first dielectric layer fills the third opening.

5. The 2.5D exposed copper interposer fabrication process according to claim 1, characterized in that, The substrate has multiple spaced-apart module mounting areas, each of which is rectangular; The cross-sectional shape and size of each of the first openings are the same as the shape and size of the module mounting area; the second openings are distributed along the extension direction of the rectangular diagonal of the first opening.

6. The 2.5D exposed copper interposer fabrication process according to claim 1, characterized in that, The thickness of the insulating layer is less than the depth of the first opening and the depth of the second opening, respectively; the remaining space in the first opening and the second opening is filled by the first dielectric layer.

7. The 2.5D exposed copper interposer fabrication process according to claim 1, characterized in that, After the step of forming the bumps electrically connected to the conductive post, the method further includes: A connection terminal electrically connected to the conductive pillar is formed on the second surface of the substrate; Chips are mounted at the connection end and / or the bumps; The skeleton region is cut to separate it into individual products; wherein, the protective layer is removed.

8. The 2.5D exposed copper interposer fabrication process according to claim 7, characterized in that, Prior to the step of forming a protective layer on the first surface, the method further includes: The edge of the second surface is cut in a ring shape to form a first annular groove; A first carrier is mounted on the second surface; a first debonding adhesive on the first carrier fills the first annular groove; Before forming the connection end electrically connected to the conductive pillar on the second surface of the substrate, the first carrier and the first debonding adhesive are removed; a second carrier is mounted on the side having the bump; the cross-section of the second carrier is larger than the cross-section of the first dielectric layer.

9. The 2.5D exposed copper interposer fabrication process according to claim 8, characterized in that, Following the steps of mounting the chip at the connection end and / or the bump, the process includes: molding the chip to form a molded body; The step of cutting the skeleton region to separate and form a single product includes: making a circumferential cut on the edge of the encapsulation body; Remove the second vehicle; The skeleton region is cut to separate and form individual products.

10. The process for fabricating a 2.5D exposed copper interposer according to any one of claims 1 to 9, characterized in that, The step of forming a bump electrically connected to the conductive post includes: A second dielectric layer is formed on the first dielectric layer; A first window is formed on the second dielectric layer to expose the end face of the conductive pillar; The bump is formed by filling the first window with a first metal layer. or, A second window is formed on the second dielectric layer to expose the end face of the conductive pillar; A second metal layer is filled into the second window to form a first wiring layer; A third dielectric layer is formed on the second dielectric layer; A third window is formed on the third dielectric layer to expose the first wiring layer; The bump is formed by filling the third window with a third metal layer.

11. A packaging structure, characterized in that, It is prepared using the 2.5D exposed copper interposer fabrication process as described in any one of claims 1 to 10.

12. The packaging structure according to claim 11, characterized in that, include: Substrate, the substrate including a first surface and a second surface disposed opposite to each other; Conductive pillars, wherein the conductive pillars are embedded in the substrate; One end of the conductive post protrudes from the first surface; An insulating layer is disposed on the first surface and covers the sidewall of the conductive post; The insulating layer forms a groove between the sidewalls of the conductive pillar; A first dielectric layer, the first dielectric layer filling the groove; A second dielectric layer is disposed on the side of the first dielectric layer away from the substrate; The bump is electrically connected to the conductive post and protrudes from or is flush with the second dielectric layer.

13. The packaging structure according to claim 12, characterized in that, The conductive post is connected to a first conductive layer at one end near the first surface. The first conductive layer includes pads or wiring layers, and the first conductive layer and the conductive post are electrically connected.

14. The packaging structure according to claim 13, characterized in that, The first conductive layer connects to a plurality of the conductive pillars.

15. The packaging structure according to claim 13, characterized in that, The second surface is provided with a second wiring layer and a connection terminal; the second wiring layer is electrically connected to the conductive pillar, and the connection terminal is electrically connected to the second wiring layer; The chip is mounted on one side of the bump, and / or the chip is mounted on one side of the connector; the chip is encapsulated in a molding compound.

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