Semiconductor device

Abstract

A semiconductor device includes a semiconductor element including a surface electrode formed on an element surface. The element surface includes an active region in which a power transistor is formed, and a control circuit region in which a control circuit for controlling the power transistor is formed. The active region is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction. The surface electrode is disposed on the active region at a position different from that of the control circuit region, and is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device in which a switching circuit, an overcurrent protection circuit, an overheat protection circuit, and a low-voltage malfunction prevention circuit are formed in the active region on the surface layer of a common substrate.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-147433 Summary of the Invention

[0006] There is still room for improvement regarding the active clamping tolerance of semiconductor devices.

[0007] A semiconductor device according to one aspect of this disclosure includes: a semiconductor element including an element surface, an element back surface facing a side opposite to the element surface, and a surface electrode formed on the element surface; a chip pad supporting the semiconductor element; a plurality of leads disposed around the chip pad; and a plurality of wires connecting the surface electrode and the plurality of leads. The element surface includes an active region on which a power transistor is formed and a control circuit region on which control circuitry for controlling the power transistor is formed. Two directions orthogonal to the thickness direction of the semiconductor element are respectively designated as a first direction and a second direction. The active region is formed to surround the control circuit region from both sides of the second direction and one side of the first direction. The surface electrode is disposed at a different position from the control circuit region and disposed on the active region, and is formed to surround the control circuit region from both sides of the second direction and one side of the first direction when viewed from the thickness direction. Attached Figure Description

[0008] Figure 1 This is a simplified perspective view of the semiconductor device according to the first embodiment.

[0009] Figure 2 It means Figure 1 A simplified top view of the internal structure of a semiconductor device.

[0010] Figure 3 yes Figure 1 A simplified rear view of a semiconductor device.

[0011] Figure 4 It is Figure 2 A simplified cross-sectional view of a semiconductor device obtained by cutting the semiconductor device with the F4-F4 line.

[0012] Figure 5 yes Figure 1 A simplified circuit diagram of a semiconductor device.

[0013] Figure 6 It is Figure 2 A simplified top view of the surface electrodes and passivation film in the semiconductor element of a semiconductor device after removal.

[0014] Figure 7 yes Figure 2 A simplified top view of a semiconductor device.

[0015] Figure 8 This refers to the state where the electrode connection part is connected with a wire. Figure 2 A simplified top view of a semiconductor device.

[0016] Figure 9 It is in the state where a wire is connected. Figure 2 A simplified top view of a semiconductor device.

[0017] Figure 10 It is Figure 9 A simplified cross-sectional view obtained by cutting a semiconductor device along the F10-F10 line.

[0018] Figure 11 This is a simplified top view showing the internal structure of the semiconductor device according to the second embodiment.

[0019] Figure 12 It is Figure 11 A simplified top view of the surface electrodes and passivation film in the semiconductor element of a semiconductor device after removal.

[0020] Figure 13 Is towards Figure 12 A simplified top view of the semiconductor device with added surface electrodes and passivation film.

[0021] Figure 14 This refers to the state of the electrode connection portion connected to a wire. Figure 13 A simplified top view of a semiconductor device.

[0022] Figure 15 It is in a state where a wire is connected. Figure 13 A simplified top view of a semiconductor device.

[0023] Figure 16 This is a simplified top view of the state of the electrode connection portion of the semiconductor element connected to the wire in the modified semiconductor device. Detailed Implementation

[0024] Hereinafter, several embodiments of the semiconductor device in this disclosure will be described with reference to the accompanying drawings. Furthermore, to simplify and clarify the description, the constituent elements shown in the drawings are not necessarily drawn to a fixed scale. Additionally, for ease of understanding, shading lines are sometimes omitted in sectional views. The accompanying drawings are merely illustrative of embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. The terms "first," "second," and "third," etc., used in this disclosure are used only to distinguish objects and not to order them.

[0025] The following detailed description includes apparatus, systems, and methods for embodying exemplary embodiments of the present disclosure. These detailed descriptions are merely illustrative and are not intended to limit the embodiments of the present disclosure or their application and use.

[0026] The term "at least one" as used in this specification means "more than one" of the desired options. For example, when there are two options, "at least one" means "only one option" or "both options". As another example, when there are three or more options, "at least one" means "only one option" or "a combination of any two or more options".

[0027] The phrases “the length (size) of A is equal to the length (size) of B” or “the length (size) of A is equal to the length (size) of B” used in this specification also include relationships such as the difference between the lengths of A and B being within 10% of the length of A.

[0028] (First Implementation)

[0029] (Overall structure of a semiconductor device)

[0030] Reference Figures 1-4 The overall structure of the semiconductor device 10 according to the first embodiment will be described. Figure 1 A simplified three-dimensional structure of the semiconductor device 10 according to the first embodiment is shown. Figure 2 Show Figure 1 A simplified top view of the internal structure of the semiconductor device 10. Figure 3 Show Figure 1 A simplified rear view of the semiconductor device 10. Figure 4 Showing Figure 2 A simplified cross-sectional view of the semiconductor device 10 obtained by cutting the semiconductor device 10 using the F4-F4 line. Additionally, in Figure 2 In order to show the internal structure of the semiconductor device 10, the sealing resin 60, which will be described later, is represented by a double-dotted line, and the constituent elements within the sealing resin 60 are represented by solid lines. Furthermore, the term "top view" as used in this disclosure refers to viewing along... Figure 1 The semiconductor device 10 is observed along the Z direction of the mutually orthogonal XYZ axes. Furthermore, in this disclosure, the X direction is an example of a "second direction," and the Y direction is an example of a "first direction."

[0031] like Figure 1 As shown, the semiconductor device 10 includes a semiconductor element 20, a lead frame 30, and a sealing resin 60. The package form of the semiconductor device 10 is SO (Small Outline), and in the first embodiment, it is SOP (Small Outline Package). Furthermore, the package form of the semiconductor device 10 can be arbitrarily changed. The package form is not limited to SOP, and can also be QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package), or various similar package structures.

[0032] Semiconductor element 20 is a core component that enables the function of semiconductor device 10. Semiconductor element 20 includes, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). In the first embodiment, semiconductor element 20 is a SiC (silicon carbide) MOSFET, which is a power MOSFET. Alternatively, semiconductor element 20 may also be a Si (silicon) MOSFET. Semiconductor element 20 is formed as a rectangular plate with the Z-direction as its thickness direction. Therefore, the Z-direction can be considered the thickness direction of semiconductor element 20. In one example, semiconductor element 20 is formed as a rectangle with the X-direction as its length direction and the Y-direction as its width direction when viewed from above.

[0033] The semiconductor device 20 includes a device surface 20S and a device back surface 20R facing opposite sides in the Z direction, and four first to fourth device sides 20A to 20D connecting the device surface 20S and the device back surface 20R as device sides. The first device side 20A and the second device side 20B constitute two end faces in the X direction of the semiconductor device 20, and the third device side 20C and the fourth device side 20D constitute two end faces in the Y direction of the semiconductor device 20.

[0034] The semiconductor element 20 includes a plurality of (20 in the first embodiment) power pads 21 and a plurality of (four in the first embodiment) control pads 22 formed on the element surface 20S. The plurality of power pads 21 and the plurality of control pads 22 are disposed on the outer periphery of the element surface 20S. Details regarding the plurality of power pads 21 and the plurality of control pads 22 will be described later.

[0035] like Figure 4 As shown, the semiconductor device 20 includes a source electrode 23 formed on the device surface 20S and a drain electrode 24 formed on the device back surface 20R. The structure of the source electrode 23 will be described later. The drain electrode 24 is formed over the entire back surface 20R of the device. Here, the source electrode 23 is an example of a "surface electrode".

[0036] like Figure 2 As shown, the lead frame 30 includes a chip pad 31 supporting the semiconductor element 20 and a plurality of leads 32A-32D, 33A-33D disposed around the chip pad 31. In the following description, leads 32A-32D are referred to as "first to fourth power leads 32A-32D", and leads 33A-33D are referred to as "first to fourth control leads 33A-33D". The first to fourth power leads 32A-32D and the first to fourth control leads 33A-33D constitute the external terminals of the semiconductor device 10. Here, in this disclosure, the first to fourth power leads 32A-32D are an example of "a plurality of leads". In addition, the first power lead 32A is an example of a "first lead", the second power lead 32B is an example of a "second lead", the third power lead 32C is an example of a "third lead", and the fourth power lead 32D is an example of a "fourth lead".

[0037] The chip pad 31 is formed as a rectangular plate with the Z direction as its thickness direction. The chip pad 31 is also formed as a rectangle with the X direction as its length direction and the Y direction as its width direction when viewed from above. The chip pad 31 includes a chip pad surface 31S and a chip pad back surface 31R facing opposite sides in the Z direction, and four first to fourth chip pad sides 31A to 31D connecting the chip pad surface 31S and the chip pad back surface 31R. The first chip pad side surface 31A and the second chip pad side surface 31B constitute the two end faces of the chip pad 31 in the X direction, and the third chip pad side surface 31C and the fourth chip pad side surface 31D constitute the two end faces of the chip pad 31 in the Y direction.

[0038] like Figure 4As shown, the semiconductor element 20 is disposed on the chip pad 31 such that the drain electrode 24 faces the chip pad surface 31S. Furthermore, the semiconductor element 20 is bonded to the chip pad surface 31S via a conductive bonding material SD. Thus, the drain electrode 24 is electrically connected to the chip pad 31. The conductive bonding material SD can be, for example, solder paste or Ag (silver) paste.

[0039] The first to fourth power leads 32A to 32D are positioned, when viewed from above, closer to the side of the third chip pad 31C than the center of the chip pad 31 in the Y direction. The first power lead 32A and the second power lead 32B are positioned opposite the side of the third chip pad 31C in the Y direction. The first power leads 32A and the second power leads 32B are arranged along the X direction. The third power lead 32C is positioned closer to the side of the first chip pad 31A than the first power leads 32A and the second power leads 32B. The third power lead 32C is positioned opposite the corner portion of the chip pad 31 formed by the side of the first chip pad 31A and the side of the third chip pad 31C. The fourth power lead 32D is positioned closer to the side of the second chip pad 31B than the first power leads 32A and the second power leads 32B. The fourth power lead 32D is positioned opposite the corner portion of the chip pad 31 formed by the second chip pad side 31B and the third chip pad side 31C.

[0040] The first to fourth power leads 32A to 32D each include a conductor pad 32P and a lead portion 32Q. In one example, the conductor pad 32P and the lead portion 32Q are integrated. In one example, the first power lead 32A and the second power lead 32B have the same shape. In one example, the third power lead 32C and the fourth power lead 32D have symmetrical shapes. The conductor pad 32P of each of the first power leads 32A and the second power leads 32B is formed into a rectangular shape with the X direction being the length direction and the Y direction being the width direction. The conductor pad 32P of the third power lead 32C is formed into an L-shape that surrounds the side surface 31A of the first chip pad and the side surface 31C of the third chip pad when viewed from above. The conductor pad 32P of the fourth power lead 32D is formed into an L-shape that surrounds the side surface 31B of the second chip pad and the side surface 31C of the third chip pad when viewed from above.

[0041] The lead portion 32Q of each of the first to fourth power leads 32A to 32D extends along the Y direction when viewed from above. A portion of the lead portion 32Q forms an external terminal by protruding outwards from the sealing resin 60.

[0042] The first to fourth control leads 33A to 33D are positioned, when viewed from above, closer to the side 31D of the fourth chip pad in the Y direction than the center of the chip pad 31. The first control lead 33A and the second control lead 33B are positioned opposite the side 31D of the fourth chip pad in the Y direction. The first control lead 33A and the second control lead 33B are arranged along the X direction. In one example, the first control lead 33A and the second control lead 33B are formed with the same shape as the first power lead 32A and the second power lead 32B. The third control lead 33C is positioned closer to the side 31A of the first chip pad than the first control lead 33A and the second control lead 33B. The third control lead 33C is positioned opposite the corner portion of the chip pad 31 formed by the side 31A of the first chip pad and the side 31D of the fourth chip pad. In one example, the third control lead 33C is formed with the same shape as the fourth power lead 32D. The fourth control lead 33D is positioned closer to the side 31B of the second chip pad than the first control lead 33A and the second control lead 33B. The fourth control lead 33D is positioned opposite the corner portion of the chip pad 31 formed by the side 31B of the second chip pad and the side 31D of the fourth chip pad. In one example, the fourth control lead 33D is formed with the same shape as the third power lead 32C. The first to fourth control leads 33A to 33D, like the first to fourth power leads 32A to 32D, include a wire pad 33P and a lead portion 33Q. A portion of the lead portion 33Q of the first to fourth control leads 33A to 33D forms an external terminal by protruding outwards from the sealing resin 60.

[0043] Multiple power pads 21 of the semiconductor element 20 are electrically connected to the first to fourth power leads 32A to 32D via multiple first to fourth conductors 71 to 74. Multiple control pads 22 are electrically connected to the first to fourth control leads 33A to 33D via fifth to eighth conductors 75 to 78.

[0044] like Figure 2 As shown, the sealing resin 60 seals the semiconductor element 20 and the first to eighth conductors 71 to 78, and partially seals the lead frame 30. The sealing resin 60 is formed of an insulating material. For example, black epoxy resin is used as the insulating material.

[0045] The sealing resin 60 is formed as a rectangular plate with the Z-direction as its thickness direction. The sealing resin 60 includes a sealing surface 61 and a sealing back surface 62 facing opposite sides in the Z-direction, and four first to fourth sealing sides 63 to 66 connecting the sealing surface 61 and the sealing back surface 62 as sealing sides. The first sealing side 63 and the second sealing side 64 constitute two end faces in the X-direction of the sealing resin 60, and the third sealing side 65 and the fourth sealing side 66 constitute two end faces in the Y-direction of the sealing resin 60. Figure 3 As shown, the sealing surface 61 faces the same side as the chip pad surface 31S, and the sealing back surface 62 faces the same side as the chip pad back surface 31R. Therefore, the sealing surface 61 faces the same side as the component surface 20S of the semiconductor component 20, and the sealing back surface 62 faces the same side as the component back surface 20R. Figure 3 and Figure 4 As shown, the back surface 31R of the chip pads is exposed from the sealed back surface 62. Therefore, the back surface 31R of the chip pads constitutes the drain terminal as an external terminal of the semiconductor device 10. Figure 2 As shown, the first sealing side 63 faces the same side as the first chip pad side 31A, the second sealing side 64 faces the same side as the second chip pad side 31B, the third sealing side 65 faces the same side as the third chip pad side 31C, and the fourth sealing side 66 faces the same side as the fourth chip pad side 31D.

[0046] The lead portion 32Q of each of the first to fourth power leads 32A to 32D protrudes from the third sealing side 65 toward the outside of the sealing resin 60. The lead portion 33Q of each of the first to fourth control leads 33A to 33D protrudes from the fourth sealing side 66 toward the outside of the sealing resin 60.

[0047] (Circuit structure of a semiconductor device)

[0048] Reference Figure 5 An example of the circuit structure of the semiconductor device 10 will be described.

[0049] like Figure 5As shown, the semiconductor device 10 includes: a switching circuit 100 containing a power transistor (a power MOSFET in the first embodiment); and a control circuit 110 for controlling the switching circuit 100. Both the switching circuit 100 and the control circuit 110 are disposed on the semiconductor element 20. In one example, the control circuit 110 includes a current sensor circuit 111, a temperature sensor circuit 112, an overcurrent protection (OCD: Over Charge Current Detection) circuit 113, an overheat protection (TSD: Thermal Shut Down) circuit 114, and an undervoltage lockout (UVLO: Under Voltage LockOut) circuit 115.

[0050] The semiconductor device 10 includes an input terminal 116 and an input-side ground terminal 117, as well as an output terminal 118 and an output-side ground terminal 119. The input terminal 116 is, for example, connected by first to fourth control leads 33A to 33D (see reference). Figure 2 The input-side ground terminal 117 is formed by, for example, another control lead among the first to fourth control leads 33A to 33D. The output terminal 118 is formed by the chip pad 31 (see reference). Figure 3 The output side grounding terminal 119 is composed of the first to fourth power leads 32A to 32D.

[0051] exist Figure 5 In the example shown, a series circuit 200, including a power supply 201 and an inductive load 202, is electrically connected to the output terminal 118 and the output-side ground terminal 119. Additionally, Figure 5 In the example shown, the inductive load 202 is a repeater that includes a switch Sw and a coil L.

[0052] Switching circuit 100 is electrically connected between output terminal 118 and output-side ground terminal 119. Switching circuit 100 includes a power MOSFET. The power MOSFET includes a gate terminal G, a drain terminal D, and a source terminal S. In switching circuit 100, drain terminal D is electrically connected to output terminal 118, and source terminal S is electrically connected to output-side ground terminal 119.

[0053] The semiconductor device 10 includes: an input wiring 121 connecting an input terminal 116 to a gate terminal G in a switching circuit 100; and a ground wiring 122 connecting an input-side ground terminal 117 to an output-side ground terminal 119. A diode D1, a first resistor R1, an overcurrent protection circuit 113, an overheat protection circuit 114, an undervoltage malfunction prevention circuit 115, and a second resistor R2 are connected in parallel between the input wiring 121 and the ground wiring 122, starting from the input terminal 116 side. A third resistor R3 is connected in series between the first resistor R1 and the overcurrent protection circuit 113 in the input wiring 121. A fourth resistor R4 is connected in series between the undervoltage malfunction prevention circuit 115 and the second resistor R2 in the input wiring 121.

[0054] The current sensor circuit 111 is electrically connected to the overcurrent protection circuit 113. The current sensor circuit 111 is configured, for example, to detect the current flowing in the input wiring 121. The current value detected by the current sensor circuit 111 is output to the overcurrent protection circuit 113. The overcurrent protection circuit 113 is driven based on the current value from the current sensor circuit 111. In one example, the overcurrent protection circuit 113 is configured to protect other circuits from the effects of overcurrent when a current exceeding a specified value (overcurrent) flows through the input wiring 121 due to a short circuit or static electricity, by causing the overcurrent to flow from the input wiring 121 side to the ground wiring 122 side.

[0055] Temperature sensor circuit 112 is electrically connected to overheat protection circuit 114. Temperature sensor circuit 112 is configured to detect the temperature of semiconductor element 20. The temperature detected by temperature sensor circuit 112 is output to overheat protection circuit 114. Overheat protection circuit 114 is activated based on the temperature detected by temperature sensor circuit 112. In one example, overheat protection circuit 114 is configured to disable power supply to input wiring 121 when the temperature of semiconductor element 20 exceeds a predetermined temperature. This suppresses the temperature rise of semiconductor element 20.

[0056] The low voltage malfunction prevention circuit 115 is configured to prevent the switching circuit 100 from operating when the potential difference between the input wiring 121 and the ground wiring 122 is less than a specified value, and to allow the switching circuit 100 to operate when the potential difference is greater than or equal to the specified value.

[0057] A clamping diode D2 is electrically connected between the gate terminal G and the drain terminal D in the switching circuit 100. The clamping diode D2 is constructed by connecting two diodes in reverse bias. These two diodes may, for example, include Zener diodes. The clamping diode D2 has a breakdown voltage V2 that is lower than the breakdown voltage V1 between the drain terminal D and the source terminal S in the power MOSFET. Therefore, the clamping diode D2 is configured to break down before the switching circuit 100 when a breakdown voltage V1 is applied between the drain terminal D and the source terminal S.

[0058] When the inductive load 202 is turned off, a reverse voltage V3 is generated in the coil L that is higher than the breakdown voltage V1 between the drain terminal D and the source terminal S, the clamping diode D2 breaks down. When the clamping diode D2 breaks down, current flows through the second resistor R2, thus generating a voltage (gate voltage) between the gate terminal G and the source terminal S. This gate voltage turns on the switching circuit 100 (power MOSFET), and therefore, the current generated by the reverse voltage V3 flows between the drain terminal D and the source terminal S.

[0059] In this way, the load on the switching circuit 100 is reduced by the clamping diode D2, and the energy stored in the inductive load 202 is absorbed by the switching circuit 100. The extent to which the energy stored in the inductive load 202 is absorbed is indicated by the dynamic clamping tolerance Eac, which is one of the characteristics of the power MOSFET. The larger the value of the dynamic clamping tolerance Eac, the more energy stored in the inductive load 202 is absorbed. In addition, the structure of the control circuit 110 can be arbitrarily changed.

[0060] (Structure of a semiconductor device)

[0061] Reference Figure 6 and Figure 7 A brief description of the internal structure of semiconductor element 20 is provided.

[0062] Figure 6 A simplified top view of the internal structure of semiconductor element 20 is shown. Figure 7 show to Figure 6 The semiconductor element 20 has a simplified top view structure with the source electrode 23 and passivation film 25 described later.

[0063] The surface 20S of the semiconductor element 20 includes an active region 40 on which a power transistor (a power MOSFET in the first embodiment) is formed, and a control circuit region 50 on which a control circuit 110 is formed. The active region 40 can also be described as having... Figure 5 The area of ​​the switching circuit 100.

[0064] The control circuit region 50 is positioned centrally in the X direction and offset towards the fourth element side 20D in the Y direction. The control circuit region 50 is formed into a generally rectangular shape, with the X direction as its length and the Y direction as its width when viewed from above. The control circuit region 50 includes a first side 51 offset towards the first element side 20A, a second side 52 offset towards the second element side 20B, and a third side 53 offset towards the third element side 20C when viewed from above. Both the first side 51 and the second side 52 include portions extending along the Y direction. The third side 53 includes a portion extending along the X direction. The third side 53 is positioned on the element surface 20S of the semiconductor element 20, offset towards the third element side 20C from the center in the Y direction. The dimension of the control circuit region 50 in the X direction is larger than half the dimension of the element surface 20S in the X direction. In one example, the dimension of the control circuit region 50 in the X direction is larger than two-thirds of the dimension of the element surface 20S in the X direction. In one example, the dimension of the control circuit region 50 in the X direction is approximately 3 / 4 of the dimension of the component surface 20S in the X direction.

[0065] Here, the dimension of the control circuit region 50 in the X direction is defined by the distance in the X direction between the first side 51 and the second side 52. The dimension of the component surface 20S in the X direction is defined by the distance in the X direction between the first component side surface 20A and the second component side surface 20B.

[0066] like Figure 6 As shown, the semiconductor element 20 may also include a plurality of internal pads 54. The plurality of internal pads 54 may also include a pair of first internal pads 54A and a pair of second internal pads 54B disposed at different locations. The pair of first internal pads 54A is disposed at the corner between the first side 51 and the third side 53 of the control circuit region 50. The control circuit region 50 is recessed in a top view to avoid the pair of first internal pads 54A. The pair of first internal pads 54A are arranged along the Y direction. The pair of second internal pads 54B is disposed at the corner between the second side 52 and the third side 53 of the control circuit region 50. The control circuit region 50 is recessed in a top view to avoid the pair of second internal pads 54B. The pair of second internal pads 54B are arranged along the Y direction. In one example, the length of the second side 52 in the Y direction is shorter than the length of the first side 51 in the Y direction. Furthermore, the lengths of the first side 51 and the second side 52 in the Y direction can be arbitrarily changed.

[0067] The plurality of internal pads 54 may also include internal pads connected to the gate terminal G of the switching circuit 100. Additionally, the plurality of internal pads 54 may also include internal pads connected to the control circuit 110. The plurality of internal pads 54 may also be formed to a different size than at least one of the power pads 21 and the control pads 22 when viewed from above. In one example, the plurality of internal pads 54 may also be formed to be smaller than the power pads 21 and the control pads 22 when viewed from above.

[0068] A plurality of control pads 22 (four in the first embodiment) are provided between the control circuit region 50 and the side surface 20D of the fourth component in the Y direction. The plurality of control pads 22 are located at the same position in the Y direction and are arranged separately from each other in the X direction. Hereinafter, for convenience, the four control pads 22 will be referred to as "control pads 22A to 22D".

[0069] Control pads 22A and 22B are positioned between control pads 22C and 22D in the X direction. Control pad 22A is positioned closer to the side 20A of the first component than control pad 22B. Control pad 22C is positioned closer to the side 20A of the first component than control pads 22A and 22B. Control pad 22D is positioned closer to the side 20B of the second component than control pads 22A and 22B.

[0070] Control pad 22A is connected to the first control lead 33A via the fifth conductor 75 (both refer to...). Figure 2 Electrical connection. The control pad 22B is connected to the second control lead 33B via the sixth conductor 76 (see references). Figure 2 Electrical connection. Control pad 22C is connected to the third control lead 33C via the seventh conductor 77 (see references). Figure 2 Electrical connection. Control pad 22D is connected to the fourth control lead 33D via the eighth conductor 78 (see reference 78). Figure 2 Electrical connection. The fifth to eighth conductors 75 to 78 are formed, for example, of metallic materials such as copper (Cu), aluminum (Al), gold (Au), and Ag. In the first embodiment, the fifth to eighth conductors 75 to 78 are formed of a material containing Cu.

[0071] The active region 40 is formed to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction when viewed from above. The active region 40 is positioned adjacent to the control circuit region 50 when viewed from above. The active region 40 can be distinguished, for example, as a first transistor region 41 disposed further away from the control circuit region 50 on the side 20C of the third element, a second transistor region 42 adjacent to the first side 51 of the control circuit region 50 in the X direction, and a third transistor region 43 adjacent to the second side 52 in the X direction. The dashed lines within the active region 40 represent the boundary lines between the first transistor region 41 and the second transistor region 42, and between the first transistor region 41 and the third transistor region 43.

[0072] The active region 40 surrounds the control circuit region 50 from both sides in the X direction through the second transistor region 42 and the third transistor region 43. The active region 40 surrounds the control circuit region 50 from one side (the third element side 20C side) in the Y direction through the first transistor region 41.

[0073] The second transistor region 42 is formed into a rectangular shape with the Y direction as its length direction and the X direction as its width direction. The top edge of the second transistor region 42 is positioned adjacent to the side surface 20D of the fourth element in the Y direction when viewed from above. Therefore, the second transistor region 42 is formed to be integrally adjacent to the first side 51 of the control circuit region 50 in the X direction along the Y direction. In one example, the width dimension WA2 (dimension in the X direction) of the second transistor region 42 is approximately 1 / 8 of the dimension of the element surface 20S in the X direction. The length dimension LA2 (dimension in the Y direction) of the second transistor region 42 is larger than the width dimension WA1 (dimension in the Y direction) of the first transistor region 41.

[0074] The third transistor region 43 is formed into a rectangular shape with the Y direction as its length direction and the X direction as its width direction. In one example, the width dimension WA3 (the dimension in the X direction) of the third transistor region 43 is approximately 1 / 8 of the dimension in the X direction of the component surface 20S. That is, the width dimension WA3 of the third transistor region 43 can also be equal to the width dimension WA2 of the second transistor region 42. The length dimension LA3 (the dimension in the Y direction) of the third transistor region 43 is larger than the width dimension WA1 of the first transistor region 41. In one example, the length dimension LA3 of the third transistor region 43 is smaller than the length dimension LA2 of the second transistor region 42. Therefore, the top edge of the third transistor region 43 is positioned closer to the first transistor region 41 in the Y direction than the top edge of the second transistor region 42. The third transistor region 43 is formed to be integrally adjacent to the second side 52 of the control circuit region 50 in the X direction in the Y direction. Alternatively, the length dimension LA3 of the third transistor region 43 can also be equal to the length dimension LA2 of the second transistor region 42.

[0075] The first transistor region 41 includes a region adjacent to the third side 53 of the control circuit region 50 in the Y direction. The first transistor region 41 is formed into a rectangular shape where the X direction is the length direction and the Y direction is the width direction when viewed from above. The length dimension LA1 (dimension in the X direction) of the first transistor region 41 may also be longer than the dimension in the X direction of the control circuit region 50. In one example, the width dimension WA1 of the first transistor region 41 is less than twice the width dimension WA2 of the second transistor region 42. In one example, the width dimension WA1 of the first transistor region 41 is less than twice the width dimension WA3 of the third transistor region 43. In one example, the width dimension WA1 of the first transistor region 41 is approximately 1.5 times the width dimension WA2 (WA3) of the second transistor region 42 (third transistor region 43).

[0076] In one example, a slit 44 is formed in the first transistor region 41 to avoid the temperature sensor circuit 112. The slit 44 is positioned in the first transistor region 41 at a location offset from the center of the third transistor region 43 in the X direction.

[0077] like Figure 7 As shown, in the active region 40 (refer to...) Figure 6 An active electrode 23 is formed on the active region 40. Although not shown, the source electrode 23 is formed on an insulating layer covering the power MOSFET formed in the active region 40. The source electrode 23 and the power MOSFET in the active region 40 are electrically connected by multiple connection wires that penetrate the insulating layer along the Z direction. Thus, the source electrode 23 is located at a different position than the control circuit region 50 and is disposed on the active region 40.

[0078] exist Figure 7 In the example shown, the source electrode 23 is formed to have the same shape as the active region 40 when viewed from above. That is, as... Figure 6 and Figure 7 As shown, the source electrode 23 includes a first electrode region 23A corresponding to the first transistor region 41, a second electrode region 23B corresponding to the second transistor region 42, and a third electrode region 23C corresponding to the third transistor region 43. Therefore, the source electrode 23 is formed to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction when viewed from above. The first electrode region 23A is positioned adjacent to the control circuit region 50 in the Y direction when viewed from above. The second electrode region 23B is positioned between the control circuit region 50 and the first element side surface 20A, and the third electrode region 23C is positioned between the control circuit region 50 and the second element side surface 20B. The second electrode region 23B and the third electrode region 23C are positioned separately on both sides of the control circuit region 50 in the X direction when viewed from above.

[0079] The first electrode region 23A is an electrode region covering the first transistor region 41. Therefore, the first electrode region 23A includes a region adjacent to the third side 53 of the control circuit region 50 in the Y direction. The first electrode region 23A is formed into a rectangular shape where the X direction is the length direction and the Y direction is the width direction when viewed from above. The length dimension LB1 (dimension in the X direction) of the first electrode region 23A is longer than the dimension in the X direction of the control circuit region 50. In one example, the width dimension WB1 (dimension in the Y direction) of the first electrode region 23A is less than twice the width dimension WB2 (dimension in the Y direction) of the second electrode region 23B. In one example, the width dimension WB1 of the first electrode region 23A is less than twice the width dimension WB3 (dimension in the Y direction) of the third electrode region 23C. In one example, the width dimension WB1 of the first electrode region 23A is approximately 1.5 times the width dimension WB2 (WB3) of the second electrode region 23B (third electrode region 23C).

[0080] In one example, a slit 23AA is formed in the first electrode region 23A to avoid the temperature sensor circuit 112. The slit 23AA is positioned in the first electrode region 23A at a location offset from the center of the third electrode region 23C in the X direction. The slit 23AA is positioned to overlap with the slit 44 of the first transistor region 41 when viewed from above. Therefore, it can be said that the temperature sensor circuit 112 is exposed from the source electrode 23 when viewed from above.

[0081] The second electrode region 23B is an electrode region covering the second transistor region 42. Therefore, the second electrode region 23B is positioned adjacent to the first side 51 of the control circuit region 50 in the X direction when viewed from above. The second electrode region 23B is formed into a rectangular shape with the Y direction as its length direction and the X direction as its width direction. The top edge of the second electrode region 23B is positioned adjacent to the fourth element side surface 20D in the Y direction when viewed from above. Therefore, the second electrode region 23B is formed to be integrally adjacent to the first side 51 of the control circuit region 50 in the X direction along the Y direction. In one example, the width dimension WB2 (dimension in the X direction) of the second electrode region 23B is approximately 1 / 8 of the dimension of the element surface 20S in the X direction. The length dimension LB2 (dimension in the Y direction) of the second electrode region 23B is larger than the width dimension WB1 of the first electrode region 23A.

[0082] The third electrode region 23C is an electrode region covering the third transistor region 43. Therefore, the third electrode region 23C is positioned adjacent to the second side 52 of the control circuit region 50 in the X direction when viewed from above. The third electrode region 23C is formed into a rectangular shape with the Y direction as its length direction and the X direction as its width direction. In one example, the width dimension WB3 of the third electrode region 23C is approximately 1 / 8 of the dimension in the X direction of the component surface 20S. That is, the width dimension WB3 of the third electrode region 23C can also be equal to the width dimension WB2 of the second electrode region 23B. The length dimension LB3 (dimension in the Y direction) of the third electrode region 23C is larger than the width dimension WB1 of the first electrode region 23A. In one example, the length dimension LB3 of the third electrode region 23C is smaller than the length dimension LB2 of the second electrode region 23B. Therefore, the top edge of the third electrode region 23C is positioned in the Y direction closer to the first electrode region 23A than the top edge of the second electrode region 23B. The third electrode region 23C is formed to be integrally distributed throughout the second side 52 of the control circuit region 50 in the Y direction and adjacent to the second side 52 in the X direction. Furthermore, the length dimension LB3 of the third electrode region 23C can also be equal to the length dimension LB2 of the second electrode region 23B.

[0083] The source electrode 23 and the control circuit region 50 are covered, for example, by a passivation film 25. The passivation film 25 is a protective film that protects the semiconductor element 20, and is formed, for example, by silicon nitride (SiN) or silicon oxide (SiO2).

[0084] The passivation film 25 includes multiple first to fifth openings 25A to 25E on the source electrode 23. The portions of the source electrode 23 exposed through the multiple first to fifth openings 25A to 25E constitute power pads 21. The power pads 21 exposed through the multiple first to fourth openings 25A to 25D are source pads for connecting the first to fourth conductors 71 to 74.

[0085] Multiple first openings 25A and multiple second openings 25B are disposed in the portion of the passivation film 25 covering the first electrode region 23A.

[0086] Multiple (five in the first embodiment) first openings 25A are positioned, when viewed from above, closer to the second electrode region 23B in the X direction than the center of the first electrode region 23A. The multiple first openings 25A are arranged separately from each other in the X direction. Adjacent first openings 25A in the X direction are staggered from each other along the Y direction.

[0087] A plurality of (five in the first embodiment) second openings 25B are positioned, when viewed from above, closer to the third electrode region 23C than the center of the first electrode region 23A in the X direction. The plurality of second openings 25B are arranged separately from each other in the X direction. Adjacent second openings 25B in the X direction are staggered from each other along the Y direction. In one example, the arrangement of the plurality of second openings 25B is linearly symmetrical to the arrangement of the plurality of first openings 25A with respect to an imaginary line along the Y direction at the center of the first electrode region 23A in the X direction.

[0088] Multiple third openings 25C are arranged across both the portion of the passivation film 25 covering the first electrode region 23A and the portion covering the second electrode region 23B. The multiple third openings 25C are located at the same position in the X direction and are arranged separately from each other in the Y direction. The multiple third openings 25C are positioned closer to the side 20A of the first element than the multiple first openings 25A.

[0089] Multiple fourth openings 25D are arranged across both the portion of the passivation film 25 covering the first electrode region 23A and the portion covering the third electrode region 23C. The multiple fourth openings 25D are located at the same position in the X direction and are arranged separately from each other in the Y direction. The multiple fourth openings 25D are positioned relative to the side surface 20B of the second element compared to the multiple second openings 25B.

[0090] A plurality of fifth openings 25E are provided in the passivation film 25 covering the first electrode region 23A. The plurality of fifth openings 25E are arranged adjacent to the plurality of first openings 25A in the Y direction. In addition, the plurality of fifth openings 25E are arranged adjacent to the plurality of second openings 25B in the Y direction.

[0091] (Connection structure of semiconductor components and wires)

[0092] Reference Figures 8-10 The connection structure between semiconductor element 20 and first to fourth conductive wires 71 to 74 will be described.

[0093] Figure 8 show to Figure 7 The semiconductor element 20 has a simplified top view structure with the addition of first to fourth electrode connection portions 71A to 74A of first to fourth conductors 71 to 74 and heat dissipation areas 90A to 90D (double-dotted quadrilaterals) for heat dissipation by the first to fourth conductors 71 to 74. Figure 9 show to Figure 8 The semiconductor element 20 has a simplified top view structure with the addition of first to fourth conductors 71 to 74. Figure 10 A simplified cross-sectional view of the plurality of first conductive lines 71 and the first heat sink 81, described later, is shown. Additionally, in Figure 9 In order to make the accompanying drawings easier to understand, the heat dissipation areas 90A to 90D have been omitted.

[0094] like Figure 8 and Figure 9 As shown, multiple first wires 71 are connected to power pads 21 (source pads) exposed from multiple first openings 25A. Each first wire 71 includes a first electrode connection portion 71A. Here, the first wire 71 is a bonding wire formed by a wire bonding device. The first electrode connection portion 71A of the first wire 71 constitutes the initial bonding portion. Therefore, it can be said that the first electrode connection portion 71A constitutes a spherical bonding.

[0095] A plurality of first electrode connections 71A are arranged separately from each other in the X direction. Adjacent first electrode connections 71A in the X direction are staggered from each other in the Y direction. That is, the plurality of first electrode connections 71A includes a first electrode connection 71A that is offset from the center of the first electrode region 23A in the Y direction towards the control circuit region 50, and a first electrode connection 71A that is offset from the center of the first electrode region 23A in the Y direction towards the side 20C of the third element. The first electrode connection 71A that is most offset from the side 20B of the second element among the plurality of first electrode connections 71A is disposed at the center of the first electrode region 23A in the Y direction.

[0096] Multiple second conductors 72 are connected to the power pads 21 (source pads) exposed from multiple second openings 25B. Each second conductor 72 includes a second electrode connection portion 72A. The second electrode connection portion 72A is ball-bonded to the first electrode connection portion 71A of the first conductor 71.

[0097] A plurality of second electrode connections 72A are arranged separately from each other in the X direction. Adjacent second electrode connections 72A in the X direction are staggered in the Y direction. That is, the plurality of second electrode connections 72A includes a second electrode connection 72A that is offset from the center of the first electrode region 23A in the Y direction towards the control circuit region 50, and a second electrode connection 72A that is offset from the center of the first electrode region 23A in the Y direction towards the side of the third element 20C. The second electrode connection 72A that is most offset from the side of the first element 20A is located at the center of the first electrode region 23A in the Y direction.

[0098] Multiple third conductors 73 are connected to the power pads 21 (source pads) exposed from multiple third openings 25C. Each third conductor 73 includes a third electrode connection portion 73A. The third electrode connection portion 73A is ball-bonded to the first electrode connection portion 71A of the first conductor 71.

[0099] Multiple third electrode connectors 73A are located at the same position in the X direction and are arranged separately in the Y direction. Three of the third electrode connectors 73A are disposed in the second electrode region 23B, and the remaining two third electrode connectors 73A are disposed in the first electrode region 23A. These two third electrode connectors 73A are disposed at the end of the first electrode region 23A in the X direction, near the end closest to the first element side surface 20A.

[0100] Multiple fourth conductors 74 are connected to the power pads 21 (source pads) exposed from multiple fourth openings 25D. Each fourth conductor 74 includes a fourth electrode connection portion 74A. The fourth electrode connection portion 74A is also spherically bonded to the first electrode connection portion 71A of the first conductor 71.

[0101] A plurality of fourth electrode connections 74A are located at the same position in the X direction and are arranged separately in the Y direction. Three of the fourth electrode connections 74A are disposed in the third electrode region 23C, and the remaining two fourth electrode connections 74A are disposed in the first electrode region 23A. These two fourth electrode connections 74A are disposed at the ends of the first electrode region 23A in the X direction, near the end closest to the second element side 20B.

[0102] The first to fourth conductors 71 to 74 are formed, for example, of metallic materials such as Cu, Al, Au, and Ag. In the first embodiment, the first to fourth conductors 71 to 74 are formed of a material containing Cu. The first to fourth conductors 71 to 74 may also be formed of the same material as the fifth to eighth conductors 75 to 78.

[0103] like Figure 8 As shown, the areas where the source electrode 23 dissipates heat through the first to fourth conductors 71 to 74 are represented by heat dissipation areas 90A to 90D, indicated by double-dotted lines. The heat dissipation areas 90A to 90D implemented based on the first to fourth conductors 71 to 74 are shown as, for example, rectangular regions centered on each of the first to fourth electrode connection portions 71A to 74A. In one example, the heat dissipation areas 90A to 90D have the same dimensions.

[0104] Multiple heat dissipation regions 90A corresponding to the first conductor 71 are provided in such a way that they surround each of the multiple first electrode connection portions 71A when viewed from above. Adjacent heat dissipation regions 90A in the X direction partially overlap, for example.

[0105] Multiple heat dissipation regions 90B corresponding to the second conductor 72 are provided in such a way that they surround each of the multiple second electrode connection portions 72A when viewed from above. Adjacent heat dissipation regions 90B in the X direction partially overlap, for example.

[0106] Multiple heat dissipation regions 90C corresponding to the third conductor 73 are provided in such a way that they surround each of the multiple third electrode connection portions 73A when viewed from above. Therefore, the multiple heat dissipation regions 90C are arranged along the Y direction. Two of the multiple heat dissipation regions 90C corresponding to the first electrode region 23A partially overlap with the heat dissipation region 90A that is closest to the side 20A of the first element.

[0107] Multiple heat dissipation regions 90D corresponding to the fourth conductor 74 are provided in such a way that they surround each of the multiple fourth electrode connection portions 74A when viewed from above. Therefore, the multiple heat dissipation regions 90D are arranged along the Y direction. Two of the multiple heat dissipation regions 90D corresponding to the first electrode region 23A partially overlap with the heat dissipation region 90B that is closest to the side 20B of the second element among the multiple heat dissipation regions 90B.

[0108] The dimensions of the multiple heat dissipation regions 90C in the X direction are slightly smaller than the dimensions of the second electrode region 23B in the X direction. Three heat dissipation regions 90C are formed covering a large portion of the second electrode region 23B. Therefore, the second electrode region 23B can be easily cooled by the three heat dissipation regions 90C. Similarly, the dimensions of the multiple heat dissipation regions 90D in the X direction are slightly smaller than the dimensions of the third electrode region 23C in the X direction. Three heat dissipation regions 90D are formed covering a large portion of the third electrode region 23C. Therefore, the third electrode region 23C can be easily cooled by the three heat dissipation regions 90D.

[0109] On the other hand, the width dimension WB1 (dimension in the Y direction) of the first electrode region 23A is, for example, larger than the dimension in the Y direction of the heat dissipation region 90A. Especially Figure 7 In the example shown, the width WB1 of the first electrode region 23A is more than twice the size of the heat dissipation region 90A in the Y direction. Furthermore, four of the multiple heat dissipation regions 90A are positioned offset in the Y direction from the center of the first electrode region 23A. Therefore, there are areas in the first electrode region 23A where no heat dissipation region 90A is provided (hereinafter referred to as "non-heat dissipation region 91A"). The non-heat dissipation region 91A is an area where the temperature of the source electrode 23 is more likely to rise compared to the heat dissipation region 90A. Multiple non-heat dissipation regions 91A are provided (four in the first embodiment). Here, a fifth opening 25E is formed in each of the multiple non-heat dissipation regions 91A. That is, the multiple non-heat dissipation regions 91A include power pads 21 (source pads) formed by the source electrode 23 exposing itself from the passivation film 25.

[0110] A first heat sink 81 is disposed in each non-heat dissipation area 91A. The first heat sink 81 is formed, for example, of the same material as the first to fourth conductors 71 to 74. In the first embodiment, the first heat sink 81 is formed of a material containing Cu. Figure 10 As shown, the first heat sink 81 has the same shape as the first electrode connection portion 71A. That is, the first heat sink 81 is formed by ball bonding based on a wire bonding device.

[0111] like Figure 9 As shown, the first heat sink 81 is positioned in a direction extending along the first conductor 71 relative to the first electrode connection portion 71A when viewed from above. Therefore, the first heat sink 81, positioned adjacent to the first electrode connection portion 71A near the third element side 20C, is positioned to overlap with the first conductor 71 when viewed from above. Furthermore, the first heat sink 81, positioned adjacent to the first electrode connection portion 71A near the fourth element side 20D, is positioned where it is impossible to form an interface with the first power lead 32A (see reference 32A) in the positions where these heat sinks 81 are positioned. Figure 2The first wire 71 is connected at the location of the non-heat dissipation area 91A. In this way, the location of the first wire 71 cannot be formed in the non-heat dissipation area 91A, and the first heat sink 81 is formed in place of the first wire 71.

[0112] Furthermore, four of the multiple heat dissipation regions 90B are positioned offset in the Y direction from the center of the first electrode region 23A. Therefore, there are areas in the first electrode region 23A where no heat dissipation region 90B is provided (hereinafter referred to as "non-heat dissipation region 91B"). The non-heat dissipation region 91B is an area where the temperature of the source electrode 23 is more likely to rise compared to the heat dissipation region 90B. Multiple non-heat dissipation regions 91B are provided (four in the first embodiment). Here, a fifth opening 25E is formed in each of the multiple non-heat dissipation regions 91B. That is, each of the multiple non-heat dissipation regions 91B includes a power pad 21 (source pad) formed by the source electrode 23 exposing itself from the passivation film 25.

[0113] A second heat sink 82 is disposed in each non-heat dissipation area 91B. The second heat sink 82 is formed, for example, of the same material as the first to fourth wires 71 to 74. In the first embodiment, the second heat sink 82 is formed of a material containing Cu. That is, the second heat sink 82 is formed of the same material as the first heat sink 81. The second heat sink 82 is formed, like the first heat sink 81, by ball bonding based on a wire bonding device. Therefore, the second heat sink 82 has the same shape as the first heat sink 81. That is, the second heat sink 82 has the same shape as the second electrode connection portion 72A.

[0114] like Figure 9 As shown, the second heat sink 82 is positioned in a direction extending along the second conductor 72 relative to the second electrode connection portion 72A when viewed from above. Therefore, the second heat sink 82, positioned adjacent to the second electrode connection portion 72A near the third element side 20C, is positioned to overlap with the second conductor 72 when viewed from above. Furthermore, the second heat sink 82, positioned adjacent to the second electrode connection portion 72A near the fourth element side 20D, is positioned such that a connection with the second power lead 32B (see reference 32A) cannot be formed in the positions where these second heat sinks 82 are positioned. Figure 2 The second conductor 72 is connected at the location of the second conductor 72. In this way, the non-heat dissipation area 91B cannot form the location of the second conductor 72, and the second heat sink 82 is formed instead of the second conductor 72.

[0115] (effect)

[0116] The operation of the semiconductor device 10 in the first embodiment will be explained.

[0117] When the semiconductor device 10 performs a switching operation, heat is generated between the drain electrode 24 and the source electrode 23 due to the inductance of the inductive load. At this time, heat is dissipated from the first electrode region 23A of the source electrode 23 to the control circuit region 50, from the second electrode region 23B to the control circuit region 50, and from the third electrode region 23C to the control circuit region 50. That is, the heat from the source electrode 23 moves from the source electrode 23 to the control circuit region 50 via three heat dissipation paths. This suppresses localized temperature increases within the semiconductor element 20, thus preventing avalanche breakdown. As a result, the avalanche tolerance (active clamping tolerance) of the semiconductor device 10 can be improved.

[0118] (Effect)

[0119] The semiconductor device 10 according to the first embodiment can achieve the following effects.

[0120] (1-1) The semiconductor device 10 includes: a semiconductor element 20, including an element surface 20S, an element back surface 20R facing the side opposite to the element surface 20S, and a source electrode 23 formed on the element surface 20S; a chip pad 31 supporting the semiconductor element 20; first to fourth power leads 32A to 32D disposed around the chip pad 31; and first to fourth conductors 71 to 74 connecting the source electrode 23 to the plurality of first to fourth power leads 32A to 32D. The element surface 20S includes an active region 40 on which a power transistor is formed and a control circuit region 50 on which a control circuit 110 for controlling the power transistor is formed. The active region 40 is configured to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction. The source electrode 23 is disposed at a different position from the control circuit region 50 and is disposed on the active region 40, and is configured to surround the control circuit region 50 from both sides in the X direction and one side in the Y direction when viewed from above.

[0121] According to this structure, compared to a structure where the source electrode and the control circuit region 50 are adjacent only on one side, for example, in the Y direction, there are more heat dissipation paths from the source electrode 23 to the control circuit region 50, thus facilitating heat dissipation from the source electrode 23 to the control circuit region 50. Therefore, avalanche breakdown can be avoided, thereby improving the avalanche tolerance (active clamping tolerance) of the semiconductor device 10.

[0122] (1-2) The source electrode 23 includes: a first electrode region 23A, disposed adjacent to the control circuit region 50 in the Y direction when viewed from above; and a second electrode region 23B and a third electrode region 23C, disposed separately on both sides of the control circuit region 50 in the X direction when viewed from above. The semiconductor device 10 includes a plurality of power leads as follows: a first power lead 32A and a second power lead 32B, located on the side opposite to the control circuit region 50 in the Y direction relative to the source electrode 23, and arranged separately along the X direction; a third power lead 32C, disposed in the region near the second electrode region 23B in the region on both sides of the source electrode 23 in the X direction; and a fourth power lead 32D, disposed in the region near the third electrode region 23C in the region on both sides of the source electrode 23 in the X direction. The plurality of wires include: a plurality of first wires 71 connecting the first electrode region 23A and the first power lead 32A; a plurality of second wires 72 connecting the first electrode region 23A and the second power lead 32B; a plurality of third wires 73 connecting the second electrode region 23B and the third power lead 32C; and a plurality of fourth wires 74 connecting the third electrode region 23C and the fourth power lead 32D.

[0123] According to this structure, multiple wires are connected to each of the first to third electrode regions 23A to 23C of the source electrode 23. Therefore, heat from the source electrode 23 moves to the first to fourth power leads 32A to 32D via these wires. As a result, the source electrode 23 can easily dissipate heat, thereby improving the avalanche tolerance (active clamping tolerance) of the semiconductor device 10.

[0124] (1-3) The width WB1 of the first electrode region 23A is larger than the width WB2 of the second electrode region 23B and the width WB3 of the third electrode region 23C. Multiple first conductors 71 are arranged separately in the X direction, staggered in the Y direction. Multiple second conductors 72 are arranged separately in the X direction, staggered in the Y direction.

[0125] According to this structure, compared to a structure in which multiple first wires 71 and multiple second wires 72 are arranged in a row along the X direction in the first electrode region 23A, the number of first wires 71 and second wires 72 disposed in the first electrode region 23A can be increased. Therefore, heat dissipation of the source electrode 23 can be easily achieved through the first wires 71 and second wires 72.

[0126] (1-4) The semiconductor device 10 also includes a plurality of heat sinks 81, 82 which are coupled to the source electrode 23. The heat sinks 81, 82 are disposed in the first electrode region 23A.

[0127] According to this structure, the heat from the first electrode region 23A moves to the sealing resin 60 via the heat sinks 81 and 82. Therefore, the heat dissipation performance of the first electrode region 23A can be improved.

[0128] (1-5) The heat sink includes: a first heat sink 81, disposed in the X direction at a position closer to the second electrode region 23B than the center of the first electrode region 23A; and a second heat sink 82, disposed in the X direction at a position closer to the third electrode region 23C than the center of the first electrode region 23A.

[0129] According to this structure, the heat from the first electrode region 23A moves to the sealing resin 60 via the first heat sink 81 and the second heat sink 82. Therefore, the heat dissipation performance of the first electrode region 23A can be improved.

[0130] (1-6) Each of the plurality of first conductors 71 includes a first electrode connection portion 71A. The first heat sink 81 is disposed in a direction that extends along the first conductor 71 relative to the first electrode connection portion 71A when viewed from above.

[0131] According to this structure, the first heat sink 81 is disposed in the region of the first electrode region 23A where the first wire 71 cannot be disposed. Therefore, the heat dissipation performance of the first electrode region 23A can be further improved by means of the first heat sink 81 while maintaining the maximum number of first wires 71 that can be disposed in the first electrode region 23A.

[0132] (1-7) Each of the plurality of second conductors 72 includes a second electrode connection portion 72A. The second heat sink 82 is disposed in a direction that extends along the direction of the second conductors 72 relative to the second electrode connection portion 72A when viewed from above.

[0133] According to this structure, the second heat sink 82 is disposed in the region of the first electrode region 23A where the second wire 72 cannot be disposed. Therefore, the heat dissipation performance of the first electrode region 23A can be further improved by means of the second heat sink 82 while maintaining the maximum number of second wires 72 that can be disposed in the first electrode region 23A.

[0134] (1-8) The second electrode region 23B surrounds the entire control circuit region 50 in the Y direction when viewed from the X direction.

[0135] According to this structure, heat can easily move from the second electrode region 23B to the control circuit region 50 in the Y direction. Therefore, the heat dissipation performance of the source electrode 23 can be improved.

[0136] (1-9) The third electrode region 23C surrounds the entire control circuit region 50 in the Y direction when viewed from the X direction.

[0137] According to this structure, heat can easily move from the third electrode region 23C to the control circuit region 50 in the Y direction. Therefore, the heat dissipation performance of the source electrode 23 can be improved.

[0138] (1-10) The width dimension WB2 of the second electrode region 23B is equal to the width dimension WB3 of the third electrode region 23C.

[0139] According to this structure, the deviation in heat generation between the second electrode region 23B and the third electrode region 23C is reduced, thus the temperature difference between the second electrode region 23B and the third electrode region 23C becomes smaller. Therefore, it is possible to suppress the decrease in avalanche tolerance (active clamping tolerance) caused by excessively high temperatures in either the second electrode region 23B or the third electrode region 23C.

[0140] (1-11) Heat sinks 81 and 82 contain Cu.

[0141] According to this structure, compared with the case where the heat sinks 81 and 82 are formed of Al, for example, the heat dissipation performance of the heat sinks 81 and 82 on the source electrode 23 can be improved.

[0142] (1-12) The heat sinks 81 and 82 are formed in the same shape as the first electrode connection portion 71A of the first wire 71 and the second electrode connection portion 72A of the second wire 72.

[0143] According to this structure, heat sinks 81 and 82 can be formed by wire bonding devices that form the first wire 71 and the second wire 72. Therefore, the process for forming heat sinks 81 and 82 can be shared with the process for forming the first wire 71 and the second wire 72, thereby simplifying the manufacturing process of the semiconductor device 10.

[0144] (Second Implementation)

[0145] Reference Figures 11-15 The semiconductor device 10 according to the second embodiment will be described. The main difference between the semiconductor device 10 of the second embodiment and the semiconductor device 10 of the first embodiment is the internal structure of the semiconductor element 20. Hereinafter, the differences from the semiconductor device 10 of the first embodiment will be described in detail, and common components of the semiconductor device 10 of the first embodiment will be labeled with the same reference numerals and their descriptions will be omitted.

[0146] Figure 11 A simplified top view of the internal structure of the semiconductor device 10 is shown. Figure 12 A simplified top view of the internal structure of semiconductor element 20 is shown. Figure 13 show to Figure 12The semiconductor element 20 has a simplified top view structure with an additional source electrode 23 and a passivation film 25. Figure 14 show to Figure 13 The semiconductor element 20 has a simplified top view of the first to fourth electrode connection portions 71A to 74A and heat dissipation areas 90A to 90D with the addition of first to fourth conductors 71 to 74. Figure 15 show to Figure 14 The semiconductor element 20 has a simplified top view showing the addition of first to fourth conductive lines 71 to 74. Additionally, in Figure 15 In order to make the accompanying drawings easier to understand, the heat dissipation areas 90A to 90D have been omitted.

[0147] like Figure 12 As shown, the element surface 20S of the semiconductor element 20 includes an active region 130 on which a power transistor (power MOSFET in the second embodiment) is formed and an active region 130 on which a power transistor is formed. Figure 5 The control circuit area 140 of the control circuit 110. The active area 130 can also be said to form a... Figure 5 The area of ​​the switching circuit 100.

[0148] The control circuit region 140 is disposed on the component surface 20S at a position offset from the first component side 20A and the fourth component side 20D. The control circuit region 140, like in the first embodiment, includes first to third sides 141 to 143. The first side 141 differs from that in the first embodiment; instead, it is disposed at a position adjacent to the first component side 20A in the X direction when viewed from above.

[0149] The control circuit region 140 is formed into a roughly rectangular shape, with the X direction being the length direction and the Y direction being the width direction when viewed from above. In one example, the dimension of the control circuit region 140 in the X direction is more than 2 / 3 and less than 3 / 4 of the dimension of the component surface 20S in the X direction. In another example, the dimension of the control circuit region 140 in the Y direction is larger than 1 / 2 and less than 2 / 3 of the dimension of the component surface 20S in the Y direction. Furthermore, the dimensions of the control circuit region 140 can be arbitrarily changed.

[0150] exist Figure 12In the example shown, a plurality of (three in the second embodiment) first internal pads 54A are provided at the corner between the first side 141 and the third side 143 of the control circuit region 140. The control circuit region 140 is recessed in a top view to avoid the plurality of first internal pads 54A. The plurality of first internal pads 54A are arranged along the Y direction. A second internal pad 54B is provided at the corner between the second side 142 and the third side 143 of the control circuit region 140. The control circuit region 140 is recessed in a top view to avoid the second internal pads 54B. Furthermore, a plurality of (four in the second embodiment) control pads 22 are provided between the control circuit region 140 and the fourth component side surface 20D in the Y direction. The plurality of control pads 22 are located at the same position in the Y direction and are arranged separately in the X direction. Hereinafter, for convenience, the four control pads 22 will be referred to as "control pads 22A to 22D".

[0151] like Figure 11 As shown, control pad 22A is electrically connected to the first control lead 33A via the fifth wire 75. Control pad 22B is electrically connected to the second control lead 33B via the sixth wire 76. Control pad 22C is electrically connected to the third control lead 33C via the seventh wire 77. Control pad 22D is electrically connected to the fourth control lead 33D via the eighth wire 78.

[0152] like Figure 12 As shown, the active region 130 is formed to surround the control circuit region 140 from one side in the X direction and one side in the Y direction when viewed from above. In one example, the active region 130 is formed in an L-shape when viewed from above. The active region 130 can be distinguished, for example, as: a first transistor region 131 disposed relative to the third element side 20C of the control circuit region 140; and a second transistor region 132 adjacent to the second side 142 of the control circuit region 140 in the X direction. The dashed lines within the active region 130 represent the boundary lines between the first transistor region 131 and the second transistor region 132.

[0153] The active region 130 surrounds the control circuit region 140 from one side (the third element side 20C side) in the Y direction through the first transistor region 131. The active region 130 surrounds the control circuit region 140 from one side (the second element side 20B side) in the X direction through the second transistor region 132.

[0154] The second transistor region 132 is formed into a rectangular shape with the Y direction as its length direction and the X direction as its width direction. The top edge of the second transistor region 132 is positioned adjacent to the side surface 20D of the fourth element in the Y direction when viewed from above. Therefore, the second transistor region 132 is formed to be integrally adjacent to the second side 142 of the control circuit region 140 in the X direction along the Y direction. In one example, the width dimension WC2 (dimension in the X direction) of the second transistor region 132 is approximately 1 / 4 of the dimension of the element surface 20S in the X direction. The length dimension LC2 (dimension in the Y direction) of the second transistor region 132 is larger than the width dimension WC1 (dimension in the Y direction) of the first transistor region 131.

[0155] The first transistor region 131 includes a region adjacent to the third side 143 of the control circuit region 140 in the Y direction. The first transistor region 131 is formed into a rectangular shape where the X direction is the length direction and the Y direction is the width direction when viewed from above. The length dimension LC1 (dimension in the X direction) of the first transistor region 131 is longer than the dimension in the X direction of the control circuit region 140. For example... Figure 12 In the example shown, the width dimension WC1 of the first transistor region 131 is equal to the width dimension WC2 of the second transistor region 132.

[0156] In one example, a slit 133 is formed in the first transistor region 131 to avoid the temperature sensor circuit 112. The slit 133 is positioned in the first transistor region 131 at a location offset from the center of the second transistor region 132 in the X direction.

[0157] like Figure 13 As shown, in the active region 130 (refer to...) Figure 12 An active electrode 150 is formed on the active region 130. Although not shown, the source electrode 150 is formed on an insulating layer covering the power MOSFET formed in the active region 130. The source electrode 150 and the power MOSFET in the active region 130 are electrically connected by a plurality of connection wires that penetrate the insulating layer along the Z direction. Thus, the source electrode 150 is located at a different position than the control circuit region 140 and is located on the active region 130.

[0158] exist Figure 13 In the example shown, the source electrode 150 is formed to have the same shape as the active region 130 when viewed from above. That is, as Figure 12 and Figure 13As shown, the source electrode 150 includes a first electrode region 151 corresponding to the first transistor region 131 and a second electrode region 152 corresponding to the second transistor region 132. The first electrode region 151 can be described as covering the first transistor region 131, and the second electrode region 152 as covering the second transistor region 132. Therefore, the source electrode 150 is formed to surround the control circuit region 140 from one side in the X direction (the second element side 20B side) and one side in the Y direction (the third element side 20C side) when viewed from above. The first electrode region 151 is positioned adjacent to the control circuit region 140 in the Y direction when viewed from above. The second electrode region 152 is positioned adjacent to the control circuit region 140 in the X direction when viewed from above. The size of the first electrode region 151 is approximately the same as that of the first transistor region 131, and the size of the second electrode region 152 is approximately the same as that of the second transistor region 132. Therefore, the width dimension WD1 (dimension in the Y direction) of the first electrode region 151 is equal to the width dimension WD2 (dimension in the X direction) of the second electrode region 152. The length dimension LD1 (dimension in the X direction) of the first electrode region 151 is larger than the length dimension LD2 (dimension in the Y direction) of the second electrode region 152.

[0159] In one example, a slit 153 is formed in the first electrode region 151 to avoid the temperature sensor circuit 112. The slit 153 is positioned in the first electrode region 151, offset from the center of the second electrode region 152 in the X direction. The slit 153 is positioned to overlap with the slit 133 of the first transistor region 131 when viewed from above. Therefore, it can be said that the temperature sensor circuit 112 is exposed from the source electrode 150 when viewed from above.

[0160] The source electrode 150 and the control circuit region 140 are covered, for example, by a passivation film 160. The passivation film 160 is a protective film that protects the semiconductor element 20, and is formed, for example, by SiN or SiO2.

[0161] The passivation film 160 includes a plurality of first to fifth openings 161 to 165 on the source electrode 150. The portions of the source electrode 150 exposed through the plurality of first to fifth openings 161 to 165 constitute power pads 21 (source pads). The power pads 21 (source pads) exposed through the plurality of first to fourth openings 161 to 164 are power pads 21 (source pads) connecting the first to fourth conductors 71 to 74.

[0162] Multiple first to third openings 161 to 163 are provided in the passivation film 160 covering the portion of the first electrode region 151.

[0163] A plurality of (three in the second embodiment) third openings 163 are disposed in the X direction at a position offset from the first element side 20A compared to the plurality of (four in the second embodiment) first openings 161 and the plurality of (four in the second embodiment) second openings 162. The plurality of third openings 163 are arranged along the Y direction at their ends offset from the first element side 20A in the first electrode region 151.

[0164] Two of the plurality of first openings 161 are positioned in the Y direction closer to the side 20C of the third element than the center of the first electrode region 151. These two first openings 161 are arranged separately in the X direction. The remaining two of the plurality of first openings 161 are positioned in the Y direction closer to the control circuit region 140 than the center of the first electrode region 151. These remaining two first openings 161 are arranged adjacent to each other in the X direction.

[0165] A plurality of second openings 162 are positioned in the X direction closer to the side 20B of the second element than a plurality of first openings 161. Two of the plurality of second openings 162 are positioned in the Y direction closer to the side 20C of the third element than the center of the first electrode region 151. These two second openings 162 are arranged separately in the X direction. The remaining two of the plurality of second openings 162 are positioned in the Y direction closer to the control circuit region 140 than the center of the first electrode region 151. These remaining two second openings 162 are arranged adjacent to each other in the X direction.

[0166] A plurality of fourth openings 164 are disposed in both the portion of the passivation film 160 covering the first electrode region 151 and the portion covering the second electrode region 152. The plurality of fourth openings 164 are located at the same position in the X direction and are arranged separately in the Y direction. Two of the fourth openings 164, biased towards the third element side 20C, are disposed in the portion of the passivation film 160 covering the first electrode region 151. The remaining three fourth openings 164 are disposed in the portion of the passivation film 160 covering the second electrode region 152.

[0167] like Figure 13 and Figure 15 As shown, multiple (four in the second embodiment) first conductors 71 are connected to the power pads 21 (source pads) exposed from multiple first openings 161. The multiple first conductors 71 are connected to the first power lead 32A (see reference). Figure 11The first conductor 71 includes a first electrode connection portion 71A. Similar to the first embodiment, the first electrode connection portion 71A is configured with a spherical bond. A plurality of first electrode connection portions 71A are arranged separately in the Y direction.

[0168] Multiple (four in the second embodiment) second wires 72 are connected to the power pads 21 (source pads) exposed from the multiple second openings 162. The multiple second wires 72 are connected to the second power leads 32B (see reference 1). Figure 11 The second conductor 72, like in the first embodiment, includes a second electrode connection portion 72A formed by ball bonding.

[0169] Two of the plurality of second electrode connection portions 72A are positioned in the Y direction closer to the side 20C of the third element than the center of the first electrode region 151. The remaining two second electrode connection portions 72A are positioned in the Y direction closer to the control circuit region 140 than the center of the first electrode region 151.

[0170] Multiple (three in the second embodiment) third conductors 73 are connected to the power pads 21 (source pads) exposed from the multiple third openings 163. The multiple third conductors 73 are connected to the third power lead 32C (see reference). Figure 11 The third conductor 73, like in the first embodiment, includes a third electrode connection portion 73A formed by ball bonding.

[0171] One of the plurality of third electrode connection portions 73A is positioned in the Y direction closer to the side 20C of the third element than the center of the first electrode region 151. Another third electrode connection portion 73A is positioned in the Y direction at the center of the first electrode region 151. The remaining third electrode connection portion 73A is positioned in the Y direction closer to the control circuit region 140 than the center of the first electrode region 151.

[0172] Multiple (five in the second embodiment) fourth conductors 74 are connected to the power pads 21 (source pads) exposed from the multiple fourth openings 164. The multiple fourth conductors 74 are connected to the fourth power leads 32D (see reference 164). Figure 11 The fourth conductor 74, like in the first embodiment, includes a fourth electrode connection portion 74A formed by ball bonding.

[0173] A plurality of fourth electrode connectors 74A are located at the same position in the X direction and are arranged separately in the Y direction. Three of the fourth electrode connectors 74A are disposed in the second electrode region 152, and the remaining two fourth electrode connectors 74A are disposed in the first electrode region 151. These two fourth electrode connectors 74A are disposed at the ends of the first electrode region 151 in the X direction, near the end closest to the second element side 20B.

[0174] like Figure 14 As shown, the areas where the source electrode 23 dissipates heat through the first to fourth conductors 71 to 74 are represented by heat dissipation areas 90A to 90D, indicated by double-dotted lines. The heat dissipation areas 90A to 90D implemented based on the first to fourth conductors 71 to 74 are shown as, for example, rectangular regions centered on each of the first to fourth electrode connection portions 71A to 74A. In one example, the heat dissipation areas 90A to 90D have the same dimensions.

[0175] Multiple heat dissipation areas 90A corresponding to the first conductor 71 are provided in such a way that they each surround multiple first electrode connection portions 71A when viewed from above. Adjacent heat dissipation areas 90A in the Y direction partially overlap, for example, when viewed from the Y direction.

[0176] Multiple heat dissipation areas 90B corresponding to the second conductor 72 are provided in such a way that they surround each of the multiple second electrode connection portions 72A when viewed from above. The two heat dissipation areas 90B corresponding to the second electrode connection portions 72A that are biased towards the control circuit region 140 partially overlap when viewed from the X direction.

[0177] The heat dissipation area 90C corresponding to the third conductor 73 is provided in a manner that surrounds each of the multiple third electrode connection portions 73A when viewed from above.

[0178] Multiple heat dissipation areas 90D corresponding to the fourth conductor 74 are provided in such a way that they surround each of the multiple fourth electrode connection portions 74A when viewed from above. Therefore, the multiple heat dissipation areas 90D are arranged along the Y direction.

[0179] As described above, in the first electrode region 151, the first electrode connection portion 71A of the first conductor 71 and the second electrode connection portion 72A of the second conductor 72 are positioned offset from the center of the first electrode region 151 in the Y direction. Therefore, a non-heat-dissipating region 91A without a heat-dissipating region 90A exists in the first electrode region 151. The non-heat-dissipating region 91A is a region where the temperature of the source electrode 150 is more likely to rise compared to the heat-dissipating region 90A. Multiple non-heat-dissipating regions 91A are provided (two in the second embodiment). Here, a fifth opening 165 is formed in each of the multiple non-heat-dissipating regions 91A. That is, each of the multiple non-heat-dissipating regions 91A includes a power pad 21 (source pad) formed by the source electrode 150 exposing itself from the passivation film 160. A first heat sink 81 is provided in each non-heat-dissipating region 91A. The structure of the first heat sink 81 is the same as in the first embodiment.

[0180] like Figure 15 As shown, one of the plurality of first heat sinks 81 is positioned in a direction extending along the first conductor 71 relative to the first electrode connection portion 71A when viewed from above. More specifically, the first heat sink 81 disposed adjacent to the first electrode connection portion 71A at a position where it overlaps with the first conductor 71 when viewed from above. Furthermore, the first heat sink 81 disposed adjacent to the first electrode connection portion 71A at a position where it is impossible to form an interface with the first power lead 32A (see reference 32A) in the positions where these first heat sinks 81 are disposed. Figure 11 The first wire 71 is connected at the location of the non-heat dissipation area 91A (refer to...). Figure 14 The first heat sink 81 is formed in place of the first wire 71, which cannot be formed in the first wire 71.

[0181] like Figure 14 As shown, four of the multiple heat dissipation regions 90B are positioned offset in the Y direction from the center of the first electrode region 151. Therefore, there are non-heat dissipation regions 91B in the first electrode region 151 where no heat dissipation regions 90B are provided. Multiple non-heat dissipation regions 91B are provided (two in the second embodiment). Here, a fifth opening 165 is formed in each of the multiple non-heat dissipation regions 91B. That is, each of the multiple non-heat dissipation regions 91B includes a power pad 21 (source pad) formed by the source electrode 150 exposing itself from the passivation film 25. A second heat sink 82 is provided in each non-heat dissipation region 91B in the same manner as in the non-heat dissipation region 91A.

[0182] like Figure 15As shown, the second heat sink 82 is positioned in a direction extending along the second conductor 72 relative to the second electrode connection portion 72A when viewed from above. Therefore, the second heat sink 82, positioned adjacent to the second electrode connection portion 72A near the third element side 20C, is positioned to overlap with the second conductor 72 when viewed from above. Furthermore, the second heat sink 82, positioned adjacent to the second electrode connection portion 72A near the fourth element side 20D, is positioned such that a connection with the second power lead 32B (see reference 32A) cannot be formed in the positions where these second heat sinks 82 are positioned. Figure 11 The location of the second conductor 72 connected to the heat sink is such that the non-heat dissipation area 91B cannot be the location of the second conductor 72, and the second heat sink 82 is formed instead of the second conductor 72. Additionally, multiple first to fourth power leads 32A to 32D (see reference) Figure 11 The configuration of the first embodiment is the same.

[0183] (Effect)

[0184] The semiconductor device 10 according to the second embodiment can achieve the following effects.

[0185] (2-1) The semiconductor device 10 includes: a semiconductor element 20, including an element surface 20S, an element back surface 20R facing the side opposite to the element surface 20S, and a source electrode 150 formed on the element surface 20S; a chip pad 31 supporting the semiconductor element 20; first to fourth power leads 32A to 32D disposed around the chip pad 31; and a plurality of first to fourth conductors 71 to 74 connecting the source electrode 150 to the first to fourth power leads 32A to 32D. The element surface 20S includes an active region 130 on which a power transistor is formed and a control circuit region 140 on which a control circuit 110 for controlling the power transistor is formed. The active region 130 is configured to surround the control circuit region 140 from one side in the Y direction and one side in the X direction. The source electrode 150 is disposed at a different position from the control circuit region 140 and is disposed on the active region 130, and is formed to surround the control circuit region 140 from one side in the Y direction and one side in the X direction when viewed from above.

[0186] According to this structure, compared to a structure where the source electrode 150 and the control circuit region 140 are adjacent only on one side, for example, in the Y direction, there are more heat dissipation paths from the source electrode 150 to the control circuit region 140. Therefore, heat dissipation from the source electrode 150 to the control circuit region 140 is easier. Consequently, avalanche breakdown can be avoided, thereby improving the avalanche tolerance (active clamping tolerance) of the semiconductor device 10.

[0187] (2-2) The source electrode 150 includes: a first electrode region 151, disposed adjacent to the control circuit region 140 in the Y direction when viewed from above; and a second electrode region 152, disposed adjacent to the control circuit region 140 in the X direction when viewed from above. The semiconductor device 10 includes a plurality of power leads: a first power lead 32A and a second power lead 32B, located in the Y direction on the side opposite to the control circuit region 140 relative to the source electrode 150, and arranged separately along the X direction; and a third power lead 32C and a fourth power lead 32D, separately disposed on both sides of the source electrode 150 in the X direction. The plurality of wires include: a plurality of first wires 71 connecting the first electrode region 151 and the first power lead 32A; a plurality of second wires 72 connecting the first electrode region 151 and the second power lead 32B; a plurality of third wires 73 connecting the first electrode region 151 and the third power lead 32C; and a plurality of fourth wires 74 connecting the second electrode region 152 and the fourth power lead 32D.

[0188] According to this structure, multiple first to fourth wires 71 to 74 are connected to the first electrode region 151 and the second electrode region 152 of the source electrode 150, respectively. Therefore, heat from the source electrode 150 moves via the aforementioned first to fourth wires 71 to 74 to the first to fourth power leads 32A to 32D. Thus, the source electrode 150 is easily dissipated, thereby improving the avalanche tolerance (active clamping tolerance) of the semiconductor device 10.

[0189] (2-3) Multiple first conductors 71 are arranged separately from each other in the X direction, staggered in the Y direction. Multiple second conductors 72 are arranged separately from each other in the X direction, staggered in the Y direction.

[0190] According to this structure, compared to a structure in which multiple first wires 71 and multiple second wires 72 are arranged in a row along the X direction in the first electrode region 151, the number of first wires 71 and second wires 72 disposed in the first electrode region 151 can be increased. Therefore, the source electrode 150 can be easily cooled by the first wires 71 and second wires 72.

[0191] (2-4) Each of the plurality of first wires 71 includes a first electrode connection portion 71A connected to the source electrode 150. Each of the plurality of second wires 72 includes a second electrode connection portion 72A connected to the source electrode 150. The semiconductor device 10 further includes: a first heat sink 81 disposed in a direction extending along the first wires 71 relative to the first electrode connection portion 71A when viewed from above; and a second heat sink 82 disposed in a direction extending along the second wires 72 relative to the second electrode connection portion 72A when viewed from above.

[0192] According to this structure, the first heat sink 81 is disposed in the region of the first electrode region 151 where the first wire 71 cannot be disposed. The second heat sink 82 is disposed in the region of the first electrode region 151 where the second wire 72 cannot be disposed. Therefore, while maintaining the maximum number of first wires 71 and second wires 72 that can be disposed in the first electrode region 151, the heat dissipation performance of the first electrode region 151 can be further improved by means of the first heat sink 81 and the second heat sink 82.

[0193] (Example of amendment)

[0194] The above-described embodiments can be implemented with the following modifications. The following modifications can be combined with each other within the scope of technical inconsistency.

[0195] In each embodiment, the shape of the active regions 40 and 130 as viewed from above can be arbitrarily changed.

[0196] In one example, in the first embodiment, the width dimension WA1 of the first transistor region 41 may be less than or equal to the width dimension WA2 of the second transistor region 42. The width dimension WA1 of the first transistor region 41 may also be less than or equal to the width dimension WA3 of the third transistor region 43. The width dimension WA2 of the second transistor region 42 may also be different from the width dimension WA3 of the third transistor region 43. In one example, the width dimension WA3 of the third transistor region 43 may be larger than the width dimension WA2 of the second transistor region 42. In one example, the width dimension WA3 of the third transistor region 43 may also be smaller than the width dimension WA2 of the second transistor region 42. The first to third electrode regions 23A to 23C of the source electrode 23 may also be changed according to these changes in the active regions 40. In one example, the width dimension WB2 of the second electrode region 23B may also be different from the width dimension WB3 of the third electrode region 23C.

[0197] Furthermore, in the second embodiment, the width dimension WC1 of the first transistor region 131 may also be different from, for example, the width dimension WC2 of the second transistor region 132. In one example, the width dimension WC1 of the first transistor region 131 may also be larger than the width dimension WC2 of the second transistor region 132. In another example, the width dimension WC1 of the first transistor region 131 may also be smaller than the width dimension WC2 of the second transistor region 132. The first electrode region 151 and the second electrode region 152 of the source electrode 150 may also be changed according to these changes in the active regions 130. In one example, the width dimension WD1 of the first electrode region 151 may also be different from the width dimension WD2 of the second electrode region 152.

[0198] In each embodiment, the relationship between the dimensions of the source electrodes 23 and 150 and the dimensions of the control circuit regions 50 and 140 as viewed from above can be arbitrarily changed.

[0199] In one example, the length dimension LB2 of the second electrode region 23B of the source electrode 23 may also be shorter than the dimension in the Y direction of the control circuit region 50. In one example, the length dimension LB3 of the third electrode region 23C of the source electrode 23 may also be shorter than the dimension in the Y direction of the control circuit region 50. In one example, the length dimension LD2 of the second electrode region 152 of the source electrode 150 may also be shorter than the dimension in the Y direction of the control circuit region 140.

[0200] In each embodiment, the relationship between the size of the active regions 40 and 130 and the size of the source electrodes 23 and 150 as viewed from above can be arbitrarily changed.

[0201] In one example, source electrodes 23 and 150 may appear smaller than active regions 40 and 130 when viewed from above. In another example, source electrodes 23 and 150 may appear larger than active regions 40 and 130 when viewed from above.

[0202] In various embodiments, the arrangement positions of the first to fourth wires 71 to 74 relative to the source electrodes 23 and 150 can be arbitrarily changed. In one example, in the second embodiment, as... Figure 16 As shown, the fourth electrode connections 74A of the plurality of fourth conductors 74 that are adjacent in the Y direction can also be staggered in the X direction. In this case, a non-heat-dissipating region 91C is formed in the second electrode region 152 of the source electrode 150. A heat sink 83 is provided in the non-heat-dissipating region 91C.

[0203] In various embodiments, the first heat sink 81 and the second heat sink 82 are not limited to spherical bonding and can be arbitrarily changed. In one example, the first heat sink 81 and the second heat sink 82 may also be formed by bonding columnar members to the source electrodes 23 and 150. In this case, the columnar members may also be formed of a metallic material or a material with excellent heat dissipation properties. As a metallic material, for example, a material containing at least one of Cu, Al, Fe, Ni, and Ti can be used. As a material with excellent heat dissipation properties, for example, ceramic can be used. That is, the first heat sink 81 and the second heat sink 82 are not limited to metallic materials and may also be formed of insulating materials. In this way, the first heat sink 81 and the second heat sink 82 may have different shapes from the first to fourth electrode connection portions 71A to 74A of the first to fourth wires 71 to 74.

[0204] Furthermore, the first heat sink 81 and the second heat sink 82 can also be formed of a different material than the first to fourth conductors 71 to 74. According to this structure, materials with superior heat dissipation properties compared to the materials constituting the first to fourth conductors 71 to 74 can be used as the materials constituting the first heat sink 81 and the second heat sink 82. This allows for improved heat dissipation performance in the non-heat dissipation regions 91A and 91B.

[0205] In various embodiments, at least one of the plurality of first heat sinks 81 may be omitted.

[0206] In various embodiments, at least one of the multiple second heat sinks 82 may be omitted.

[0207] In various embodiments, the drain electrode 24 formed on the back surface 20R of the semiconductor element 20 may also be formed locally relative to the back surface 20R.

[0208] In various embodiments, the structure of the semiconductor element 20 can be arbitrarily changed. In one example, the source electrode 23 (150) and the drain electrode 24 may also be formed on the element surface 20S of the semiconductor element 20.

[0209] In various embodiments, the entire chip pad 31 of the lead frame 30 may also be covered by the sealing resin 60. That is, the chip pad 31 may not be exposed from the sealing resin 60.

[0210] In various embodiments, the sealing resin 60 may be omitted from the semiconductor device 10.

[0211] It is possible to combine one or more of the various examples described in this specification within a range that is not technically contradictory.

[0212] As used in this disclosure, the term "on" includes both "on" and "above". Thus, for example, the expression "the first element is disposed on the second element" may mean, in one embodiment, that the first element is in contact with the second element and is directly disposed on the second element, but in other embodiments, it may mean that the first element is disposed above the second element without contacting it. That is, the term "on" does not preclude the construction of other elements between the first and second elements.

[0213] The Z-direction used in this disclosure does not necessarily need to be vertical, nor does it need to be completely consistent with the vertical direction. Therefore, the various constructions of this disclosure are not limited to the case where the "up" and "down" of the Z-direction described in this specification are the "up" and "down" of the vertical direction. For example, the X-direction can be vertical, or the Y-direction can also be vertical.

[0214] (Postscript)

[0215] Hereinafter, the technical concepts that can be grasped based on this disclosure will be described. Furthermore, the reference numerals for the constituent elements in the embodiments corresponding to the constituent elements described in each appendix are shown in brackets. The reference numerals are shown as examples to aid understanding, and the constituent elements described in each appendix should not be limited to those indicated by the reference numerals.

[0216] (Note A1)

[0217] A semiconductor device (10) includes:

[0218] The semiconductor element (20) includes an element surface (20S), an element back surface (20R) facing the side opposite to the element surface (20S), and a surface electrode (23) formed on the element surface (20S).

[0219] Chip pads (31) support the semiconductor element (20);

[0220] Multiple leads (32A-32D) are arranged around the chip pad (31); and

[0221] Multiple wires (71-74) connect the surface electrode (23) to the multiple leads (32A-32D).

[0222] The component surface (20S) includes an active region (40) on which a power transistor is formed and a control circuit region (50) on which a control circuit (110) for controlling the power transistor is formed.

[0223] Two directions orthogonal to each other in a direction orthogonal to the thickness direction (Z direction) of the semiconductor element (20) are respectively designated as the first direction (Y direction) and the second direction (X direction).

[0224] The active region (40) is formed to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction).

[0225] The surface electrode (23) is disposed at a different position from the control circuit region (50) and disposed on the active region (40), and is formed to surround the control circuit region (50) from both sides of the second direction (X direction) and one side of the first direction (Y direction) when viewed from the thickness direction (Z direction).

[0226] (Note A2)

[0227] According to the semiconductor device described in Appendix A1, wherein,

[0228] The surface electrode (23) includes:

[0229] The first electrode region (23A) is positioned adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction); and

[0230] The second electrode region (23B) and the third electrode region (23C) are separately arranged on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0231] The plurality of leads (32A to 32D) include:

[0232] The first lead (32A) and the second lead (32B) are located in the region on the side opposite to the control circuit region (50) relative to the surface electrode (23) in the first direction (Y direction), and are arranged separately in the second direction (X direction);

[0233] The third lead (32C) is disposed in the region adjacent to the second electrode region (23B) in the regions on both sides of the surface electrode (23) in the second direction (X direction); and

[0234] The fourth lead (32D) is disposed in the region adjacent to the third electrode region (23C) on both sides of the surface electrode (23) in the second direction (X direction).

[0235] The plurality of conductors (71-74) include:

[0236] Multiple first wires (71) connect the first electrode region (23A) to the first lead (32A);

[0237] Multiple second wires (72) connect the first electrode region (23A) to the second lead (32B);

[0238] Multiple third wires (73) connect the second electrode region (23B) to the third lead (32C); and

[0239] Multiple fourth wires (74) connect the third electrode region (23C) to the fourth lead (32D).

[0240] (Note A3)

[0241] According to the semiconductor device described in Appendix A2, wherein,

[0242] The width dimension (WB1) of the first electrode region (23A) is larger than the width dimension (WB2) of the second electrode region (23B) and the width dimension (WB3) of the third electrode region (23C).

[0243] The plurality of first conductors (71) are arranged separately from each other in the second direction (X direction) in a state of being staggered in the first direction (Y direction).

[0244] The plurality of second conductors (72) are arranged separately from each other in the second direction (X direction) in a state of being staggered in the first direction (Y direction).

[0245] (Note A4)

[0246] According to the semiconductor device described in Appendix A3, wherein,

[0247] It also includes a plurality of heat sinks (81, 82) that are coupled to the surface electrode (23).

[0248] The heat sinks (81, 82) are disposed in the first electrode region (23A).

[0249] (Note A5)

[0250] According to the semiconductor device described in Appendix A4, wherein,

[0251] The heat sink includes:

[0252] The first heat sink (81) is positioned in the second direction (X direction) at a position offset from the center of the first electrode region (23A) towards the second electrode region (23B); and

[0253] The second heat sink (82) is positioned in the second direction (X direction) at a position offset from the center of the first electrode region (23A) towards the third electrode region (23C).

[0254] (Note A6)

[0255] According to the semiconductor device described in Appendix A5, among which,

[0256] The plurality of first conductors (71) each include a first electrode connection portion (71A).

[0257] The first heat sink (81) is positioned in a direction that extends along the first wire (71) relative to the first electrode connection portion (71A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0258] (Note A7)

[0259] According to the semiconductor device described in Appendix A5 or A6, wherein,

[0260] The plurality of second conductors (72) each include a second electrode connection portion (72A).

[0261] The second heat sink (82) is positioned in a direction that extends along the second wire (72) relative to the second electrode connection portion (72A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0262] (Note A8)

[0263] A semiconductor device (10) includes:

[0264] The semiconductor element (20) includes an element surface (20S), an element back surface (20R) facing the side opposite to the element surface (20S), and a surface electrode (23) formed on the element surface (20S).

[0265] Chip pads (31) support the semiconductor element (20);

[0266] Multiple leads (32A-32D) are arranged around the chip pad (31); and

[0267] Multiple wires (71-74) connect the surface electrode (23) to the multiple leads (32A-32D).

[0268] The component surface (20S) includes an active region (130) on which a power transistor is formed and a control circuit region (140) on which a control circuit (110) for controlling the power transistor is formed.

[0269] Two directions orthogonal to each other in a direction orthogonal to the thickness direction (Z direction) of the semiconductor element (20) are respectively designated as the first direction (Y direction) and the second direction (X direction).

[0270] The active region (130) is formed to surround the control circuit region (140) from one side in the first direction (Y direction) and one side in the second direction (X direction).

[0271] The surface electrode (150) is disposed at a different location from the control circuit region (140) and disposed on the active region (130), and is formed to surround the control circuit region (140) from one side of the first direction (Y direction) and one side of the second direction (X direction) when viewed from the thickness direction (Z direction).

[0272] (Note A9)

[0273] According to the semiconductor device described in Appendix A8, among which,

[0274] The surface electrode (150) includes:

[0275] The first electrode region (151) is positioned adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction); and

[0276] The second electrode region (152) is positioned adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0277] The plurality of leads (32A to 32D) include:

[0278] The first lead (32A) and the second lead (32B) are located in the region on the side opposite to the control circuit region (140) relative to the surface electrode (150) in the first direction (Y direction), and are arranged separately along the second direction (X direction); and

[0279] The third lead (32C) and the fourth lead (32D) are respectively disposed in the regions on both sides of the surface electrode (150) in the second direction (X direction).

[0280] The plurality of conductors (71-74) include:

[0281] Multiple first wires (71) connect the first electrode region (151) to the first lead (32A).

[0282] Multiple second wires (72) connect the first electrode region (151) to the second lead (32B).

[0283] Multiple third wires (73) connect the first electrode region (151) to the third lead (32C); and

[0284] Multiple fourth wires (74) connect the second electrode region (152) to the fourth lead (32D).

[0285] (Note A10)

[0286] According to the semiconductor device described in Appendix A9, among which,

[0287] The plurality of first conductors (71) are arranged separately from each other in the second direction (X direction) in a state of being staggered in the first direction (Y direction).

[0288] The plurality of second conductors (72) are arranged separately from each other in the second direction (X direction) in a state of being staggered in the first direction (Y direction).

[0289] (Note A11)

[0290] According to the semiconductor device described in Appendix A10, wherein,

[0291] Each of the plurality of first conductors (71) includes a first electrode connection portion (71A) connected to the surface electrode (150).

[0292] Each of the plurality of second conductors (72) includes a second electrode connection portion (72A) connected to the surface electrode (150).

[0293] The semiconductor device further includes:

[0294] The first heat sink (81) is disposed in a direction extending along the first wire (71) relative to the first electrode connection portion (71A) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and

[0295] The second heat sink (82) is positioned in the direction in which the second wire (72) extends relative to the second electrode connection portion (72A) when viewed from the thickness direction (Z direction) of the semiconductor element (20).

[0296] (Note A12)

[0297] According to the semiconductor device described in Appendix A1 or A8, wherein,

[0298] The plurality of wires (71-74) include electrode connection portions (71A-74A) connected to the surface electrode (23 / 150).

[0299] Heat sinks (81, 82) are attached to the surface electrodes (23 / 150).

[0300] The heat sinks (81, 82) are separately disposed from the electrode connection portions (71A to 74A) of the plurality of wires (71 to 74).

[0301] (Note A13)

[0302] According to the semiconductor device described in Appendix A12, wherein,

[0303] The heat sinks (81, 82) are positioned adjacent to the electrode connection portions (71A, 72A) of the plurality of wires (71-74).

[0304] (Note A14)

[0305] According to the semiconductor device described in Appendix A12, wherein,

[0306] The heat sinks (81, 82) are made of the same material as the wires (71-74).

[0307] (Note A15)

[0308] According to the semiconductor device described in Appendix A14, wherein,

[0309] The heat sinks (81, 82) contain Cu.

[0310] (Note A16)

[0311] According to the semiconductor device described in Appendix A15, wherein,

[0312] The heat sinks (81, 82) have the same shape as the electrode connection portions (71A, 72A).

[0313] (Note A17)

[0314] According to any one of the appendices A1 to A16, the semiconductor device described therein,

[0315] The semiconductor element (20) includes a source electrode (23 / 150) formed on the surface of the element (20S) as the surface electrode and a drain electrode (24) formed on the back side of the element (20R).

[0316] (Note A18)

[0317] According to the semiconductor device described in Appendix A17, wherein,

[0318] The drain electrode (24) is formed over the entire back surface (20R) of the element.

[0319] (Note A19)

[0320] According to any one of the appendices A1 to A18, the semiconductor device described therein,

[0321] It also includes a sealing resin (60) for sealing the semiconductor element (20) and the plurality of wires (71-78).

[0322] (Note A20)

[0323] According to the semiconductor device described in Appendix A19, wherein,

[0324] The sealing resin (60) has a sealing surface (61) facing the same side as the surface (20S) of the element and a sealing back surface (62) facing the opposite side to the sealing surface (61).

[0325] The chip pads (31) are exposed from the sealed back side (62).

[0326] (Note A21)

[0327] According to any one of the notes A2 to A7, the semiconductor device described therein,

[0328] The second electrode region (23B) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0329] (Note A22)

[0330] According to any one of the notes A2 to A7, the semiconductor device described therein,

[0331] The third electrode region (23C) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0332] (Note A23)

[0333] According to any one of the notes A2 to A7, the semiconductor device described therein,

[0334] The width dimension (WB2) of the second electrode region (23B) is equal to the width dimension (WB3) of the third electrode region (23C).

[0335] (Note A24)

[0336] According to any one of the appendices A9 to A11, the semiconductor device described therein,

[0337] The second electrode region (152) surrounds the entire first direction (Y direction) of the control circuit region (140) when viewed from the second direction (X direction).

[0338] (Note A25)

[0339] According to the semiconductor device described in appendices A12 or A13, wherein,

[0340] The heat sinks (81, 82) are formed of a different material than the wires (71-78).

[0341] (Note B1)

[0342] A semiconductor element (20) includes:

[0343] The component surface (20S) includes an active region (40) on which a power transistor is formed and a control circuit region (50) on which a control circuit (110) for controlling the power transistor is formed; and

[0344] The surface electrode (23) is disposed at a different location from the control circuit region (50) and is disposed on the active region (40).

[0345] Two mutually orthogonal directions along the surface (20S) of the component are designated as the first direction (Y direction) and the second direction (X direction).

[0346] The active region (40) is formed to surround the control circuit region (50) from both sides in the second direction (X direction) and one side in the first direction (Y direction).

[0347] The surface electrode (23) is formed to surround the control circuit region (50) from both sides of the second direction (X direction) and one side of the first direction (Y direction).

[0348] (Note B2)

[0349] According to the semiconductor element described in Appendix B1, among which,

[0350] The surface electrode (23) includes:

[0351] The first electrode region (23A) is positioned adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and

[0352] The second electrode region (23B) and the third electrode region (23C) are separately arranged on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0353] (Note B3)

[0354] According to the semiconductor elements described in Appendix B2, among which,

[0355] The second electrode region (23B) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0356] (Note B4)

[0357] According to the semiconductor elements described in notes B2 or B3, among which,

[0358] The third electrode region (23C) surrounds the entire control circuit region (50) in the first direction (Y direction) when viewed from the second direction (X direction).

[0359] (Note B5)

[0360] According to any one of the semiconductor elements described in notes B1 to B4, among which,

[0361] The active region (40) includes:

[0362] The first transistor region (41) is positioned adjacent to the control circuit region (50) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and

[0363] The second transistor region (42) and the third transistor region (43) are separately arranged on both sides of the control circuit region (50) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0364] (Note B6)

[0365] According to the semiconductor elements described in Appendix B5, among which,

[0366] The second transistor region (42) surrounds the entire first direction (Y direction) of the control circuit region (50) when viewed from the second direction (X direction).

[0367] (Note B7)

[0368] According to the semiconductor elements described in Appendix B5 or B6, among which,

[0369] The third transistor region (43) surrounds the entire first direction (Y direction) of the control circuit region (50) when viewed from the second direction (X direction).

[0370] (Note C1)

[0371] A semiconductor element (20) includes:

[0372] The component surface (20S) includes an active region (130) on which a power transistor is formed and a control circuit region (140) on which a control circuit (110) for controlling the power transistor is formed; and

[0373] The surface electrode (150) is located at a different position from the control circuit region (140) and is disposed on the active region (130).

[0374] Two mutually orthogonal directions along the surface (20S) of the component are designated as the first direction (Y direction) and the second direction (X direction).

[0375] The active region (130) is formed to surround the control circuit region (140) from both sides in the second direction (X direction) and one side in the first direction (Y direction).

[0376] The surface electrode (150) is formed to surround the control circuit region (140) from one side of the second direction (X direction) and one side of the first direction (Y direction).

[0377] (Note C2)

[0378] According to the semiconductor element described in Appendix C1, among which,

[0379] The surface electrode (150) includes:

[0380] The first electrode region (151) is positioned adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and

[0381] The second electrode region (152) is positioned adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0382] (Note C3)

[0383] According to the semiconductor elements described in Appendix C2, among which,

[0384] The second electrode region (152) surrounds the entire first direction (Y direction) of the control circuit region (140) when viewed from the second direction (X direction).

[0385] (Note C4)

[0386] According to any one of the semiconductor elements described in notes C1 to C3, among which,

[0387] The active region (130) includes:

[0388] The first transistor region (131) is positioned adjacent to the control circuit region (140) in the first direction (Y direction) when viewed from the thickness direction (Z direction) of the semiconductor element (20); and

[0389] The second transistor region (132) is positioned adjacent to the control circuit region (140) in the second direction (X direction) when viewed from the thickness direction (Z direction).

[0390] (Note C5)

[0391] According to the semiconductor elements described in Appendix C4, among which,

[0392] The second transistor region (132) surrounds the entire first direction (Y direction) of the control circuit region (140) when viewed from the second direction (X direction).

[0393] The above description is merely illustrative. Those skilled in the art will recognize that many other feasible combinations and substitutions are possible besides the constituent elements and methods (manufacturing processes) listed for illustrating the technology of this disclosure. This disclosure is intended to include all alternatives, modifications, and alterations within the scope of this disclosure, including the claims.

[0394] Explanation of reference numerals in the attached figures

[0395] 10… Semiconductor Devices

[0396] 20… Semiconductor components

[0397] 20S… Component Surface

[0398] 20R… Component back

[0399] 20A~20D…First to fourth element side

[0400] 21…Power soldering pads

[0401] 22… Control pads

[0402] 23…Source Electrode

[0403] 23A…First electrode region

[0404] 23AA…slit

[0405] 23B…Second Electrode Region

[0406] 23C…Third electrode region

[0407] 24…Drain electrode

[0408] 25…passivation film

[0409] 25A~25E…First to Fifth Openings

[0410] 30…lead frame

[0411] 31…chip pads

[0412] 31S… Chip pad surface

[0413] 31R… Back of chip pads

[0414] 32A~32D…First to Fourth Power Leads

[0415] 33A~33D…First to Fourth Control Leads

[0416] 40… Active Area

[0417] 41…First transistor region

[0418] 42…Second transistor region

[0419] 43…Third transistor region

[0420] 44…slit

[0421] 50…Control Circuit Area

[0422] 51~53…First to Third Sides

[0423] 54…Internal pads

[0424] 54A…First internal pad

[0425] 54B…Second internal pad

[0426] 60…sealing resin

[0427] 61…Sealing surface

[0428] 62…Sealed back

[0429] 63~64…First~Fourth Sealing Sides

[0430] 71~78…First to Eighth Conductors

[0431] 71A~74A…First~Fourth Electrode Connection Section

[0432] 81…First heat sink

[0433] 82…Second heat sink

[0434] 83… Heat sink

[0435] 90A~90D… Heat dissipation area

[0436] 91A~91C…Non-heat dissipation areas

[0437] 100…Switching circuit

[0438] 110… control circuit

[0439] 111… Current sensor circuit

[0440] 112…Temperature sensor circuit

[0441] 113…Overcurrent Protection Circuit

[0442] 114…Overheat protection circuit

[0443] 115…Low Voltage Malfunction Prevention Circuit

[0444] 116… Input Terminal

[0445] 117…Input side grounding terminal

[0446] 118… Output Terminal

[0447] 119… Output side grounding terminal

[0448] 121…Input wiring

[0449] 122…Grounding wiring

[0450] 200… Series circuit

[0451] 201…Power Supply

[0452] 202…Inductive load

[0453] 130… Active area

[0454] 131…First transistor region

[0455] 132…Second transistor region

[0456] 133… Slit

[0457] 140…Control Circuit Area

[0458] 141~143…First to Third Sides

[0459] 150…Source Electrode

[0460] 151…First electrode region

[0461] 152…Second electrode region

[0462] 153…slit

[0463] 160…passivation film

[0464] 161~163…First to Third Openings

[0465] Diodes D1, D2...

[0466] R1~R4…first to fourth resistors

[0467] L…coil

[0468] Sw… switch

[0469] WA1… Width dimension of the first transistor region

[0470] WA2… Width dimension of the second transistor region

[0471] WA3… Width dimension of the third transistor region

[0472] LA1…Length dimension of the first transistor region

[0473] LA2…Length dimension of the second transistor region

[0474] LA3…Length dimension of the third transistor region

[0475] WB1… Width dimension of the first electrode region

[0476] WB2… Width dimension of the second electrode region

[0477] WB3… Width dimension of the third electrode region

[0478] LB1…Length dimension of the first electrode region

[0479] LB2…Length dimension of the second electrode region

[0480] LB3…Length dimension of the third electrode region

[0481] WC1… Width dimension of the first transistor region

[0482] WC2… Width dimension of the second transistor region

[0483] LC1…Length dimension of the first transistor region

[0484] LC2…Length dimension of the second transistor region

[0485] WD1… Width dimension of the first electrode region

[0486] WD2… Width dimension of the second electrode region

[0487] LD1…Length dimension of the first electrode region

[0488] LD2…Length dimension of the second electrode region

Claims

1. A semiconductor device, comprising: A semiconductor device includes a device surface, a device back surface facing a side opposite to the device surface, and a surface electrode formed on the device surface; Chip pads support the semiconductor element; Multiple leads are arranged around the chip pads; as well as Multiple wires connect the surface electrode to the multiple leads. The surface of the component includes an active region on which a power transistor is formed and a control circuit region on which a control circuit for controlling the power transistor is formed. Two directions orthogonal to each other in a direction orthogonal to the thickness direction of the semiconductor element are respectively designated as the first direction and the second direction. The active region is formed to surround the control circuit region from both sides in the second direction and one side in the first direction. The surface electrode is disposed at a different location from the control circuit region and is disposed on the active region, and is formed to surround the control circuit region from both sides of the second direction and one side of the first direction when viewed from the thickness direction.

2. The semiconductor device according to claim 1, wherein, The surface electrode includes: A first electrode region is positioned adjacent to the control circuit region in the first direction when viewed from the thickness direction; and The second electrode region and the third electrode region are separately arranged on both sides of the control circuit region in the second direction when viewed from the thickness direction. The plurality of leads include: The first lead and the second lead are located in the region on the side opposite to the control circuit region relative to the surface electrode in the first direction, and are arranged separately in the second direction; The third lead is disposed in the region adjacent to the second electrode region on both sides of the surface electrode in the second direction; and The fourth lead is located in the region adjacent to the third electrode region in the areas on both sides of the surface electrode in the second direction. The plurality of wires includes: Multiple first wires connect the first electrode region to the first lead; Multiple second wires connect the first electrode region to the second leads; Multiple third wires connect the second electrode region to the third lead; and Multiple fourth wires connect the third electrode region to the fourth leads.

3. The semiconductor device according to claim 2, wherein, The width of the first electrode region is larger than the width of the second electrode region and the width of the third electrode region. The plurality of first conductors are arranged separately from each other in the second direction, staggered in the first direction. The plurality of second conductors are arranged separately from each other in the second direction, staggered from each other in the first direction.

4. The semiconductor device according to claim 3, wherein, The semiconductor device also includes a plurality of heat sinks coupled to the surface electrodes. The heat sink is disposed in the first electrode region.

5. The semiconductor device according to claim 4, wherein, The heat sink includes: A first heat sink is disposed in the second direction, offset from the center of the first electrode region from the second electrode region; and The second heat sink is disposed in the third electrode region, which is offset from the center of the first electrode region in the second direction.

6. The semiconductor device according to claim 5, wherein, The plurality of first wires each include a first electrode connection portion. The first heat sink is positioned in a direction that extends the first wire relative to the first electrode connection when viewed from the thickness direction of the semiconductor element.

7. The semiconductor device according to claim 5 or 6, wherein, The plurality of second wires each include a second electrode connection portion. The second heat sink is positioned in a direction that extends the second wire relative to the second electrode connection when viewed from the thickness direction of the semiconductor element.

8. A semiconductor device, comprising: A semiconductor device includes a device surface, a device back surface facing a side opposite to the device surface, and a surface electrode formed on the device surface; Chip pads support the semiconductor element; Multiple leads are arranged around the chip pads; as well as Multiple wires connect the surface electrode to the multiple leads. The surface of the component includes an active region on which a power transistor is formed and a control circuit region on which a control circuit for controlling the power transistor is formed. Two directions orthogonal to each other in a direction orthogonal to the thickness direction of the semiconductor element are respectively designated as the first direction and the second direction. The active region is formed to surround the control circuit region from one side in the first direction and one side in the second direction. The surface electrode is disposed at a different location from the control circuit region and is disposed on the active region, and is formed to surround the control circuit region from one side of the first direction and one side of the second direction when viewed from the thickness direction.

9. The semiconductor device according to claim 8, wherein, The surface electrode includes: A first electrode region is positioned adjacent to the control circuit region in the first direction when viewed from the thickness direction; and The second electrode region is positioned adjacent to the control circuit region in the second direction when viewed from the thickness direction. The plurality of leads include: The first lead and the second lead are located in a region on the side opposite to the control circuit region relative to the surface electrode in the first direction, and are arranged separately along the second direction; and The third and fourth leads are separately disposed in the regions on both sides of the surface electrode in the second direction. The plurality of wires includes: Multiple first wires connect the first electrode region to the first lead; Multiple second wires connect the first electrode region to the second leads; Multiple third wires connect the first electrode region to the third lead; and Multiple fourth wires connect the second electrode region to the fourth leads.

10. The semiconductor device according to claim 9, wherein, The plurality of first conductors are arranged separately from each other in the second direction, staggered in the first direction. The plurality of second conductors are arranged separately from each other in the second direction, staggered from each other in the first direction.

11. The semiconductor device according to claim 10, wherein, The plurality of first wires each include a first electrode connection portion connected to the surface electrode. The plurality of second wires each include a second electrode connection portion connected to the surface electrode. The semiconductor device further includes: A first heat sink is disposed in a direction extending along the first conductive line relative to the first electrode connection portion when viewed from the thickness direction of the semiconductor element; and The second heat sink is disposed in a direction along which the second wire extends relative to the second electrode connection portion when viewed from the thickness direction of the semiconductor element.

12. The semiconductor device according to claim 1 or 8, wherein, The plurality of wires include electrode connection portions connected to the surface electrodes. A heat sink is attached to the surface electrode. The heat sink is disposed separately from the electrode connection portion of the plurality of wires.

13. The semiconductor device according to claim 12, wherein, The heat sink is positioned adjacent to the electrode connection portion of the plurality of wires.

14. The semiconductor device according to claim 12, wherein, The heat sink is made of the same material as the wire.

15. The semiconductor device according to claim 14, wherein, The heat sink contains Cu.

16. The semiconductor device according to claim 15, wherein, The heat sink is formed in the same shape as the electrode connection portion.

17. The semiconductor device according to any one of claims 1 to 16, wherein, The semiconductor device includes a source electrode formed on the surface of the device as a surface electrode and a drain electrode formed on the back side of the device.

18. The semiconductor device according to claim 17, wherein, The drain electrode is formed over the entire back surface of the element.

19. The semiconductor device according to any one of claims 1 to 18, wherein, The semiconductor device also includes a sealing resin for sealing the semiconductor element and the plurality of wires.

20. The semiconductor device of claim 19, wherein, The sealing resin has a sealing surface facing the same side as the surface of the element and a sealing back side facing the opposite side of the sealing surface. The chip pads are exposed from the back of the seal.

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