A master-slave device cooperation-based thermal test method and system

Abstract

The application discloses a kind of hot test method and system based on master-slave device cooperation, multiple test devices involved are connected using cascade topology on control signal network, and the power output end of each test device is interconnected in electrical parallel mode and forms common power supply interface, which is used to be connected to the device under test.The method comprises the following steps: the master device in multiple test devices generates and sequentially outputs current output signal, data acquisition signal, current off signal and power off signal and other multiple reference test signals according to preset order in response to the start test instruction issued by host computer, and executes the test operation corresponding to each reference test signal.The remaining each slave device, based on the multiple reference test signals sequentially received from the upstream device in the cascade, sequentially synchronously executes the corresponding test operation;Wherein, the test data collected by each of the multiple test devices is uploaded to the host computer for hot test analysis.

Description

Technical Field

[0001] This specification relates to the field of thermal testing technology, and in particular to a thermal testing method and system based on master-slave device collaboration. Background Technology

[0002] Thermal testing is a crucial step in evaluating the thermal performance and reliability of electronic equipment and power systems, especially their core power components, under normal or extreme conditions. During testing, specific electrical stress (usually operating current) is applied to the device under test (DUT) to generate Joule heating, simulating its temperature rise, heat distribution, and heat dissipation characteristics in actual operation. Precise measurement and analysis of parameters such as device temperature and thermal resistance effectively assesses design margins, lifespan expectations, and failure risks, making it a core technical means to ensure the reliability of products in fields such as electric vehicles, industrial frequency converters, new energy, and high-power-density semiconductors.

[0003] With the rapid development of downstream applications, especially the widespread use of electric vehicle drive systems, large-scale energy storage devices, and third-generation semiconductor devices represented by IGBTs and SiC MOSFETs, product power levels continue to rise. This directly leads to a dramatic increase in the continuous test current required for performance verification and aging tests of core power components, from the traditional hundreds of amperes to thousands or even tens of thousands of amperes. This exponential growth in test current demand has become one of the most severe challenges facing the field of thermal testing.

[0004] To address this challenge, the current industry standard solution is to design and manufacture dedicated test equipment with higher single-unit output capabilities, essentially increasing the rated output current of a single device through a "single-unit capacity expansion" approach. However, this approach suffers from a fundamental bottleneck in its physical principles. According to Joule's law (P = I²R, where I is the current and R is the internal resistance), the heat generated by the conductor circuit and power devices inside the test equipment is proportional to the square of the current flowing through it. See also... Figure 1 This means that when the test current demand (IH = 2I0) doubles, the heat generated by the device itself will increase to four times. This geometric increase in heat generation triggers a series of intractable systemic problems:

[0005] 1. Thermal management disaster: In order to dissipate huge amounts of heat, extremely complex and expensive high-performance forced cooling systems (such as high-flow water cooling) must be equipped. Not only does this consume a lot of energy, but it also causes the stability and control accuracy of the temperature field in the test environment to deteriorate sharply, which seriously affects the accuracy and repeatability of the test data.

[0006] 2. Deterioration of equipment reliability: Power devices operate under extreme thermal stress for a long time, and their lifespan decreases exponentially with the increase of junction temperature, resulting in a significant decrease in the reliability, stability and service life of the test equipment itself.

[0007] 3. Soaring Costs and Size: To handle ultra-high currents, thicker cables and copper busbars are required, along with larger power devices, leading to a non-linear increase in equipment size, weight, and raw material costs. Simultaneously, the supporting power supply and distribution infrastructure also needs a complete upgrade, making the overall solution exceptionally bulky and expensive.

[0008] 4. Technological ceilings are emerging: Limited by material properties, heat dissipation efficiency and engineering feasibility, the path of continuously increasing the current capacity of a single device has reached obvious technological, cost and reliability ceilings, making it difficult to meet the continuously growing testing needs in the future.

[0009] As can be seen from the above, the traditional "single-machine capacity expansion" high-current testing scheme is constrained by the square thermal effect brought about by I²R in terms of physical principle, and falls into the dilemma of mutual constraints between efficiency, cost, reliability and accuracy in practical application.

[0010] Therefore, in the thermal testing of electronic equipment or power systems, there is an urgent need for an innovative technical solution that can meet the ultra-large test current requirements of thousands to tens of thousands of amperes, fundamentally break the above-mentioned square heat growth law, effectively suppress the total heat generation of the system, and thus solve a series of core problems such as low equipment reliability, poor test accuracy, high operating costs and limited system scalability. Summary of the Invention

[0011] This invention provides a thermal testing method and system based on master-slave device collaboration, which can solve the above-mentioned technical problems.

[0012] According to the first aspect, a thermal testing method based on master-slave device collaboration is provided, involving multiple test devices. These test devices are connected in a cascaded topology on a control signal network, and the power output terminals of each test device are interconnected in electrical parallel to form a common power supply interface, which is used to connect to the device under test. The method includes the following steps:

[0013] The master device among the multiple testing devices responds to the start test command issued by the host computer, generates and outputs multiple reference test signals in a preset order, and executes the test operation corresponding to each reference test signal. The multiple reference test signals include: power-on signal, current output signal, data acquisition signal, current-off signal, and power-off signal. Each slave device among the multiple testing devices, based on the multiple reference test signals received sequentially from the upstream devices in the cascade, synchronously executes the corresponding test operation. The test data collected by each of the multiple testing devices is uploaded to the host computer for thermal test analysis.

[0014] In one embodiment, each of the plurality of test devices is equipped with an anti-backflow switch device connected in series in its output circuit; and throughout the entire test process, the anti-backflow switch device of each test device remains in a conducting state to prevent current backflow caused by potential differences between the test devices.

[0015] In one embodiment, before the master device responds to the start test command, the method further includes: a first test device among the plurality of test devices sets its operating mode to master mode according to a first configuration signal received from a host computer, thereby being configured as a master device. Each of the other test devices among the plurality of test devices, excluding the first test device, sets its operating mode to slave mode according to a second configuration signal received from a host computer, thereby being configured as a slave device; in slave mode, the device is configured to: shut down its internal signal source and enter a follow state for reference control signals transmitted from upstream devices.

[0016] In one embodiment, before the master device responds to the start test command, the method further includes: the plurality of test devices respectively receiving operating parameters from the host computer, the operating parameters including: an upper limit of output voltage, a target current value for stable output, and parameter information to be collected.

[0017] In one embodiment, the cascading is electrically connected via connectors.

[0018] According to a second aspect, a thermal testing system based on master-slave device collaboration is provided, comprising: a host computer and multiple test devices. The multiple test devices are interconnected via a cascaded topology on a control signal network, and the power output terminals of each test device are electrically connected in parallel to form a common power supply interface, which is used to connect to the device under test (DUT). The host computer is used to issue a start test command to the device designated as the master device among the multiple test devices. The master device, in response to the start test command, generates and sequentially outputs multiple reference test signals according to a preset order, and executes test operations corresponding to each reference test signal. The multiple reference test signals include at least a power-on signal, a current output signal, a data acquisition signal, a current-off signal, and a power-off signal. Each slave device among the multiple test devices is used to sequentially and synchronously execute the corresponding test operation based on the multiple reference test signals received sequentially from its upstream device in the cascaded topology. The multiple test devices are also used to upload the collected test data to the host computer for thermal test analysis.

[0019] In one embodiment, each of the plurality of test devices is equipped with an anti-backflow switch device connected in series in its output circuit; and throughout the entire test process, the anti-backflow switch device of each test device remains in a conducting state to prevent current backflow caused by potential differences between the test devices.

[0020] In one embodiment, the host computer is further configured to, before the start test command is issued: issue a first configuration signal to a first test device among the plurality of test devices to configure the first test device as a master device; and issue a second configuration signal to the remaining test devices respectively to configure the remaining test devices as slave devices, wherein the slave device is specifically configured to: shut down its internal signal source and enter a follow state of the reference control signal transmitted by the upstream device.

[0021] In one embodiment, the host computer is further configured to send operating parameters to the plurality of test devices respectively before the start test command is issued. The operating parameters include: upper limit of output voltage, output current value, and parameter information to be collected.

[0022] In one embodiment, the cascaded topology is electrically connected via connectors.

[0023] In summary, by using the methods and apparatus disclosed in the embodiments of this specification, a safe, reliable, and accurate supply of ultra-large test current can be achieved. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the system structure of a traditional single-unit capacity expansion solution for high current problems;

[0026] Figure 2 A schematic diagram of a simple parallel connection scheme for addressing high current problems;

[0027] Figure 3 This is a timing diagram illustrating the asynchronous output currents between devices in a simple parallel connection scheme.

[0028] Figure 4 This is a schematic diagram of the system structure of the master-slave collaborative scheme proposed in this invention. Detailed Implementation

[0029] The solution provided in this specification will now be described with reference to the accompanying drawings.

[0030] As mentioned earlier, the exponential growth in test current requirements has become one of the most severe challenges facing the field of thermal testing. To address this challenge, the industry's traditional "single-unit capacity expansion" high-current testing solutions are physically constrained by the square thermal effect caused by I²R, and in practical applications, they are caught in a dilemma of mutual constraints between efficiency, cost, reliability, and accuracy.

[0031] To address the "squared thermal growth" bottleneck encountered when expanding the capacity of a single device, an alternative approach has emerged: connecting multiple standard or medium-capacity testing devices in parallel to collectively provide the required large testing current. The initial intention of this solution is to leverage existing, mature, reliable, and relatively cost-controllable standardized products, using quantity aggregation to meet the ever-increasing total current demand, thereby fundamentally avoiding the technical challenges, high costs, and reliability risks associated with developing and manufacturing a single ultra-large, customized special device.

[0032] See Figure 2 The basic implementation of this scheme is as follows: the output terminals of two or more independent test devices are directly connected in parallel, that is, their positive terminals are connected to positive terminals and their negative terminals are connected to negative terminals to form a common output port. This port is then connected to the two ends of the device under test (DUT). From the perspective of circuit principle, the current output by each device will converge at the parallel connection point, and theoretically, the arithmetic superposition of currents can be achieved, thereby multiplying the total output current.

[0033] However, this seemingly straightforward "simple parallel" solution has proven to have serious and fundamental system flaws in engineering practice, making it unable to meet the requirements of high-precision and high-reliability thermal testing. The core problems can be summarized in the following two aspects:

[0034] 1. Static flow sharing failure and internal circulation

[0035] Due to manufacturing tolerances, component aging, and the influence of ambient temperature, each parallel device, acting as an independent voltage or current source, will inevitably exhibit slight but not negligible differences in its key parameters (such as internal reference voltage, output internal resistance, and current sampling accuracy). When the output terminals are directly hard-connected, these parameter differences will lead to a serious consequence: the devices will be unable to automatically and stably share the total load current. The device with a slightly higher output voltage will attempt to carry more current, and may even reverse-feed current to the device with a slightly lower output voltage, thus forming an internal circulating current loop among the parallel devices that does not flow through the measured load. This circulating current not only does not perform external work, but also generates huge additional losses in the internal circuitry and power devices of the equipment (P_circulating current = I_circulating current² * R_internal resistance), causing a surge in system reactive power consumption, abnormal heat generation of the equipment, and a sharp deterioration in overall heat generation, which may even offset or exceed the "single-machine squared heat effect" that the parallel scheme aims to avoid.

[0036] 2. Dynamic response mismatch and synchronization failure

[0037] In thermal testing, especially when observing the transient thermal response of devices, it is required that the applied test current can achieve rapid and accurate step changes. In a simple parallel architecture, each device is regulated by its own independent control loop. The response speed, compensation characteristics, and delays for start-up and shutdown commands of these loops are difficult to make completely consistent. When the system receives a rapid current step command, the outputs of each device cannot achieve true synchronization; time differences and waveform variations will occur during the current rise or fall. For example, Figure 3 The result shows that due to asynchrony, the test current applied at time t1 is I0, but it only reaches 2I0 at time t2.

[0038] This dynamic mismatch leads to severely uneven current distribution among devices during transient processes. This can momentarily trigger the overcurrent protection of one device, causing it to shut down and interrupting the entire test process. More seriously, the composite current waveform applied to the device under test will be distorted, overshooting, or oscillating, rather than an ideal, pure step signal. This directly results in distorted transient thermal response data of the device under test, rendering characteristic analyses based on this data (such as junction temperature and thermal resistance testing) inaccurate and meaningless. It may even damage valuable test samples due to current surges.

[0039] Therefore, although parallel connection of multiple devices conceptually bypasses the thermal bottleneck of single-machine capacity expansion, its simple direct parallel implementation introduces more intractable problems such as static operating point instability and dynamic coordination failure. These problems fundamentally undermine the current stability, accuracy, and synchronization required for testing, making this solution infeasible in actual high-standard engineering testing.

[0040] Based on the above in-depth observation and analysis of the thermal bottleneck of the traditional "single-machine expansion" scheme and the uncontrolled coordination problem of the "simple parallel" scheme, this invention proposes an improved scheme, involving a multi-test device parallel system architecture based on master-slave collaboration and distributed output, as well as a high-precision synchronous control method. This invention aims to integrate multiple standard test units into a unified, high-performance "virtual high-power source" electrically and logically through top-level system design and bottom-level circuit reconstruction, thereby fundamentally avoiding inherent defects such as circulating current and loss of synchronization while aggregating ultra-large test currents.

[0041] This invention can bring about the following multiple beneficial effects and systematically solve the aforementioned technical difficulties:

[0042] 1) Architectural innovation to eliminate the root cause of circulating current: By configuring each parallel unit with an independent output loop that is isolated from each other, the path of internal circulating current between devices is cut off from the physical topology, completely eliminating static circulating current and additional losses caused by parameter differences, and ensuring system efficiency and thermal safety.

[0043] 2) Unified control for dynamic synchronization: A master-slave high-precision synchronous control mechanism is adopted, in which the master controller uniformly generates and issues current commands and synchronization signals, ensuring that all parallel units achieve microsecond-level synchronous start-up, stop, and dynamic adjustment. This eliminates dynamic current distribution imbalance and waveform distortion caused by differences in the response of independent control loops, ensuring the purity and transient accuracy of the current waveform applied to the device under test.

[0044] 3) Performance Equivalence and Linear Expansion: Through the above architecture and control, multiple devices connected in parallel are electrically equivalent to a single high-power device with excellent performance. The total output capacity, bandwidth, and stability of the system increase linearly with the number of parallel units, overcoming the limitations in performance and reliability of traditional single-unit expansion, and providing a smooth and economical capacity expansion path.

[0045] 4) Optimized thermal management for linear heat growth: By completely eliminating circulating current losses and achieving efficient current sharing, the total system heat generation primarily originates from the active power losses of the load current in each unit across its internal resistance. Therefore, when the total output current doubles, the total system heat generation strictly follows a linear growth pattern, rather than a quadratic one. This significantly reduces the extreme requirements on the cooling system, improves the equipment's reliability and lifespan, and provides a stable thermal boundary for the testing environment, significantly enhancing testing accuracy and repeatability.

[0046] In summary, through system-level innovation, this invention not only achieves safe, reliable, and accurate supply of ultra-large test current, but also fundamentally optimizes the system's thermal growth pattern from a "geometric series" to an "arithmetic series," thereby systematically solving the four core challenges faced in high-power thermal testing: heat dissipation challenges, reliability risks, test accuracy distortion, and limited scalability.

[0047] Next, we will first introduce the improvements in system architecture of this invention, and then introduce the workflow of thermal testing based on the improved testing system.

[0048] I. Improvements in System Architecture

[0049] See Figure 4 The thermal testing system provided by the present invention includes a host computer and multiple testing devices (testing device 1 to testing device n).

[0050] The host computer is the computer device at the management level in the thermal testing system. It is responsible for providing the human-machine interface and undertaking the functions of centralized monitoring, command scheduling, and data management of the lower-level testing equipment. In actual deployment, the host computer usually uses an industrial personal computer as its hardware carrier, that is, it utilizes the environmental adaptability, rich interface, and computing stability of the industrial personal computer (IPC) to run the corresponding control software.

[0051] A "monitor-execution" collaborative relationship is established between the host computer and multiple test devices. Specifically, the host computer connects to each test device via an industrial communication network (executively, it can be Ethernet, Controller Area Network, or Universal Serial Bus), and is used to issue configuration commands, operating parameters, and start test commands, as well as receive test data collected by each device. Dedicated control software runs on the host computer, used to perform dynamic configuration of master and slave devices, test parameter setting, test process control, and comprehensive data analysis.

[0052] Each test device is equipped with a corresponding firmware module, enabling it to switch between master / slave operating modes according to instructions from the host computer. These test devices are interconnected in a cascaded topology on the control signal network, forming a signal series link. The cascaded structure can use connectors (such as DB9, RJ45, or dedicated multi-core interfaces) to achieve electrical connections between devices, facilitating equipment installation and maintenance.

[0053] In this cascaded link, control signals are sequentially transmitted from upstream devices to downstream devices. Since signal attenuation or distortion may occur during transmission, each test device can reshape and amplify the received signal before forwarding it to the next device, thus ensuring signal integrity and timing consistency at the end of the entire link. This approach avoids the synchronization errors and complexity caused by signal distribution in star topologies, providing a reliable hardware foundation for high-precision synchronization among multiple devices.

[0054] Meanwhile, the power output terminals (including the positive and negative terminals for current output) of each test device are interconnected in electrical parallel to form a common power supply interface, which is used to connect to the device under test (DUT). Through the aforementioned firmware module, the test devices can receive, follow, or forward reference test signals in the cascaded link, thereby achieving high-precision synchronization of power supply, sampling, and other operations among multiple devices.

[0055] The above design achieves hierarchical decoupling between management control and real-time execution. It ensures the flexibility of system configuration and scheduling through the host computer software, and ensures the timing consistency of parallel output and data acquisition through the device firmware, thereby improving the overall reliability, synchronization and maintainability of thermal testing.

[0056] Furthermore, a reverse-current protection switch controlled by the device firmware can be connected in series in the output circuit of each test device (i.e., the complete current path from the positive terminal of the device, through the external load, and back to the negative terminal). This device can employ ideal diode circuits or MOSFET switches to ensure that current flows only unidirectionally from the test device, effectively preventing reverse current from flowing into the device due to minor differences in output voltage between devices or faults. This design not only avoids potential damage to the test device itself caused by reverse current but also eliminates output unevenness and abnormal power consumption caused by circulating current between parallel devices, thereby further improving the safety and output stability of the system under high-current, multi-device parallel operation modes.

[0057] II. Workflow for Thermal Testing Based on the Improved Testing System

[0058] The hot testing process can be divided into two core phases: the system configuration and initialization phase, and the synchronous test execution phase. These two phases will be introduced in turn below.

[0059] 1. System Configuration and Initialization Phase

[0060] After the system is powered on, the first step is to determine the roles of the devices. This system supports two master-slave configuration methods: dynamic configuration and static configuration. In dynamic configuration mode, operators use dedicated control software in the host computer to send configuration signals to multiple test devices to complete the master / slave device configuration.

[0061] Specifically, the host computer sends a first configuration signal to the first test device among multiple test devices. Upon receiving the first configuration signal, the device sets its operating mode to master mode, thus being configured as the master device. In this mode, the master device will, in the subsequent synchronous test phase, use its internal signal source as a reference to generate and output a reference signal sequence that controls the entire test process.

[0062] It should be noted that the first test device can be any one of multiple test devices. In addition, the "first" in "first test device" and "first configuration signal", as well as similar terms such as "second" and "third" elsewhere in the text, are all for the purpose of distinguishing similar things and do not have any other limiting function such as ordering or quantity restriction.

[0063] The host computer also sends a second configuration signal to the remaining test devices to configure them as slave devices. Upon receiving the second configuration signal, each slave device switches its operating mode to slave mode. In this mode, during subsequent synchronization testing, the slave device shuts down its internal signal source and relies on the cascaded link to receive benchmark test signals from upstream devices, and uses its own control resources to accurately reproduce and follow these signals.

[0064] In addition, the system also supports static configuration, which means that specific test equipment can be fixed as master equipment at the factory or through hardware settings, and other equipment can be fixed as slave equipment. This eliminates the need for dynamic configuration before each test and is suitable for test scenarios with fixed roles.

[0065] After completing the master-slave role configuration of the test equipment, the host computer continues to send operating parameters to all test equipment to unify test conditions and execution specifications. The operating parameters may include: the upper limit protection value of the output voltage, the target value of the steady-state output current, and the parameter information to be collected (such as the sampling frequency and accuracy of voltage, current, and temperature).

[0066] It should be noted that the host computer can issue the same or different operating parameters to each test device according to the actual test requirements. For example, each device can be set with the same upper limit of output voltage and target current value to achieve current sharing. Alternatively, different parameters can be set for different devices, such as setting a target current value of 1000A for device A and a target current value of 500A for device B.

[0067] Through this process of issuing and setting operating parameters, each test device obtains a clear and independently configurable execution basis before the test begins. This allows them to output and collect data according to predetermined electrical parameters under unified timing control during the subsequent synchronous test phase, ensuring the system's flexibility and consistency under complex testing requirements.

[0068] 2. Synchronous test execution phase

[0069] After system configuration and initialization are complete, the testing process enters the synchronous test execution phase. The host computer sends a start test command to the master device, triggering the master device to execute a preset test program. This test program can be understood as being pre-installed in the hardware of the test device.

[0070] In response to the start test command, the master device uses its internal signal source as a timing reference to generate and sequentially output multiple reference test signals to the cascaded link (arranged in sequence to form a reference test signal sequence), while simultaneously performing corresponding operations itself. This reference signal sequence typically includes:

[0071] Power-on signal: The master device initiates its own power soft-start, and at the same time, this signal is transmitted along the cascade link to notify the slave devices to prepare for power supply.

[0072] Current output signal: The main equipment controls its output current to reach the set target value.

[0073] Data acquisition signal: The main device starts its own data acquisition module to sample information such as the operating voltage, current and temperature of the device under test.

[0074] Current shutdown signal and power off signal: The main equipment stops current output and turns off power in sequence to complete the test process.

[0075] In the cascaded link, each slave device sequentially receives the aforementioned benchmark test signals from its upstream device and immediately and synchronously executes operations completely identical to those of the master device. For example, upon receiving a current output signal, the slave device synchronously outputs a set current according to the set parameters; upon receiving a data acquisition signal, it synchronously starts its own data acquisition. During this process, each test device independently controls its output current magnitude and acquisition behavior according to the issued operating parameters, thereby achieving high-precision collaborative output and synchronous sampling of multiple devices under a unified timing sequence.

[0076] Furthermore, throughout the entire testing process (e.g., from the time the master device receives the start test command until the test ends), the anti-backflow switching devices in the output circuits of all test equipment (including the master device and each slave device) remain in the ON (OP) state. Generally, the ON and OFF of these devices are independent of the reference test signal control flow. For example, they do not operate in response to the current output signal of the master device or any other test phase signal. Instead, they are set to the normally OFF state before the system is powered on or the test process starts, and remain so until the end of the entire test task. This ensures that unwanted current backflow caused by the DC bus potential difference between the devices is prevented throughout the entire test cycle, guaranteeing the strict unidirectionality of the output current and the safety of system operation.

[0077] To enhance system safety, the benchmark test signal itself or its accompanying enable signal can be designed as a step-triggered or level-holding signal. When the device detects an abnormal transition of the signal from a valid state (e.g., high level "1") to an invalid state (e.g., low level "0") during the test, an emergency stop procedure can be immediately triggered, simultaneously shutting down its output current and power circuits, thus achieving rapid coordinated protection for all devices.

[0078] During testing, real-time data collected by all test equipment can be uploaded to a host computer. Dedicated control software on the host computer integrates, analyzes, and visualizes this timing-aligned data to evaluate the thermal characteristics and operating status of the device under test under different power supply conditions, ultimately completing the entire test process.

[0079] In summary, the thermal testing method based on master-slave device collaboration provided by this invention not only achieves safe, reliable, and accurate supply of ultra-large test current, but also fundamentally optimizes the system's thermal growth pattern from a "geometric progression" to an "arithmetic progression," thereby systematically solving the four core challenges faced in high-power thermal testing: heat dissipation challenges, reliability risks, test accuracy distortion, and limited scalability.

[0080] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium.

[0081] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A thermal testing method based on master-slave device collaboration, involving multiple testing devices, characterized in that: The multiple test devices are connected in a cascaded topology on the control signal network, and the power output terminals of each test device are interconnected in an electrical parallel manner to form a common power supply interface, which is used to connect to the device under test. The method includes the following steps: The master device among the multiple test devices responds to the start test command issued by the host computer, generates and outputs multiple reference test signals in a preset order, and performs test operations corresponding to each reference test signal; the multiple reference test signals include: power on signal, current output signal, data acquisition signal, current off signal, and power off signal; Each slave device in the plurality of test devices sequentially and synchronously executes corresponding test operations based on the plurality of reference test signals received sequentially from the upstream devices in the cascade. The test data collected by each of the multiple test devices are uploaded to the host computer for thermal test analysis. Before the master device responds to the start test command, the method further includes: The first test device among the plurality of test devices sets its working mode to the master mode according to the first configuration signal received from the host computer, and is thus configured as the master device. Each of the multiple test devices, except for the first test device, sets its operating mode to slave mode according to the second configuration signal received from the host computer, and is thus configured as a slave device; in the slave mode, the device is configured to: shut down the internal signal source and enter a following state of the reference control signal transmitted by the upstream device.

2. The method according to claim 1, characterized in that, Each of the multiple test devices is equipped with an anti-backflow switch connected in series in its output circuit; and throughout the entire test process, the anti-backflow switch of each test device remains in a conducting state to prevent current backflow caused by potential differences between the test devices.

3. The method according to claim 1, characterized in that, Before the master device responds to the start test command, the method further includes: The multiple test devices receive operating parameters from the host computer, including: the upper limit of output voltage, the output current value, and the parameter information to be collected.

4. The method according to claim 1, characterized in that, The cascading is electrically connected via connectors.

5. A thermal testing system based on master-slave device collaboration, characterized in that, include: The host computer and multiple testing devices; The multiple test devices are interconnected in a cascaded topology on the control signal network, and the power output terminals of each test device are interconnected in an electrically parallel manner to form a common power supply interface, which is used to connect to the device under test. The host computer is used to send a start test command to the device designated as the master device among the plurality of test devices; The main device is used to respond to the start test command, generate and output multiple reference test signals in a preset order, and perform test operations corresponding to each reference test signal. The multiple reference test signals include at least a power-on signal, a current output signal, a data acquisition signal, a current-off signal, and a power-off signal. Each slave device among the plurality of test devices is used to sequentially and synchronously execute the corresponding test operation based on the plurality of reference test signals received sequentially from its upstream device in the cascaded topology; The multiple testing devices are also used to upload the collected test data to the host computer, which then performs thermal test analysis. The host computer is also used to: Before the start test command is issued: A first configuration signal is sent to a first test device among the plurality of test devices to configure the first test device as the master device; and A second configuration signal is sent to the remaining test devices to configure them as slave devices. Specifically, the slave devices are configured to: shut down their internal signal sources and enter a follow state for the reference control signals transmitted by the upstream devices.

6. The system according to claim 5, characterized in that, Each of the multiple test devices is equipped with an anti-backflow switch connected in series in its output circuit; and throughout the entire test process, the anti-backflow switch of each test device remains in a conducting state to prevent current backflow caused by potential differences between the test devices.

7. The system according to claim 5, characterized in that, The host computer is also used to send operating parameters to the multiple test devices respectively before the start test command is issued; The operating parameters include: upper limit of output voltage, output current value, and information on parameters to be collected.

8. The system according to claim 5, characterized in that, The cascaded topology achieves electrical connection through connectors.

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