基于异构多核系统的时间同步方法、装置及片上系统

By employing bidirectional message interaction with hardware timestamps and a precise time protocol in a heterogeneous multi-core system, sub-microsecond-level time synchronization is achieved, solving the problems of insufficient synchronization accuracy and high hardware cost in existing technologies. It is suitable for highly integrated SoC architectures and meets the needs of advanced autonomous driving.

CN121807103BActive Publication Date: 2026-07-17BEIJING YUNCHI FUTURE TECH CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING YUNCHI FUTURE TECH CO LTD
Filing Date
2025-12-25
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing technologies struggle to achieve sub-microsecond level high-precision time synchronization in heterogeneous multi-core on-chip systems. Furthermore, existing solutions suffer from insufficient synchronization accuracy, high hardware costs, and significant integration challenges, failing to meet the demands of advanced autonomous driving.

Method used

By using bidirectional message exchange with hardware timestamps in a heterogeneous multi-core system, synchronization time parameters, including basic time deviation, reference synchronization timestamp, and frequency ratio, are obtained. By utilizing the bidirectional measurement mechanism of the precision time protocol and combining it with hardware counters to directly read the timestamp, sub-microsecond time synchronization between cores is achieved.

Benefits of technology

It achieves sub-microsecond time synchronization accuracy at the pure software level, reduces hardware costs and integration complexity, adapts to highly integrated SoC architectures, provides a reliable time reference, and solves the time consistency requirements of L3 and above autonomous driving systems.

✦ Generated by Eureka AI based on patent content.

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Abstract

本公开提供了一种基于异构多核系统的时间同步方法、装置及片上系统,异构多核系统包括作为主节点的第一内核和作为从节点的第二内核,该方法由所述第二内核执行,该方法包括:确定待同步事件发生时的本地硬件时间戳;通过第一内核与第二内核之间基于硬件时间戳的双向报文交互,获取同步时间参数;基于同步时间参数,将本地硬件时间戳转换为对应的全局时间戳。通过将精密时间协议(PTP)的双向测量机制移植至芯片内部的核间通信,并结合硬件级时间戳捕获,系统性地消除了软件抖动和通信延迟不确定性,从而在纯软件层面实现了以往依赖外部硬件连线才能达到的亚微秒级同步精度,同时显著降低了硬件成本与集成复杂度。
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