Address mapping method, address mapping device, electronic device, and storage medium

Abstract

The present disclosure provides an address mapping method, an address mapping device, an electronic device and a storage medium, and belongs to the technical field of communication. The method comprises: in response to a memory access request of a target system, determining a target channel group corresponding to the memory access request, the target channel group being at least one of a plurality of channel groups corresponding to the target system, each channel group comprising a plurality of memory channels; and performing interleaved mapping on a target access address of the memory access request based on the memory channels in the target channel group, to obtain a memory address corresponding to the target access address. The embodiments of the present disclosure can reduce system power consumption and improve memory access efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to an address mapping method, address mapping device, electronic device, and computer-readable storage medium. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a core technology of computer main memory and is widely used in servers, mobile devices, and other applications. A DRAM channel is the channel connecting DRAM in processing systems such as servers, and it is the core carrier for data transfer between the processor (such as CPU or GPU) and memory. When multiple DRAM channels exist in a processing system, address interleaving is typically used to map software addresses to DRAM addresses. As the number of DRAM channels increases, a larger memory footprint is required to balance the performance of multiple DRAM channels, and a larger number of DRAM channels also results in significant power consumption. Summary of the Invention

[0003] This disclosure provides an address mapping method, an address mapping device, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] In a first aspect, this disclosure provides an address mapping method, which includes: in response to a memory access request for a target system, determining a target channel group corresponding to the memory access request, wherein the target channel group is at least one of a plurality of channel groups corresponding to the target system, and each channel group includes a plurality of memory channels; and performing interleaving mapping on the target access address of the memory access request based on the memory channels in the target channel group to obtain a memory address corresponding to the target access address.

[0005] Secondly, this disclosure provides an address mapping apparatus, which includes: a determining module, configured to determine a target channel group corresponding to a memory access request of a target system in response to the memory access request, wherein the target channel group is at least one of a plurality of channel groups corresponding to the target system, and each channel group includes a plurality of memory channels; and a mapping module, configured to perform interleaving mapping on the target access address of the memory access request based on the memory channels in the target channel group to obtain a memory address corresponding to the target access address.

[0006] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the address mapping method described above.

[0007] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the address mapping method described above.

[0008] Fifthly, this disclosure provides a computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the address mapping method described above.

[0009] The address mapping method provided in this disclosure divides multiple memory channels of the target system into multiple channel groups and performs interleaving mapping on a channel group basis. Therefore, only the memory channels in one channel group are needed to meet the address mapping requirements at the same time, without all memory channels participating in the interleaving mapping, thereby reducing system power consumption. In addition, compared with all memory channels participating in the interleaving mapping, only the memory channels in one channel group participate in the interleaving mapping at the same time in this disclosure embodiment. This allows the memory to "see" more intensive memory access requests, which facilitates the overall coordination of these requests. As a result, these requests can be better coordinated, scheduled, and executed, effectively improving the memory access efficiency.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a flowchart illustrating an address mapping method provided in an embodiment of the present disclosure.

[0013] Figure 2This is a schematic diagram of a channel grouping provided in an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram of an interleaving block provided in an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram of a channel grouping provided in an embodiment of the present disclosure.

[0016] Figure 5 This is a schematic diagram of a channel grouping provided in an embodiment of the present disclosure.

[0017] Figure 6 This is a schematic diagram of the composition structure of an address mapping device provided in an embodiment of the present disclosure.

[0018] Figure 7 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure.

[0019] Figure 8 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0021] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0022] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0024] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0025] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals. The use of user data in this technical solution follows relevant national laws and regulations (e.g., the "Information Security Technology - Personal Information Security Specification"). For example, appropriate measures are taken for personal information access control; restrictions are imposed on the display of personal information; the purpose of using personal information does not exceed the scope of direct or reasonable association; and explicit identity targeting is eliminated when using personal information to avoid precisely identifying specific individuals.

[0026] In related technologies, when multiple memory channels exist in a system, address interleaving is typically used to map logical addresses to memory addresses. The granularity of interleaving is usually the cache line size, such as 64B or 128B, to improve bandwidth in practical applications. For example, in a system with 8 DRAM channels, each channel corresponding to a 1GB target address space, the 8GB physical addresses seen by the software, with an interleaving granularity of 128B, are arranged as follows: the 8 128Bs corresponding to 0-1K are mapped to DRAM channels 0, 1, ... 7; the 128Bs corresponding to 1k-2K are mapped to DRAM channels 0, 1, ... 7; and so on.

[0027] When the number of memory channels is large, a large memory footprint is required to achieve good channel balancing, and all memory channels need to be active simultaneously to effectively serve upstream requests. For example, if the system has around 1000 memory channels with an interleaving granularity of 1kB, a memory footprint in the MB range is needed. However, upstream bandwidth capacity is typically much smaller than the bandwidth capacity of the memory; therefore, only a portion of the memory channels (e.g., 100 memory channels) are needed to meet bandwidth requirements at any given time. In short, this implementation leads to wasted system power and bandwidth, and requires a large memory footprint.

[0028] In view of this, the present disclosure provides an address mapping method, an address mapping device, an electronic device, a computer-readable storage medium, and a computer program product, which can reduce system power consumption and improve memory access efficiency.

[0029] Figure 1 This is a flowchart illustrating an address mapping method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The address mapping method may include the following steps:

[0030] Step S11: In response to a memory access request for the target system, determine the target channel group corresponding to the memory access request. The target channel group is at least one of multiple channel groups corresponding to the target system, and each channel group includes multiple memory channels.

[0031] Step S12: Based on the memory channels within the target channel group, the target access address of the memory access request is interleaved and mapped to obtain the memory address corresponding to the target access address.

[0032] In some optional embodiments, the access address corresponding to the memory access request of the target system is usually a contiguous logical address (such as a virtual address or software address). Through interleaving mapping, on the one hand, the contiguous logical address can be distributed to different memory channels for address mapping, enabling the processing unit of the target system to read / write data from multiple memory channels simultaneously, thereby improving system throughput. On the other hand, logical address mapping allows the operating system in the target system to "assemble" scattered physical memory blocks (such as memory blocks in memory) into a contiguous virtual address space, so that the program does not need to modify the logical address when accessing memory data, resulting in high memory access efficiency. Returning to the embodiments of this disclosure, after obtaining the target access address, the target system performs corresponding interleaving mapping based on one or more channel groups (i.e., the target channel group) among multiple channel groups, thereby mapping the target access address to a memory address in the target system.

[0033] In other words, for the target system, the multiple memory channels are divided into multiple channel groups, and each channel group includes one or more memory channels. Based on this structure, when the target system processes the target access address, it no longer processes the entire memory channel, but rather processes the channel group. The target access address is interleaved and mapped to the memory to obtain the memory address corresponding to the target access address. This realizes the mapping between the target access address and the memory address, thereby enabling memory access processing based on the memory address and the corresponding memory space.

[0034] Interleaving mapping is performed on a channel-group basis, which uses memory channels within a single channel group to interleave and map the target access address, rather than interleaving and mapping the target access address across all memory channels of the target system. Because of this, the number of memory channels involved in a single interleaving mapping is relatively small, thus effectively reducing the amount of data in the memory footprint.

[0035] Furthermore, to reduce the power consumption of the target system, multiple memory channels in the channel group currently participating in the interleaving mapping can be set to an active state. Since other channel groups do not yet need to participate in address mapping, multiple memory channels in those other channel groups can enter a sleep state. Compared to related technologies where all memory channels are active regardless of whether they participate in address mapping, this embodiment only requires a few memory channels to be active, while the remaining memory channels can enter a low-power sleep state, thereby effectively reducing system power consumption.

[0036] It should be noted that, typically, upstream bandwidth capacity and / or task bandwidth requirements are much smaller than the bandwidth service capacity of the memory. Therefore, only a few memory channels are needed to meet the requirements. Correspondingly, in this embodiment of the disclosure, only the memory channels in the channel group are needed to meet the bandwidth requirements. Therefore, address mapping can be performed on a per-channel-group basis.

[0037] It should also be noted that the grouping operation for multiple memory channels in the target system only needs to be performed once, and subsequent memory access operations can be performed at least once based on the divided channel groups. If the upstream bandwidth capacity and / or task bandwidth requirements change in the future, the channel groups can be re-divided according to the new requirements so that address interleaving mapping can be performed based on the re-divided channel groups.

[0038] In summary, in this embodiment of the present disclosure, since the multiple memory channels of the target system are divided into multiple channel groups, and the interleaving mapping is performed on a channel group basis, only the memory channels in one channel group are needed to meet the address mapping requirements at the same time, without all memory channels participating in the interleaving mapping, thereby reducing system power consumption. In addition, compared with all memory channels participating in the interleaving mapping, only the memory channels in one channel group participate in the interleaving mapping at the same time in this embodiment of the present disclosure, which allows the memory to "see" a more intensive memory access request, thereby facilitating the overall coordination of these requests, and thus enabling better overall scheduling and execution of these requests, effectively improving the memory access efficiency.

[0039] The address mapping method of this disclosure embodiment will be described in detail below.

[0040] For example, a target system refers to a processing system with certain data processing and data storage capabilities.

[0041] For example, the target system can be a single-core processing system or a many-core processing system, wherein a single-core processing system includes one processing core (or processing unit) and a many-core processing system includes multiple processing cores (or processing units).

[0042] In some alternative embodiments, before determining the target channel group corresponding to the memory access request in response to a memory access request of the target system, the address mapping method may further include: dividing the multiple memory channels of the target system into multiple channel groups.

[0043] Therefore, for multiple memory channels in the target system, they can be pre-divided into multiple channel groups, so that address interleaving mapping can be performed on a channel group basis.

[0044] In some optional embodiments, the target system includes at least one processing core (or controller). The target system can adjust the input signal of the group register through one of the processing cores (or controllers) to achieve channel grouping of multiple memory channels. Upon receiving a memory access request, the processing core schedules the address translation module to perform interleaving mapping of the target access address on a channel group basis. The address translation module can be a functional module integrated inside the processing unit, or it can be a functional module independently located outside the processing core and communicating with the processing core (such as a wireless communication connection or a wired communication connection).

[0045] The group register is used to configure or adjust channel grouping. Different channel grouping methods can be implemented by writing different input signals to the group register. For example, if the input signal of the group register is Signal1, the multiple memory channels of the target system are divided into N1 channel groups, each group including M1 memory channels; if the input signal of the group register is Signal2, the multiple memory channels of the target system are divided into N2 channel groups, each group including M2 memory channels, and M1×N1=M2×N2.

[0046] Furthermore, as mentioned earlier, the power consumption of the target system is related to the number of memory channels within a single channel group. Generally, the smaller the number of memory channels within a single channel group, the fewer memory channels are frequently active, thus effectively reducing system power consumption. In practical applications, appropriate input signals can be written to the group register as needed to balance power consumption and address mapping requirements.

[0047] In some optional embodiments, the memory is the memory of the target system, used to store data such as the processing results or intermediate results of the target system, and this disclosure does not limit this.

[0048] In some optional embodiments, the target system includes K1 memories and K2 memory channels, where K1 and K2 are both integers greater than 1, and K2 ≥ K1. Further, assuming the storage space of each memory is S1, if K2 = K1, then the target storage space corresponding to each memory channel is S1; if K2 > K1, then the target storage space corresponding to each memory channel is S1 × (K1 / K2).

[0049] For example, the memory includes DRAM memory, and correspondingly, the memory channel includes DRAM channel, through which a target memory space within the memory connected to it can be accessed. Accordingly, the memory address can be the DRAM local address.

[0050] In some alternative embodiments, multiple memory channels of the target system can be evenly grouped to obtain multiple channel groups including the same number of memory channels.

[0051] In some optional embodiments, the multiple memory channels of the target system are divided into multiple channel groups, including: uniformly grouping the multiple memory channels of the target system to obtain multiple channel groups, wherein each channel group has the same number of channels, and the number of channels in each group is the number of memory channels included in the channel group.

[0052] For example, the target system includes K memory channels. The multiple memory channels in the target system can be divided into N channel groups, and each channel group includes M memory channels. Here, K, M, and N are all integers, and K = M × N, M ≥ 2.

[0053] Therefore, the memory channels in the target system are divided into N channel groups, each of which includes M memory channels. During address mapping, interleaving mapping is performed with a period of M. After all the target memory spaces corresponding to the M memory channels in a certain memory group have been mapped, the next channel group is then used for interleaving mapping with the M memory channels in that next channel group, and so on.

[0054] Figure 2 This is a schematic diagram of a channel grouping method provided in an embodiment of this disclosure. (Refer to...) Figure 2 The target system includes 6 memory channels, namely memory channel 0 to memory channel 5, and the address range of the target memory space corresponding to each memory channel is 0 to 4.

[0055] like Figure 2 As shown, the six memory channels are divided into three groups of two channels each. Group 0 includes memory channels 0 and 1; group 1 includes memory channels 2 and 3; and group 2 includes memory channels 4 and 5. Based on this grouping, the memory addresses corresponding to memory channels are determined as follows: 0, 2, 4, 6, 8; 1, 3, 5, 7, 9; 10, 12, 14, 16, 18; 11, 13, 15, 17, 19; 20, 22, 24, 26, 28; and 21, 23, 25, 27, 29.

[0056] Correspondingly, based on Figure 2 When the channel groups shown are interleaved, memory channel 0 and memory channel 1 are used to perform interleaving mapping in channel group 0 first. After all memory addresses 0 to 9 are mapped, channel group 1 is used to perform interleaving mapping, and so on, until the corresponding memory access process is completed.

[0057] Furthermore, after the target system receives the memory access request for the first time, it obtains the target access address Addr1 from the memory access request, and uses the first channel group as the channel group to be interleaved. Using memory channel 0 (or memory channel 0 and memory channel 1 if cross-channel is required), it performs interleaving mapping on the target access address Addr1 with memory address 0 as the start address, obtaining the memory address corresponding to the target access address Addr1. In other words, the memory addresses corresponding to the target access address Add1 range from 0 to Localaddr1, memory address 0 corresponds to the start address of the interleaving mapping, and Localaddr1 corresponds to the end address of the interleaving mapping. Localaddr1 can be an address in the target memory space corresponding to memory channel 0 or memory channel 1 (if the amount of data to be written is particularly large, the end address Localaddr1 may be an address in the target memory space corresponding to the memory channel in channel group 1).

[0058] If the initial memory access request does not map all memory addresses 0 to 9, then upon receiving the second memory access request and determining the target access address to be Addr2, the address adjacent to the previous interleaving mapping end address Localaddr1 is used as the starting address for this interleaving mapping. The memory channel (which could be memory channel 0 or memory channel 1) corresponding to this interleaving mapping starting address in the channel group is then used to perform interleaving mapping on the target access address Addr2, thus obtaining the memory address corresponding to Addr2. Upon receiving a new memory access request, interleaving mapping can be performed in the same manner.

[0059] Furthermore, if the target access address is a continuous logical address starting from 0, an address mapping table as shown in Table 1 can be obtained. This address mapping table exemplarily illustrates the mapping relationship between the target access address, memory channel, and memory address.

[0060] Table 1. Example of Address Mapping

[0061]

[0062] It should be noted that by using a uniform grouping method, it can be ensured that the bandwidth and storage capacity of each channel group are the same. Therefore, when performing address interleaving mapping, there is no need to worry about uneven processing pressure of address mapping due to different channel group capabilities.

[0063] In some alternative embodiments, multiple memory channels can be grouped according to bandwidth requirements.

[0064] In some optional embodiments, the multiple memory channels of the target system are uniformly grouped to obtain multiple channel groups, including: determining the number of grouped channels based on the acquired bandwidth requirement information, memory channel bandwidth information, and the total number of memory channels of the target system; and uniformly dividing the multiple memory channels of the target system into multiple channel groups according to the number of grouped channels. The bandwidth requirement information includes the first bandwidth requirement information corresponding to the upstream device of the target system and / or the second bandwidth requirement information of the target task to be executed. The memory channel bandwidth information is used to characterize the amount of data transmitted per unit time between the memory channel and the connected memory. The upstream device is equivalent to the supply end of the target system and can input data, control signals, etc., to the target system.

[0065] For example, the first bandwidth requirement information corresponding to the upstream device represents the minimum bandwidth required as B1, and the memory channel bandwidth information represents the bandwidth of each memory channel as b1. Based on this, combined with the total number of memory channels in the target system, the multiple memory channels of the target system can be divided into N1 channel groups, each channel group including M1 memory channels, and satisfying the following relationship: b1×M1≥B1.

[0066] For example, the second bandwidth requirement information of the target task represents the minimum bandwidth required as B2, and the memory channel bandwidth information represents the bandwidth of each memory channel as b1. Based on this, combined with the total number of memory channels of the target system, the multiple memory channels of the target system can be divided into N2 channel groups, each channel group including M2 memory channels, and satisfying the following relationship: b1×M2≥B2.

[0067] For example, the first bandwidth requirement information corresponding to the upstream device represents its minimum required bandwidth as B1, the second bandwidth requirement information of the target task represents its minimum required bandwidth as B2, and the memory channel bandwidth information represents the bandwidth of each memory channel as b1. Based on this, combined with the total number of memory channels in the target system, the multiple memory channels of the target system can be divided into N3 channel groups, each channel group including M3 memory channels, and satisfying the following relationship: b1×M3≥max(B1,B2), where max(B1,B2) represents the maximum value among B1 and B2. In this way, it can be ensured that the current channel grouping method can simultaneously meet the first bandwidth requirement and the second bandwidth requirement.

[0068] Therefore, it can be seen that the bandwidth service capacity of the channel groups corresponding to the number of grouped channels determined by the bandwidth requirement information, memory channel bandwidth information, and the total number of memory channels in the target system can meet the bandwidth requirements while achieving uniform grouping. In other words, this grouping method ensures that each channel group can meet the bandwidth requirements, and that the bandwidth requirements will not be unmet due to memory channel grouping, thus not affecting data storage efficiency.

[0069] After obtaining multiple channel groups, the target access address can be interleaved and mapped on a channel group basis to obtain the memory address corresponding to the target access address. "Channel group as unit" means that only one channel group needs to participate in the interleaving mapping at a time. After the memory space corresponding to that channel group has been completely interleaved and mapped, the process jumps to the next channel group, and the memory channels in the next channel group perform the interleaving mapping, and so on.

[0070] It should be noted that, apart from the memory channels in the channel groups currently participating in the interleaving mapping, the memory channels in other channel groups can enter a sleep state to reduce the power consumption of the target system.

[0071] Furthermore, compared to the related technologies in which all memory channels in the target system participate in interleaving mapping, in the embodiments of this disclosure, only one memory channel in a channel group participates in interleaving mapping at any given time. This allows the memory (or memory controller) connected to the memory channel participating in interleaving mapping to "see" more intensive memory access requests. Therefore, the memory (or memory controller) can coordinate these memory access requests, thereby better scheduling and executing these requests and effectively improving the memory access efficiency.

[0072] For example, for DRAM or its controller, if more requests are "seen" during scheduling, then addresses more favorable to DRAM access can be scheduled. For instance, in related technologies, DRAM receives only one request per unit time, preventing request backlog. Therefore, data processing is performed on a fixed basis for each request. In this application, due to the increased request density, request backlog can occur, allowing for more flexible scheduling, determining addresses more favorable to DRAM access, and improving bandwidth utilization.

[0073] In some optional embodiments, memory access requests can instruct the execution of data writing or data reading. The processing methods for these two types of memory access requests will be described in detail below.

[0074] In some optional embodiments, the memory access request includes a first memory access request for indicating the writing of data, the first memory access request corresponding to a first target access address; correspondingly, in response to the memory access request for the target system, determining the target channel group corresponding to the memory access request includes: in response to the first memory access request, determining the target channel group corresponding to the first memory access request from multiple channel groups based on a preset order, wherein the group storage space corresponding to the previous channel group of the target channel group is completely interleaved and mapped, and the group storage space corresponding to the next channel group of the target channel group has not yet been interleaved and mapped, the group storage space including the target storage space corresponding to multiple memory channels of the corresponding channel group; performing interleaving mapping on the target access address of the memory access request based on the memory channels in the target channel group to obtain the memory address corresponding to the target access address, including: determining the interleaving mapping start address corresponding to the target channel group, the interleaving mapping start address being adjacent to the previous interleaving mapping end address; according to the interleaving mapping start address, performing interleaving mapping on the first target access address based on at least one memory channel in the target channel group to obtain the memory address corresponding to the first target access address.

[0075] Therefore, since there are multiple channel groups in the target system, for the first target access address, it is necessary to select the channel group to be used this time, i.e., determine the target channel group. As mentioned above, the storage space corresponding to the previous channel group of the target channel group is completely interleaved and mapped, and there is no usable address space. The storage space of the next channel group is not yet occupied. This is how the target channel group can be determined. After determining the target channel group, since the target channel group may include multiple memory channels, it is also necessary to determine the start address of the current interleaving mapping. This start address is the address of the target storage space of a memory channel in the target channel group, usually adjacent to the end address of the previous interleaving mapping. Based on this, the first target access address can be interleaved and mapped using at least one memory channel in the target channel group, thereby obtaining the memory address corresponding to the first target access address.

[0076] by Figure 2 Let's take an example to illustrate this. If the end address of the previous interleaving mapping corresponds to the memory address 2 of the target memory space of memory channel 2 in channel group 1, then the target channel group to be interleaved and mapped this time can be determined to be channel group 1, and the start address of the interleaving mapping can be the memory address 2 of the target memory space of memory channel 3. Based on this, the interleaving mapping to the first target access address can be performed from the start address of the interleaving mapping.

[0077] By determining the target channel group and performing interleaving mapping based on the starting address of the interleaving mapping, orderly and accurate address mapping can be achieved, reducing fragmented addresses and thus improving address utilization.

[0078] In some optional embodiments, address interleaving mapping can be performed according to a preset interleaving granularity. The interleaving granularity is the unit that determines the mapping from logical address to physical address (i.e., memory address). This disclosure does not limit the size of the interleaving granularity.

[0079] In some optional embodiments, the target storage space includes multiple interleaving blocks, and the first target access address includes a first starting address and a first access length. Accordingly, based on the interleaving mapping start address, the first target access address is interleaved and mapped based on at least one memory channel in the target channel group to obtain a memory address corresponding to the first target access address. This includes: determining an access range based on the first starting address and the first access length; determining a first memory channel in the target channel group for interleaving and mapping the target access address based on the access range and the interleaving mapping start address, wherein the number of first memory channels is one or more; and mapping the first target access address to the interleaving block corresponding to the first memory channel based on the first memory channel to obtain a memory address corresponding to the first target access address.

[0080] Here, the first starting address represents the starting address of the logical address, and the first access length represents the length of the address to be accessed. Combining these two values ​​determines the corresponding access range. The first memory channel is the memory channel in the target channel group used to perform this address mapping. If the access range is small, only one memory channel may be needed to meet the data writing requirements; if the access range is large, multiple memory channels may be required to meet the data writing requirements.

[0081] In some optional embodiments, determining a first memory channel in the target channel group for interleaving mapping a first target access address based on the access range and the interleaving mapping start address includes: determining whether cross-channel access is required based on the access range and the interleaving mapping start address; if cross-channel access is not required, using the memory channel in the target channel group corresponding to the interleaving mapping start address as the first memory channel to perform interleaving mapping of the target access address based on the first memory channel; if cross-channel access is required, determining the required number of channels based on the access range and the interleaving mapping start address; determining multiple first memory channels based on the interleaving mapping start address and the required number of channels, thereby enabling the use of multiple first memory channels to perform interleaving mapping of the target access address.

[0082] Therefore, it can be seen that, firstly, based on the access address and the interleaving mapping start address, it is determined whether the memory channel corresponding to the interleaving mapping start address is sufficient to perform interleaving mapping on the first target access address. If it is sufficient, the memory channel can be used for interleaving mapping. If it is insufficient, cross-channel access is involved, that is, the aforementioned memory channel and at least one other memory channel need to be used together to complete this interleaving mapping.

[0083] In determining whether cross-channel access is required, the main consideration is whether the remaining mappable area in the current interleaving block can cover the access range. If it can cover the access range, cross-channel access is not required; otherwise, it is required.

[0084] In some optional embodiments, determining whether cross-channel access is required based on the access range and the interleaving mapping start address includes: determining the mappable area of ​​the interleaving block based on the location of the interleaving mapping start address within the interleaving block; determining that cross-channel access is not required if the mappable area is greater than or equal to the access range; and determining that cross-channel access is required if the mappable area is less than the access range.

[0085] Figure 3 This is a schematic diagram of an interleaving block provided in an embodiment of this disclosure. (Refer to...) Figure 3 It shows a portion of the interleaving blocks in the target storage space of memory channel P in a certain channel group, namely interleaving block N-1, interleaving block N and interleaving block N+1, and the size of each interleaving block is S.

[0086] In this process, the memory address corresponding to interleaving block N-1 is interleaved and mapped. The memory address in the shaded area above the dashed line in interleaving block N (corresponding to S1) is interleaved and mapped. The memory address in the blank area below the dashed line (corresponding to S2) is not interleaved and mapped. The memory address corresponding to interleaving block N+1 is not interleaved and mapped. That is, the dashed line in interleaving block N is the boundary between the end address of the previous interleaving mapping and the start address of the current interleaving mapping. Therefore, only the address space of S2 in interleaving block N can be interleaved and mapped, that is, the mapped area is S2.

[0087] During this interleaving mapping, if the access range is less than or equal to S2, the memory channel P can perform address interleaving mapping starting from the interleaving mapping start address to obtain the memory address corresponding to the access range. Conversely, if the access range is greater than or equal to S2, cross-channel access is required. Assuming the access range is A, A can be split into A1 and A2, with the size of A1 corresponding to S2. Based on this, memory channel P can be used to interleave A1 within S2 of interleaving block N. For the remaining access range A2, if its size is less than or equal to S, A2 can be interleaved within interleaving block N in the next memory channel P+1 adjacent to memory channel P in this channel group. If A2 is greater than S, A2 can be further split into A21 and A22 in the aforementioned manner, with the size of A21 corresponding to S. Then, A21 is first interleaved within interleaving block N in memory channel P+1, and then the remaining access range A22 is interleaved in a similar manner. This will not be described in detail here.

[0088] It should be noted that, in order to simplify the operation during interleaving mapping, if the remaining mappable area in the current interleaving block is small after this interleaving mapping, a preset value (such as 0) can be used to fill this part of the mappable area to reduce cross-channel access.

[0089] Figure 4 This is a schematic diagram of a channel grouping method provided in an embodiment of this disclosure. (Refer to...) Figure 4 The channel group includes two memory channels, namely memory channel 1 and memory channel 2. The target storage space corresponding to each memory channel includes 5 interleaving blocks. The size of each interleaving block is S. That is, the target storage space corresponding to memory channel 1 corresponds to interleaving blocks 10, 11, 12, 13 and 14, and the target storage space corresponding to memory channel 2 corresponds to interleaving blocks 20, 21, 22, 23 and 24.

[0090] Through the preceding interleaving mapping, the S1 region in interleaving blocks 10, 11, and 12 of memory channel 1 has been interleaved and mapped, as have interleaving blocks 20 and 21 of memory channel 2 (the areas already interleaved and mapped correspond to the light-shaded areas in the diagram); the S2 region in interleaving block 12 is the remaining mappable region. Based on this, when a new memory access request is received, the channel group is determined to be the target channel group, and the starting address for interleaving mapping shown in the diagram is determined. Further, if the coverage area corresponding to the target access address is S2+S, since the coverage area is larger than the S2 region, address mapping needs to be performed across channels. Based on this, firstly, interleaving mapping needs to be performed in the S2 region using memory channel 1, and then switching to memory channel 2, where memory channel 2 continues address interleaving mapping in interleaving block 22. Since the coverage area is S2+S, the mappable region S2 in interleaving block 12 and interleaving block 22 can meet the address mapping requirements for this time (the area for this interleaving mapping corresponds to the dark-shaded area in the diagram). In other words, when performing the next interleaving mapping, the starting address of interleaving block 13 is the new interleaving mapping starting address. The interleaving mapping process is similar and will not be described in detail here.

[0091] Figure 5 This is a schematic diagram of a channel grouping method provided in an embodiment of this disclosure. (Refer to...) Figure 5The channel group includes three memory channels: memory channel 1, memory channel 2, and memory channel 3. The target storage space corresponding to each memory channel includes 5 interleaving blocks. The size of each interleaving block is S. That is, the target storage space corresponding to memory channel 1 corresponds to interleaving blocks 10, 11, 12, 13, and 14; the target storage space corresponding to memory channel 2 corresponds to interleaving blocks 20, 21, 22, 23, and 24; and the target storage space corresponding to memory channel 3 corresponds to interleaving blocks 30, 31, 32, 33, and 34.

[0092] Through the preceding interleaving mapping, the S1 region in interleaving blocks 10, 11, and 12 of memory channel 1 has been interleaved and mapped; interleaving blocks 20 and 21 of memory channel 2 have also been interleaved and mapped; and interleaving blocks 30 and 31 of memory channel 3 have also been interleaved and mapped (the areas that have been interleaved and mapped correspond to the light-shaded areas in the figure); the S2 region in interleaving block 12 is the remaining mappable region. Based on this, when a new memory access request is received, the channel group is determined to be the target channel group, and the starting address for interleaving mapping shown in the figure is determined. Further, if the coverage area corresponding to the target access address is S2+S+S3, since the coverage area is larger than the S2 region, address mapping needs to be performed across channels. Based on this, memory channel 1 is first used to perform mapping in the S2 region. After completion, the process switches to memory channel 2, where memory channel 2 continues address mapping in interleaving block 22. After completion, the process switches to memory channel 3, where memory channel 3 continues address mapping in interleaving block 32, which will occupy the S3 region of interleaving block 32. Since the coverage area is S2+S+S3, the mappable region S2 in interleaving block 12, the region S3 in interleaving block 22, and the region S3 in interleaving block 32 can satisfy the address mapping requirements for this time (the region for this interleaving mapping corresponds to the dark shaded area in the figure). In other words, when performing the next interleaving mapping, the boundary between the region S3 and the region S4 in interleaving block 32 will be the new starting address for the interleaving mapping. The interleaving mapping process is similar and will not be described in detail here.

[0093] In some optional embodiments, the first memory access request further includes first target data to be written; correspondingly, the address mapping method further includes: storing the first target data into the corresponding memory according to the memory address corresponding to the first target access address. In other words, the first target data can be written into the storage space corresponding to the memory address.

[0094] In this way, accurate memory access operations can be achieved, writing data into the corresponding memory space, thereby mapping consecutive logical addresses to scattered physical memory blocks. This eliminates the need to modify logical addresses when accessing memory data, effectively improving memory access efficiency.

[0095] As discussed above, address interleaving mapping can be used to map logical addresses to physical addresses and enable data writing operations. Correspondingly, when needed, the corresponding data can be read from the memory.

[0096] In some optional embodiments, the memory access request includes a second memory access request for indicating data to be read, and the second memory access request corresponds to a second target access address; accordingly, the address mapping method further includes: determining a target memory address corresponding to the second target access address based on preset address mapping information, wherein the address mapping information is used to characterize the mapping relationship between the first target access address and the memory address; and reading the second target data from the corresponding memory according to the target memory address.

[0097] In other words, the address mapping information includes the mapping relationship between each logical address and the corresponding memory address. Therefore, it is possible to determine the corresponding memory address based on the address to be accessed in the memory access request, thereby enabling the reading operation of the corresponding data in the memory address.

[0098] For example, the second target data is written to the memory space corresponding to memory Addresses Addr1 to Addr3 via memory channel 1 through the first memory access request Q1 (i.e., memory addresses are Addr1 to Addr3). The first target access address of the first memory access request Q1 is LA1. When it is necessary to read the second target data, a second memory access request Q2 is sent, carrying the second target access address LA1. Based on this, the memory channel corresponding to LA1 can be determined as memory channel 1 according to the address mapping information, and the corresponding memory addresses are Addr1 to Addr3. Therefore, the second target data can be read from Addr1 to Addr3 through memory channel 1.

[0099] In summary, this method ensures that data in the memory is read correctly.

[0100] In some optional embodiments, multiple memory channels in the target channel group are in an active state, while multiple memory channels in channel groups other than the target channel group enter a sleep state when preset sleep conditions are met. These preset sleep conditions include the requirement that address interleaving mapping is not performed within a preset duration, such as not receiving an interleaving mapping instruction within the preset duration.

[0101] For example, each memory channel corresponds to a memory controller, which can detect whether the corresponding memory channel needs to perform address interleaving mapping. If no address interleaving mapping is detected for a long time, the memory controller can control the memory channel to enter a sleep state.

[0102] For example, multiple memories correspond to one memory controller. The memory controller can detect whether the corresponding multiple memory channels need to perform address interleaving mapping. For any memory channel, if no address interleaving mapping is detected for a long time, the memory controller can control the memory channel to enter a sleep state, while other memory channels can work normally.

[0103] Therefore, by grouping memory channels, the memory channels in the target channel group can be configured to be active, while the memory channels in the remaining channel group can be configured to be in a dormant state because they do not need or do not need to perform address interleaving mapping at present. This results in lower power consumption for most memory channels, thereby effectively reducing the overall power consumption of the target system.

[0104] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0105] In addition, this disclosure also provides address mapping apparatus, electronic devices, and computer-readable storage media, all of which can be used to implement any of the address mapping methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding descriptions in the method section, and will not be repeated here.

[0106] Figure 6 This is a schematic diagram of the composition structure of an address mapping device provided in an embodiment of the present disclosure.

[0107] Reference Figure 6 This disclosure provides an address mapping device 600, which may include the following modules.

[0108] The determination module 601 is used to determine the target channel group corresponding to the memory access request in response to the memory access request of the target system. The target channel group is at least one of multiple channel groups corresponding to the target system, and each channel group includes multiple memory channels.

[0109] The mapping module 602 is used to perform interleaving mapping on the target access address of the memory access request based on the memory channel within the target channel group, so as to obtain the memory address corresponding to the target access address.

[0110] In this embodiment, since the target system's multiple memory channels are divided into multiple channel groups, and interleaving mapping is performed on a channel group basis, only the memory channels in one channel group are needed to meet the address mapping requirements at any given time. This eliminates the need for all memory channels to participate in the interleaving mapping, thereby reducing system power consumption. For example, if the target system includes N channel groups, and each channel group includes M memory channels, the processing method of this embodiment ensures that the M memory channels can meet the bandwidth requirements, while also reducing power consumption to 1 / N of the original. Furthermore, compared to all memory channels participating in the interleaving mapping, this embodiment only requires memory channels in one channel group to participate in the interleaving mapping at any given time. This allows the memory to "see" more intensive memory access requests, facilitating the coordination of these requests and enabling better scheduling and execution of these requests, effectively improving memory access efficiency.

[0111] Each module in the aforementioned address mapping device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0112] Figure 7 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure.

[0113] Reference Figure 7 This disclosure provides an electronic device, which includes: at least one processor 701, at least one memory 702, and one or more I / O interfaces 703; wherein the memory 702 stores one or more computer programs that can be executed by at least one processor 701, and the one or more computer programs are executed by at least one processor 701 to enable at least one processor 701 to perform the address mapping method described above.

[0114] Figure 8 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure.

[0115] Reference Figure 8 This disclosure provides an electronic device that includes multiple processing cores 801 and an on-chip network 802. The multiple processing cores 801 are all connected to the on-chip network 802, which is used to exchange data between the multiple processing cores and external data.

[0116] One or more processing cores 801 store one or more instructions, which are executed by one or more processing cores 801 to enable one or more processing cores 801 to perform the address mapping method described in any of the embodiments of this disclosure.

[0117] The modules in the aforementioned electronic devices can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0118] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the address mapping method described above. The computer-readable storage medium may be volatile or non-volatile.

[0119] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the above-described address mapping method.

[0120] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0121] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0122] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0123] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0124] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0125] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0126] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0127] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0129] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. An address mapping method, characterized in that, include: In response to a memory access request to the target system, a target channel group corresponding to the memory access request is determined. The target channel group is at least one of a plurality of channel groups corresponding to the target system, and each channel group includes a plurality of memory channels. Based on the memory channels within the target channel group, the target access address of the memory access request is interleaved and mapped to obtain the memory address corresponding to the target access address; Among them, multiple memory channels in the target channel group are in an active state, while multiple memory channels in channel groups other than the target channel group enter a hibernation state when preset hibernation conditions are met.

2. The method according to claim 1, characterized in that, Before determining the target channel group corresponding to the memory access request in response to the memory access request of the target system, the method further includes: The target system's multiple memory channels are divided into multiple channel groups.

3. The method according to claim 2, characterized in that, The step of dividing the multiple memory channels of the target system into multiple channel groups includes: The multiple memory channels of the target system are evenly grouped to obtain multiple channel groups. Each channel group has the same number of channels, and the number of channels in each group is the number of memory channels included in the channel group.

4. The method according to claim 3, characterized in that, The step of uniformly grouping multiple memory channels of the target system to obtain multiple channel groups includes: The number of packet channels is determined based on the obtained bandwidth requirement information, memory channel bandwidth information, and the total number of memory channels in the target system. Based on the number of grouped channels, the multiple memory channels of the target system are evenly divided into multiple channel groups; The bandwidth requirement information includes the first bandwidth requirement information corresponding to the upstream device of the target system and / or the second bandwidth requirement information of the target task to be executed. The memory channel bandwidth information is used to characterize the amount of data transmitted per unit time between the memory channel and the connected memory.

5. The method according to any one of claims 1 to 4, characterized in that, The memory access request includes a first memory access request for instructing the writing of data, the first memory access request corresponding to a first target access address; The step of determining the target channel group corresponding to the memory access request in response to the memory access request of the target system includes: In response to the first memory access request, a target channel group corresponding to the first memory access request is determined from a plurality of channel groups based on a preset order. The group storage space corresponding to the previous channel group of the target channel group is completely interleaved and mapped, and the group storage space corresponding to the next channel group of the target channel group has not yet been interleaved and mapped. The group storage space includes the target storage space corresponding to a plurality of memory channels of the corresponding channel group. The step of interleaving and mapping the target access address of the memory access request based on the memory channel within the target channel group to obtain the memory address corresponding to the target access address includes: Determine the start address of the interleaving mapping corresponding to the target channel group, wherein the start address of the interleaving mapping is adjacent to the end address of the previous interleaving mapping; Based on the interleaving mapping start address, the first target access address is interleaved and mapped according to at least one memory channel in the target channel group to obtain the memory address corresponding to the first target access address.

6. The method according to claim 5, characterized in that, The target storage space includes multiple interleaving blocks, and the first target access address includes a first starting address and a first access length; The step of performing interleaving mapping on the first target access address based on at least one memory channel in the target channel group according to the interleaving mapping start address to obtain the memory address corresponding to the first target access address includes: The access range is determined based on the first starting address and the first access length; Based on the access range and the interleaving mapping start address, a first memory channel in the target channel group is determined for interleaving mapping the target access address, and the number of the first memory channels is one or more. Based on the first memory channel, the first target access address is mapped to the interleaving block corresponding to the first memory channel to obtain the memory address corresponding to the first target access address.

7. The method according to claim 6, characterized in that, The step of determining the first memory channel in the target channel group for interleaving the first target access address based on the access range and the interleaving mapping start address includes: Based on the access range and the interleaving mapping start address, determine whether cross-channel access is required; In cases where cross-channel access is not required, the memory channel in the target channel group corresponding to the interleaving mapping start address is used as the first memory channel; In cases where cross-channel access is required, the number of channels needed is determined based on the access range and the interleaving mapping start address; Multiple first memory channels are determined based on the interleaving mapping start address and the required number of channels.

8. The method according to claim 7, characterized in that, The step of determining whether cross-channel access is required based on the access range and the interleaving mapping start address includes: Based on the position of the interleaving mapping start address within the interleaving block, determine the mappable region of the interleaving block; If the mappable area is greater than or equal to the access range, it is determined that cross-channel access is not required; If the mappable area is smaller than the access range, it is determined that cross-channel access is required.

9. The method according to claim 5, characterized in that, The first memory access request also includes the first target data to be written; The method further includes: The first target data is stored in the corresponding memory according to the memory address corresponding to the first target access address.

10. The method according to claim 5, characterized in that, The memory access request also includes a second memory access request for instructing the reading of data, and the second memory access request corresponds to a second target access address; The method further includes: Based on preset address mapping information, a target memory address corresponding to the second target access address is determined, wherein the address mapping information is used to characterize the mapping relationship between the first target access address and the memory address; The second target data is read from the corresponding memory according to the target memory address.

11. An address mapping device, characterized in that, include: The determination module is configured to determine, in response to a memory access request for the target system, a target channel group corresponding to the memory access request, wherein the target channel group is at least one of a plurality of channel groups corresponding to the target system, and each channel group includes a plurality of memory channels; The mapping module is used to perform interleaving mapping on the target access address of the memory access request based on the memory channel within the target channel group, so as to obtain the memory address corresponding to the target access address; Among them, multiple memory channels in the target channel group are in an active state, while multiple memory channels in channel groups other than the target channel group enter a hibernation state when preset hibernation conditions are met.

12. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the address mapping method as described in any one of claims 1-10.

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