A method, product, device and medium for reading and writing hard disk data.

Abstract

This application discloses a hard disk data read / write method, product, device, and medium, relating to the field of computer technology. The method includes: reading and parsing read data commands generated by the host from the solid-state drive's (SSD) submission queue to obtain read command data; reading a flash translation layer mapping table from a first cache partition of random access memory (RAM) to determine the physical block address corresponding to the logical block start address in the read command data; reading target data corresponding to the physical block address from the flash memory according to the data length in the read command data, and writing the target data to a second cache partition of the memory. This application uses a programmable logic device (PLD) board as extended memory for the host. The board has two partitions: one for storing the flash translation layer mapping table and the other for storing the data to be read / written. This reduces the SSD's dependence on host memory and improves data read / write efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a hard disk data reading and writing method, product, device and medium. Background Technology

[0002] Currently, multiple SSDs (Solid State Drives) are typically connected to the host computer using HMB (Host Memory Buffer) technology and a PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard). After the SSD is powered on, the controller requests HMB space from the host via NVMe (Non-Volatile Memory Express) commands (such as the SetFeatures command). Once the host allocates the corresponding memory space, the SSD loads the complete FTL (Flash Translation Layer) mapping table from its NAND flash memory (i.e., non-volatile flash memory) into the allocated HMB space. During runtime, updates to the FTL mapping table (such as the L2P table) are performed directly in the HMB space and synchronized back to the NAND flash memory via a background mechanism (to prevent data loss in case of power failure). After this initialization process, the host program can then perform read and write operations on the SSD based on the NVMe protocol. However, connecting SSDs based on HMB technology will consume host memory, and when there are many SSDs, it will seriously increase the burden on host memory, thus affecting SSD read and write operations. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a hard disk data read / write method, product, device, and medium. By using the random access memory (RAM) in the FPGA board as extended memory of the host, the dependence of the solid-state drive (SSD) on the host memory can be reduced, and it does not occupy the host's memory resources. Furthermore, by using the RAM as a cache, the efficiency of data reading can be effectively improved. The specific solution is as follows:

[0004] In a first aspect, this application discloses a hard disk data read / write method, applied to a solid-state drive controller, comprising:

[0005] Read and parse the read data command generated by the host from the submission queue of the target solid-state drive to obtain the read command data; the read command data includes the data length and the logical block start address;

[0006] The flash translation layer mapping table corresponding to the target solid-state drive is read from the first cache partition in the target random access memory. The target random access memory is located on a programmable logic device board that supports high-speed serial protocols. The host and the target solid-state drive and the programmable logic device board, as well as the target solid-state drive and the programmable logic device board, are connected through a peripheral component fast interconnect bus.

[0007] The first physical block address is determined from the flash translation layer mapping table; the first physical block address is the physical block address corresponding to the logical block start address in the read command data;

[0008] According to the data length in the read command data, the target data corresponding to the first physical block address is read from the flash memory in the target solid-state drive, and the target data is written to the second cache partition in the target random access memory to complete the data read operation for the target data.

[0009] Secondly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described hard disk data read / write methods.

[0010] Thirdly, this application discloses an electronic device, including a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the aforementioned hard disk data read / write method.

[0011] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned hard disk data read / write method.

[0012] In this application, a programmable logic device board (supporting high-speed serial protocols) interconnecting with the host and SSD is pre-created. Two partitions are set in the random access memory (RAM) of this board. The first partition stores the flash translation layer mapping table for data read / write operations on the SSD, and the second partition stores the data to be read / written during data read / write operations. Thus, when a data read operation is needed, the physical block address of the data to be read can be obtained by querying the flash translation layer mapping table recorded in the first partition. Then, the target data to be read is directly retrieved from the SSD's flash memory based on the physical block address and written to the second partition, thereby completing the data read operation. Through this method, when performing data read operations, there is no need to occupy host memory; instead, the RAM in the programmable logic device board is used as extended memory for the host. This reduces the SSD's dependence on host memory, does not consume host memory resources, and uses the RAM as a cache, effectively improving data read efficiency. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 This application discloses a flowchart of a hard disk data reading operation.

[0015] Figure 2 This is a schematic diagram of the hardware connection relationship of a specific hard disk data read / write system disclosed in this application;

[0016] Figure 3 This is a flowchart of a specific hard disk data writing operation disclosed in this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0018] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0019] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] This application discloses a hard disk data reading method, applied to a solid-state drive controller. See [link to relevant documentation]. Figure 1 As shown, the method includes:

[0021] Step S11: Read and parse the read data command generated by the host from the submission queue of the target solid-state drive to obtain the read command data; the read command data includes the data length and the logical block start address.

[0022] It should be noted that the hard disk data reading scheme proposed in this application is applied to solid-state drive controllers (i.e., SSD controllers).

[0023] Understandably, when any user program (i.e., APP, application) on the host needs to perform data read / write operations (such as obtaining user data like images, files, and videos), it will send a corresponding read or write data request to the host. Upon receiving the request, the host will forward it to the corresponding SSD for the data read / write operation. Additionally, after startup, the host system will enumerate all NVMe devices (such as SSD0, SSD1, etc.) via PCIe and establish corresponding management queues (Admin Queues).

[0024] Specifically, when a data read operation is required, the user program initiates a data read request through the `read()` system call, specifying information such as the target file descriptor, the buffer for receiving data, and the data read length. For example, an application might initiate a data read request by calling `read(fd, buf, 8192)` to read 8KB of target user data (i.e., `buf`) from a specified file. Upon receiving this data read request, the kernel layer forwards the request to the corresponding host file system (such as ext4 or Btrfs) via the VFS (Virtual File System). The host file system then converts the file offset into the logical block address (LBA) of the NVMe SSD based on the file's inode information and block mapping table. Simultaneously, it generates a `bio` (Block Input Output, a core data structure of the Linux kernel's general block layer) structure (containing key information such as the LBA start address, data read length, and the physical address of the host's data receiving buffer). Furthermore, the bio structure is sorted and optimized by a block-level I / O (Input / Output) scheduler (such as mq-deadline, bfq) (e.g., prioritizing the processing order of read requests). The optimized bio structure is then sent to the NVMe driver on the host side. The NVMe driver then converts the bio structure into an NVMe read command (e.g., Opcode=0x02) and fills the command structure with the LBA start address, data read length, and PRP (Physical Region Page) list (pointing to the buffer that receives data from the host). The generated read data command is then written to the SSD's Submission Queue (SQ) via the PCIe bus, and the doorbell register is updated to notify the SSD controller that there is a new command to be processed.

[0025] In this embodiment, when the SSD controller detects that a new command is written in the commit queue (i.e., SQ) of any SSD, it reads the newly written read data command from the corresponding SSD's commit queue (i.e., SQ) and parses the command to obtain read command data containing the data length and logical block start address (i.e., LBA start address).

[0026] In one specific implementation, the read data command generated by the host is read and parsed from the commit queue of the target SSD to obtain read command data. Specifically, this may include: when a new command is detected being written to the commit queue of the target SSD through a preset queue monitoring mechanism, the read data command to be processed is read from the commit queue of the target SSD through direct memory access, and the read data command is saved to the internal register of the target SSD; the read data command in the internal register is parsed to obtain read command data. In this embodiment, the SSD controller can discover new commands in the SQ through a hardware-level queue monitoring mechanism and trigger a direct memory access (DMA) operation to read the read data command to be processed from the SSD's SQ through direct memory access, and read the command into the internal register group; then, the read data command in the register group is parsed to obtain read command data containing data length, LBA start address, and physical region page list (i.e., PRP list).

[0027] Step S12: Read the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory; the target random access memory is located on a programmable logic device board that supports high-speed serial protocols, and the host and the target solid-state drive and the programmable logic device board, as well as the target solid-state drive and the programmable logic device board, are connected through a peripheral component fast interconnect bus.

[0028] It should be noted that, see Figure 2As shown, this application pre-creates a programmable logic device board, such as an FPGA (Field-Programmable Gate Array) board, and creates two partitions in the DRAM (Dynamic Random Access Memory) of the board, namely a first cache partition and a second cache partition; wherein the first cache partition is used to store the flash translation layer mapping table (i.e., FTL mapping table), and the second cache partition serves as the cache area of ​​the SSD to store data to be read and written. Furthermore, this FPGA board supports the high-speed serial protocol (ComputeExpress Link, CXL), enabling the expansion of host memory based on CXL TYPE3 mode. Connecting to the host via the PCIe bus, this board can function as extended host memory (i.e., a buffer for host data reception). Additionally, the SSD connects to the host and the FPGA board via the PCIe bus. The host program can perform read and write operations on the SSD based on the NVMe protocol. The SSD can interact with the FPGA board using PCIe's PTP mode, reading and writing cached data on the extended memory (i.e., the second cache partition) on the FPGA, and then synchronizing data with the Nand-flash memory in the SSD. It should be noted that data transfer between the second cache partition and the user program can be performed via the CXL.mem protocol (a protocol providing low-latency direct communication between the host and memory).

[0029] The FTL (File Transfer Table) acts as the "address translator" for SSDs. By recording the mapping relationship between logical addresses and physical addresses, it overcomes the physical limitations of NAND flash memory (such as non-overwrite and block-by-block erasure), while maintaining the ease of use of the SSD for the host. Its dynamically updated mapping relationship supports core operations such as data writing, updating, reading, and garbage collection, and is a key guarantee for the high performance and high reliability of SSDs.

[0030] Specifically, the host can set the address of the data content to be read (buf) to the corresponding location of the extended memory area of ​​the DRAM of the FPGA board (i.e., the location of the second cache partition). Furthermore, each SSD has its own independent space area in the DRAM of the FPGA board, thereby quickly realizing data read and write operations for each SSD.

[0031] In this embodiment, after parsing the read command data from the submission queue of the target solid-state drive, the FTL mapping table corresponding to the target solid-state drive (such as SSD1) can be directly read from the first cache partition of the target random access memory (such as DRAM) of the FPGA board.

[0032] Specifically, reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory can include: determining whether the range corresponding to the logical block start address in the read command data is within the total capacity of the target solid-state drive; if the range corresponding to the logical block start address is within the total capacity of the target solid-state drive, then determining whether the data length in the read command data meets the page read alignment requirements of the flash memory in the target solid-state drive; if the data length meets the page read alignment requirements of the flash memory in the target solid-state drive, then verifying the validity of the physical region page list in the read command data and obtaining the verification result; if the verification result shows that the verification is successful, then reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory. In this embodiment, the LBA range corresponding to the LBA start address is first checked to see if it is within the total capacity of SSD1. If it is, the length of the data in the read command data is further checked to see if it meets the page read alignment requirements of the Nand-flash memory, such as 4KB / 16KB. If it does, the validity of the PRP list is checked, such as whether the host buffer address (i.e., the two cache partitions) is accessible. If it is accessible, the validity of the read data command is verified, and the FTL mapping table corresponding to SSD1 can be read from the first cache partition in DRAM. By verifying the information in the read command data through a multi-verification mechanism, the validity of the read data command can be ensured, thus laying the foundation for the smooth execution of subsequent hard disk data write operations.

[0033] Furthermore, after successful verification, the SSD controller allocates internal resources (such as command ID (IdentityDocument, unique code), data transfer channel, etc.) to the command, preparing to execute address mapping and data reading operations.

[0034] In another specific implementation, it may further include: if the range corresponding to the logical block start address is not within the total capacity of the target solid-state drive, or the data length does not meet the page read alignment requirements of the flash memory in the target solid-state drive, or the verification result indicates that the verification failed, then a first completion queue entry containing an error code is generated; the first completion queue entry is written into the completion queue of the target solid-state drive. That is, if the verification fails, a completion queue entry (CQE) containing an error code (such as 0x02, invalid field) is generated, and the completion queue entry (i.e., CQE) is written into the completion queue (i.e., CQ) of SSD1 to inform the host that the command verification failed.

[0035] Specifically, reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory can include: determining whether a mapping entry corresponding to the logical block start address in the read command data exists in the first cache partition in the target random access memory; if a mapping entry corresponding to the logical block start address in the read command data exists in the first cache partition, then the flash translation layer mapping table corresponding to the target solid-state drive is read from the first cache partition in the target random access memory via a time synchronization network protocol. In this embodiment, if a hybrid FTL design is adopted, that is, part of the mapping table is stored in the NAND-flash memory of the SSD and the other part is stored in the first cache partition of the DRAM, then it can be first determined whether a mapping entry corresponding to the logical block start address (i.e., LBA start address) in the read command data exists in the first cache partition of the DRAM on the FPGA board. If it exists, then the FTL mapping table (such as the L2P table) corresponding to SSD1 is read from the first cache partition of the DRAM via a time synchronization network protocol (PTP, Precision Time Protocol).

[0036] In another specific implementation, if the mapping entry corresponding to the logical block start address (i.e., LBA start address) in the read command data is not hit in the first cache partition in DRAM, the corresponding mapping information can be read from the metadata area of ​​the NAND-flash memory and loaded into the first cache partition in DRAM so that it can be hit directly in subsequent accesses.

[0037] Step S13: Determine the first physical block address from the flash memory translation layer mapping table; the first physical block address is the physical block address corresponding to the logical block start address in the read command data.

[0038] In this embodiment, after obtaining the FTL mapping table (such as the FTL TABLE0 mapping table) corresponding to SSD1, the first physical block address (PBA) corresponding to the logical block start address (LBA start address) in the read command data can be located by querying the FTL mapping table. This PBA includes the physical block number, physical page number, and page offset. For example, the PBA corresponding to LBA=0x12345 may be block 0x20 and page 0x8.

[0039] Step S14: According to the data length in the read command data, read the target data corresponding to the first physical block address from the flash memory in the target solid-state drive, and write the target data into the second cache partition in the target random access memory to complete the data reading operation for the target data.

[0040] In this embodiment, after determining the first physical block address (PBA) corresponding to the logical block start address in the read command data, the target data corresponding to the first physical block address (PBA) can be read from the NAND-flash memory in SSD1 according to the data length recorded in the read command data, and then the read target data is written into the second cache partition in DRAM to complete the data reading operation.

[0041] It should be noted that the SSD controller and FPGA board can be connected via a PCIe bridge on the host, and the PCIe link needs to be trained (rate / width negotiation, such as PCIe 5.0 x16). Additionally, device enumeration is performed through the host Root Complex (RC) to obtain the BAR (Base Address Register) address ranges of the SSD controller and FPGA board (e.g., SSD controller's BAR0 is 0x1000000000-0x100007FFFF, FPGA board's BAR0 is 0x2000000000-0x200007FFFF). Next, the SSD controller maps the FPGA board's BAR address (e.g., 0x20000000000) to a locally accessible virtual address space; for example, in Linux, this is done using ioremap() to map physical addresses to kernel space.

[0042] Through the aforementioned hardware initialization and P2P (Peer-to-Peer) permission configuration operations, a data reading process based on the Time Synchronization Network Protocol (PTP) mode can be implemented. Specifically, a Memory Read TLP request can be constructed and sent through the SSD controller. For example, a Memory Read TLP request can be constructed through the DMA controller in the SSD controller, including:

[0043] Requester ID: BDF of the SSD controller (e.g., 0000:01:00.0);

[0044] Tag: A unique identifier (e.g., 0x0001);

[0045] Address: BAR address of the FPGA board (e.g., 0x2000000000);

[0046] Length: The length of the target data (e.g., 4KB).

[0047] Among them, BDF (Bus, Device, Function) is the device location identifier.

[0048] After constructing the above Memory Read TLP request, it can be sent to the host's PCIe bridge via the PCIe link. Then, the host's PCIe bridge determines whether the target address belongs to the address window of the FPGA board (e.g., 0x2000000000-0x200007FFFF). If so, it is forwarded to the FPGA board.

[0049] Next, when the FPGA board receives the aforementioned Memory Read TLP request, it parses it and reads the target data (e.g., 4KB at address 0x2000000000) from local memory (e.g., DDR5, Double Data Rate 5) and generates a Completion TLP (i.e., CplD, completion response) containing the target data. Specifically, the fields of the CplD may include:

[0050] Completer ID: BDF of EP2 (e.g., 0000:02:00.0);

[0051] Requester ID: BDF of EP1;

[0052] Tag: Consistent with the request TLP (0x0001);

[0053] Data Payload: Actual data (4KB).

[0054] The link layer ensures the integrity of TLP requests through LCRC (Link Cyclic Redundancy Check) verification and retransmission mechanisms (up to 3 times).

[0055] Furthermore, after the SSD controller receives the CPLD response, it performs an ECRC (End-to-End CRC) check and writes the target data to local memory (e.g., 0x1000000000). If the ECRC check fails or a timeout occurs without a response, a retry mechanism can be triggered or an error log can be logged.

[0056] In addition, after completing the transmission of the target data, the FPGA board can write a Completion Queue Entry (CQE) to the SSD controller's CQ (e.g., base address 0x1000001000) by sending a Memory Write TLP request to inform the host that the data transmission is complete. The Completion Queue Entry (CQE) can specifically include the command ID, status code (0x00 indicates success), and the actual number of bytes transmitted. Furthermore, the FPGA board can also notify the SSD controller of the transmission completion via the MSI-X interrupt mechanism, and then the SSD controller's driver will respond to the interrupt and verify data integrity.

[0057] Similarly, the data write process based on the Time Synchronization Network Protocol (PTP) mode also requires pre-configuration of address mapping and permissions. For example, the BAR address of the SSD controller is mapped to the BAR address of the FPGA board, and write permissions are enabled on EP2 (e.g., through configuration via registers within the FPGA board). After the above configuration, a Memory Write TLP request can be constructed and sent through the SSD controller. For example, a Memory Write TLP (Posted TLP, no completion required, i.e., no expectation of a response) request can be constructed through the DMA controller in the SSD controller, including:

[0058] Address: BAR address of the FPGA board (e.g., 0x2000000000);

[0059] Data Payload: Data to be written (e.g., 8KB);

[0060] Length: Data length (e.g., 8KB).

[0061] If the amount of data to be written exceeds MPS (Max Payload Size, which refers to the maximum amount of data a packet can carry), such as 256B for PCIe 5.0, then it needs to be sent in multiple TLP requests, and the order of sending should be ensured by sequence ID.

[0062] Next, when the FPGA board receives the aforementioned Memory Write TLP request, it parses it and converts the PCIe address into a local memory address (such as the physical address of DRAM). Then, the memory controller writes the data to be written to the corresponding address. If multiple TLP requests are sent, the data needs to be concatenated according to the sequence ID to obtain the data to be written. If an error occurs during the data writing process (such as address out of bounds), the FPGA board constructs an Error Completion TLP request and returns it to the SSD controller to indicate that an error has occurred.

[0063] In addition, the SSD controller can confirm successful writing in the following ways: if the FPGA board supports it, it can notify the write completion via an interrupt; or, it can initiate a "dummy read" request to verify whether the data written to the address is correct.

[0064] Specifically, reading the target data corresponding to the first physical block address from the flash memory in the target solid-state drive (SSD) according to the data length in the read command data can include: detecting whether there is user data marked as valid corresponding to the first physical block address in the flash memory of the target SSD; if there is user data marked as valid corresponding to the first physical block address in the flash memory of the target SSD, then reading the user data corresponding to the first physical block address from the flash memory according to the data length in the read command data to obtain the target data. In this embodiment, it is possible to first detect whether there is user data marked as valid corresponding to the first physical block address (PBA) in the NAND-flash memory of SSD1; if so, the user data marked as valid is read according to the data length in the read command data to obtain the target data.

[0065] In this embodiment, the system can also detect whether there is valid data for the corresponding physical page in the second cache partition of the DRAM based on the first physical block address (PBA) (high-frequency access data is cached in DRAM). For example, operating system kernel files and frequently used application data may reside in the cache space of DRAM for a long time. If it exists, the system directly reads the corresponding user data marked as valid from the second cache partition of the DRAM to obtain the target data, and sends the target data to the user program to complete the data read operation. Since the data access process of the NAND-flash memory is skipped, the read latency can be reduced to less than 10 microseconds (the access latency of DRAM is about 10-50 nanoseconds). It can be understood that the DRAM on the FPGA board acts as the host's extended memory. When data is found to be hit in the extended memory, the host program can directly access the data (i.e., the data in the second cache partition) without copying it to the host's local memory, thus achieving the effect of not occupying host memory.

[0066] In this embodiment, the method may further include: determining whether there is valid user data corresponding to the first physical block address in the second cache partition; if there is no valid user data corresponding to the first physical block address in the second cache partition, sending a read command containing the first physical block address to the flash memory controller to activate the target storage unit corresponding to the first physical block address, and obtaining the original user data corresponding to the first physical block address from the target storage unit; performing error detection on the original user data to obtain the detection result; if the detection result indicates that there is a bit error in the original user data, correcting the original user data using a preset decoding algorithm to obtain the corrected data; removing metadata of the free area from the corrected data to extract valid user data, and obtaining the data access type of the valid user data; if the data access type is a high-frequency access type, writing the valid user data into the second cache partition, and updating the flash translation layer mapping table in the first cache partition based on the write address of the valid user data. In this embodiment, it can first be determined whether there is valid user data corresponding to the first physical block address (PBA) in the second cache partition of the DRAM. If not, (i.e., a miss), a read command can be sent to the NAND flash controller, specifying the physical page address corresponding to the first physical block address (PBA). Then, the target memory cell corresponding to the first physical block address (PBA) is activated by the flash controller, and the charge state is read by the sensing circuit and converted into a digital signal to generate the original user data (containing metadata of the OOB (Out-Of-Band) area). Next, the original user data is verified by the hardware ECC (Error Checking and Correction) module. If there is a bit error (such as the 1-3 bit error commonly found in TLC flash memory), it is corrected by LDPC (Low-density parity-check) or BCH algorithm (Bose-Chaudhuri-Hocquenghem, an error correction algorithm) to obtain the error-corrected data. For example, LDPC code can correct more than 50 bits of error in every 512 bytes, thereby ensuring data integrity. Furthermore, the SSD controller extracts OOB metadata (such as page state markers, checksums, etc.) from the error-corrected data to obtain valid user data. If the valid user data is a high-frequency access type (such as access type with multiple consecutive reads), it is written to the second cache partition of DRAM and the cache index table (i.e., FTL mapping table) is updated for subsequent fast access.

[0067] In this embodiment, it may further include: if the error correction of the original user data fails, the corresponding physical page is marked as a bad page, and a new physical page is allocated from the spare block; the flash translation layer mapping table in the first cache partition is updated based on the second physical block address corresponding to the new physical page, and the relevant information of the bad block marked as a bad page is recorded in the bad block table of the flash memory.

[0068] In this embodiment, if error correction of the original user data fails during the data reading process (e.g., the number of error bits exceeds the correction capability), the corresponding physical page can be marked as a "bad page" and a remapping mechanism can be triggered. Specifically, a new physical page is allocated from the spare block, then the FTL mapping table is updated (the original LBA points to the new PBA), and bad block information is recorded in the bad block table of the NAND-flash memory (stored in the metadata area).

[0069] In addition, for transient errors (such as temporary charge fluctuations in NAND cells), the SSD controller will automatically retry the read operation (by default, 2-3 times). If the read still fails, a bad block remapping operation can be performed.

[0070] In this embodiment, the method may further include: counting the number of bad blocks marked as bad pages, obtaining the number of bad blocks, and determining whether the number of bad blocks exceeds a preset spare block threshold; if the number of bad blocks exceeds the preset spare block threshold, generating a second completion queue entry containing an error status code, and writing the second completion queue entry into the completion queue of the target solid-state drive. In this embodiment, if bad pages occur, the number of bad blocks can be counted for all bad blocks marked as bad pages, and then it can be determined whether the number of bad blocks exceeds the preset spare block threshold. If it does, a second completion queue entry (CQE) containing an error status code (such as 0x05, media error) can be generated, and then the second completion queue entry can be written into the completion queue (i.e., CQ) of SSD1. In this way, the host can know that there is a media error. Furthermore, the host driver can alert the user through dmesg (a command-line tool used to access the kernel ring buffer in Linux system) or the logging system.

[0071] Specifically, writing target data into the second cache partition in the target random access memory (RAM) can include: obtaining the physical address and length information of the second cache partition in the target RAM based on the physical region page list in the read command data; configuring data transfer parameters based on the physical address and length information; and writing the target data into the second cache partition according to the data transfer parameters. For example, the SSD controller can obtain the physical address and length information of the host memory receive buffer (i.e., the second cache partition in DRAM) based on the PRP list in the read command data, configure the transfer parameters of the PCIe DMA engine (such as transfer block size and address increment mode) based on the obtained physical address and length information, and then directly transfer the batch of target data marked as valid to the second cache partition through the configured PCIe DMA engine and the PCIe bus. It should be noted that no CPU (Central Processing Unit) intervention is required during the transfer process (zero-copy mechanism). If a PCIe 4.0 x4 channel is used, the transfer bandwidth can reach 8GB / s, which can ensure high speed when reading large files.

[0072] It should be noted that the process of writing the target data into the second cache partition of the target random access memory may also include: detecting errors in the transmission process of the target data through the peripheral component fast interconnect transaction layer in the peripheral component fast interconnect bus; if a data transmission error is detected, the target data is retransmitted through the link layer in the peripheral component fast interconnect bus according to a preset retransmission mechanism. In this embodiment, transmission integrity verification can be performed during the data writing process to the cache partition. Specifically, errors in data transmission can be detected through the PCIe transaction layer using the CRC (Cyclic Redundancy Check) algorithm, and when a blade error is detected, retransmission is performed through the link layer based on the ACK / NACK mechanism (a communication protocol that confirms whether the data has been successfully received through a response), thereby ensuring that the data accurately reaches the second cache partition.

[0073] Furthermore, after writing the target data into the second cache partition in the target random access memory, the process may further include: generating a third completion queue entry containing a success status code and writing the third completion queue entry into the completion queue of the target solid-state drive; and sending an interrupt signal to the host through a preset interrupt mechanism to inform the host that the read data command has been executed. In this embodiment, after the data transmission is completed, a completion queue entry (CQE) can be generated, containing information such as the command ID, the number of bytes read, and the success status code (0x00), and the completion queue entry (CQE) can be written into the completion queue (CQ) to inform the host that the data transmission has been completed.

[0074] Specifically, an interrupt signal can be sent to the host via the MSI-X interrupt vector to indicate that command execution has completed. Furthermore, NVMe SSDs supporting multiple queues can allocate independent interrupts to different applications, thereby reducing interrupt conflicts. The host's NVMe driver responds to the interrupt, reads and parses the CQE from the Completion Queue (CQ), and then passes the read result back to the user program through the block layer, file system, and VFS. Additionally, the `read()` system call can return the actual number of bytes read (e.g., 8192), allowing the user program to directly obtain the target data from the buffer (secondary cache partition).

[0075] Furthermore, since the NVMe protocol supports up to 65,535 independent SQ / CQ queues, the SSD controller can simultaneously handle read requests from different queues (such as application queues, system queues, etc.). For example, database query requests and video stream read requests can be assigned to different queues to avoid mutual blocking. For the above-mentioned multi-queue parallel processing scenario, QoS (Quality of Service) priority scheduling strategies can be used to ensure the response speed of critical services. Specifically, read data requests can be scheduled based on queue priority flags (such as the Priority field in NVMe), allowing high-priority requests (such as real-time transaction data read requests) to preferentially utilize NAND and PCIe resources, thereby ensuring the response speed of critical services. For example, a request with priority 0 can receive 90% of the bandwidth allocation, while a request with priority 7 only receives 10%.

[0076] In this embodiment, the SSD controller can also trigger a pre-read mechanism based on the host read request pattern (such as sequential reads). For example, when it detects that data LBA=0x1000-0x100F needs to be read continuously, it can automatically read data LBA=0x1010-0x101F in advance and cache it in the second cache partition of DRAM, thereby reducing the latency of subsequent read data requests. In addition, when the DRAM cache space is insufficient, the SSD controller can also use algorithms such as LRU (Least Recently Used) or LFU (Least Frequently Used) to evict cold data. For example, cache pages that have not been accessed for more than 30 minutes can be marked as invalid to free up space for new data.

[0077] As can be seen, this embodiment pre-creates a programmable logic device board (supporting high-speed serial protocols) interconnecting with the host and SSD. Two partitions are set in the random access memory (RAM) of this board. The first partition stores the flash translation layer mapping table for SSD data read / write operations, and the second partition stores the data to be read / written during data read / write operations. Thus, when a data read operation is needed, the physical block address of the data to be read can be obtained by querying the flash translation layer mapping table recorded in the first partition. Then, the target data to be read is directly retrieved from the SSD's flash memory based on the physical block address and written to the second partition, thereby completing the data read operation. Through this method, when performing data read operations, there is no need to occupy host memory; instead, the RAM in the programmable logic device board is used as extended memory for the host. This reduces the SSD's dependence on host memory, does not consume host memory resources, and uses the RAM as a cache, effectively improving data read efficiency.

[0078] This application discloses a specific hard disk data writing method, applied to a solid-state drive controller. See [link to relevant documentation]. Figure 3 As shown, the method includes:

[0079] Step S21: Read and parse the write data command generated by the host from the commit queue of the target solid-state drive to obtain the write command data; the write command data includes the data length, logical block start address and physical region page list.

[0080] It should be noted that the hard disk data writing scheme proposed in this application is applied to solid-state drive controllers (i.e., SSD controllers).

[0081] It should be noted that, see Figure 2As shown, the host pre-sets the address of the data content (buf) to be written to the corresponding location in the extended memory area of ​​the FPGA board's DRAM (i.e., the location of the second cache partition). Furthermore, each SSD has its own independent space area in the FPGA board's DRAM. Specifically, when a write operation is needed, the user program initiates a write data request through the write() system call, specifying the target file descriptor, the buffer for writing data, and the data read length. For example, the application calls write(fd, buf, 4096) to initiate a write data request to write 4KB of data to a file. Then, after receiving the write data request, the kernel layer forwards the request to the corresponding host file system (such as ext4 or Btrfs) through the VFS. The host file system then converts the file offset into the logical block address (LBA) of the NVMe SSD based on the file's inode (index node) block mapping relationship, and simultaneously generates a bio structure (containing key information such as the LBA start address, data write length, and the physical address of the host's data receiving buffer). Furthermore, the bio structure is optimized by merging / sorting through a block-level I / O scheduler (such as mq-deadline or kyber) to reduce random write fragmentation. The optimized bio structure is then sent to the NVMe driver on the host side. The NVMe driver converts the bio structure into an NVMe write command (such as Opcode=0x01) and fills the LBA start address, data write length, and PRP list (pointing to the host's data receiving buffer) in the command structure. The generated write data command is then written to the SSD's commit queue (SQ) through the PCIe bus, and the doorbell register is updated to notify the SSD controller that there is a new command to be processed.

[0082] In this embodiment, when the SSD controller detects a new command being written in the SSD's commit queue (SQ) through a hardware queue mechanism, it reads the newly written write data command from the SSD's commit queue (SQ) into an internal register via DMA, and parses the write data command in the internal register to obtain write command data containing the data length (referring to the write data length), the logical block start address (i.e., the LBA start address), and the PRP list.

[0083] Furthermore, the write command data can be validated for validity. For example, it can be checked whether the range corresponding to the LBA start address exceeds the total capacity of the SSD, whether the data length meets the NAND page alignment requirements (e.g., 4KB / 8KB), and the validity of the PRP list (whether the address is within the memory range accessible to the host). If the validation fails, a completion queue entry (CQE) with an error status is directly generated and written to the completion queue (CQ). If the validation passes, internal resources (such as command ID and DRAM cache buffer) can be allocated for the command to prepare for receiving the data to be written from the host.

[0084] Step S22: Read the data to be written from the second cache partition in the target random access memory according to the physical region page list in the write command data.

[0085] In this embodiment, the data to be written can be read from the second cache partition in the target random access memory (such as SSD1) according to the PRP list in the write command data.

[0086] For hard drive data write requests, the SSD controller first uses the PCIe DMA engine to read the user data to be written in batches from the host memory to the second cache partition of the FPGA board's DRAM, based on the host memory address in the PRP list. During data transmission, the PCIe link layer uses DLLPs (Data Link Layer Packets) for error detection and retransmission to ensure data integrity. It should be noted that when data is written to a designated cache area located in the second cache partition of the DRAM (usually stored contiguously in LBA format to optimize subsequent data writes to flash memory), the data is in a temporary storage state, relying on a power loss protection mechanism (PLP) for safety. For example, 1GB of DRAM cache can temporarily store approximately 2.62 million 4KB data blocks.

[0087] Step S23: Based on the data length and logical block start address in the write command data, allocate the corresponding flash physical address for the data to be written in the flash translation layer mapping table of the first cache partition.

[0088] In this embodiment, based on the data length and LBA start address in the write command data, the corresponding flash physical address is allocated for the data to be written in the FTL mapping table (such as the L2P table) of the first cache partition in the DRAM of the FPGA board, that is, a new physical page address (i.e., PBA) is allocated. If the newly allocated flash physical address (i.e., PBA) is the first write, it can be directly associated with a free physical page (i.e., establish a mapping between LBA and PBA); if it is an existing LBA (i.e., overwrite write), the old physical page address (i.e., PBA) can be marked as "invalid".

[0089] Additionally, metadata for this write operation can be recorded in DRAM, including the mapping relationship between LBA and PBA, data verification information (such as ECC pre-calculated values), and write timestamps (used for cache eviction policies). Simultaneously, wear leveling statistics are updated, and the number of erase / write operations for the corresponding physical blocks is recorded.

[0090] After the data to be written is cached in DRAM and the FTL mapping table is updated, a Completion Queue Entry (CQE) containing the command ID and a success status code (0x00) is generated and written to the Completion Queue (CQ). Then, an interrupt signal is sent to the host via the MSI-X interrupt mechanism to inform the host that the caching and update operations are complete. Next, the host's NVMe driver responds to the interrupt, reads the CQE from the CQ, and confirms successful caching and update. Further, the NVMe driver relays the "write complete" status through the block layer, file system, and VFS, and returns the actual number of bytes written (e.g., 4096) via the user program's write() call, before releasing the application from blocking and waiting.

[0091] Step S24: Write the data to be written to the flash memory of the target solid-state drive according to the flash physical address to complete the data writing operation for the data to be written.

[0092] In this embodiment, the data to be written is written to the Nand-flash memory of the target solid-state drive (SSD1) according to the newly allocated flash physical address (i.e., PBA), thereby completing the data writing operation.

[0093] In this embodiment, writing the data to be written to the flash memory of the target solid-state drive (SSD) according to the flash physical address can specifically include: when a preset trigger condition is met, persistently storing the data in the second cache partition of the target random access memory (RAM) to the flash memory of the target SSD according to the flash physical address; wherein, the preset trigger condition is any one of the following: the utilization rate of the target RAM reaches a preset utilization threshold, a forced data persistence command is detected from the host, or a preset data refresh cycle is reached. In this embodiment, when the preset trigger condition is met, a background refresh operation can be initiated through the SSD controller. For example, when the utilization rate of the first cache partition and / or the second cache partition in the DRAM reaches a preset threshold (e.g., 80%), or when a FLUSH command (forced data persistence command) is detected from the host, or when a preset timed refresh cycle (e.g., every 5 seconds) is reached, the background persistently stores the data to be written cached in the second cache partition of the DRAM to the Nand-flash memory.

[0094] Specifically, in the process of writing the data to be written cached in the second cache partition to the Nand-flash memory, it can be batched according to the NAND block size (such as 128KB / 256KB), thereby reducing the number of NAND writes (the NAND block erase / write unit is much larger than the page write unit).

[0095] Additionally, during the data writing process to the Nand-flash memory, a checksum (such as an LDPC code, which supports correcting 60 bits of error every 512 bytes) can be generated by a hardware ECC encoder. This checksum is then merged with the valid data to be written and written into the physical page of the Nand-flash memory. Simultaneously, additional metadata (such as page status markers, logical page numbers, etc.) is written to the OOB area.

[0096] In one specific implementation, when the SSD controller receives a Flush command initiated by the host, for example when an application calls fsync() or fdatasync(), the kernel sends an NVMe Flush command (Opcode=0x04) to the SSD controller, requesting that all cached data in the second cache partition be forcibly written to the NAND-flash memory. Then, upon receiving the NVMe Flush command (Opcode=0x04), the SSD controller suspends new write requests, prioritizes writing all cached data in DRAM to the NAND-flash memory, and waits for all write operations to complete. After confirming that the data write is complete, the latest FTL mapping table in DRAM can be completely written to the metadata area of ​​the NAND-flash memory, thereby ensuring the consistency of data and mapping relationships.

[0097] Furthermore, once all write operations are complete, a CQE for the Flush command can be generated, and the CQE can be written into the CQ. Then, an interrupt is triggered. Subsequently, the NVMe driver confirms and returns the result of the fsync() call, informing the application that the data has been safely and persistently stored.

[0098] In one specific implementation, the process of writing data to be written to the flash memory of the target solid-state drive (SSD) according to the flash physical address may further include: selecting physical blocks with fewer than a preset number of erase / write cycles from the flash memory of the target SSD as target write blocks using a wear leveling algorithm, and determining whether old data exists in the target write blocks; if old data exists in the target write blocks, the old data in the target write blocks are migrated to temporary blocks, and a block erase operation is performed on the target write blocks, and then the data to be written is written to the erased target write blocks. In this embodiment, a wear leveling algorithm (e.g., dynamic wear leveling algorithm) can be used to select physical blocks with fewer than a preset number of erase / write cycles as target write blocks. If there are multiple target write blocks, they can be sorted, and the physical block with the fewest erase / write cycles is prioritized as the first write block to write data, thereby avoiding excessive wear on individual blocks, achieving wear leveling of each block, improving the lifespan of the Nand-flash memory, and saving hardware costs. For example, blocks with fewer than 1000 erase / write cycles are preferred over blocks with more than 5000 erase / write cycles. Next, it checks if old data exists in the target write block. If old data exists, the valid pages are migrated to a temporary block, and then a block erase operation is performed (NAND requires erasure before writing). The erase process uses a high-voltage pulse to remove the charge from the storage cells, taking approximately 1-10 milliseconds. Further, the SSD controller writes the data into the erased write block, and upon completion, returns a write completion signal and updates the physical block status to "used." Then, in the DRAM, the corresponding data to be written is marked to transition from "cache state" to "persistent state."

[0099] The process of writing the data to be written to the flash memory of the target solid-state drive may further include: activating the power-loss protection circuit when a power-loss detection signal is detected, and supplying power through a preset power supply component; writing the data to be written from the second cache partition to the power-loss protection block of the flash memory through a hardware acceleration channel, updating the flash translation layer mapping table in the first cache partition based on the address of the power-loss protection block, and writing the updated flash translation layer mapping table to the metadata area of ​​the flash memory. In this embodiment, if a power outage occurs during data writing, the SSD power management module triggers a power-loss detection signal to immediately activate the power-loss protection circuit, thereby quickly switching to the main power supply through the supercapacitor or lithium battery pack built into the power-loss protection circuit, providing power support for approximately 10-50 milliseconds (depending on the capacitor capacity). Next, the data to be written that has not yet been written to the Nand-flash memory in the second cache partition of DRAM is written to the Nand-flash memory first, and the FTL mapping table in the first cache partition is modified. Specifically, the unwritten data can be forcibly written to the "power-loss protection block" of the Nand-flash memory through the hardware acceleration channel, thereby ensuring that critical data is not lost.

[0100] Additionally, after all data to be written is complete, the latest version of the FTL mapping table can be written to the metadata area of ​​the Nand-flash memory (such as a separate mapping block), ensuring that the corresponding address mapping relationship can be completely restored upon the next power-on. Through the above power-loss protection strategy, data loss due to power failure during data writing can be avoided, thereby improving the security of the data writing process.

[0101] Specifically, the process of writing data to be written to the flash memory of the target SSD based on the flash physical address may further include: scanning the flash memory of the target SSD at a preset period to identify invalid physical blocks in the flash memory whose invalid page ratio exceeds a preset threshold through invalid page marking; adding the invalid physical blocks to the garbage collection queue for garbage collection. In this embodiment, the SSD controller may also periodically scan the Nand-flash memory, identify invalid physical blocks whose invalid page ratio exceeds a preset threshold (e.g., 70%) through invalid page marking in the DRAM, and add them to the garbage collection queue for garbage collection. Specifically, during idle periods (e.g., when the SSD load is <20%), valid page data from invalid physical blocks can be read into the second cache partition of the DRAM and then written into new free blocks. Simultaneously, the FTL mapping table in the first cache partition is updated synchronously during the data migration process to ensure data address consistency. After the migration of valid data is completed, the old blocks can be erased and marked as "free blocks," thereby incorporating them into the available physical block pool for subsequent write operations. It should be noted that garbage collection can be performed in parallel with host I / O, and the impact on front-end performance can be reduced by using DRAM cache isolation.

[0102] Furthermore, after writing the data to be written to the flash memory of the target solid-state drive according to the flash physical address, the process may further include: generating a fourth completion queue entry containing a success status code and writing the fourth completion queue entry into the completion queue of the target solid-state drive; sending an interrupt signal to the host through a preset interrupt mechanism to inform the host that the data write command has been executed. In this embodiment, after writing the data to be written to the Nand-flash memory, a completion queue entry (CQE) containing a command ID and a success status code (0x00) can be generated, then written into the completion queue (CQ), and an interrupt signal can be sent to the host through the MSI-X interrupt mechanism to inform the host that the data write operation has been completed. Further, the host's NVMe driver responds to the interrupt and reads the CQE from the CQ to confirm successful writing.

[0103] As can be seen, this embodiment stores the flash translation layer mapping table for SSD data read / write operations in the first partition of a pre-created programmable logic device board (supporting high-speed serial protocols), and caches the data to be read / written in the second partition. In this way, when a write operation is needed, the corresponding flash physical address can be allocated for the data to be written in the flash translation layer mapping table of the first partition, and then the data to be written is written from the second partition to the SSD's Nand-flash memory, thus completing the data write operation. Through this method, when performing a write operation, there is no need to occupy host memory; instead, the random access memory in the programmable logic device board is used as extended memory of the host (for caching the data to be written). This reduces the SSD's dependence on host memory and does not consume host memory resources, thereby improving data write efficiency. Furthermore, the programmable logic device board can be dynamically added, thus providing flexible scalability.

[0104] Accordingly, this application also discloses a hard disk data read / write device applied to a solid-state drive controller, the device comprising:

[0105] The command parsing module is used to read and parse the read data commands generated by the host from the submission queue of the target solid-state drive to obtain read command data; the read command data includes the data length and the logical block start address;

[0106] The mapping table reading module is used to read the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory. The target random access memory is located on a programmable logic device board that supports high-speed serial protocols. The host and the target solid-state drive and the programmable logic device board, as well as the target solid-state drive and the programmable logic device board, are connected through a peripheral component fast interconnect bus.

[0107] The address determination module is used to determine the first physical block address from the flash translation layer mapping table; the first physical block address is the physical block address corresponding to the logical block start address in the read command data;

[0108] The data reading module is used to read the target data corresponding to the first physical block address from the flash memory in the target solid-state drive according to the data length in the read command data;

[0109] The data writing module is used to write the target data into the second cache partition in the target random access memory in order to complete the data reading operation for the target data.

[0110] The specific workflow of each of the above modules can be found in the relevant content disclosed in the foregoing embodiments, and will not be repeated here.

[0111] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the hard disk data read / write method.

[0112] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the hard disk data read / write method when running.

[0113] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0114] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the hard disk data read / write method.

[0115] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the hard disk data read / write method.

[0116] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] The above provides a detailed description of a hard disk data read / write method, product, device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for reading and writing data on a hard disk, characterized in that, Applications in solid-state drive controllers include: The read command data is obtained by reading and parsing the read data command generated by the host from the submission queue of the target solid-state drive; the read command data includes the data length and the logical block start address. The flash translation layer mapping table corresponding to the target solid-state drive is read from the first cache partition in the target random access memory; the target random access memory is located on a programmable logic device board that supports high-speed serial protocols; the host and the target solid-state drive and the programmable logic device board, as well as the target solid-state drive and the programmable logic device board, are connected through a peripheral component fast interconnect bus. The first physical block address is determined from the flash memory translation layer mapping table; the first physical block address is the physical block address corresponding to the logical block start address in the read command data; According to the data length in the read command data, the target data corresponding to the first physical block address is read from the flash memory in the target solid-state drive, and the target data is written to the second cache partition in the target random access memory to complete the data reading operation for the target data; The step of reading and parsing read data commands generated by the host from the submission queue of the target SSD to obtain read command data includes: when a new command is detected being written to the submission queue of the target SSD through a preset queue monitoring mechanism, reading the read data command to be processed from the submission queue of the target SSD through direct memory access, and saving the read data command to the internal register of the target SSD; the preset queue monitoring mechanism is a hardware-level queue monitoring mechanism; parsing the read data command in the internal register to obtain read command data; wherein, the read command data also includes a physical region page list; The step of reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory includes: determining whether the range corresponding to the logical block start address in the read command data is within the total capacity of the target solid-state drive; if the range corresponding to the logical block start address is within the total capacity of the target solid-state drive, then determining whether the data length in the read command data meets the page read alignment requirements of the flash memory in the target solid-state drive; if the data length meets the page read alignment requirements of the flash memory in the target solid-state drive, then verifying the validity of the physical region page list in the read command data to obtain a verification result; if the verification result shows that the verification is successful, then reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory.

2. The hard disk data read / write method according to claim 1, characterized in that, Also includes: If the range corresponding to the starting address of the logical block is not within the total capacity of the target solid-state drive, or the data length does not meet the page read alignment requirements of the flash memory in the target solid-state drive, or the verification result indicates that the verification failed, then a first completion queue entry containing an error code is generated. Write the first completion queue entry into the completion queue of the target solid-state drive.

3. The hard disk data read / write method according to claim 1, characterized in that, The step of writing the target data into the second cache partition in the target random access memory includes: Based on the physical region page list in the read command data, obtain the physical address and length information of the second cache partition in the target random access memory; Configure data transmission parameters according to the physical address and length information, and write the target data into the second cache partition according to the data transmission parameters.

4. The hard disk data read / write method according to claim 3, characterized in that, The process of writing the target data into the second cache partition of the target random access memory further includes: Errors during the transmission of the target data are detected through the Peripheral Component Fast Interconnect Transaction Layer in the Peripheral Component Fast Interconnect Bus. If a data transmission error is detected, the target data is retransmitted through the link layer in the external component interconnect bus and according to the preset retransmission mechanism.

5. The hard disk data read / write method according to claim 1, characterized in that, The step of reading the flash translation layer mapping table corresponding to the target solid-state drive from the first cache partition in the target random access memory includes: Determine whether a mapping entry corresponding to the logical block start address in the read command data exists in the first cache partition of the target random access memory; If the first cache partition contains a mapping entry corresponding to the logical block start address in the read command data, then the flash translation layer mapping table corresponding to the target solid-state drive is read from the first cache partition in the target random access memory via a time synchronization network protocol.

6. The hard disk data read / write method according to claim 1, characterized in that, The step of reading the target data corresponding to the first physical block address from the flash memory in the target solid-state drive according to the data length in the read command data includes: Detect whether there is valid user data in the flash memory of the target solid-state drive that corresponds to the first physical block address; If the flash memory in the target solid-state drive contains user data marked as valid corresponding to the first physical block address, then the user data corresponding to the first physical block address is read from the flash memory according to the data length in the read command data to obtain the target data.

7. The hard disk data read / write method according to claim 6, characterized in that, Also includes: Determine whether there is valid user data in the second cache partition that corresponds to the first physical block address; If there is no valid user data corresponding to the first physical block address in the second cache partition, a read command containing the first physical block address is sent to the flash memory controller to activate the target storage unit corresponding to the first physical block address and obtain the original user data corresponding to the first physical block address from the target storage unit. Error detection is performed on the original user data to obtain the detection results; If the detection result indicates that there is a bit error in the original user data, then the original user data is corrected using a preset decoding algorithm to obtain the corrected data. Metadata of the idle area is removed from the corrected data to extract valid user data, and the data access type of the valid user data is obtained. If the data access type is a high-frequency access type, the valid user data is written to the second cache partition, and the flash translation layer mapping table in the first cache partition is updated based on the write address of the valid user data.

8. The hard disk data read / write method according to claim 7, characterized in that, Also includes: If the correction of the original user data fails, the corresponding physical page is marked as a bad page, and a new physical page is allocated from the spare block; The flash translation layer mapping table in the first cache partition is updated based on the second physical block address corresponding to the new physical page, and the relevant information of the bad block marked as the bad page is recorded in the bad block table of the flash memory.

9. The hard disk data read / write method according to claim 8, characterized in that, Also includes: The number of bad blocks marked as bad pages is counted to obtain the number of bad blocks, and it is determined whether the number of bad blocks exceeds a preset spare block threshold; If the number of bad blocks exceeds a preset spare block threshold, a second completion queue entry containing an error status code is generated and written into the completion queue of the target solid-state drive.

10. The hard disk data read / write method according to claim 1, characterized in that, After writing the target data into the second cache partition of the target random access memory, the method further includes: Generate a third completion queue entry containing a success status code, and write the third completion queue entry into the completion queue of the target solid-state drive; An interrupt signal is sent to the host through a preset interrupt mechanism to inform the host that the read data command has been executed.

11. The hard disk data read / write method according to claim 1, characterized in that, Also includes: The write command data is obtained by reading and parsing the write data command generated by the host from the submission queue of the target solid-state drive; the write command data includes the data length, logical block start address and physical region page list; Based on the physical region page list in the write command data, read the data to be written from the second cache partition in the target random access memory; Based on the data length and logical block start address in the write command data, allocate a corresponding flash physical address for the data to be written in the flash translation layer mapping table of the first cache partition; The data to be written is written to the flash memory of the target solid-state drive according to the physical address of the flash memory, so as to complete the data writing operation for the data to be written.

12. The hard disk data read / write method according to claim 11, characterized in that, After writing the data to be written to the flash memory of the target solid-state drive according to the flash physical address, the method further includes: Generate a fourth completion queue entry containing a success status code, and write the fourth completion queue entry into the completion queue of the target solid-state drive; An interrupt signal is sent to the host through a preset interrupt mechanism to inform the host that the write data command has been completed.

13. The hard disk data read / write method according to claim 11, characterized in that, The step of writing the data to be written to the flash memory of the target solid-state drive according to the flash physical address includes: When the preset triggering condition is met, the data in the second cache partition of the target random access memory is persistently stored in the flash memory of the target solid-state drive according to the physical address of the flash memory; The preset triggering condition is any one of the following: the utilization rate of the target random access memory reaches a preset utilization threshold, the host sends a forced data persistence command, or a preset data refresh cycle is reached.

14. The hard disk data read / write method according to claim 11, characterized in that, The process of writing the data to be written to the flash memory of the target solid-state drive according to the flash physical address further includes: The wear leveling algorithm selects physical blocks with fewer than a preset number of erase / write cycles from the flash memory of the target solid-state drive as target write blocks, and determines whether old data exists in the target write blocks. If old data exists in the target write block, the old data in the target write block is migrated to a temporary block, and a block erasure operation is performed on the target write block. Then, the data to be written is written into the erased target write block.

15. The hard disk data read / write method according to any one of claims 11 to 14, characterized in that, The process of writing the data to be written to the flash memory of the target solid-state drive according to the flash physical address further includes: Scan the flash memory in the target solid-state drive at a preset cycle to identify invalid physical blocks in the flash memory whose invalid page ratio exceeds a preset percentage threshold by invalid page marking; The invalid physical block is added to the garbage collection queue for garbage collection.

16. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the hard disk data read / write method as described in any one of claims 1 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the hard disk data read / write method as described in any one of claims 1 to 15.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the hard disk data read / write method as described in any one of claims 1 to 15.

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