Training method and prediction method of electrical parameter prediction model and related device
By combining a geometric domain encoder, an electrical behavior domain encoder, and a cross-domain attention fusion module, the problem of integrating electrical parameters of various transistor types is solved, achieving high-precision electrical parameter prediction and reducing modeling costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-03-10
- Publication Date
- 2026-07-14
AI Technical Summary
Existing technologies struggle to effectively integrate the electrical parameters of various transistor types, resulting in weak model generalization ability and limited prediction accuracy. In particular, transistor parameter variations exhibit nonlinearity and coupling under complex process conditions, making it difficult to achieve systematic characterization.
Employing a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, this method acquires geometric and electrical behavior domain features from various types of transistors, calculates physical perception attention scores to achieve dynamic matching and weighted fusion of the geometric and electrical behavior domains, outputs predicted values of transistor electrical parameters, and optimizes model parameters through backpropagation until convergence.
It achieves feature fusion and dynamic weighting across device types, improves the prediction accuracy of transistor electrical parameters, reduces modeling costs, can adaptively focus on key structural features, and is applicable to the prediction of electrical parameters for various transistor types.
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Figure CN121808745B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a training method, prediction method and related apparatus for an electrical parameter prediction model. Background Technology
[0002] In semiconductor device modeling and performance analysis, it is often necessary to establish mathematical models for key electrical parameters of transistors (such as turn-off current Ioff, saturation region on-state current Idsat, and linear region threshold voltage Vtlin) to reflect their intrinsic physical mechanisms or predict device behavior. Currently, modeling is typically performed on the correlation of multiple parameters for a single type of transistor, for example, by constructing mapping relationships between parameters within a certain type of device based on empirical formulas or statistical methods. However, these methods only focus on parameter coupling within a single boundary and do not consider the electrical correlation characteristics between different transistors due to structural similarities or process commonalities. When facing multiple devices requiring unified modeling, traditional methods struggle to capture parameter dependencies across device types, resulting in weak model generalization ability and limited prediction accuracy. Especially under complex process conditions, transistor parameter variations exhibit nonlinearity and coupling, making it difficult to achieve systematic characterization by relying solely on single-device modeling. Therefore, there is an urgent need to provide a modeling mechanism that can integrate the electrical parameters of multiple transistor types and uncover their cross-device correlation patterns to improve the accuracy of device performance prediction. Summary of the Invention
[0003] In view of the above problems, the purpose of this application is to provide a training method, prediction method and related apparatus for an electrical parameter prediction model, which aims to improve the prediction accuracy of transistor electrical parameters and reduce modeling costs.
[0004] According to a first aspect of the embodiments of this application, a training method for an electrical parameter prediction model for transistors is provided. The electrical parameter prediction model includes a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor. The training method includes:
[0005] Obtain a training sample set, which contains geometric domain features and electrical behavior domain features of various types of transistors;
[0006] The geometric domain features are input into the geometric domain encoder to obtain a geometric feature representation vector, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector;
[0007] The geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. By calculating the physical perception attention score, dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved to obtain the fused feature representation of various types of transistors.
[0008] The fused feature representation is input into the regression predictor to output predicted values of transistor electrical parameters. Based on the error between the predicted values and the corresponding true electrical parameter values, the parameters of the electrical parameter prediction model are optimized through backpropagation until the model converges.
[0009] Optionally, the geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module, and the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved by calculating the physical perception attention score, to obtain fused feature representations of various types of transistors, including:
[0010] A first attention score is calculated for each transistor based on the geometric feature representation vector and the electrical behavior feature representation vector.
[0011] The first attention score is weighted using a geometric sensitivity coefficient and then normalized to obtain the physical perception attention score.
[0012] The value vector of the corresponding transistor is weighted using the physical perception attention score to obtain the fused feature representation of the corresponding transistor. The value vector is obtained by mapping the electrical behavior domain feature of the corresponding transistor.
[0013] Optionally, the geometric sensitivity coefficient includes a nonlinear term for simulating short-channel effects and a linear enhancement term for reflecting wide device current characteristics.
[0014] Optionally, the step of weighting and normalizing the first attention score using a geometric sensitivity coefficient to obtain the physical perception attention score includes:
[0015] The product of the nonlinear term and the linear enhancement term is used as the geometric sensitivity coefficient;
[0016] The product of the first attention score and the geometric sensitivity coefficient is normalized to obtain the physical perception attention score.
[0017] Optionally, obtaining the training sample set includes:
[0018] Acquire test data for various types of transistors, including the geometric parameters, electrical response parameters, and corresponding device codes of each transistor;
[0019] The test data of the transistors are matched based on the device code to construct a complete data record;
[0020] Generate learnable embedding vectors for each transistor type to identify its process category;
[0021] Derivative features are constructed for the electrical response parameters of each transistor;
[0022] Each training sample includes geometric domain features and electrical behavior domain features of the corresponding transistor, and the electrical behavior domain features of the corresponding transistor include derived features of the corresponding transistor.
[0023] Optionally, the geometric domain features include channel length and channel width, and the electrical behavior domain features include one or more of linear region threshold voltage, saturation region on-state current, and off-state current.
[0024] According to a second aspect of the embodiments of this application, a method for predicting electrical parameters of a transistor is provided, applied to an electrical parameter prediction model trained according to any one of the training methods described above, the electrical parameter prediction model including a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the electrical parameter prediction method including:
[0025] Obtain the geometric domain characteristics and electrical behavior domain characteristics of the transistor under test;
[0026] The geometric domain features are input into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test.
[0027] The geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. By calculating the physical perception attention score, dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved to obtain the fused feature representation of the transistor under test.
[0028] The fused feature representation is input into the regression predictor to output predicted values of the transistor electrical parameters of the transistor under test.
[0029] According to a third aspect of the embodiments of this application, a training apparatus for a transistor electrical parameter prediction model is provided, the electrical parameter prediction model including a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the training apparatus comprising:
[0030] A training sample acquisition unit is used to acquire a training sample set, which contains geometric domain features and electrical behavior domain features of various types of transistors.
[0031] The feature representation vector acquisition unit is used to input the geometric domain features into the geometric domain encoder to obtain a geometric feature representation vector, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector;
[0032] The fusion feature representation acquisition unit is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score, so as to obtain the fusion feature representation of various types of transistors;
[0033] The parameter adjustment unit is used to input the fused feature representation into the regression predictor to output the predicted value of the transistor electrical parameter, and optimize the parameters of the electrical parameter prediction model through backpropagation based on the error between the predicted value and the corresponding true electrical parameter value until the model converges.
[0034] According to a fourth aspect of the embodiments of this application, an electrical parameter prediction device for a transistor is provided, applied to an electrical parameter prediction model trained according to any one of the training methods described above, the electrical parameter prediction model including a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the electrical parameter prediction device comprising:
[0035] The feature acquisition unit is used to acquire the geometric domain features and electrical behavior domain features of the transistor under test.
[0036] The encoding unit is used to input the geometric domain features into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test.
[0037] The feature fusion unit is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score to obtain the fused feature representation of the transistor under test;
[0038] A parameter prediction unit is used to input the fused feature representation into the regression predictor to output predicted values of transistor electrical parameters.
[0039] According to a fifth aspect of the embodiments of this application, an electronic device is provided, comprising:
[0040] One or more processors;
[0041] A memory for storing executable instructions that, when executed by the one or more processors, cause the electronic device to perform any of the methods described above.
[0042] The unexpected technical effect of this application is:
[0043] A training sample set containing geometric and electrical behavior features of various transistor types is obtained. Geometric features are input into a geometric encoder to obtain geometric feature representation vectors, and electrical behavior features are input into an electrical behavior encoder to obtain electrical behavior feature representation vectors. These vectors are then input into a cross-domain attention fusion module. Dynamic matching and weighted fusion of the geometric and electrical behavior domains are achieved by calculating physical perception attention scores, resulting in fused feature representations for various transistor types. These fused feature representations are input into a regression predictor to output predicted values of transistor electrical parameters. Based on the error between the predicted values and the corresponding true electrical parameter values, the parameters of the prediction model are optimized through backpropagation until the model converges. Thus, through dual-domain coupling and cross-domain attention mechanisms of the geometric and electrical behavior domains, feature fusion and dynamic weighting across device types are achieved. This allows the model to adaptively focus on key structural features that have a greater impact on electrical parameters, improving the prediction accuracy of transistor electrical parameters. A single model can handle the prediction of electrical parameters for multiple transistor types within the transistor family, eliminating the need to build specific sub-models for different devices and saving modeling costs.
[0044] Furthermore, based on the geometric feature representation vector and the electrical behavior feature representation vector, a first attention score is calculated for each transistor. This first attention score is then weighted using a geometric sensitivity coefficient and normalized to obtain a physical perception attention score. This physical perception attention score is then used to weight the value vector of the corresponding transistor to obtain a fused feature representation of that transistor. The geometric sensitivity coefficient includes a nonlinear term to simulate short-channel effects and a linear enhancement term to reflect the current characteristics of wide-device applications. This fused feature representation fully integrates the physical relationship between the geometric structure and electrical response parameters. It not only retains the modeling ability of traditional attention mechanisms for dynamic dependencies between features but also enhances the model's sensitivity and expressive power to key device physical effects by introducing prior knowledge terms with clear physical meaning. Specifically, the nonlinear term increases rapidly with decreasing channel length, reflecting the exponential impact of short-channel effects; the linear enhancement term increases linearly with increasing device width, reflecting the improved current carrying capacity of wide-device applications. The geometric sensitivity coefficient formed by the coupling of these two terms can more accurately characterize the combined influence of transistor geometric parameters on its electrical behavior. By introducing a geometric sensitivity coefficient, the physical perception attention score can dynamically adjust the contribution weights of devices with different geometric features in cross-domain mapping, enabling the model to prioritize transistors that are sensitive to structural changes when predicting electrical behavior. Attached Figure Description
[0045] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0046] Figure 1The diagram shown is a schematic frame of an exemplary electrical parameter prediction model for a transistor according to an embodiment of this application.
[0047] Figure 2 The diagram shown is a schematic flowchart of an exemplary training method for a transistor electrical parameter prediction model according to an embodiment of this application.
[0048] Figure 3 The diagram shown is an exemplary flowchart of a method for predicting electrical parameters of a transistor according to an embodiment of this application.
[0049] Figure 4A The diagram shown is a schematic representation of the predicted value of the linear region threshold voltage of an exemplary multi-type transistor according to an embodiment of this application.
[0050] Figure 4B The diagram shown is a schematic representation of the predicted saturation region conduction current of an exemplary multi-type transistor according to an embodiment of this application.
[0051] Figure 4C The diagram shown is a schematic representation of the predicted turn-off current of an exemplary type of transistor according to an embodiment of this application.
[0052] Figure 5 The diagram shown is a schematic structural diagram of an exemplary training device for a transistor electrical parameter prediction model according to an embodiment of this application.
[0053] Figure 6 The diagram shown is a schematic structural diagram of an exemplary device for predicting electrical parameters of a transistor according to an embodiment of this application.
[0054] Figure 7 The diagram shown is a schematic representation of an exemplary electronic device according to an embodiment of this application. Detailed Implementation
[0055] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.
[0056] This application may be presented in various forms, some of which will be described below.
[0057] Figure 1 The diagram shown is a schematic framework of an exemplary electrical parameter prediction model for a transistor according to an embodiment of this application. Figure 1As shown, the electrical parameter prediction model 100 includes an input layer 110, a geometric domain encoder 120, an electrical behavior domain encoder 130, a cross-domain attention fusion module 140, and a regression predictor 150.
[0058] In some embodiments, the input layer 110 receives test data from various types of transistors and maps it to structured input features (i.e., geometric domain features and electrical behavior domain features) as a training sample set. The test data includes the geometric parameters, electrical response parameters, and corresponding device codes of each transistor. The geometric domain encoder 120, for example, employs a feedforward neural network to encode the geometric domain features of the transistors into geometric feature representation vectors. The electrical behavior domain encoder 130 encodes the electrical behavior domain features to generate electrical behavior feature representation vectors. The two encoders map the input features of their respective domains to the same latent feature space, obtaining high-level nonlinear representations while maintaining semantic consistency. The cross-domain attention fusion module 140, based on geometric feature representation vectors and electrical behavior feature representation vectors, uses a cross-domain attention mechanism. The output of the geometric domain encoder 120 is used as the query vector, and the output of the electrical behavior domain encoder 130 is used as the key and value vectors. This achieves dynamic weighted fusion of the dual-domain features, fully capturing the nonlinear influence of geometric structure on electrical response, calculating inter-domain correlations, and adaptively integrating key information to obtain a fused feature representation. The regression predictor 150, as the output layer (e.g., a multilayer perceptron (MLP) regression head), receives the fused feature representation and predicts transistor electrical parameters. For example, it regresses and predicts the transistor's turn-off current Ioff, saturation region on-state current Idsat, and linear region threshold voltage Vtlin.
[0059] Figure 2 The diagram shown is a schematic flowchart of an exemplary training method for a transistor electrical parameter prediction model according to an embodiment of this application. The training method for a transistor electrical parameter prediction model according to this embodiment is applied to... Figure 1 The electrical parameter prediction model 100 is shown. (As shown...) Figure 2 As shown, the training method includes the following steps:
[0060] In step S210, a training sample set is obtained, which contains geometric domain features and electrical behavior domain features of various types of transistors.
[0061] In some embodiments, the input layer 110 acquires test data for various types of transistors. The transistor device types cover a variety of voltage levels and structural designs, including, for example: 1.1 V low-voltage transistors (such as n-type and p-type LVT, SVT, and HVT devices), 1.1 V SRAM-specific transistors (such as n-type PD / PG devices and p-type PU devices), medium-voltage transistors (such as 3.3 V underdriven and 8 V standard n / p channel devices), and high-voltage transistors (such as n-type and p-type high-voltage devices with symmetrical and asymmetrical structures). Each type of device employs different channel doping, gate dielectric structures, and electrical characteristic optimization designs according to application requirements. The test data covers the electrical response parameters and corresponding geometric parameters of the device under different bias conditions. The test data for each device is structured into two main domains: geometric domain characteristics and electrical behavior domain characteristics. Geometric domain features include physical dimension parameters such as channel length (L) and channel width (W), while electrical behavior domain features cover the electrical response parameters of the device under different bias conditions, including parameters such as transistor turn-off current Ioff, saturation region on-state current Idsat, and linear region threshold voltage Vtlin. In some embodiments, each training sample includes both geometric domain features and electrical behavior domain features of the corresponding transistor.
[0062] In some embodiments, a learnable embedding vector is generated for each transistor type to identify its process category. For example, a learnable embedding vector is generated for each specific type of device in the transistor family (such as LVT NMOS, HVT PMOS, etc.) to explicitly identify its process category. Derived features are constructed for the electrical response parameters of each transistor. For example, derived features (such as ratios, differences, etc.) are constructed using physical equations or model constraints as prior knowledge to enhance physical interpretability and model structure. The derived features of the corresponding transistor are included in the electrical behavior domain features of the corresponding transistor.
[0063] In step S220, the geometric domain features are input into the geometric domain encoder to obtain a geometric feature representation vector, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector.
[0064] In some embodiments, geometric domain features are input to geometric domain encoder 120 via input layer 110 to obtain a geometric feature representation vector. The formula for calculating the geometric feature representation vector is:
[0065] gi=MLPg([L i W i ])(1)
[0066] Where gi is the geometric feature representation vector of the i-th transistor (i is an integer greater than 0); [L iW i [L] is the channel length of the i-th transistor. i With channel width W i The geometric domain features are composed of MLPg, which represents the multilayer perceptron model of the geometric domain encoder 120, used to extract the nonlinear representation of the geometric domain features.
[0067] In some embodiments, the electrical behavior domain features are input to the electrical behavior domain encoder 130 via the input layer 110 to obtain an electrical behavior feature representation vector. The formula for calculating the electrical behavior feature representation vector is:
[0068] (2)
[0069] Where ei is the electrical behavior feature representation vector of the i-th transistor; It is an input vector composed of the electrical behavior domain characteristics of the i-th transistor and an embedding vector identifying its process category; e numi It is the electrical behavior domain feature composed of the standardized electrical behavior features of the i-th transistor, for example, e numi Vtlin is the threshold voltage Vtlin in the linear region of the i-th transistor. i , Saturation region conduction current Idsat i and the turn-off current Ioff i (Due to the turn-off current Ioff) i Since the range is relatively large, logarithmic transformation can be used for normalization to eliminate dimensional differences. For example, using... To calculate e numi The electrical behavior domain features are composed of components such as ) and others. is the embedding vector that identifies the process category of the i-th transistor; MLPe represents the multilayer perceptron model of the electrical behavior domain encoder 130, used to capture high-order nonlinear correlations of electrical behavior features.
[0070] In step S230, the geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. By calculating the physical perception attention score, dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved to obtain the fused feature representation of various types of transistors.
[0071] In some embodiments, the geometric feature representation vector G (G=[g1,g2,...,gm] (where m is the number of transistors and m is an integer greater than 0)) and the electrical behavior feature representation vector E (E=[e1,e2,...,em]) are input into the cross-domain attention fusion module 140. The geometric feature representation vector G is used as the query vector Q, and the electrical behavior feature representation vector E is used as the key vector K and the value vector V. In some embodiments, the query vector Q corresponding to the i-th transistor... iThe calculation formula is:
[0072] Q i =f G (L i W i (3)
[0073] Among them, Q i It is based on the channel length L of the i-th transistor. i With channel width W i The obtained query vector; f G It is the query vector Q i The mapping function is used to transform geometric domain features into query vectors that can be used for attention mechanisms.
[0074] In some embodiments, the bond vector K corresponding to the i-th transistor i The calculation formula is:
[0075] (4)
[0076] Among them, K i It is based on the linear region threshold voltage Vtlin of the i-th transistor. i , Saturation region conduction current Idsat i and the turn-off current Ioff i The obtained key vector; f E1 It is the key vector K i The mapping function is used to map electrical behavior domain features to key vectors.
[0077] In some embodiments, the value vector V corresponding to the i-th transistor i The calculation formula is:
[0078] (5)
[0079] Among them, V i It is based on the linear region threshold voltage Vtlin of the i-th transistor. i , Saturation region conduction current Idsat i and the turn-off current Ioff i The resulting value vector; f E2 It is a value vector V i The mapping function is used to map the electrical behavior domain features into a value vector.
[0080] Next, in some embodiments, a first attention score is calculated for the i-th transistor. i In some embodiments, the first attention score is... i The calculation formula is:
[0081] (6)
[0082] Among them, Score i Q is the first attention score of the i-th transistor; i K is the query vector corresponding to the i-th transistor; i It is the bond vector corresponding to the i-th transistor; d k This is the dimension of the key vector, used to scale the dot product result to stabilize the gradient. First attention score. i It reflects the correlation strength between the geometric characteristics and electrical behavior characteristics of the i-th transistor. The higher the score, the more significant the influence of the geometric parameters on the electrical performance of the transistor under the current operating conditions.
[0083] Next, in some embodiments, the geometric sensitivity coefficient α is used. i Score for first attention i After weighting and normalization, the physical perception attention score γ is obtained. i In some embodiments, the first attention score is used. i and geometric sensitivity coefficient α i The product of these values is normalized to obtain the physical perception attention score γ. i Physical perception attention score γ i The calculation formula is:
[0084] (7)
[0085] Where, α i It is the geometric sensitivity coefficient corresponding to the i-th transistor; Score i It is the first attention score of the i-th transistor. softmax is a normalization function used to transform the weighted attention score into a probability distribution.
[0086] In some embodiments, the geometric sensitivity coefficient α corresponding to the i-th transistor i This includes a nonlinear term to simulate short-channel effects and a linear enhancement term to reflect wide device current characteristics. The product of the nonlinear and linear enhancement terms is used as the geometric sensitivity coefficient α. i Geometric sensitivity coefficient α i The calculation formula is:
[0087] (8)
[0088] in, It is a nonlinear term used to simulate the short-channel effect; It is a linear enhancement term used to represent the wide current characteristics of devices; L i W is the channel length of the i-th transistor.i is the channel width of the i-th transistor; L0 is the reference channel length, W0 is the reference channel width, and k and β are empirical adjustment parameters. The nonlinear term increases rapidly as the channel length decreases, reflecting the exponential effect of the short-channel effect; the linear enhancement term increases linearly with the device width, reflecting the improvement in current carrying capacity of a wider device. The geometric sensitivity coefficient α formed by the coupling of these two is... i This allows for a more accurate characterization of the combined effects of transistor geometry parameters on its electrical behavior. This is achieved by introducing a geometry sensitivity coefficient α. i Physical perception attention score γ i It can dynamically adjust the contribution weights of devices with different geometric features in cross-domain mapping, so that the model can prioritize transistors that are sensitive to structural changes when predicting electrical behavior.
[0089] Next, in some embodiments, the physical perception attention score γ is utilized. i The value vector V of the i-th transistor i After weighting, the fused feature representation fi of the i-th transistor is obtained. The formula for calculating the fused feature representation fi of the i-th transistor is:
[0090] (9)
[0091] Where, γ i V is the physical perception attention score of the i-th transistor; i This is the value vector corresponding to the i-th transistor. This fused feature representation fully integrates the physical relationship between the geometric structure and the electrical response parameters. It not only retains the ability of traditional attention mechanisms to model the dynamic dependencies between features, but also enhances the model's sensitivity and expressive power to the physical effects of key devices by introducing prior knowledge terms with clear physical meaning.
[0092] In step S240, the fused feature representation is input into the regression predictor to output the predicted values of the transistor electrical parameters. Based on the error between the predicted values and the corresponding true electrical parameter values, the parameters of the electrical parameter prediction model are optimized through backpropagation until the model converges.
[0093] In some embodiments, the fusion feature representation fi of the i-th transistor is input to the regression predictor 150, and the regression predictor 150 outputs the predicted value of the transistor electrical parameters of the i-th transistor. Predicted values of the electrical parameters of the i-th transistor. The calculation formula is:
[0094] (10)
[0095] Wherein, MLPout is the mapping function of the regression predictor 150, used to map the fused feature representation fi to the target electrical parameter space.
[0096] In some embodiments, the predicted values of the transistor electrical parameters of the i-th transistor are used. Corresponding to the actual electrical parameter values The error between them is optimized through backpropagation to refine the parameters of the electrical parameter prediction model 100 until the model converges. In some cases, the predicted values of the transistor electrical parameters are based on the i-th transistor. Corresponding to the actual electrical parameter values Error calculation loss function loss function The calculation formula is:
[0097] (11)
[0098] in, It is the predicted value of the transistor electrical parameters of the i-th transistor; These correspond to the actual electrical parameter values. This is achieved by minimizing the loss function. The model parameters are continuously updated during backpropagation, thereby improving prediction accuracy. During training, the physics-aware attention mechanism effectively captures the deep correlation between transistor structure and electrical performance, enabling the model to maintain good generalization ability across different process nodes and device types.
[0099] In some embodiments, a random feature masking strategy is employed during the training phase, enabling the model to make predictions based on arbitrary subsets of parameters. This strategy forces the model to learn the nonlinear mapping relationship between the remaining features and the target electrical parameters by randomly masking some process parameters in the input features, thereby enhancing its robustness to incomplete input data in practical applications. Combined with interpretability tools such as SHAP (Shapley Additive Interpretation), the contribution of each process parameter to the prediction results is further revealed, providing traceable decision-making basis for device design and process optimization, and realizing the transformation from "black box" prediction to "transparent" reasoning.
[0100] It is understood that the prediction model trained by the training method in this application embodiment achieves feature fusion and dynamic weighting across device types through dual-domain coupling of the geometric domain and the electrical behavior domain and a cross-domain attention mechanism. This enables the model to adaptively focus on key structural features that have a greater impact on electrical parameters, thereby improving the prediction accuracy of transistor electrical parameters. Furthermore, it achieves unified and accurate prediction capabilities for multiple devices within the transistor family: a single model can handle the prediction of electrical parameters for multiple transistor types within the transistor family, eliminating the need to build specific sub-models for different devices and saving modeling costs.
[0101] Figure 3 The diagram shown is an exemplary flowchart of a method for predicting electrical parameters of a transistor according to an embodiment of this application. The method for predicting electrical parameters of a transistor according to this embodiment is applied to... Figure 1 The electrical parameter prediction model 100 is shown. (As shown...) Figure 3 As shown, the training method includes the following steps:
[0102] In step S310, the geometric domain characteristics and electrical behavior domain characteristics of the transistor under test are obtained.
[0103] In step S320, the geometric domain features are input into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test.
[0104] In step S330, the geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. By calculating the physical perception attention score, dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved to obtain the fused feature representation of the transistor under test.
[0105] In step S340, the fused feature representation is input into the regression predictor to output predicted values of the transistor electrical parameters of the transistor under test.
[0106] In the model application stage, only the geometric domain features and electrical behavior domain features of the transistor under test need to be input. Steps S310 to S340 can be used to quickly and accurately predict the electrical parameters of various types of transistors in the transistor family. There is no need to model different devices separately, which significantly improves prediction efficiency and generalization ability and reduces modeling cost.
[0107] Figure 4A The diagram shown is a schematic representation of the predicted value of the linear region threshold voltage of an exemplary multi-type transistor according to an embodiment of this application. Figure 4B The diagram shown is a schematic representation of the predicted saturation region conduction current of an exemplary multi-type transistor according to an embodiment of this application. Figure 4C The diagram illustrates a predicted value of the turn-off current for an exemplary type of transistor according to an embodiment of this application. Figures 4A to 4CAs shown, the transistor types include LVT (Low Threshold Voltage Transistor), SVT (Standard Threshold Voltage Transistor), HVT (High Threshold Voltage Transistor), PD / PU (Pull-Down / Pull-Up Transistor), PG (Power Gating Transistor), UD3.3 (Under Drive 3.3 V Transistor), 8VMv (8 V Medium-voltage Transistor), Sym.HV (Symmetric High-Voltage Transistor), and Asy.HV (Asymmetric High-Voltage Transistor), which are labeled A, B, C, D, E, F, G, H, and I in the attached figures, respectively.
[0108] exist Figure 4A In the figure, the horizontal axis represents the transistor type, and the vertical axis represents the predicted linear region threshold voltage Vtlin (in mV) for n-type and p-type MOSFETs. As can be seen from the figure, the mean absolute percentage error (MAPE) for predicting the linear region threshold voltage Vtlin for various transistor types is 2.35%, and the goodness of fit R² is 0.96.
[0109] exist Figure 4B In the figure, the horizontal axis represents the transistor type, and the vertical axis represents the predicted saturation region on-state current Idsat (unit: μA / μm) for n-type and p-type MOSFETs. As can be seen from the figure, the mean absolute percentage error (MAPE) for predicting the saturation region on-state current Idsat for all types of transistors is 4.15%, and the goodness of fit R² is 0.97.
[0110] exist Figure 4C In the figure, the horizontal axis represents the transistor type, and the vertical axis represents the predicted turn-off current Ioff (unit: pA / μm) for n-type and p-type MOSFETs. As can be seen from the figure, the mean absolute percentage error (MAPE) for predicting the turn-off current Ioff is 38% for all types of transistors, and the goodness of fit R² is 0.912.
[0111] Understandable Figures 4A to 4CAs shown, the electrical parameter distributions of n-type and p-type MOSFETs exhibit a typical bipolar topology. The prediction model shows a mean absolute percentage error (MAPE) of less than 5% and a goodness of fit (R²) greater than 0.95 in predicting the linear region threshold voltage Vtlin and the saturation region on-state current Idsat. In predicting the turn-off current Ioff, the MAPE is approximately 38%, yet it still maintains a good fit (R²) greater than 0.9. The turn-off current Ioff itself exhibits greater inherent volatility compared to the linear region threshold voltage Vtlin and the saturation region on-state current Idsat, resulting in a relatively higher prediction error. This result is consistent with the device's physical characteristics.
[0112] Figure 5 The diagram shows a schematic representation of an exemplary training apparatus for a transistor electrical parameter prediction model according to an embodiment of this application. The training apparatus 500 of this embodiment is used for the prediction model trained by the training method. Figure 5 As shown, the training device 500 includes a training sample acquisition unit 510, a feature representation vector acquisition unit 520, a fusion feature representation acquisition unit 530, and a parameter adjustment unit 540.
[0113] The training sample acquisition unit 510 is used to acquire a training sample set, which contains geometric domain features and electrical behavior domain features of various types of transistors.
[0114] The feature representation vector acquisition unit 520 is used to input the geometric domain features into the geometric domain encoder to obtain a geometric feature representation vector, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector.
[0115] The fusion feature representation acquisition unit 530 is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score, so as to obtain the fusion feature representation of various types of transistors.
[0116] The parameter adjustment unit 540 is used to input the fused feature representation into the regression predictor to output the predicted value of the transistor electrical parameter, and optimize the parameters of the electrical parameter prediction model through backpropagation based on the error between the predicted value and the corresponding true electrical parameter value until the model converges.
[0117] Since the specific process of model training has been described in detail above, it will not be repeated here.
[0118] Figure 6The diagram shows an exemplary structural schematic of an electrical parameter prediction device for a transistor according to an embodiment of this application. The electrical parameter prediction device 600 of this embodiment is used for the prediction model trained by the training method. Figure 6 As shown, the electrical parameter prediction device 600 includes a feature acquisition unit 610, an encoding unit 620, a feature fusion unit 630, and a parameter prediction unit 640.
[0119] The feature acquisition unit 610 is used to acquire the geometric domain features and electrical behavior domain features of the transistor under test.
[0120] The encoding unit 620 is used to input the geometric domain features into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test.
[0121] The feature fusion unit 630 is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score, so as to obtain the fused feature representation of the transistor under test.
[0122] The parameter prediction unit 640 is used to input the fused feature representation into the regression predictor to output predicted values of transistor electrical parameters.
[0123] Since the specific process of predicting electrical parameters has been described in detail above, it will not be repeated here.
[0124] This disclosure also provides an electronic device 700, such as... Figure 7 As shown, it includes a memory 720, a processor 710, a power supply component 730, a network interface 740, an input / output interface 750, and a program stored in the memory 720 and executable on the processor 710. When the program is executed by the processor 710, it can implement the various processes of the embodiments of the above methods and achieve the same technical effects. To avoid repetition, it will not be described again here.
[0125] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, this disclosure also provides a storage medium storing a computer program or instructions that, when executed by a processor, can implement the various processes of the embodiments of the above methods.
[0126] Since the instructions stored in the storage medium can execute the steps of the method provided in the embodiments of this disclosure, the beneficial effects achievable by the method provided in the embodiments of this disclosure can be realized, as detailed in the preceding embodiments, and will not be repeated here. The specific implementation of each of the above operations can be found in the preceding embodiments, and will not be repeated here.
[0127] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.
Claims
1. A training method for an electrical parameter prediction model for transistors, the electrical parameter prediction model comprising a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the training method comprising: Obtain a training sample set, which contains geometric domain features and electrical behavior domain features of various types of transistors; The geometric domain features are input into the geometric domain encoder to obtain a geometric feature representation vector, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector; The geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. Dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved by calculating the physical perception attention score, resulting in fused feature representations for various types of transistors. Specifically, a first attention score is calculated for each transistor based on the geometric feature representation vector and the electrical behavior feature representation vector. The first attention score is weighted using a geometric sensitivity coefficient and normalized to obtain the physical perception attention score. The value vector of the corresponding transistor is weighted using the physical perception attention score to obtain the fused feature representation of the corresponding transistor. The value vector is obtained by mapping the electrical behavior domain features of the corresponding transistor. The fused feature representation is input into the regression predictor to output predicted values of transistor electrical parameters. Based on the error between the predicted values and the corresponding true electrical parameter values, the parameters of the electrical parameter prediction model are optimized through backpropagation until the model converges.
2. The training method according to claim 1, wherein, The geometric sensitivity coefficient includes a nonlinear term for simulating short-channel effects and a linear enhancement term for reflecting wide device current characteristics.
3. The training method according to claim 2, wherein, The step of weighting and normalizing the first attention score using a geometric sensitivity coefficient to obtain the physical perception attention score includes: The product of the nonlinear term and the linear enhancement term is used as the geometric sensitivity coefficient; The product of the first attention score and the geometric sensitivity coefficient is normalized to obtain the physical perception attention score.
4. The training method according to claim 1, wherein, The acquisition of the training sample set includes: Acquire test data for various types of transistors, including the geometric parameters, electrical response parameters, and corresponding device codes of each transistor; The test data of the transistors are matched based on the device code to construct a complete data record; Generate learnable embedding vectors for each transistor type to identify its process category; Derivative features are constructed for the electrical response parameters of each transistor; Each training sample includes geometric domain features and electrical behavior domain features of the corresponding transistor, and the electrical behavior domain features of the corresponding transistor include derived features of the corresponding transistor.
5. The training method according to claim 1, wherein, The geometric domain features include channel length and channel width, and the electrical behavior domain features include one or more of the following: linear region threshold voltage, saturation region on-state current, and off-state current.
6. A method for predicting electrical parameters of a transistor, applied to an electrical parameter prediction model trained by the training method according to any one of claims 1 to 5, wherein the electrical parameter prediction model includes a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, and the electrical parameter prediction method includes: Obtain the geometric domain characteristics and electrical behavior domain characteristics of the transistor under test; The geometric domain features are input into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and the electrical behavior domain features are input into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test. The geometric feature representation vector and the electrical behavior feature representation vector are input into the cross-domain attention fusion module. By calculating the physical perception attention score, dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain are achieved to obtain the fused feature representation of the transistor under test. A first attention score is calculated for each transistor based on the geometric feature representation vector and the electrical behavior feature representation vector. The first attention score is weighted using a geometric sensitivity coefficient and then normalized to obtain the physical perception attention score. The value vector of the corresponding transistor is weighted using the physical perception attention score to obtain the fused feature representation of the corresponding transistor. The value vector is obtained by mapping the electrical behavior domain feature of the corresponding transistor. The fused feature representation is input into the regression predictor to output predicted values of the transistor electrical parameters of the transistor under test.
7. A training apparatus for a transistor electrical parameter prediction model, the electrical parameter prediction model comprising a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the training apparatus comprising: A training sample acquisition unit is used to acquire a training sample set, which contains geometric domain features and electrical behavior domain features of various types of transistors. The feature representation vector acquisition unit is used to input the geometric domain features into the geometric domain encoder to obtain a geometric feature representation vector, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain an electrical behavior feature representation vector; The fusion feature representation acquisition unit is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score, so as to obtain the fusion feature representation of various types of transistors; A first attention score is calculated for each transistor based on the geometric feature representation vector and the electrical behavior feature representation vector. The first attention score is weighted using a geometric sensitivity coefficient and then normalized to obtain the physical perception attention score. The value vector of the corresponding transistor is weighted using the physical perception attention score to obtain the fused feature representation of the corresponding transistor. The value vector is obtained by mapping the electrical behavior domain feature of the corresponding transistor. The parameter adjustment unit is used to input the fused feature representation into the regression predictor to output the predicted value of the transistor electrical parameter, and optimize the parameters of the electrical parameter prediction model through backpropagation based on the error between the predicted value and the corresponding true electrical parameter value until the model converges.
8. An electrical parameter prediction device for transistors, applied to an electrical parameter prediction model trained by the training method according to any one of claims 1 to 5, the electrical parameter prediction model comprising a geometric domain encoder, an electrical behavior domain encoder, a cross-domain attention fusion module, and a regression predictor, the electrical parameter prediction device comprising: The feature acquisition unit is used to acquire the geometric domain features and electrical behavior domain features of the transistor under test. The encoding unit is used to input the geometric domain features into the geometric domain encoder to obtain the geometric feature representation vector of the transistor under test, and to input the electrical behavior domain features into the electrical behavior domain encoder to obtain the electrical behavior feature representation vector of the transistor under test. The feature fusion unit is used to input the geometric feature representation vector and the electrical behavior feature representation vector into the cross-domain attention fusion module, and realize the dynamic matching and weighted fusion of the geometric domain and the electrical behavior domain by calculating the physical perception attention score to obtain the fused feature representation of the transistor under test; A first attention score is calculated for each transistor based on the geometric feature representation vector and the electrical behavior feature representation vector. The first attention score is weighted using a geometric sensitivity coefficient and then normalized to obtain the physical perception attention score. The value vector of the corresponding transistor is weighted using the physical perception attention score to obtain the fused feature representation of the corresponding transistor. The value vector is obtained by mapping the electrical behavior domain feature of the corresponding transistor. A parameter prediction unit is used to input the fused feature representation into the regression predictor to output predicted values of transistor electrical parameters.
9. An electronic device, comprising: One or more processors; A memory for storing executable instructions, which, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1-6.