A large model driven semiconductor device generation method based on code chain reasoning

Abstract

The application discloses a large model driven semiconductor device generation method based on code chain reasoning, which fundamentally guarantees the high quality of the generated device code in terms of structural integrity, parameter validity and compilability. The method comprises the following steps: step 1, constructing a device code dataset according to a "geometry-contact-doping-grid" code structure chain; step 2, using the data generated in step 1 to supervise the fine-tuning of the model, so that the model learns the semiconductor device preliminarily; and step 3, on the basis of step 2, entering a customized reinforcement learning stage, and the customized reinforcement learning comprises a multi-dimensional reward and punishment mechanism and an incremental learning strategy.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a large model-driven method for generating semiconductor devices based on code chain reasoning. Background Technology

[0002] Technology-Driven Co-optimization (DTCO) and System Technology Co-optimization (STCO) have become central to reducing development costs and shortening development time, driving the urgent need for novel semiconductor devices suitable for advanced process nodes. However, current device development workflows are tightly coupled with commercial technology computer-aided design (TCAD) toolchains, involving labor-intensive steps such as geometry definition, doping, and mesh generation. This process relies on scarce expert knowledge, thus limiting the exploration of the design space and slowing down iteration cycles.

[0003] Therefore, an automated approach is needed to directly generate semiconductor devices from high-level device design intent, reducing development barriers and improving efficiency. Traditionally, engineers write complex and semantically abstract scripts to describe devices. These scripts must strictly adhere to the device's physical structure and constraints; even small errors can lead to structural imbalances, degraded mesh quality, or compilation failures. Furthermore, the logic of the device code is primarily governed by inherent semiconductor characteristics, such as doping distribution and geometric representation, which are highly coupled. This makes manual adjustments extremely challenging. Therefore, the manual approach is not only inefficient but also prone to bias, resulting in unstable device performance, limited reusability, and difficulty in adapting to new process specifications.

[0004] Recent advances in large-scale language models (LLMs) have demonstrated the immense potential of electronic design automation (EDA), providing new insights into automated device generation. These models have been successfully used for hardware description language (HDL) generation and automated design verification code writing by applying supervised fine-tuning (SFT) to general LLMs with specific EDA task cues. They master hardware syntax and gain deep insights into circuit structure, timing constraints, and other complex design requirements. However, the application of LLMs in device generation tasks involving complex physical structures and highly coupled relationships remains in its early stages. The ChatTCAD method employs an SFT training strategy, statically mapping formatted table cues to device coordinates rather than directly generating compilable device code. This rigid mapping paradigm prevents the model from effectively capturing the physical dependencies between parameters, thus limiting its generalization performance when faced with new tasks.

[0005] In summary, current technical methods have the following three main limitations: 1) Semiconductor device samples are limited by the specialization of the field and the privatization of internal databases, leaving very few public datasets available for training and evaluation; 2) Existing models only capture surface-level syntax and basic commands, making it difficult to perform logical analysis on the interrelationships within the physical structure of the device, and the generated code cannot be correctly compiled in real-world scenarios; 3) When applied to device generation tasks, existing training strategies struggle to stably optimize the physical characteristics and structural details of the device, leading to training instability and reduced code reliability.

[0006] Therefore, the present invention aims to solve the following three technical problems:

[0007] (1) How to customize relevant semiconductor device code data so that it can support model optimization and training;

[0008] (2) How to perform logical analysis on the interrelationships within the physical structure of the device so that the generated code can be correctly compiled in a real-world scenario;

[0009] (3) How to design training strategies that can stably optimize the physical characteristics and structural details of the device and improve the reliability of the generated code. Summary of the Invention

[0010] To overcome the shortcomings of existing technologies, the present invention aims to provide a large model-driven method for generating semiconductor devices based on code chain reasoning, so as to fundamentally ensure the high quality of the generated device code in terms of structural integrity, parameter validity and compilability.

[0011] To achieve the above objectives, the following specific technical solutions may be adopted in this application:

[0012] The aforementioned large model-driven semiconductor device generation method based on code chain reasoning includes the following steps:

[0013] Step 1: Construct the device code dataset based on the "geometry-contact-doping-mesh" code structure chain;

[0014] Step 2: Use the data generated in Step 1 to perform supervised fine-tuning of the model, enabling the model to perform initial learning on semiconductor devices;

[0015] Step 3: Building on Step 2, we move into the customized reinforcement learning phase, which includes multi-dimensional reward and punishment mechanisms and incremental learning strategies.

[0016] Furthermore, in step 1, the device code is divided into four stages according to the code structure chain: region definition, contact definition, doping definition, and mesh refinement. In the region definition stage, the geometric structure of the device is designed according to physical constraints to ensure that the shape and size meet the expected performance requirements. In the contact definition stage, the electrical contacts of key regions are defined to ensure the accuracy of the current path and the electrical performance of the device. In the doping definition stage, the doping profile is precisely adjusted through doping configuration to optimize the electrical characteristics of the device. In the mesh refinement stage, the mesh structure is used to ensure that the code conforms to the physical characteristics and is compatible with the subsequent numerical simulation process.

[0017] Furthermore, in step 2, the SFT cold-start Qwen2.5-7B model is adopted. Through the cold-start process, the model is able to understand the basic framework and components of the device code in the initial stage through supervised learning.

[0018] Furthermore, in step 3, the customized reinforcement learning phase includes the following two sub-steps:

[0019] Step 3.1 Multi-dimensional reward and punishment mechanism: The generated device code is evaluated through format rewards, code logic tree matching rewards, and device geometry compilation penalties, thereby promoting model learning and optimization;

[0020] Step 3.2 Incremental learning strategy: Based on the code structure chain of "geometry-contact-doping-mesh", the learning difficulty is gradually increased from "geometry" to "geometry-contact", then to "geometry-contact-doping", and finally to "geometry-contact-doping-mesh".

[0021] Furthermore, the multi-dimensional reward and punishment mechanism includes:

[0022] Format reward: Set according to system prompts;

[0023] Code logic tree matching reward: A reward algorithm based on abstract syntax tree node matching is adopted to evaluate the logical similarity of device code through structure-oriented syntax analysis;

[0024] Device geometry compilation penalty: A visual penalty algorithm based on geometry compilation is adopted to directly evaluate the actual compilation status and geometric fidelity of the two-dimensional device image generated by the compilation script.

[0025] Furthermore, the format reward requires the model to place the reasoning process in a specific location. <think>and< / think> The generated device code is placed in the tag. <answer> and< / answer> Within the tags; in the context of the answer, each structural part is contained separately. <step1> and< / step1> arrive <step4> and< / step4> The labels are used for geometry, contact, doping, and mesh, respectively; 1 point is awarded for correct formatting, otherwise 0 points are awarded.

[0026] Furthermore, the code logic tree matching reward process is as follows: First, comments are removed and parsable macros are expanded to reduce surface differences; then, the AST is recursively constructed from the smallest subexpression, and user-defined names are standardized at the specified parameters of the functions; subsequently, nodes are filtered according to function names, initial calculations are performed by comparing parameter values ​​based on position, and subtree similarities are recursively aggregated using a depth-first matching algorithm; finally, for each branch node in the reference tree, the best match is selected from candidate nodes with the same name in another tree, and the scores of these best matches are averaged to obtain the overall metric.

[0027] Furthermore, the process for compiling the device geometry penalty is as follows: First, the generated device code is input into a commercial automated compilation script and command-line tool to visualize the device structure; then, a standardized 2D image is output; if compilation fails, 0.5 points are deducted from the total score of the current step as a penalty; if successful, subsequent geometric consistency evaluation and structural similarity analysis are performed to ensure the geometric accuracy of the device.

[0028] Furthermore, the incremental learning strategy employs a dynamic threshold triggering mechanism. During the training process, the convergence of the current step is continuously monitored, and the next step is automatically added when the total reward of the current step consistently reaches the preset threshold of 1.8.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] (1) This invention generates high-quality device code that meets TCAD requirements through a four-step inference process and a custom reinforcement learning strategy. The inference process first constructs the geometric framework of the device to ensure that the physical structure of the design meets the requirements; then, the model defines the electrical contact area to ensure the current path and electrical performance of the device; then, the doping profile is precisely configured to control the electrical characteristics of the device; finally, the mesh generation step ensures that the generated device can adapt to subsequent numerical simulation and analysis. Experimental results show that this invention not only achieves a significant improvement in the accuracy of device generation, but also performs well in terms of efficiency, and can quickly generate high-quality device code, providing strong technical support for automated design, process optimization and rapid iteration in the EDA field.

[0031] (2) This invention is based on the overall reasoning paradigm of the “Geometry-Contact-Doping-Mesh” code structure chain, which guides the device generation process step by step to ensure that the design at each stage follows physical and engineering specifications. Attached Figure Description

[0032] Figure 1 This is a flowchart of the method of the present invention;

[0033] Figure 2 The reward and penalty score trends for each step in the experimental examples of this invention are shown in (a) for the geometric region definition stage, (b) for the contact definition stage, (c) for the doping definition stage, and (d) for the mesh refinement stage. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] As shown in Figure 1, the present invention provides a large model-driven semiconductor device generation method based on code chain reasoning, comprising the following steps:

[0036] (a) Step 1: Construct the device code dataset.

[0037] This step constructs data based on a "geometry-contact-doping-mesh" code structure chain. The device's geometry is designed according to physical constraints, ensuring its shape and size meet expected performance requirements. The accuracy of current paths and the device's electrical performance are guaranteed by defining electrical contacts in key areas. The doping profile is precisely adjusted through doping configuration to optimize the device's electrical characteristics. The mesh structure ensures the code conforms to physical properties and is compatible with subsequent numerical simulation processes.

[0038] The construction of the device dataset involved defining the physical structure, materials, electrode contacts, doping, and mesh settings of the devices through proprietary functions in the device code. Specifically, each device is composed of a device code (the terms "device" and "device code" are used interchangeably), which is manually divided into four parts according to the proposed code structure chain rules: region definition, contact definition, doping definition, and mesh refinement. Furthermore, representative device code samples covering typical semiconductor device types were collected from various engineering cases and public databases. The training set includes nine device types, such as MISFET, FeFET, and HEMT, while the test set contains four device types in addition to those in the training set, including MultiValleyMOS and Thyristor. To enhance data diversity and generalization, an automated data augmentation process was designed, including the transformation and combination of key parameters, enabling the samples to cover a wider range of device forms and sizes while maintaining physical validity, thus creating a high-quality yet diverse dataset for both training and testing.

[0039] (ii) Step 2, supervised fine-tuning: Use the data generated in step 1 to perform supervised fine-tuning on the model, so that the model can learn initially about semiconductor devices.

[0040] This step begins by using the data generated in Step 1 to perform supervised fine-tuning of the model, ensuring it grasps the basic syntax and standard format of the device code structure chain. Through this step, the model learns and understands the basic framework of device code, enabling it to generate compliant device code. In this stage, the model will perform preliminary learning on the basic geometry and material distribution of semiconductor devices, laying the foundation for subsequent reinforcement learning.

[0041] This invention employs a SFT cold-start model, Qwen2.5-7B, to ensure it masters the basic syntax and standard format of the device code structure chain. Through this cold-start process, the model can effectively understand the basic framework and components of the device code in the initial stage via supervised learning, thus laying the foundation for subsequent generation tasks. This process involves training the model with a large amount of labeled data, enabling it to accurately capture various patterns and rules in the device code, including key elements such as geometric structure, doping distribution, and electrical contact design. Ensuring the model understands these fundamentals allows it to generate high-quality code that meets design requirements, adhering to the correct format and logical structure, and providing a good starting point for subsequent optimization stages. This cold-start process provides a solid foundation for subsequent reinforcement learning and further model optimization, ensuring the efficiency and accuracy of the entire design process.

[0042] (III) Step 3, Customized Reinforcement Learning: Based on Step 2, we enter the customized reinforcement learning stage, which includes multi-dimensional reward and punishment mechanisms and incremental learning strategies.

[0043] This step optimizes the model through reinforcement learning, combining a unique reward and penalty mechanism with an incremental learning strategy to enhance the model's reasoning ability and further improve the accuracy and efficiency of its generated device code. Furthermore, the application of reinforcement learning enables the model not only to automatically complete basic tasks but also to spontaneously optimize the application of the code structure chain, thereby continuously improving the quality and adaptability of the generated devices. The customized reinforcement learning phase includes the following two sub-steps:

[0044] Step 3.1 Multi-dimensional reward and punishment mechanism: The generated device code is evaluated through format rewards, code logic tree matching rewards, and device geometry compilation penalties, thereby promoting model learning and optimization;

[0045] Step 3.2 Incremental Learning Strategy: Based on the “geometry-contact-doping-mesh” code structure chain, the learning progresses from “geometry” to “geometry-contact”, then to “geometry-contact-doping”, and finally to “geometry-contact-doping-mesh”. By gradually increasing the learning difficulty, the model can improve its performance through continuous adaptation and optimization.

[0046] 1. Regarding the multi-dimensional reward and punishment mechanism

[0047] Learning a static mapping from design description to code without delving into the underlying semiconductor physics limits the model's ability to fit physical properties in the environment, leading to "speculative optimization" behavior. In this behavior, the model sacrifices the accuracy of physical parameters for surface convergence, thus compromising the physical fidelity of the device. Given the strict dependencies between physical parameters, any deviation will be amplified in subsequent development. To explicitly embed physical rules into the learning process, a multi-dimensional reward and penalty mechanism based on code logic trees and device geometry was designed. By combining fine-grained physical constraints, this mechanism ensures the syntactic correctness, physical integrity, and compileability of the generated device code. An independent reward and penalty score is defined for each step:

[0048] ,

[0049] in, , and These represent the format reward, code logic tree matching reward, and device geometry compilation penalty, respectively. Adaptive parameter factors, respectively assigned to , and As their coefficients α, β, θ, and γ, α + β + θ + γ = 1.

[0050] (1) Format rewards ( )

[0051] The format reward is set according to system prompts to ensure the model strictly adheres to the specified output structure and content guidelines. The model is required to place the inference process within... <think> and< / think> The generated device code is placed in the tag. <answer> and< / answer> Within the tags. In the context of the answer, each structural part is contained separately. <step1> and< / step1> arrive <step4> and< / step4> The labels are used for geometry, contact, doping, and mesh, respectively. A correct format earns 1 point; otherwise, 0 points. The scoring formula is:

[0052] ;

[0053] .

[0054] (2) Code logic tree matching reward ( )

[0055] To quantify the logical structural consistency between the generated device code and the reference device code, this application designs a reward algorithm based on Abstract Syntax Tree (AST) node matching. This algorithm evaluates the logical similarity of the device code through structure-oriented syntactic analysis, more realistically reflecting the functional composition and parameter sequence of the device code compared to traditional text similarity algorithms. Specifically, first, comments are removed and parsable macros are expanded to reduce surface differences; then, the AST is recursively constructed from the smallest subexpressions, and user-defined names are standardized at specified parameters of certain functions; to match individual nodes, nodes are filtered according to function names, initial calculations are performed by comparing parameter values ​​based on position, and subtree similarity is recursively aggregated using a depth-first matching algorithm; finally, for each branch node in the reference tree, the best match is selected from candidate nodes with the same name in another tree, and the scores of these best matches are averaged to obtain the overall metric.

[0056] Given a node named n with the function name "name(n)", its parameter sequence is as follows: Its length is P; its subsequence is: The length is K. Define the position parameter match count. Accumulated similarity between positional subtrees as follows: ,

[0057] ,

[0058] in, It is a node and The similarity score between them. When hour, And if name(n) is different, According to the implementation logic of AST structural similarity, when At that time, two branch nodes and Similarity score It can be defined as:

[0059] .

[0060] For the overall structural similarity of the AST, the "reference tree best matching average" strategy was adopted. Let B(T) be the AST " The set of all nodes in the tree is used as the reference tree, and the tree with more branch nodes is selected. The other tree is a reference tree. For each reference branch node ,when Only candidate nodes are considered. The highest score is taken. Final similarity score. It can be defined as:

[0061] ,

[0062] in, represent Quantity; when hour, ; and if ,definition .

[0063] Compared to text similarity, the similarity algorithm in this application is more sensitive to function composition and parameter order, can reflect the reproduction of logical structure in a fine-grained manner, and remains robust to surface changes such as macroscopic expansion, constant folding and variable renaming.

[0064] (3) Compilation penalty for device geometry ( )

[0065] Existing constraints ensure the logical correctness and syntactic compliance of the generated devices, but they cannot further verify the actual compilability of the device code. To address this issue, this application designs a visual penalty algorithm based on geometric structure compilation, which directly evaluates the actual compilation status and geometric fidelity of the 2D device image generated by the compilation script. The algorithm first inputs the generated device code into a commercial automated compilation script and command-line tool to visualize the device structure, and then outputs a standardized 2D image. If compilation fails, 0.5 points are deducted from the total score of the current step as a penalty; if successful, subsequent geometric consistency evaluation and structural similarity analysis are performed to ensure the geometric accuracy of the device.

[0066] A structural similarity index is used to evaluate the geometric similarity of the generated device. Each 2D device image is divided into 16×16 pixel blocks, and a similarity index is calculated based on the local statistical properties of pixels within each block (such as mean, variance, and covariance). This allows comparison of color, shape, and structural differences between the generated and reference device images. The scoring rules are as follows:

[0067] ,

[0068] in, Two-dimensional device images that represent color information Average brightness; The covariance between images that reflect shape and structural information; This represents the variance that reflects the contrast; while These are constants set to 6.5 and 58.5 to prevent division by zero errors.

[0069] Considering the difficulty of compiling device code, and to avoid introducing penalties prematurely that might interfere with early learning, this application only matches reward scores. The visual penalty is activated when the logic tree score reaches 0.5, and terminated at the start of the next training step. This design ensures that the model masters the basic device code logic before compilable constraints are imposed. Visual penalty The calculation method is as follows:

[0070] ;

[0071] .

[0072] 2. Regarding incremental learning strategies

[0073] Considering the strict hierarchical dependencies between optimization objectives in the device generation task, adaptive incremental learning is customized based on the code structure chain. Unlike traditional global and fixed-step training strategies, it employs a dynamic threshold triggering mechanism to achieve autonomous scheduling of training objectives. Specifically, the training process continuously monitors the convergence of the current step, and automatically adds the next step when the total reward of the current step consistently reaches a preset threshold of 1.8. To protect the logic learned in early steps and prevent it from being corrupted in subsequent training, while ensuring optimization balance across all training steps, an adaptive parameter factor is defined for each step. When activating subsequent steps, the corresponding factors dynamically adjust the total score of the current training step, thereby maintaining co-optimization. This design allows for stepwise training along the "geometry-contact-doping-mesh" physical dependency sequence, optimizing local physical features while preventing error propagation during global optimization.

[0074] Define Step Index This indicates the currently active training step. Reward / penalty score. The steps are as follows When querying response The score. Then, the overall loss function. It can be defined as:

[0075] ,

[0076] ,

[0077] in, Representative in steps At that time, for all samples in the same group The corresponding score ; and "clip" represents the current and old strategy models; "clip" represents the clipping operation. It is a hyperparameter set to 0.1. The ultimate learning objective of this method is:

[0078] .

[0079] (iv) Verification Example

[0080] 1. Experimental Details: This invention uses Qwen2.5-7B as the base model, then performs an initial full-parameter SFT for 2 epochs, followed by 10 epochs (1000 steps) of customized RL fine-tuning. During training, the batch size is set to 16, with 8 response samples per group, an initial learning rate of 1e-6, and a weight decay of 0.01. The experiments were conducted on 8 NVIDIA A800 gGPUs using the internal device code dataset, which included 7,943 training pairs and 816 test pairs. Specifically, the SFT stage was performed on a subset of 4,343 samples, while the RL stage was trained using a different set of 3,600 samples.

[0081] 2. Experimental Evaluation Metrics: To comprehensively evaluate the quality of the generated device code, this application employs several domain-specific metrics tailored for device code: BLEU captures syntactic similarity through n-gram matching to assess whether the generated code conforms to the expected structure and format; ROUGE@1 measures the coverage of basic code units through recall, indicating whether necessary functional elements are included even with different wording, thereby assessing the code's completeness; Semantic Similarity (SemSim) calculates the cosine similarity between code vector representations to assess semantic consistency in the generated code; Logical Similarity (LogicSim) analyzes logical consistency through AST matching to ensure the code's logical rationality and expected functionality; CodeBERT uses pre-trained model embeddings to evaluate the semantic alignment between the generated code and the target specification; ModelEval uses Qwen2.5-72B to compare the differences between the generated device code and the reference device code to evaluate quality; ExpertEval provides a comprehensive quality assessment through manual scoring by domain experts, considering compilation pass rate and simulation results.

[0082] 3. Experimental Results:

[0083] (1) Results of the customized reinforcement learning paradigm:

[0084] To comprehensively evaluate the impact of different training strategies on the performance of the code generation model, a comparative experiment was conducted over 10 training epochs using the same dataset, and the best results for each epoch were recorded. Table 1 shows that the customized reinforcement learning training strategy proposed in this application achieves significant advantages in key metrics: compared to standard supervised fine-tuning, it improves the LogicSim metric (evaluating code logical consistency) by 0.495; compared to the current state-of-the-art GRPO method, it also achieves an improvement of 0.207 in the SemSim metric (measuring semantic similarity). Furthermore, in expert evaluation (ExpertEval), the training strategy of this application performs particularly well in terms of code logical rigor and functional correctness. Expert review results show that the model in this application exhibits higher logical consistency and stronger functional accuracy in the generated code, significantly outperforming other training strategies. This indicates that the customized reinforcement learning strategy can not only improve the overall performance of the model but also effectively enhance the reliability and usability of the code.

[0085] Furthermore, Figure 2 illustrates the evolution trend of reward and penalty scores in each training step under customized reinforcement learning training. According to the experimental results, the reward score shows a continuous and stable upward trend, indicating that the model is continuously optimized in each training cycle, gradually improving its performance and generation quality. Simultaneously, the penalty score also gradually rises from negative to positive values. This change reflects the model's continuous reduction in the frequency of error generation during training, demonstrating continuous optimization and convergence. Specifically, the gradual decrease in negative penalty scores indicates that the model can better follow the preset logical and syntactic rules during inference, thereby generating more compliant code. Overall, the evolution trend of reward and penalty scores demonstrates that the optimization strategy of this application not only improves the model's effectiveness but also promotes the stability and consistency of the training process, ultimately driving continuous improvement in the model's performance on the code generation task.

[0086] Table 1. Performance of Qwen2.5-7B on the dataset constructed in this invention using a customized reinforcement learning paradigm and other training strategies.

[0087]

[0088] (2) Result of device code generation:

[0089] This invention was compared with other large-scale code models on a constructed custom dataset, demonstrating its superior performance across multiple metrics. The left side of Table 2 lists the results of large-parameter, closed-source large models accessed via the API. Table 3 shows the best results obtained by the open-source LLM after 10 SFT fine-tunings at the same parameter size (7B). The results show that compared to large-parameter models like GPT-5, this invention improves performance on the SemSim and LogicSim tasks by 0.355 and 0.689 respectively, demonstrating a significant improvement. Compared to the fine-tuned 7B LLM, this invention outperforms StarCoder2 by 0.107 and 0.343 on the CodeBERT and ModelEval metrics respectively, showing equally outstanding performance. Furthermore, while many large models struggle to generate logically sound and compilable device code, this invention outperforms all comparable models by nearly 70% on the ExpertEval metric, which is particularly noteworthy. This demonstrates a significant advantage in physical and functional accuracy, enabling the generation of device code that is difficult for other models to match. These results highlight the unique advantages of this invention in terms of code logic accuracy, execution efficiency, and generation quality, demonstrating its superior performance and strong generalization ability in complex design tasks.

[0090] In terms of performance, this application also deployed a fine-tuned model locally and compared the inference time of a single sample on a single NVIDIA A800 GPU. The results show that the present invention generates more accurate devices in a shorter inference time, reducing the inference time by nearly 19 seconds compared to Deepseek-Coder. It was observed that the inference process of the baseline model is typically long and mostly invalid or incorrect, while the present invention effectively avoids invalid inference paths and reduces unnecessary computation by learning reasonable code structure chains, significantly improving inference efficiency. This optimization allows the present invention to not only surpass other models in code generation quality but also gain advantages in computational efficiency and response time.

[0091] Table 2 reports the test results of calling the API for different non-open-source models in the dataset.

[0092]

[0093] Table 3 reports the test results of different open-source models after supervised fine-tuning in the dataset.

[0094]

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A large model-driven method for generating semiconductor devices based on code chain reasoning, characterized in that, Includes the following steps: Step 1: Construct the device code dataset based on the "geometry-contact-doping-mesh" code structure chain; Step 2: Use the data generated in Step 1 to perform supervised fine-tuning of the model, enabling the model to perform initial learning on semiconductor devices; Step 3: Building upon Step 2, proceed to the customized reinforcement learning phase. This phase includes a multi-dimensional reward and punishment mechanism and an incremental learning strategy. The customized reinforcement learning phase comprises the following two sub-steps: Step 3.1 Multi-dimensional reward and punishment mechanism: The generated device code is evaluated through format rewards, code logic tree matching rewards, and device geometry compilation penalties, thereby promoting model learning and optimization; Step 3.2 Incremental learning strategy: Based on the "geometry-contact-doping-mesh" code structure chain, the learning difficulty is gradually increased from "geometry" to "geometry-contact" to "geometry-contact-doping" and finally to "geometry-contact-doping-mesh".

2. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 1, characterized in that, In step 1, the device code is divided into four stages according to the code structure chain: region definition, contact definition, doping definition, and mesh refinement. In the region definition stage, the geometric structure of the device is designed according to physical constraints to ensure that the shape and size meet the expected performance requirements. In the contact definition stage, the electrical contacts of key regions are defined to ensure the accuracy of the current path and the electrical performance of the device. In the doping definition stage, the doping profile is precisely adjusted through doping configuration to optimize the electrical characteristics of the device. In the mesh refinement stage, the mesh structure is used to ensure that the code conforms to the physical characteristics and is compatible with the subsequent numerical simulation process.

3. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 1, characterized in that, In step 2, the SFT cold-start Qwen2.5-7B model is used. Through the cold-start process, the model can understand the basic framework and components of the device code in the initial stage through supervised learning.

4. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 1, characterized in that, The multi-dimensional reward and punishment mechanism includes: Format reward: Set according to system prompts; Code logic tree matching reward: A reward algorithm based on abstract syntax tree node matching is adopted to evaluate the logical similarity of device code through structure-oriented syntax analysis; Device geometry compilation penalty: A visual penalty algorithm based on geometry compilation is adopted to directly evaluate the actual compilation status and geometric fidelity of the two-dimensional device image generated by the compilation script.

5. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 4, characterized in that, Formatted reward requirements require the model to place the reasoning process in <think> and< / think> The generated device code is placed in the tag. <answer> and< / answer> Within the tags; in the context of the answer, each structural part is contained separately. <step1> and arrive <step4> and The labels are used for geometry, contact, doping, and mesh, respectively. 1 point for correct format, otherwise 0 points.

6. The method for generating semiconductor devices driven by code chain reasoning according to claim 4, characterized in that, The code logic tree matching reward process is as follows: First, comments are removed and parsable macros are expanded to reduce surface differences; then, the AST is recursively constructed from the smallest subexpression, and user-defined names are standardized at the specified parameters of the functions; next, nodes are filtered according to function names, initial calculations are performed by comparing parameter values ​​based on position, and subtree similarity is recursively aggregated using a depth-first matching algorithm; finally, for each branch node in the reference tree, the best match is selected from candidate nodes with the same name in another tree, and the scores of these best matches are averaged to obtain the overall metric.

7. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 4, characterized in that, The process for compiling device geometry penalties is as follows: First, the generated device code is input into a commercial automated compilation script and command-line tool to visualize the device structure; then, a standardized 2D image is output; if compilation fails, 0.5 points are deducted from the total score of the current step as a penalty; if successful, subsequent geometric consistency evaluation and structural similarity analysis are performed.

8. The method for generating semiconductor devices based on code chain reasoning driven by a large model according to claim 1, characterized in that, The incremental learning strategy employs a dynamic threshold triggering mechanism. During the training process, the convergence of the current step is continuously monitored. When the total reward of the current step consistently reaches the preset threshold of 1.8, the next step is automatically added.

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