Network connectivity determination method for integrated circuit, computer device and storage medium

Abstract

The application provides a network connectivity judgment method of an integrated circuit, a computer device and a storage medium, and the method comprises the following steps: extracting design data of the integrated circuit from a design file; constructing a geometric polygon of each geometric object based on a central axis of the geometric object; constructing a correspondence data set of the network data set and the polygon; obtaining a source geometric object and a target geometric object to be judged for connectivity; adding geometric objects intersecting with the geometric polygon of the source geometric object on a wiring network to a source correspondence data set; performing iterative calculation on the newly added geometric objects until no new geometric object intersecting with the geometric polygon of the source geometric object is searched; and judging whether any geometric object of a target correspondence data set exists in the source correspondence data set, and if yes, confirming that the source geometric object and the target geometric object are connected. The computer device and the storage medium can realize the above method. The application has less calculation and high calculation efficiency.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit design, specifically to a method for determining the network connectivity of an integrated circuit, and a computer device and computer-readable storage medium for implementing this method. Background Technology

[0002] With the rapid development of Virtual Large Scale Integration (VLSI), the transistor density and circuit density within integrated circuits have increased rapidly, with high-end chips already boasting transistor integration levels in the hundreds of billions. Simultaneously, to accelerate the development of VLSI, mature, off-the-shelf functional modules from specific fields are extensively used during the chip design and development phases to shorten the overall R&D cycle of integrated circuit projects. For example, high-end chips used in industries such as artificial intelligence, 5G communication, and the Internet of Things have already reached an integration level of 100 billion transistors. Therefore, existing high-end chip designs heavily reuse mature IP cores and employ extremely complex internal wiring.

[0003] In integrated circuit design, it is often necessary to determine whether certain wirings are connected to other wirings, which is called connectivity testing. Existing connectivity testing methods usually rely on graph traversal algorithms such as recursion or depth / breadth-first search. These algorithms need to search in large-scale graph structures, and their computational time complexity is high. When the scale of integrated circuits reaches a certain level, the connectivity testing time becomes very long, often unacceptable, and becomes a bottleneck in integrated circuit design.

[0004] Currently, the connectivity assessment of integrated circuit internal networks faces several challenges: First, there is a lack of efficient methods for connectivity assessment; second, there is a lack of efficient methods for assessing the connectivity between the internal network of an integrated circuit and the network of functional modules; and third, each functional module or IP core has its own network name and identifier, resulting in inconsistencies in the network naming of integrated circuits, which leads to high complexity in global LVS (Logic Versus Schematic) verification or network connectivity assessment. Summary of the Invention

[0005] The primary objective of this invention is to provide a network connectivity determination method for integrated circuits that can effectively reduce the complexity of connectivity determination and improve its efficiency.

[0006] A second objective of this invention is to provide a computer device for implementing the network connectivity determination method of the aforementioned integrated circuit.

[0007] A third objective of this invention is to provide a readable storage medium for implementing the network connectivity determination method of the aforementioned integrated circuit.

[0008] To achieve the first objective of this invention, the method for determining the network connectivity of an integrated circuit provided by this invention includes: acquiring the design file of the integrated circuit and extracting the design data of the integrated circuit from the design file; constructing a global coordinate system of the integrated circuit based on the coordinate system of the design file, transforming the coordinates of each functional module of the integrated circuit to the global coordinate system, and constructing geometric polygons of the geometric objects based on the central axis of each geometric object; constructing a network dataset of the correspondence between various networks, functional modules, components, and pins within the integrated circuit, and constructing a dataset of the correspondence between the wiring network within the integrated circuit and the polygons of the elements constituting the wiring network; acquiring the source geometric object and the target geometric object whose connectivity is to be determined, and identifying geometric polygons within the search interval constructed by the network where the source geometric object is located that intersect with the geometric polygons of the source geometric object. Objects are added to the source correspondence dataset. Iterative calculations are performed on newly added geometric objects until no new geometric objects with intersections are found. Furthermore, geometric objects that intersect with the geometric polygons of the target geometric object on the wiring network within the search interval constructed by the target geometric object are added to the target correspondence dataset. Iterative calculations are performed on newly added geometric objects until no new geometric objects with intersections are found. It is then determined whether any geometric object in the target correspondence dataset exists in the source correspondence dataset. If so, the source and target geometric objects are confirmed to be connected; otherwise, it is determined whether any geometric object in the source correspondence dataset exists in the target correspondence dataset. If so, the source and target geometric objects are confirmed to be connected; otherwise, the source and target geometric objects are confirmed to be disconnected.

[0009] As can be seen from the above scheme, this invention transforms geometric objects into geometric polygons within an integrated circuit, constructs a source correspondence dataset for wiring routes based on these geometric polygons, and iteratively searches for geometric objects within the integrated circuit that intersect with the geometric polygons of the geometric objects, adding the found geometric objects to the source correspondence dataset. When performing connectivity checks, it is only necessary to determine whether any geometric object in the target correspondence dataset exists in the source correspondence dataset, or further, whether any geometric object in the source correspondence dataset exists in the target correspondence dataset. The overall computational load is low, improving the efficiency of connectivity checks.

[0010] Furthermore, this invention determines the connection relationship between two geometric objects by considering whether there is an intersection between their geometric polygons. Specifically, it can be implemented using Boolean AND operations, which requires less computation and can further improve the efficiency of connectivity determination.

[0011] A preferred approach is to add geometric objects on the wiring network that intersect with the geometric polygons of the source geometric object to the source correspondence dataset by: constructing a search region centered on the central axis of the source geometric object, finding intersecting geometric objects in the search region, and adding the found geometric objects to the source correspondence dataset.

[0012] Therefore, by constructing a search region, the search range for whether two geometric objects intersect can be clearly defined, thus providing a stable computational basis for subsequently determining whether two geometric objects intersect through Boolean AND operations.

[0013] A further approach involves constructing a search region centered on the central axis of the source geometry object. This includes: constructing a search region centered on the central axis of the source geometry object, with one side width being the sum of the minimum interval between wiring centerlines and the minimum width between the edges of the geometry object.

[0014] Therefore, the above method can quickly calculate the search area, and the constructed search area is of appropriate range, thus enabling accurate calculation of whether two geometric objects intersect.

[0015] A further approach is to determine the extension direction of the search area based on the routing direction of the source geometric object when constructing the search area centered on the central axis of the source geometric object.

[0016] Therefore, the extension direction of the search area is consistent with the routing direction of the source geometric object, which can ensure that the search area can accurately reflect the routing of the geometric object and provide the necessary basis for determining the scope of the search area.

[0017] A further approach involves finding intersecting geometric objects within the search region by performing Boolean operations on the geometric objects in the derived search region and the geometric objects whose vertices fall within the search region.

[0018] A further approach is to construct the geometric polygon of the geometric object based on the central axis of each source geometric object, which also includes: shaping the ends of the wiring path so that the ends of the wiring path form a preset shape.

[0019] Therefore, by shaping the ends of the wiring path, a standardized polygon for geometric connectivity analysis can be accurately generated, providing a key solution to bridge the gap between path-based design data and polygon-based analysis algorithms.

[0020] A further approach involves shaping the ends of the wiring path by setting a square at the end of the wiring path, centered on the endpoint of the wiring path and with the width of the wiring path as its side length, as the end of the geometric polygon.

[0021] Therefore, forming a square end at the end of the wiring path in a simple way can simplify the computation of end shaping. On the other hand, the square end is closer to the shape of the geometric polygon and is closer to the actual structure of the integrated circuit, thus accurately calculating the intersection probability between geometric objects.

[0022] A further approach is to add geometric objects that intersect with the geometric polygons of the source geometric object on the wiring network to the source correspondence dataset. The wiring network being searched includes geometric polygons within the search area that are located on the same or adjacent layers as the wiring network of the source geometric object and have intersections with it.

[0023] Therefore, searching only non-network geometric polygons that are on the same or adjacent layers as the wiring network of the source geometric object and have intersections with it, rather than searching all geometric polygons in the integrated circuit, can quickly complete the geometric polygon search and more effectively search the geometric polygons within the effective range, resulting in more accurate search results.

[0024] To achieve the second objective described above, the computer device provided by the present invention includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the various steps of the network connectivity determination method of the integrated circuit described above.

[0025] To achieve the third objective mentioned above, the storage medium provided by the present invention stores a computer program, which, when executed by a processor, implements each step of the network connectivity determination method for the aforementioned integrated circuit. Attached Figure Description

[0026] Figure 1 This is a flowchart of an embodiment of the network connectivity determination method for integrated circuits of the present invention.

[0027] Figure 2 This is a schematic diagram of the end of a geometric polygon in an embodiment of the network connectivity determination method for integrated circuits of the present invention.

[0028] Figure 3 This is a schematic diagram of constructing the search region in an embodiment of the network connectivity determination method for integrated circuits of the present invention.

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0030] The integrated circuit network connectivity determination method of the present invention is used to determine the connectivity between different functional modules, IP cores, pads, signal network links, and power distribution network links within an integrated circuit during the integrated circuit design stage. Specifically, it analyzes the connectivity between wiring networks and geometric objects to determine whether there are electrical connections between specific wiring networks and geometric objects, thereby ensuring that the integrated circuit design meets pre-defined requirements. The method of the present invention can be implemented on a computer device having a processor and a memory. The memory is a readable storage medium of the present invention, storing a computer program. When the computer program is executed by the processor, it can implement the aforementioned integrated circuit network connectivity determination method.

[0031] Example of a method for determining network connectivity of integrated circuits: In integrated circuit design, it is often necessary to determine the connectivity between design elements such as routing networks, routing paths, design pads, and links. For example, in an integrated circuit design file, if two routing networks need to be electrically connected or electrically isolated, it is necessary to analyze the connectivity between these two routing networks to determine whether a connection exists. This embodiment implements connectivity analysis between routing networks through a simple calculation method to improve the computational efficiency of connectivity determination.

[0032] See Figure 1 This implementation first executes step S1 to obtain the integrated circuit design file, including various definition library files and layout files of the integrated circuit. It then extracts the integrated circuit design data from the design file, such as the definition of wiring networks, the definition of various functional devices, and the geometric shape definition of metal layers in the layout. The geometric shape definition of metal layers in the layout mainly includes two data types: "wiring path" and "polygon". In step S1, only the geometry of the current metal layer and via layer of the integrated circuit is read in.

[0033] Then, step S2 is executed to construct the global coordinate system of the integrated circuit and perform unified modeling of geometric data. Specifically, the global coordinate system of the entire integrated circuit is constructed based on the coordinate system of the integrated circuit design file, thereby determining the origin of the global coordinate system. Then, the coordinates of the functional modules of the integrated circuit are transformed into this global coordinate system. For example, if a functional module is IP core A, and the coordinates of the lower left vertex and upper right vertex of IP core A in the global coordinate system of the integrated circuit are (x1, y1) and (x2, y2) respectively, then in step S2, the coordinates of all geometric objects in IP core A need to be transformed into the global coordinate system. That is, using the coordinates (x1, y1) and (x2, y2) as a reference, the coordinates of all geometric objects in IP core A are translated. Of course, if IP core A is not arranged in the same direction within the integrated circuit, rotation transformation is also required. For example, if IP core A is a long strip module with a horizontal layout, but the integrated circuit is vertically laid out, then rotation calculation is also required during coordinate transformation.

[0034] The coordinate changes mentioned above mainly apply to the two-dimensional direction. For three-dimensional stacked chips, the coordinates in the z-axis direction are also involved. Typically, the bottom layer of the lowest entity in the design model file is taken as the first layer of the global model, which is the lowest layer in the z-axis direction, usually defined as z=0. Since most geometric objects in integrated circuit design can be called polygons, when performing connectivity checks, the model only includes geometric objects such as metal layers and via layers, ignoring geometric objects of non-conductive materials like polysilicon.

[0035] Then, based on the central axis of the geometric object, a geometric polygon is constructed. Since the design documents for each layer of metal conductors in an integrated circuit are often described as polygons, and wires may also be described as paths, when constructing the geometric polygon of the geometric object, it is necessary to obtain the width information of the traces in each layer from the process definition, that is, to obtain the width W of the routing path in that layer. Interconnect structures in layout design are usually stored in the form of "routing paths" and "geometric objects," with the core data being the central axis coordinates and width. Typically, the central axis coordinates only include the coordinates of the endpoints of the central axis. For accurate geometric connectivity analysis, this embodiment needs to convert all routing paths into standard geometric polygons.

[0036] The specific conversion method is as follows: For a given routing path, the central axis is defined by a series of endpoints, including the start and end points of the routing path and the endpoints at intermediate bends. Routing paths on the same layer have a uniform width W, while routing paths across layers may have different widths. For each segment of the central axis, based on the direction of the segment (horizontal, vertical, or diagonal) and the width of the routing path, the boundary of the corresponding geometric polygon can be calculated. Specifically, by offsetting half the width of the routing path on both sides of the normal of the central axis segment, a closed polygon enclosing the routing path segment is generated. Typically, this polygon is a rectangle, that is, the region centered on the central axis segment, with the width of the routing path being the width of the rectangle.

[0037] In addition, the start and end points of wiring paths, such as the ends of wires and via connections, require shaping. For example, the start and end points of the wiring path can be shaped into semi-circular or square ends to ensure sufficient geometric overlap with other polygons at the connection points, thereby accurately representing electrical connectivity. Taking a square end as an example, at the end of the geometric polygon, a square is designed with the endpoint of the central axis as the center and the width of the wiring path as the side length. In this way, the start and end points of the constructed geometric polygon form a square end, which is defined by four vertices, namely the four vertices of the square mentioned earlier.

[0038] Finally, after converting each segment of all wiring paths into geometric polygons, these polygons are incorporated into a unified dataset along with the original polygon data in the integrated circuit design file to facilitate subsequent processing. This approach transforms abstract cable data into concrete geometric shapes that can be used for Boolean AND operations, laying the foundation for subsequent high-precision connectivity analysis.

[0039] See Figure 2 Assuming the coordinates of the starting and ending points of a central axis 13 are (X1, Y0) and (X2, Y0) respectively, and the width of the wiring path is W, then when constructing the geometric polygon, we first expand the "segment portion" based on the central axis. That is, along the normal direction (i.e., the perpendicular direction) of the central axis, we translate the wiring path width by half, i.e., W / 2, to both sides of the central axis, thus obtaining a rectangular polygonal pattern 11. The coordinates of the four vertices of the obtained rectangular polygonal pattern 11 are: the lower left corner is (X1, Y0-W / 2), the lower right corner is (X2, Y0-W / 2), the upper right corner is (X2, Y0+W / 2), and the upper left corner is (X1, Y0+W / 2). At this point, the wiring path has changed from a line to a rectangular plane.

[0040] Then, the start and end points of the routing path are reshaped, that is, a square end is added to the start and end points of the routing path. In this embodiment, taking the start point 14 as an example, assuming that the coordinates of the start point 14 are (X1, Y0), the end is constructed as a square with the start point 14 as the center and the width W of the routing path as the side length. This square has four vertices 15. Similarly, an end is constructed in the same way for the end point of the routing path. At this point, the construction of the geometric polygon of the routing path is completed. After obtaining the two ends of the start and end points, it is also necessary to record the coordinates of the eight vertices 15 of the two ends at the start and end points into the vertex sequence of the geometric polygon corresponding to the routing path. At this time, the routing path is finally transformed into a complex polygon composed of more vertices, instead of a simple rectangle containing four vertices, but a complex rectangle containing multiple vertices at the ends. At this point, step S2 is completed.

[0041] Next, step S3 is executed to construct the data structure of the search algorithm, which provides a basis for subsequent Boolean AND operations on geometric objects at each layer, simplifies geometric design, and reduces the number of geometric polygons.

[0042] Specifically, data cleaning and processing are required based on the design documents defined in steps S1 and S2 to construct the data structure for the search algorithm. First, the correspondence between the IP IDs of each functional module within the integrated circuit, the pins of functional devices (or functional modules) within the chip, and the wiring network is constructed, thereby creating a two-dimensional dataset. The columns of this dataset include: NETID (wiring network ID), IP ID (functional module ID), Component ID (component ID), and ComponentPIN (component pin). Each row of this dataset contains the specific values ​​of the aforementioned correspondences. The constructed dataset is shown in Table 1. Here, NET ID is a global network identifier that includes the IP ID, and a separate IP ID column is used for fast retrieval.

[0043] Table 1

[0044] Table 1 clearly shows the data correspondence between the wiring network, each functional module (IP), each component, and its corresponding pins. This helps resolve issues related to overall and local data consistency, as well as the hierarchy and network attribution of geometric objects—specifically, the network attribution of main chip pins, module pins, and device pins. These datasets provide the necessary foundation for subsequent search operations.

[0045] Then, a mapping dataset of wiring networks and the polygons that make up the wiring network is constructed. The columns of the mapping dataset include NET ID, IP ID, and Polygon ID, and the data of each geometric polygon is recorded. The constructed mapping dataset is shown in Table 2. The mapping data of wiring networks and corresponding geometric objects stored in Table 2 can solve the problem of mapping wiring networks to geometric objects.

[0046] Table 2

[0047] There are two sources of geometric polygons: one is the geometric polygons directly defined in the design file, and the other is the geometric polygons constructed by the method in step S2 above, which is the geometric polygons generated from the centerline and width information.

[0048] Next, the relationship between the Polygon ID of the polygon and the coordinates of each vertex is constructed, thereby constructing a data set of polygon and vertex coordinates. The columns of the table of this data set include Polygon ID, X, Y, and Z; where Polygon ID is the polygon ID, and X, Y, and Z are the coordinate values ​​in the global coordinate system. For each vertex of each polygon, a row is used for data storage, as shown in Table 3 below.

[0049] Table 3

[0050] This allows for the extraction of coordinate information from the published drawing, including vertex information of the original polygons and the geometric polygons generated by the wiring paths. Storing the correspondence between geometric objects and their coordinates in Table 3 solves the problem of matching geometric objects with their descriptive coordinates.

[0051] Next, chip design model data modeling is performed. Based on the unified coordinate system and simplified and merged geometric design data mentioned above, an identification system for geometric objects is defined from macroscopic to microscopic. Specifically, an identification system for each geometric polygon in the layout is defined, using the following string as the unique identifier for the polygon: (Polygon ID): Layer ID, Z; X1, Y1; X2, Y2; X3, Y3..., where Layer ID is the global layer identifier containing chip information in the design definition file, Z is the height coordinate of that layer, and Xi, Yi (i = 1,2,3, …) are the planar coordinates of each vertex of the geometric polygon.

[0052] Next, the layer information of the design library is constructed as shown in Table 4 below. The columns of Table 4 include Layer ID (layer name), direction (routing direction), Pitching (minimum spacing between routing center lines) and Spacing (minimum width between the edges of different metal traces).

[0053] Table 4

[0054] Then, a network connectivity search algorithm based on geometric relationships is applied to find geometric polygons that intersect. Specifically, in step S4, for the two geometric objects whose connectivity needs to be determined, for example, designated as the source geometric object and the target geometric object respectively, the original correspondence dataset corresponding to the source geometric object is first constructed. For example, another geometric object that intersects with the geometric polygon of the source geometric object on the wiring network is searched, and the geometric object obtained from the search is added to the wiring network and polygon correspondence dataset, that is, added to the source correspondence dataset.

[0055] Specifically, to determine whether two geometric objects intersect, we can check if there is an intersection between the corresponding geometric polygons of the two objects. This can be done using standard geometric Boolean operations, specifically a Boolean AND operation. If the Boolean AND operation returns an empty value, it means the two geometric objects do not intersect. If the Boolean AND operation returns a non-empty value, it means the two geometric objects intersect, indicating that the metal conductor is conductive.

[0056] For example, for a given target geometry, the corresponding polygon needs to have its layer number (LayerID) determined. Then, the direction of the routing in that layer (e.g., horizontal or vertical) is obtained from the dataset shown in Table 4. Additionally, data on Pitching (minimum spacing between routing centerlines) and Spacing (minimum width between edges of different metal traces) are also obtained. Based on this data, a search region for the target geometry is constructed. See also... Figure 3 Assuming the target geometric object 21 has a start point 22 and an end point 23, and an adjacent geometric object 25 is arranged beside it, then the minimum interval between the wiring center lines is: Figure 3 In D2, the minimum width between the edges of different metal traces is Figure 3In D1, when constructing the search area, a search area is constructed with the central axis of the geometric object as the center and the sum of the pitching and spacing of the wiring in that layer as one side width. Assuming that the X-axis coordinate of the central axis of the target geometric object 21 is X0, the range of the horizontal coordinate of the search area is -(Pitching + Spacing) ≤ X0 ≤ (Pitching + Spacing), and the range of the vertical coordinate is the same as the vertical coordinate of the start and end points of the target geometric object 21.

[0057] Then, on the source correspondence dataset, search for geometric polygons that satisfy the x-coordinate range of -(Pitching + Spacing) ≤ X0 ≤ (Pitching + Spacing), and obtain multiple vertices of these geometric polygons to obtain a vertex dataset, denoted as {p1,..pk,..pn}, (1≤k≤n). The set of geometric polygons to which these points belong is denoted as {P1,..Pk,..,Pn}, (1≤k≤n). Among them, the polygon data relationship dataset shown in Table 3 has three entities. The first entity is the global polygon entity that loads the polygon coordinates and other information of the polygons in the design file and the polygon coordinates converted from the wiring path when importing the design file. This entity is used for searching geometric objects. Another entity is the coordinate information of the geometric objects that are found to have intersections in the tree search starting from the source geometric object. The third entity is the entity of the search record dataset expanded by the target geometric object whose connectivity is to be determined.

[0058] Suppose the geometric polygon of the t-th source geometric object in a wiring network N(x) is PP(t). Then, perform Boolean AND operations between the vertex dataset from the above results and the geometric polygon PP(t). If the geometric polygon Pk (1≤k≤n) intersects with the geometric polygon PP(t), then add the geometric polygon Pk to the source correspondence dataset. This process is iterated until new geometric polygons with intersections are found. If new geometric polygons with intersections are found, they are added to the source correspondence dataset one by one using the search method described above, until no new geometric polygons with intersections are found.

[0059] The above method constitutes a recursive tree-like search process, which means that new geometric objects found during the search process that intersect with the previous geometric object through geometric Boolean operations are added to the source correspondence dataset until no new geometric objects with intersections are found.

[0060] Then, proceed to step S5, using the same method as step S4 to construct the target correspondence dataset. The specific construction process will not be described in detail here.

[0061] Next, step S6 is executed to determine whether any geometric object from the target mapping dataset can be found in the source mapping dataset. If found, step S8 is executed to confirm that the source and target geometric objects are connected. If not found, step S7 is executed to determine whether any geometric object from the source mapping dataset can be found in the target mapping dataset. If found, step S8 is executed to confirm that the source and target geometric objects are connected. If not found, step S9 is executed to confirm that the source and target geometric objects are not connected.

[0062] As can be seen, this invention, through precise wiring path to geometric polygon reconstruction technology, clarifies the connectivity of the wiring network within the integrated circuit, thereby optimizing the overall wiring scheme of the integrated circuit. The optimization of the wiring scheme is achieved by merging connected wiring networks, reducing the number of wirings, and shortening the trace distance.

[0063] In addition, the present invention can improve the signal quality of integrated circuits. Based on the optimized routing scheme, it can improve the signal transmission quality by using fewer wirings and better routing distances, reduce the latency of high-frequency signals, reduce the energy attenuation of signal transmission, reduce crosstalk between different signals, and improve the overall signal quality.

[0064] Finally, the present invention can improve the efficiency of logic processing of integrated circuits. The present invention can achieve shorter signal delay and signal energy attenuation, and less signal crosstalk can greatly reduce the signal transmission error rate, avoid repeated calculations and signal transmission, thereby improving the overall processing efficiency of integrated circuits.

[0065] Computer device embodiment: The computer device in this embodiment can be a desktop computer or a data center or data station. It has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above-described information processing method. When the processor executes the computer program, it implements each step of the network connectivity determination method of the above-described integrated circuit.

[0066] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to complete the various modules of the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.

[0067] The processor referred to in this invention can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting various parts of the terminal device through various interfaces and lines.

[0068] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0069] Storage medium examples: If a computer program stored in a computer device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the various steps of the network connectivity determination method of the above integrated circuit.

[0070] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in computer-readable media can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0071] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Methods for determining network connectivity of integrated circuits, including: Obtain the design documents of the integrated circuit and extract the design data of the integrated circuit from the design documents; Its features are: Based on the coordinate system of the design file, a global coordinate system for the integrated circuit is constructed. The coordinates of each functional module of the integrated circuit are transformed to the global coordinate system, and the geometric polygons of the geometric objects are constructed based on the central axis of each geometric object. Construct a network dataset showing the correspondence between various networks, functional modules, components, and pins within the integrated circuit, and construct a dataset showing the correspondence between the wiring network within the integrated circuit and the polygons that make up the elements of the wiring network. The polygons include geometric polygons directly defined in the design file and geometric polygons generated by the centerline and width information. Obtain the source and target geometric objects whose connectivity needs to be determined. Add geometric objects that intersect with the geometric polygons of the source geometric object within the search interval constructed by the network where the source geometric object is located to the source correspondence dataset. Iterate and calculate for the newly added geometric objects until no new geometric objects with intersections are found. Similarly, add geometric objects that intersect with the geometric polygons of the target geometric object on the wiring network within the search interval constructed by the network where the target geometric object is located to the target correspondence dataset. Iterate and calculate for the newly added geometric objects until no new geometric objects with intersections are found. Determine whether any geometric object in the target correspondence dataset exists in the source correspondence dataset. If yes, confirm that the source geometric object and the target geometric object are connected. Otherwise, determine whether any geometric object in the source correspondence dataset exists in the target correspondence dataset. If yes, confirm that the source geometric object and the target geometric object are connected. Otherwise, confirm that the source geometric object and the target geometric object are not connected. To determine whether two geometric objects intersect, use the Boolean AND operation. Constructing the geometric polygon of the geometric object based on the central axis of each geometric object also includes: setting a square with the endpoint of the wiring path as the center and the width of the wiring path as the side length at the end of the wiring path, so that the end of the wiring path forms a preset shape.

2. The method for determining network connectivity of integrated circuits according to claim 1, characterized in that: Adding geometric objects that intersect with the geometric polygons of the source geometric object within the search interval constructed by the network containing the source geometric object to the source correspondence dataset includes: Construct a search region centered on the central axis of the source geometric object, find intersecting geometric objects within the search region, and add the found geometric objects to the source correspondence dataset.

3. The method for determining network connectivity of integrated circuits according to claim 2, characterized in that: Constructing the search region centered on the central axis of the source geometry includes: Construct a search region centered on the central axis of the source geometry, with the sum of the minimum interval between wiring centerlines and the minimum width between the edges of the geometry as one side width.

4. The method for determining network connectivity of integrated circuits according to claim 3, characterized in that: When constructing a search region centered on the central axis of the source geometric object, the extension direction of the search region is determined based on the routing direction of the source geometric object.

5. The method for determining network connectivity of integrated circuits according to claim 2, characterized in that: Finding intersecting geometric objects within a search region involves performing Boolean operations on geometric objects in the derived search region and geometric objects whose vertices fall within the search region.

6. The method for determining the network connectivity of an integrated circuit according to any one of claims 1 to 5, characterized in that: When adding geometric objects that intersect with the geometric polygons of the source geometric object within the search range constructed by the network of the source geometric object to the source correspondence dataset, the wiring network being searched includes: geometric polygons within the search range that are located on the same layer or adjacent layer as the wiring network of the source geometric object and have intersection with it.

7. A computer device, characterized in that, It includes a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the various steps of the network connectivity determination method for an integrated circuit as described in any one of claims 1 to 6.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements each step of the network connectivity determination method for integrated circuits as described in any one of claims 1 to 6.

Images