A method, apparatus, and storage medium for improving the data retention capability of NOR Flash chips.

Abstract

This application provides a method, apparatus, and storage medium for improving the data retention capability of NOR Flash chips. Applied to the field of semiconductor integrated circuit technology, the method involves performing read operations and verification calculations on the storage cells of the NOR Flash chip. When a correctable single-bit error is detected, and the error type is a transition from a first logic state to a second logic state, the target location information of the erroneous storage cell is determined. Based on this location information, a programming operation is performed on the storage cell to restore the data from the second logic state to the first logic state. This proactively repairs the physical degradation of the storage cell, fundamentally improving the data retention capability of the NOR Flash chip and preventing data from ultimately failing due to long-term degradation. It has the advantage of being able to proactively detect and repair the physical degradation of NOR Flash chip storage cells, fundamentally improving data retention capability and preventing data from ultimately failing due to long-term degradation.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a method, apparatus and storage medium for improving the data retention capability of NOR Flash chips. Background Technology

[0002] NOR Flash chips, as a type of non-volatile memory, are widely used in embedded systems, IoT devices, and automotive electronics due to their fast write / erase speeds, high reliability, and strong data retention capabilities. With the continuous expansion of their application scenarios, higher demands are placed on the data reliability and data retention capabilities of NOR Flash chips. To improve data reliability, existing technologies typically incorporate Error Checking and Correction (ECC) algorithms into NOR Flash chips. This ECC algorithm can verify and correct errors when reading data from NOR Flash memory cells, thus providing error-corrected data to the user. Currently, widely used ECC algorithms can typically correct single-bit (1-bit) errors and detect double-bit (2-bit) errors.

[0003] The principle of ECC error correction is that after reading the data and checksum from the storage unit, the ECC algorithm is used for calculation. If a single-bit error is detected, the ECC algorithm can locate and correct the error, thus obtaining the correct data. However, if a double-bit or more bit error is detected, although the ECC algorithm can indicate the presence of an error, it cannot guarantee the accuracy of the data, nor can it correct it.

[0004] Data stored in NOR Flash chips gradually undergoes physical state changes due to prolonged storage and environmental temperature variations (such as high-temperature baking), leading to data degradation. When the ECC error correction algorithm integrated within the NOR Flash chip detects data degradation from an error-free state to a single-bit error, although the data can be corrected and read correctly by ECC, the physical state of the storage cell has already degraded. If this physical degradation is not addressed, the data in the storage cell may further degrade over time, progressing from a single-bit error to a double-bit or more bit error. Once a double-bit or more bit error is reached, existing ECC algorithms will be unable to correct it, resulting in data loss or unreliability. This means that while existing ECC error correction mechanisms can provide data reliability in the short term, they do not fundamentally solve the problem of NOR Flash chip data retention decreasing over time; that is, they fail to actively repair the physical degradation of the storage cell, merely delaying the occurrence of data failure.

[0005] To address the aforementioned issues, there is currently no effective technical solution in NOR Flash chips that can proactively correct data errors upon detecting a correctable single-bit error, and also restore the physical state of the memory cell through programming operations, restoring it to an error-free or more stable initial stage, thereby fundamentally improving the data retention capability of NOR Flash chips.

[0006] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0007] In view of the shortcomings of the prior art, this application provides a method, apparatus and storage medium for improving the data retention capability of NOR Flash chips. It is applied to the field of semiconductor integrated circuit technology and has the advantages of being able to actively detect and repair the physical degradation of NOR Flash chip storage cells, fundamentally improving data retention capability and avoiding data failure due to long-term degradation.

[0008] In a first aspect, a method for improving the data retention capability of a NOR Flash chip, the method comprising the steps of:

[0009] S1: Perform a read operation on the storage cell of the NOR Flash chip, and use error checking and correction logic to perform verification calculations on the read data;

[0010] S2: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, the target location information of the storage cell where the error occurred is determined.

[0011] S3: Based on the target location information, perform a programming operation on the corresponding storage unit to restore the data in the storage unit from the second logical state to the first logical state.

[0012] Furthermore, in step S1, performing a read operation on the memory cell of the NOR Flash chip includes the following steps:

[0013] S11: In response to the idle state of the NOR Flash chip or a preset timed trigger signal, start the automatic scanning mode of the NOR Flash chip;

[0014] S12: In automatic scanning mode, the internal address counter of the NOR Flash chip is used to generate a read address, and the data of the memory cell is read continuously in the order of the read addresses.

[0015] Furthermore, in step S12, continuously reading the data of the storage unit according to the order of the read addresses includes the following steps:

[0016] S121: Divide the storage space of the NOR Flash chip into multiple pages, and organize the read operation in units of pages;

[0017] S122: Use a pipeline control mechanism to perform the switching operation from the current page to the next page.

[0018] Furthermore, step S122 includes:

[0019] S1221: When the reading operation reaches the end of the current page, the end data is sent to the error checking and correction logic to perform the verification calculation;

[0020] S1222: During the time period when the error checking and correction logic performs verification calculations on the last data, the internal address counter is synchronously controlled to jump to the starting address of the next page;

[0021] S1223: Before the verification calculation is completed, the data reading operation of the starting address of the next page is initiated in advance to achieve seamless switching between pages.

[0022] Furthermore, the NOR Flash chip also includes a temporary cache. In step S2, determining the target location information of the memory cell where the error occurred includes the following steps:

[0023] S21: Obtain the physical address of the memory cell where the error occurred;

[0024] S22: Based on the result of the verification calculation, parse out the bit index information of the error bit in the data word;

[0025] S23: Write the physical address and the bit index information into the temporary buffer for latching.

[0026] Furthermore, step S3 includes:

[0027] S31: Pause the read operation;

[0028] S32: Retrieve the physical address and the bit index information from the temporary buffer;

[0029] S33: Obtain the correction data output by the error checking and correction logic, wherein the bit corresponding to the bit index information in the correction data is the first logic state;

[0030] S34: Execute programming instructions on the storage unit corresponding to the physical address to write the correction data into the storage unit, so as to use the physical characteristics of the programming operation to reset the physical state of the error bit in the storage unit from the second logical state to the first logical state.

[0031] Furthermore, the method also includes:

[0032] S4: When the verification calculation detects an uncorrectable error in the data, or detects a correctable single-bit error in the data but the type of the error is that the data is flipped from the second logic state to the first logic state, an error alarm signal is generated;

[0033] S5: Prohibit the programming operation from being performed on the corresponding storage unit, and mark the corresponding storage unit as physically failed or requiring external intervention.

[0034] Furthermore, prior to step S1, the following is also included:

[0035] S01: Receive an externally input repair instruction, the repair instruction containing start address information and end address information;

[0036] S02: Based on the start address information and the end address information, the target storage area for data repair to be performed is parsed out;

[0037] S03: When the starting address information points to the first address of the NOR Flash chip and the ending address information points to the last address of the NOR Flash chip, the target storage area is determined to be the entire NOR Flash chip area.

[0038] S04: When the start address information and the end address information define a local range within the NOR Flash chip, the target storage area is determined to be a partial storage area;

[0039] S05: Limit the traversal range of the read operation to the target storage area.

[0040] In a second aspect, an apparatus for improving the data retention capability of a NOR Flash chip, the apparatus comprising:

[0041] Read module: Performs read operations on the storage cells of the NOR Flash chip and uses error checking and correction logic to perform verification calculations on the read data;

[0042] Error correction module: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, the target location information of the storage cell where the error occurred is determined;

[0043] Programming module: Based on the target location information, performs programming operations on the corresponding storage unit to restore the data in the storage unit from the second logical state to the first logical state.

[0044] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, performs the steps of any of the above methods.

[0045] Beneficial Effects: This application proposes a method, apparatus, and storage medium for improving the data retention capability of NOR Flash chips. By performing read operations and verification calculations on the storage cells of the NOR Flash chip, when a correctable single-bit error is detected and the error type is a transition from a first logic state to a second logic state, the target location information of the erroneous storage cell is determined. Based on this location information, a programming operation is performed on the storage cell to restore the data from the second logic state to the first logic state. This actively repairs the physical degradation of the storage cell, fundamentally improving the data retention capability of the NOR Flash chip and preventing data from eventually failing due to long-term degradation. It has the advantages of being able to actively detect and repair the physical degradation of NOR Flash chip storage cells, fundamentally improving data retention capability, and preventing data from eventually failing due to long-term degradation. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating a method for improving the data retention capability of NOR Flash chips proposed in this application.

[0047] Figure 2 This is a structural diagram of a device for improving the data retention capability of NOR Flash chips according to this application.

[0048] Labeling explanation: 201, Reading module; 202, Error correction module; 203, Programming module. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and marked in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0050] This application proposes a method to improve the data retention capability of NOR Flash chips. Before explaining the method, the data storage principle of NOR Flash chips and its data retention capability problem are first explained. NOR Flash chips record data by storing charge in the floating gate of a floating-gate transistor. When charge is injected into the floating gate, the threshold voltage of the transistor increases, which is represented by a logic state, such as logic 0; when the charge in the floating gate is removed, the threshold voltage decreases, which is represented by another logic state, such as logic 1. Data retention capability refers to the ability of the floating gate to maintain its charge. However, over time, or under harsh environments such as high temperatures, the charge stored in the floating gate may slowly leak, causing the threshold voltage to gradually drift. This gradual change at the physical level will eventually lead to errors at the logical level. For example, a memory cell that originally stored logic 0 may be misread as logic 1 due to charge leakage.

[0051] To address such data errors, existing NOR Flash chips generally integrate error checking and correction logic, commonly referred to as ECC logic. This logic can detect and correct a limited number of bit errors during data reading. For example, a common ECC algorithm can correct one-bit errors and detect two-bit errors. When the data in a storage cell evolves from an error-free state to having a one-bit error due to factors such as charge leakage, the ECC logic can successfully correct it and provide the user with the correct data. However, the role of ECC logic is passive; it only corrects errors during reading and cannot prevent the continued deterioration of the storage cell's physical state. As time goes on, this storage cell that has already developed a single-bit error may continue to degrade, developing a second bit error. At this point, the ECC logic will be unable to correct it, leading to permanent data loss.

[0052] To fundamentally solve this problem, this application proposes an active repair mechanism that, upon detecting a specific type of correctable single-bit error, not only performs logical-level correction but, more importantly, physically repairs the faulty memory cell, restoring it to a healthy, error-free state. This prevents further accumulation of errors and significantly extends the effective data retention time of the NOR Flash chip.

[0053] Specifically, please refer to Figure 1 The method for improving the data retention of NOR Flash chips includes the following steps:

[0054] S1: Perform a read operation on the storage cell of the NOR Flash chip, and use error checking and correction logic to perform verification calculations on the read data;

[0055] S2: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, determine the target location information of the memory cell where the error occurred.

[0056] S3: Based on the target location information, perform programming operations on the corresponding storage unit to restore the data in the storage unit from the second logical state to the first logical state.

[0057] Here, the working principle of the aforementioned core technical solution is explained in detail. The first and second logic states are relative concepts used to characterize the correct state of the data bits and the erroneous state caused by physical degradation. In a typical NOR Flash chip, the programming operation injects electrons into the floating gate, making it negatively charged, representing logic 0; the erasure operation extracts electrons from the floating gate, making it nearly electrically neutral, representing logic 1. The main manifestation of charge leakage is the gradual loss of electrons from the programmed memory cell (logic 0), causing its state to drift towards the erased state (logic 1). Therefore, in a specific implementation of this application, the first logic state can be defined as logic 0, and the second logic state as logic 1. The specific error type targeted by this method is the flip from logic 0 to logic 1, which is precisely the most significant data retention failure mode of NOR Flash chips.

[0058] During a read operation, the internal controller of the NOR Flash chip reads a data word from the memory array. This data word typically contains user data and its corresponding ECC checksum. This complete data word is then fed into the chip's built-in ECC logic unit. The ECC logic unit performs a comprehensive calculation on the input data word based on a preset error correction algorithm, such as Hamming code or BCH code, generating a checksum result called a syndrome. If the syndrome value is all zeros, it indicates that no errors occurred during data transmission and storage. If the syndrome value is non-zero, it indicates that errors exist in the data.

[0059] When a correctable single-bit error is detected in the data, the non-zero syndrome value itself contains key information about the error. The ECC logic can decode this syndrome to directly locate the specific bit in the data word where the error occurred, i.e., the bit index information. Simultaneously, the ECC logic can generate a correction code based on this syndrome. By XORing the correction code with the original read data, the corrected data can be obtained. At this point, the core judgment condition of the method takes effect: not only must the existence of a correctable single-bit error be confirmed, but the type of error must also be determined. The control logic compares the value of the erroneous bit in the original read data with the value of the corresponding bit in the corrected data. If the original read value is in the second logic state (e.g., logic 1), while the corrected value is in the first logic state (e.g., logic 0), then the error is confirmed to be a 0-to-1 flip caused by charge leakage.

[0060] Once this specific type of error is confirmed, the control logic immediately captures and records the target location information of the memory cell where the error occurred. This target location information contains at least two parts: the physical address of the data word currently being read, and the bit index information of the error bit within the data word, decoded by the ECC logic. Together, these two pieces of information precisely point to the transistor in the chip's memory array whose physical state is degrading.

[0061] After obtaining precise target location information, the method enters the active repair phase. Based on this location information, the control logic initiates an internal programming operation on the faulty memory cell. The physical essence of this programming operation is to utilize the chip's internal charge pump to generate a high voltage, which is applied to the control gate and drain of the target transistor. Through hot carrier injection or the Fowler-Nordheim tunneling effect, electrons are re-injected into the floating gate. The data source used in this programming operation is the corrected data already generated by the ECC logic. Through this programming, the floating gate of the memory cell, which had previously experienced a threshold voltage drop due to charge leakage, is refilled with sufficient charge, and the threshold voltage returns to the normal level representing the first logic state (logic 0). Thus, a complete repair operation is completed. This memory cell is not only logically corrected, but its physical state is also refreshed and restored, as if returning to its initial healthy state, effectively preventing the evolution from a single-bit error to a multi-bit uncorrectable error.

[0062] Through the above methods, the NOR Flash chip is transformed from a passive data error correction device into an intelligent storage device with proactive self-healing capabilities. This proactive repair mechanism can periodically inspect and repair potential data degradation problems in the background without affecting normal user operation, thereby significantly improving the chip's overall data retention, reliability, and lifespan.

[0063] Furthermore, in step S1, performing a read operation on the memory cell of the NOR Flash chip includes the following steps:

[0064] S11: In response to the idle state of the NOR Flash chip or a preset timer trigger signal, start the automatic scan mode of the NOR Flash chip;

[0065] S12: In automatic scan mode, the internal address counter of the NOR Flash chip is used to generate read addresses, and the data of the memory cells are read continuously in the order of the read addresses.

[0066] This implementation aims to automate and internalize the process of enhancing data retention, making it an inherent function of the chip without continuous intervention from an external host processor. Automatic scan mode is a special operating state within the chip, independent of regular read, write, and erase commands initiated by the user. This mode can be triggered by two different mechanisms to adapt to different application scenarios.

[0067] The first triggering mechanism is based on the chip's idle state. In this implementation, the NOR Flash chip's internal control logic continuously monitors its own activity status. When the chip select signal is inactive and the internal command queue is empty, with no user commands being executed or waiting to be executed, the control logic determines that the chip has entered an idle state. At this time, if the automatic scanning function is enabled, the control logic will automatically trigger to enter the automatic scanning mode. The advantage of this approach is that it can make full use of the system's idle time slices for background maintenance, minimizing the impact on the system's real-time performance. For example, in an embedded system, when the main processor completes a task and enters a low-power wait state, the NOR Flash chip can use this time to perform self-health checks and repairs.

[0068] The second triggering mechanism is based on a preset timer. In this implementation, the NOR Flash chip integrates a programmable timer or counter. Users or system designers can preset a time period using dedicated commands, such as every 24 hours or after each power-on run of 1000 hours. This timer runs independently in the background, and when the preset value is reached, an internal interrupt signal is generated, directly triggering the start of the automatic scan mode. This method provides a deterministic, periodic maintenance guarantee, ensuring that data integrity checks are performed regularly regardless of system load, making it particularly suitable for industrial control or automotive electronics fields with extremely high data reliability requirements.

[0069] In automatic scan mode, the core driving force for the read operation comes from the chip's internal address counter. Unlike conventional read operations, which require an external host to provide an address via the address bus, the internal address counter is a hardware logic unit that automatically generates a continuous address sequence. At the start of the scan, the counter is initialized to the starting address of the scan area. Each time a data word is read and verified, the counter automatically increments, pointing to the next address. This process continues until the entire preset scan area has been traversed. This design significantly reduces the burden on the external host and decreases bus communication on the chip pins, making the entire scan and repair process transparent to the outside world, resulting in lower power consumption and higher efficiency.

[0070] To further improve data reading efficiency in automatic scanning mode, in some preferred embodiments, the step of continuously reading data from memory units according to the order of read addresses can be specifically designed as follows:

[0071] S121: Divide the NOR Flash chip's storage space into multiple pages and organize read operations in units of pages;

[0072] S122: Use a pipeline control mechanism to perform the switching operation from the current page to the next page.

[0073] Dividing storage space into pages is a common memory organization structure; for example, a contiguous 256 bytes or 512 bytes can be defined as a page. Managing data in pages simplifies address decoding and internal control logic. Pipeline control mechanisms are then introduced to eliminate or hide latency that may occur during page switching, achieving a seamless, continuous data flow and maximizing scan throughput.

[0074] Specifically, the execution process of this pipeline control mechanism can be broken down into the following collaborative sub-steps:

[0075] S1221: When the read operation reaches the end of the current page, the end data is sent to the error checking and correction logic to perform verification calculation;

[0076] S1222: During the time period when the error checking and correction logic performs verification calculations on the last data, the internal address counter is synchronously controlled to jump to the starting address of the next page;

[0077] S1223: Before the verification calculation is completed, the data reading operation of the starting address of the next page is started in advance to achieve seamless switching between pages.

[0078] To better understand this process, consider a specific timing scenario. Assume the internal address counter is pointing to the address of the last data word on the current page. The controller issues a read command, the data word is read from the memory array, and immediately sent to the ECC logic unit. The ECC logic unit begins its verification calculation, a process that takes a fixed amount of time, such as tens of clock cycles.

[0079] In a non-pipelined design, the controller must wait for the ECC calculation to complete and provide the result before proceeding to the next step, namely updating the address to the beginning of the next page and initiating a new read. This involves a significant waiting window.

[0080] In the pipeline mechanism proposed in this application, the operations are parallelized. The moment the ECC logic begins calculating the data at the end of the current page, the chip's control logic does not wait but immediately executes two parallel actions. The first action is to command the internal address counter to update its value, directly jumping to the starting address of the next page. The second action is to use this newly updated address to pre-send a read request to the memory array for the first data word of the next page. The reading from the memory array itself also takes time, including a series of physical processes such as decoding the row address, activating the corresponding word line, and transferring data to the sense amplifier via bit lines.

[0081] In addition, when the storage array reads the first data word of the next page, the controller also needs to determine whether there are any errors in the current page that need to be corrected. If there are, the physical address where the error bit of the current page occurred and the bit index information in the data word are written into the temporary cache for latching. If there are no errors, the verification calculation step of the first address data of the next page is performed.

[0082] Through ingenious timing design, the time spent on address jumps and pre-fetching the next page overlaps with the time spent by the ECC logic calculating the data at the end of the previous page. Ideally, when the ECC logic completes its calculation and is ready to receive the next data word, the first data word of the next page is also ready from the storage array. The data stream can be continuously fed into the ECC logic, thus eliminating the pauses caused by page switching. This design greatly improves the overall speed of automatic scanning, allowing for the inspection and repair of a larger area of ​​storage within limited idle time.

[0083] When the ECC logic detects a specific type of single-bit error during the scan, it needs to accurately record the error location for repair. In some embodiments, the NOR Flash chip also includes one or more temporary buffers. The step of determining the target location information of the memory cell where the error occurred is correspondingly specified as follows:

[0084] S21: Obtain the physical address of the memory cell where the error occurred;

[0085] S22: Based on the result of the check calculation, parse out the bit index information of the error bit in the data word;

[0086] S23: Write the physical address and bit index information into a temporary buffer and latch it.

[0087] The temporary buffer here can be implemented in hardware as a set of dedicated registers. When the ECC logic's accompanying decoder calculates a non-zero result and confirms the error as a correctable single-bit error, it generates an internal error capture signal. This signal triggers a series of actions: First, the value in the current internal address counter, i.e., the physical address of the data word where the error occurred, is copied and latched into a region of the temporary buffer. Second, the error bit index information output by the ECC logic's accompanying decoder is also latched into another region of the temporary buffer. By embedding these two key pieces of information in hardware registers, it ensures that this precise error coordinate will not be lost during subsequent repair processes, even if the main scan process is paused or the state changes.

[0088] After the error location information is reliably latched, a precise repair operation can be initiated. In some embodiments, the step of performing a programming operation on the corresponding storage unit based on the target location information specifically includes:

[0089] S31: Pause read operation;

[0090] S32: Retrieve physical address and bit index information from the temporary buffer;

[0091] S33: Obtain the correction data output by the error checking and correction logic. The bit corresponding to the bit index information in the correction data is the first logic state.

[0092] S34: Execute programming instructions on the memory cell corresponding to the physical address, write correction data into the memory cell, and use the physical characteristics of the programming operation to reset the physical state of the error bit in the memory cell from the second logic state to the first logic state.

[0093] This process is a rigorous closed-loop control flow. Once the error location information is latched, the chip's internal main state machine switches from automatic scanning to repair. In this state, the internal address counter is paused and stops incrementing, and the entire background scanning process is temporarily suspended to ensure the atomicity of the repair operation and avoid conflicts with other possible operations.

[0094] Subsequently, the programming control logic unit reads the previously latched physical address and bit index information from the temporary buffer. Simultaneously, the output of the ECC logic unit is ready with a corrected, fully accurate data word. Using this corrected data word as the programming target data and the latched physical address as the target address, the programming control logic issues internal programming instructions to the core circuitry of the memory array. The chip's internal charge pump begins operation, generating the high voltage required for programming and applying it precisely to the word line and bit line specified by the physical address. This programming process rewrites the entire corrected data word back into the target memory cell. Although the entire data word is written, its physical effect is primarily reflected in the bit that was originally erroneous. Since this bit is in the first logic state (e.g., logic 0) in the programming data, the programming operation forcibly injects charge into the floating gate of that bit, restoring its physical state from a degraded second logic state (e.g., logic 1) back to a healthy first logic state. After the programming operation is complete, there is usually an internal verification step to confirm that the data has been written correctly. After confirming that everything is correct, the main state machine can switch from the repair state back to the automatic scanning state, and the internal address counter will continue scanning from the previously paused address.

[0095] To make the overall data retention enhancement method more complete and secure, it is also necessary to consider handling other types of errors. Therefore, in some embodiments, the method further includes:

[0096] S4: When the verification calculation detects an uncorrectable error in the data, or detects a correctable single-bit error in the data but the type of the error is that the data is flipped from the second logic state to the first logic state, an error alarm signal is generated;

[0097] S5: Prohibit programming operations on the corresponding memory cell and mark the corresponding memory cell as physically failed or requiring external intervention.

[0098] This supplementary scheme adds a crucial protection and diagnostic barrier to the entire self-healing system. The first scenario involves detecting an uncorrectable error, such as a two-bit or more error. In this case, the ECC logic's symmetric expression will point to an invalid decoding result, indicating that the error is beyond its corrective capabilities. Forced repair in this situation is meaningless and dangerous. Therefore, the control logic bypasses the repair process and instead sets an error flag, for example, by setting an uncorrectable error flag in the chip's status register. Simultaneously, an interrupt signal can be generated to notify the external host processor of a serious data integrity problem.

[0099] The second scenario is more nuanced, where the detected single-bit error is reversed, such as a flip from logic 1 to logic 0. The physical cause of this flip is usually not charge leakage, but rather programming interference, excessive erasure, or other more complex defects. Reprogramming a bit that has already been incorrectly changed to logic 0 (i.e., writing logic 0) not only fails to fix the problem but may also cause further damage to the memory cell. Therefore, this application explicitly stipulates that programming repair operations must be prohibited when this type of error is detected.

[0100] The subsequent processing is similar for both scenarios. In addition to generating an alarm signal, the address of the faulty memory cell needs to be recorded and marked as physically failed. This marking can be done in a dedicated, non-volatile defect information area within the chip, forming a list of bad blocks or bad cells. When responding to future user read / write requests, the chip's controller can query this list to replace or mask these known bad cells, preventing users from using these unreliable memory spaces and thus ensuring the overall reliability of the chip.

[0101] Furthermore, to provide greater flexibility to adapt to different application requirements and system management strategies, some embodiments include a series of preprocessing steps before performing read operations on the memory cells of the NOR Flash chip:

[0102] S01: Receive externally input repair instructions, which include start address information and end address information;

[0103] S02: Based on the start address information and end address information, parse out the target storage area for data repair to be performed;

[0104] S03: When the start address information points to the first address of the NOR Flash chip and the end address information points to the last address of the NOR Flash chip, the target storage area is determined to be the entire NOR Flash chip area.

[0105] S04: When the start address information and end address information limit a local range within the NOR Flash chip, the target memory region is determined to be a partial memory region.

[0106] S05: Limit the traversal range of the read operation to the target storage area.

[0107] This set of steps adds a configurable interface to the automatic scan and repair function. An external host processor can proactively initiate a repair scan by sending a specific vendor-defined command, rather than relying solely on internal chip idle timers or timer triggers. This command is followed by two parameters: the start address and the end address of the scan.

[0108] Upon receiving the instruction, the chip's command interface and decoder load the two address parameters into the internal address range register. The control logic then determines the scan range based on the values ​​of these two addresses. If the starting address is the chip's lowest address (e.g., 0x00000000) and the ending address is the highest address (e.g., 0x0FFFFFFF), it means a complete health check of the entire chip is required. If the address parameters define a small range, such as covering only the area containing the file system or critical firmware code, the scan will only be performed within that local area.

[0109] During the subsequent automatic scan, the internal address counter is initialized to the specified starting address, and a comparator continuously compares its current value with the ending address as the counter increments. Once the counter value exceeds the ending address, the scan and repair operation is considered complete, and the chip reports the completion status to the host. This on-demand, partitioned repair capability allows system administrators to develop differentiated maintenance strategies based on the importance of different data areas. For example, critical data areas can be checked more frequently, while non-critical data areas can be checked less frequently, thus achieving an optimal balance between reliability, time, and power consumption.

[0110] Accordingly, please refer to Figure 2 This application also provides an apparatus for improving the data retention capability of NOR Flash chips, which is a hardware implementation of the above-described method. The apparatus includes:

[0111] Read module 201: Performs read operations on the storage cells of the NOR Flash chip and uses error checking and correction logic to perform verification calculations on the read data;

[0112] Error correction module 202: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, the target location information of the memory cell where the error occurred is determined.

[0113] Programming module 203: Based on the target location information, it performs programming operations on the corresponding storage unit to restore the data in the storage unit from the second logical state to the first logical state.

[0114] Specifically, the read module 201 is configured to perform read operations on the memory cells of the NOR Flash chip and to perform verification calculations on the read data using error checking and correction logic. The read module 201 can be a dedicated hardware circuit, such as one containing an address generator, a data buffer, and a controller that interfaces with the NOR Flash memory array. As one implementation, the read module 201 can be designed to perform single or multiple reads in response to external commands, or it can be configured to periodically scan and read the memory area.

[0115] The error correction module 202 is configured to determine the target location information of the storage unit where the error occurred when the verification calculation detects a correctable single-bit error in the data, and the error type is a data flip from a first logical state to a second logical state. This error correction module 202 can be integrated with error checking and correction logic, or it can function as a separate logic unit, receiving the output of the error checking and correction logic and determining the error type and location according to preset logic. For example, the error correction module 202 can include a state machine for analyzing the error codeword and extracting the physical address and bit index information.

[0116] The programming module 203 is configured to perform a programming operation on the corresponding storage unit based on the target location information, so as to restore the data in the storage unit from the second logical state to the first logical state. The programming module 203 can be a programming controller that receives target location information from the error correction module and generates corresponding programming instructions and data, writing to the specified storage unit through the programming interface of the NOR Flash chip. As one implementation, the programming module 203 can be designed to pause the current read operation and prioritize programming repair upon receiving a repair request to ensure timely data recovery.

[0117] The device of this application, through the coordinated operation of the aforementioned modules, achieves early detection and proactive repair of data errors in NOR Flash chips. While traditional NOR Flash chips also integrate error checking and correction logic, their primary function is real-time error correction during data reading, without proactively repairing the storage cells. This means that once data errors accumulate beyond the error-correction capabilities of the logic, the data becomes unreliable. The device of this application, however, immediately performs a programming operation on the erroneous storage cell upon detecting a correctable single-bit error, restoring the data to its correct logical state, thereby effectively preventing further deterioration of the data error. This proactive repair mechanism is equivalent to repairing data errors before they become uncorrectable, significantly improving the data retention capability of the NOR Flash chip and extending its reliable lifespan. Compared to existing technologies that only perform passive error correction during reading, the proactive repair mechanism of this application fundamentally solves the problem of data error accumulation, ensuring that the NOR Flash chip maintains high reliability during long-term use.

[0118] This application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it performs the method in any optional implementation of the above embodiments to achieve the following functions: performing a read operation on the storage cell of a NOR Flash chip and performing verification calculation on the read data using error checking and correction logic; when the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from a first logic state to a second logic state, determining the target location information of the storage cell where the error occurred; and performing a programming operation on the corresponding storage cell according to the target location information to restore the data of the storage cell from the second logic state to the first logic state.

[0119] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0120] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0121] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0122] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0123] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for improving the data retention capability of a NOR Flash chip, characterized in that, The method includes the following steps: S1: Perform a read operation on the storage cell of the NOR Flash chip, and use error checking and correction logic to perform verification calculations on the read data; In step S1, performing a read operation on the memory cell of the NOR Flash chip includes the following steps: S11: In response to the idle state of the NOR Flash chip or a preset timed trigger signal, start the automatic scanning mode of the NOR Flash chip; S12: In automatic scanning mode, the internal address counter of the NOR Flash chip is used to generate a read address, and the data of the memory cell is read continuously in the order of the read addresses; In step S12, reading the data of the storage unit sequentially according to the read address order includes the following steps: S121: Divide the storage space of the NOR Flash chip into multiple pages, and organize the read operation in units of pages; S122: Use a pipelined control mechanism to perform the switching operation from the current page to the next page; Step S122 includes: S1221: When the reading operation reaches the end of the current page, the end data is sent to the error checking and correction logic to perform the verification calculation; S1222: During the time period when the error checking and correction logic performs verification calculations on the last data, the internal address counter is synchronously controlled to jump to the starting address of the next page; S1223: Before the verification calculation is completed, the data reading operation of the starting address of the next page is initiated in advance to achieve seamless switching between pages; S2: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, the target location information of the storage cell where the error occurred is determined. S3: Based on the target location information, perform a programming operation on the corresponding storage unit to restore the data in the storage unit from the second logical state to the first logical state.

2. The method for improving data retention of NOR Flash chips according to claim 1, characterized in that, The NOR Flash chip also includes a temporary cache. In step S2, determining the target location information of the memory cell where the error occurred includes the following steps: S21: Obtain the physical address of the memory cell where the error occurred; S22: Based on the result of the verification calculation, parse out the bit index information of the error bit in the data word; S23: Write the physical address and the bit index information into the temporary buffer for latching.

3. The method for improving the data retention capability of a NOR Flash chip according to claim 2, characterized in that, Step S3 includes: S31: Pause the read operation; S32: Retrieve the physical address and the bit index information from the temporary buffer; S33: Obtain the correction data output by the error checking and correction logic, wherein the bit corresponding to the bit index information in the correction data is the first logic state; S34: Execute programming instructions on the storage unit corresponding to the physical address to write the correction data into the storage unit, so as to use the physical characteristics of the programming operation to reset the physical state of the error bit in the storage unit from the second logical state to the first logical state.

4. The method for improving the data retention capability of a NOR Flash chip according to claim 1, characterized in that, The method further includes: S4: When the verification calculation detects an uncorrectable error in the data, or detects a correctable single-bit error in the data but the type of the error is that the data is flipped from the second logic state to the first logic state, an error alarm signal is generated; S5: Prohibit the programming operation from being performed on the corresponding storage unit, and mark the corresponding storage unit as physically failed or requiring external intervention.

5. The method for improving data retention of NOR Flash chips according to claim 1, characterized in that, The steps preceding step S1 also include: S01: Receive an externally input repair instruction, the repair instruction containing start address information and end address information; S02: Based on the start address information and the end address information, the target storage area for data repair to be performed is parsed out; S03: When the starting address information points to the first address of the NOR Flash chip and the ending address information points to the last address of the NOR Flash chip, the target storage area is determined to be the entire NOR Flash chip area. S04: When the start address information and the end address information define a local range within the NOR Flash chip, the target storage area is determined to be a partial storage area; S05: Limit the traversal range of the read operation to the target storage area.

6. A device for improving the data retention capability of NOR Flash chips, characterized in that, The device includes: Read module: Performs read operations on the storage cells of the NOR Flash chip and uses error checking and correction logic to perform verification calculations on the read data; The reading module is also used to start the automatic scanning mode of the NOR Flash chip in response to the idle state of the NOR Flash chip or a preset timed trigger signal. In automatic scanning mode, the internal address counter of the NOR Flash chip is used to generate read addresses, and the data of the memory cell is read continuously in the order of the read addresses; The reading module is also used to divide the storage space of the NOR Flash chip into multiple pages and organize the reading operation in units of pages; A pipelined control mechanism is used to execute the switching operation from the current page to the next page; The reading module is also used to, when the reading operation reaches the end of the current page, send the end data to the error checking and correction logic to perform the verification calculation; During the time period when the error checking and correction logic performs verification calculations on the last data, the internal address counter is synchronously controlled to jump to the starting address of the next page; Before the verification calculation is completed, the data reading operation of the starting address of the next page is initiated in advance to achieve seamless switching between pages; Error correction module: When the verification calculation detects a correctable single-bit error in the data, and the type of the error is that the data is flipped from the first logic state to the second logic state, the target location information of the storage cell where the error occurred is determined; Programming module: Based on the target location information, performs programming operations on the corresponding storage unit to program the storage unit. The data of the element is restored from the second logical state to the first logical state.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-5.

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