Method, device and equipment for suppressing output DC bus voltage fluctuation of load mutation and medium

Abstract

The application provides a method and device for suppressing voltage fluctuation of a load mutation output DC bus, an equipment and a medium, which are used for quickly suppressing overshoot or undershoot of voltage fluctuation and restoring its steady state. The method comprises the following steps: collecting actual voltage of an output DC bus of a target rectification module in real time, and calculating deviation voltage value between the actual voltage and a DC voltage target setting value; when the deviation voltage value reaches a mutation threshold set, generating a voltage target given value by mutation correction of the DC voltage target setting value according to an adjustment coefficient and the deviation voltage value; and inputting voltage adjustment of a voltage outer loop controller in the target rectification module according to the voltage target given value, so as to suppress voltage of the output DC bus.

Description

Technical Field

[0001] This application relates to the field of voltage fluctuation suppression technology, and in particular to a method, apparatus, equipment and medium for suppressing output DC bus voltage fluctuations caused by load changes. Background Technology

[0002] The rectifier module's requirements for suppressing DC bus voltage during load surges (sudden switching on or off) focus on three points: First, a fast response to suppress instantaneous voltage spikes or dips, avoiding transient impacts on downstream converters and loads; second, short recovery time and small steady-state deviation to meet voltage regulation accuracy (e.g., ±1%) and system safety margin requirements; and third, robustness without causing malfunctions, i.e., the ability to distinguish between steady-state ripple and real surges while balancing hardware protection and software limiting.

[0003] Existing voltage fluctuation suppression methods mainly rely on a combination of hardware and traditional control methods: passive or protective measures such as increasing DC-side energy storage and filtering capacity, using higher bandwidth current inner loop and PI-type voltage outer loop, feedforward or decoupling, overvoltage or undervoltage protection, voltage clamping or parallel energy storage (capacitors, supercapacitors or batteries) are used to mitigate fluctuations; at the software level, most of them are fixed voltage setpoints plus conventional PI settings or threshold triggering protection logic, lacking a mechanism for real-time adaptive adjustment of setpoints according to direction and amplitude. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for suppressing output DC bus voltage fluctuations caused by load changes, which is used to quickly suppress overshoot or undershoot of voltage fluctuations and restore their steady state.

[0005] In a first aspect, this application provides a method for suppressing output DC bus voltage fluctuations due to load changes, the method comprising: Step S1: Real-time acquisition of the actual voltage of the output DC bus of the target rectifier module, and calculation of the deviation voltage value between the actual voltage and the preset DC voltage target setting value; Step S2: When the deviation voltage value reaches a preset mutation threshold set, the DC voltage target set value is mutated and corrected according to the preset adjustment coefficient and the deviation voltage value to generate a voltage target set value. Step S3: Adjust the input voltage of the outer loop controller in the target rectifier module according to the target voltage setpoint to suppress the voltage of the output DC bus.

[0006] In one possible implementation, the step of abruptly correcting the DC voltage target setpoint based on a preset adjustment coefficient and the deviation voltage value to generate the voltage target setpoint includes: The sign of the abrupt compensation direction is determined based on the sign of the deviation voltage value using a preset compensation control direction mapping strategy. The voltage compensation amount is generated by multiplying the preset adjustment coefficient and the absolute value of the deviation voltage value. Based on the mutation compensation direction sign and the voltage compensation amount, the DC voltage target setpoint is corrected to generate the voltage target given value.

[0007] In one possible implementation, the method further includes: Based on the received voltage regulation accuracy requirement data and the DC voltage target setting value, calculate the upper limit and lower limit of voltage fluctuation allowed for voltage regulation operation; The received adjustment safety margin and the upper limit of voltage fluctuation are multiplied to calculate the first sudden change threshold. The adjustment safety margin and the lower limit of voltage fluctuation are multiplied to calculate the second mutation threshold.

[0008] In one possible implementation, the method further includes: According to the preset data format, the voltage regulation accuracy requirement data, the DC voltage target set value, the adjustment safety margin, and the preset maximum full-load power are aggregated into the standard operating parameter set of the target rectifier module; The standard operating parameter set is subjected to multi-level forward nonlinear transformation to obtain the adjustment coefficient and the timeout adjustment threshold.

[0009] In one possible implementation, the method further includes: The safe adjustment safety margin and the DC voltage target set value are multiplied to obtain the safe adjustment DC voltage threshold. The maximum expected reset deviation is set according to the safety regulation DC voltage threshold by using a preset hardware safety regulation strategy; Calculate the total number of reset steps based on the preset total reset completion time and the preset unit control cycle duration; Calculate the voltage reset adjustment step size within each unit control cycle based on the maximum expected reset deviation and the total number of reset steps.

[0010] In one possible implementation, the step of regulating the input voltage of the outer loop controller in the target rectifier module according to the target voltage setpoint to suppress the voltage of the output DC bus includes: Step S31: Reset and start the preset timeout timer, and adjust the input voltage of the voltage outer loop controller in the target rectifier module according to the voltage target given value; Step S32: Read the adjustment duration of the timeout timer in real time, and collect the actual voltage of the output DC bus of the target rectifier module in real time; When the adjustment duration does not reach the timeout adjustment threshold, repeat steps S1 to S32 until the deviation voltage value is less than the first mutation threshold and the deviation voltage value is greater than the second mutation threshold. When the adjustment duration reaches the timeout adjustment threshold, and the deviation voltage value is greater than or equal to the first sudden change threshold, or the deviation voltage value is less than or equal to the second sudden change threshold, the voltage target setpoint is unidirectionally reset and adjusted according to the voltage reset adjustment step size to update the voltage target setpoint, and the input voltage of the voltage outer loop controller in the target rectifier module is adjusted according to the voltage target setpoint until the voltage target setpoint returns to the DC voltage target setpoint.

[0011] Secondly, this application provides an output DC bus voltage fluctuation suppression device for load surges, the device comprising: The deviation calculation module is used to collect the actual voltage of the output DC bus of the target rectifier module in real time, and calculate the deviation voltage value between the actual voltage and the preset DC voltage target setting value. The mutation judgment module is used to perform mutation correction on the DC voltage target set value according to the preset adjustment coefficient and the deviation voltage value when the deviation voltage value reaches the preset mutation threshold set, and generate the voltage target set value. A sudden change suppression module is used to adjust the input voltage of the outer loop controller in the target rectifier module according to the voltage target given value, so as to suppress the voltage of the output DC bus.

[0012] In summary, this application includes at least the following beneficial technical effects: 1. Effectively suppresses DC bus voltage overshoot and undershoot caused by sudden load or unload, thereby reducing transient impact on downstream converters and loads.

[0013] 2. By dynamically adjusting and using timeout reset, the voltage fluctuation recovery time is shortened and the fluctuation amplitude is reduced, thereby improving the steady-state voltage quality and power supply reliability.

[0014] 3. It has parameterization and protection mechanisms to avoid false triggering due to noise or normal ripple and to ensure the safe and stable operation of the system. Attached Figure Description

[0015] Figure 1 This is a schematic flowchart of a method for suppressing output DC bus voltage fluctuations caused by load mutations, provided in an embodiment of this application. Figure 2This is a schematic diagram of the structure of an output DC bus voltage fluctuation suppression device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the computing device provided in the embodiments of this application; Figure 4 This is a schematic diagram of the voltage and current waveforms output on the DC side during a sudden load change, provided in an embodiment of this application. Figure 5 This is a schematic diagram of the voltage and current waveforms output on the DC side under voltage fluctuation suppression during load sudden changes, provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. With the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0017] The terms "first," "second," etc., used in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the description of embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to those processes, methods, products, or apparatuses.

[0018] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0019] For ease of understanding, the operating environment of the technical solution in this application is explained below: The physical and control system environment of the technical solution in this application is built on a three-phase pulse width modulation rectifier platform widely used in industrial power electronics. The core control objective of this platform is to convert unstable three-phase AC power into high-quality, high-stability DC power. The stability of its output DC bus voltage directly determines the operational safety and reliability of downstream electrical equipment or energy storage units. To achieve this objective, the industry generally adopts a dual-closed-loop control architecture based on instantaneous power theory and coordinate transformation as the standard control framework. The outer loop of this framework is a DC voltage control loop, whose input is the deviation between the target setpoint and the actual sampled value of the DC bus voltage. This deviation is processed by a proportional-integral regulator, and the output is a direct-axis current reference value characterizing the magnitude of the active current required by the system. The inner loop is an AC current control loop, which receives the direct-axis current reference value from the outer loop and ensures that the quadrature-axis current reference value is set to zero to achieve unity power factor operation. It achieves precise regulation of the three-phase current on the grid side through fast tracking control. In this architecture, the instantaneous voltage and current signals on the three-phase AC side are transformed from a stationary abc coordinate system to a dq coordinate system that rotates synchronously with the grid voltage via Clarke and Parker transformations. In this rotating coordinate system, the originally time-varying AC quantities are converted into DC quantities, enabling the traditional proportional-integral (PI) regulator to achieve zero steady-state error tracking of sinusoidal signals. The final dq-axis voltage modulation signal output from the control loop is then transformed via inverse Parker and inverse Clarke transformations to generate a pulse-width modulation (PWM) signal for driving the insulated-gate bipolar transistor (IGBT), thus completing the closed-loop control of the entire rectification process.

[0020] The aforementioned control framework exhibits excellent performance under steady-state conditions with constant or slowly varying loads, accurately stabilizing the DC bus voltage near the target setpoint with fluctuations strictly limited to a small range permitted by technical specifications. Its voltage regulation principle lies in the inherent dynamic adjustment mechanism of the proportional-integral (PI) regulator. When the output voltage deviates from the setpoint due to a small disturbance, the proportional element immediately generates a corrective action proportional to the deviation, while the integral element continuously accumulates the deviation, gradually eliminating the system's steady-state error. Combined with the fast response capability of the inner current loop, the system can effectively maintain the instantaneous balance between AC input power and DC output power. However, maintaining this balance relies on the continuous detection and progressive correction of the deviation signal by the control loop, and its dynamic response speed is fundamentally limited by the bandwidth of the PI regulator and the overall inertial nature of the system.

[0021] When the load connected to the rectifier module undergoes a sudden and drastic change, such as the instantaneous connection or disconnection of a high-power load, the inherent limitations of the aforementioned control framework become apparent. A step-like change in load power means that the DC-side output power demand changes dramatically within a very short time. Because the grid-side input power is limited by the dynamic response of the current loop and the constraints of energy storage components such as AC inductors, a step-like change at the same speed cannot be achieved, making instantaneous power imbalance unavoidable. A large amount of power deficit will be drawn from the energy stored in the DC bus capacitor, causing the capacitor voltage, i.e., the DC bus voltage, to drop rapidly; conversely, when the load is suddenly disconnected, excess input power will flood into the DC bus capacitor, causing its voltage to rise sharply. At this moment, although the proportional-integral regulator in the voltage outer loop immediately detects the suddenly increased voltage deviation and begins to operate, the rate of change of its output command is limited by the preset controller parameters. While the proportional loop can provide an immediate response, its output amplitude is related to a fixed gain, and may still be insufficient in the face of large initial deviations; the integral loop's action is even slower, and its output requires time to accumulate and increase. Therefore, there is an unavoidable time delay and adjustment process from when the system detects the deviation to when it outputs a current command sufficient to compensate for the power deficit or surplus.

[0022] refer to Figure 4 As shown, without the application of the technical solution of this application, the control framework's suppression effect on such load surges manifests as significant overshoot or undershoot of the DC bus voltage, with large fluctuations and a long recovery time. Specifically, in a rectifier system with a target setpoint of 750V and a rated power of 125kW, if a full load is suddenly applied, the DC bus voltage may drop by more than 100V and slowly recover over a timescale of hundreds of milliseconds. Such large voltage fluctuations, even if they do not ultimately trigger hardware protection, pose a threat to downstream precision equipment and may cause a chain reaction of system instability. The fundamental shortcoming is that the traditional proportional-integral (PI) control strategy is essentially a deviation-driven lag correction mechanism, which always starts the correction process only after the fluctuation occurs. The parameter design of the regulator needs to make trade-offs between dynamic response speed, system stability, and noise immunity. Excessive gain may lead to system oscillation, while excessively low gain will inevitably lead to sluggish response. Therefore, when facing rapid and large load surges, a PI controller operating with fixed parameters cannot simultaneously achieve the two conflicting goals of suppressing fluctuation amplitude and shortening recovery time. While increasing the DC bus capacitor can mitigate the rate of voltage change at the hardware level, this significantly increases the system's size, cost, and weight, and is not a fundamental solution. Furthermore, some more complex advanced control algorithms, although theoretically potentially achieving superior dynamic performance, suffer from high implementation complexity, demanding processor computing power, and difficult parameter tuning, making them unsuitable for widespread deployment and application in industrial products.

[0023] Therefore, the operating environment described above clearly reveals a long-standing technical contradiction: on the one hand, three-phase rectifiers based on dual-loop proportional-integral control exhibit excellent performance in steady state; on the other hand, when dealing with sudden load changes, the DC output voltage experiences unacceptable fluctuations and slow recovery due to the hysteresis of the control structure. This fluctuation stems from the fundamental contradiction between the sharp power imbalance during load changes and the limited response speed of the control loop. Existing parameter optimizations or local improvements within the aforementioned control framework cannot fundamentally overcome this contradiction. This constitutes the core technical problem that the technical solution of this application needs to solve: how to significantly suppress large fluctuations in DC bus voltage caused by sudden load increases and decreases, and improve the dynamic stability and power supply quality of the system, while retaining the existing mature and reliable dual-loop control architecture, in a simple, effective, and easily engineering-implementable manner.

[0024] The output DC bus voltage fluctuation suppression method for load surges provided in this application is executed by an electronic device, and correspondingly, the output DC bus voltage fluctuation suppression device for load surges operates within the electronic device. The following description, from the perspective of the electronic device and in conjunction with the process of suppressing output voltage fluctuations caused by full-load surges by a target rectifier module using a preset standard operating parameter set, illustrates the output DC bus voltage fluctuation suppression method for load surges provided in this application. The standard operating parameter set in this application includes, but is not limited to, a voltage regulation accuracy requirement of ±1%, a DC voltage target setting of 750V, an adjustment safety margin of 15%, and a maximum full-load power of 125kW.

[0025] like Figure 1 The diagram shown is a flowchart illustrating the method for suppressing output DC bus voltage fluctuations due to load surges provided in this application. The method for suppressing output DC bus voltage fluctuations due to load surges provided in this application includes the following steps.

[0026] Before performing monitoring and adjustment operations on the target rectifier module, this application requires initial setting of key parameters and thresholds based on a pre-defined set of standard operating parameters for the target rectifier module. This setting process forms the basis for the correct and effective operation of the technical solution in this application. The standard operating parameter set is not a dynamic variable collected during system operation, but rather a set of static parameters determined during the design or configuration phase of the target rectifier module to fully describe its core performance specifications and safe operating boundaries. This set specifically includes four key data items: the voltage regulation accuracy requirement defines the allowable fluctuation range of the output voltage that the system must maintain under steady-state conditions, directly reflecting the core performance constraints on output power quality; the DC voltage target set value clarifies the DC bus voltage center value that the system needs to maintain stably over a long period, which is the ultimate goal and reference benchmark for all control activities; the adjustment safety margin is a design buffer coefficient reserved to ensure the system can still operate safely and stably during extreme or transient processes, determining the boundary for intervention and protection by the control system; and the maximum full-load power characterizes the maximum output power capability that the rectifier module can continuously provide, limiting the upper limit of the system's load handling capacity. The standard operating parameter set together constitutes the performance index of the target rectifier module. The acquisition process originates from the product design specification or the user's field configuration input. Their role is to provide a unified and quantitative design basis for all subsequent control logic, ensuring that the strength and scale of the suppression strategy are precisely matched with the module's own physical capabilities and performance requirements.

[0027] Based on the above standard operating parameter set, the setting of key parameters and thresholds is carried out in sequence, and the specific operation is as follows: First, a threshold set for sudden changes is set to establish a reliable triggering limit, accurately distinguishing between normal steady-state voltage fluctuations and genuine load surge events, thus avoiding malfunctions. Specifically, based on the received voltage regulation accuracy requirement data and the DC voltage target setting, the upper and lower limits of allowable voltage fluctuations for regulated operation are calculated. Taking a DC voltage target setting of 750V and a voltage regulation accuracy requirement of ±1% as an example, the upper limit of voltage fluctuation is 750V + (750V × 1%) = 757.5V, and the lower limit is 750V - (750V × 1%) = 742.5V. However, directly using this ±7.5V range as the judgment threshold is unreliable, because the voltage may operate normally near this boundary under full-load steady-state operation or in the presence of measurement noise. Therefore, a safety margin is needed to broaden this judgment range. The received safety margin is then combined with the calculated upper limit of voltage fluctuation for further calculation. The combined calculation here is not a simple multiplication. Its actual meaning is that the difference between the upper limit of voltage fluctuation and the target set value is multiplied by a coefficient set according to the adjustment safety margin to obtain a new positive voltage deviation threshold, i.e., 7.5V × 1.5 = 11.25V. In practice, it is often rounded to 12V, and this value is set as the first mutation threshold. Similarly, the difference between the lower limit of voltage fluctuation and the target set value is multiplied by a coefficient set according to the adjustment safety margin to obtain a negative voltage deviation threshold, which serves as the second mutation threshold. The first and second mutation thresholds together form a mutation threshold set. This threshold set is used to judge the load mutation of the target rectifier module based on the real-time detected voltage deviation, avoiding controller false triggering caused by steady-state ripple, sensor noise, or full-load steady-state voltage drop, ensuring the targeted and necessary nature of the suppression action.

[0028] Simultaneously, the system enters the intelligent tuning stage for the regulation coefficient and timeout regulation threshold. This application uses a pre-trained artificial intelligence model to perform multi-layer forward nonlinear transformation processing on the aforementioned standard operating parameter set to obtain the regulation coefficient and timeout regulation threshold. The artificial intelligence model is trained offline using a large number of samples, learning the complex mapping relationship between the standard operating parameter set and the optimal dynamic response parameters. Specifically, the artificial intelligence model uses the standard operating parameter set as its input feature vector. This parameter set consists of four core specifications: voltage regulation accuracy requirements, DC voltage target setpoint, regulation safety margin, and maximum full-load power. These parameters collectively characterize the operating boundaries and performance requirements of the rectifier module. Before being input into the model, these parameters are concatenated in a preset order and normalized to eliminate the influence of dimensional differences on model calculations; for example, voltage values ​​are mapped to [0,1], and percentages are converted to decimal form. The output layer of the artificial intelligence model corresponds to two continuous values: the regulation coefficient and the timeout regulation threshold. The regulation coefficient is used to dynamically suppress the amplification of the deviation voltage value during the process; the timeout regulation threshold defines the maximum allowed duration of dynamic regulation. It should be understood that both the adjustment coefficient and the timeout adjustment threshold are dimensionless or real numbers with a time dimension, and their numerical range needs to be limited in conjunction with physical meaning. For example, the adjustment coefficient k is usually greater than 1 and less than a certain upper limit, and the timeout adjustment threshold is on the order of hundreds of milliseconds.

[0029] The artificial intelligence model in this embodiment employs a deep neural network structure, which includes an input layer, multiple hidden layers, and an output layer. The number of neurons in the input layer is consistent with the feature dimension of the standard operating parameter set, i.e., 4 neurons. This embodiment uses two hidden layers: a fully connected layer with 64 neurons and a fully connected layer with 36 neurons, and applies the ReLU activation function to introduce nonlinear transformation capability. The output layer uses a linear activation function to directly output continuous predicted values.

[0030] During the training phase, the AI ​​model relies on a high-quality labeled dataset. For each possible combination of rectifier module specifications, the model obtains its optimal regulation coefficient and timeout threshold through simulation or numerous repeated physical experiments. The AI ​​model in this embodiment performs extensive load surge condition scans under different input standard operating parameter sets through simulation, constructing an optimized fitness function with voltage fluctuation suppression as the objective. Specifically, for each set of candidate regulation coefficient and timeout threshold parameter combinations, a standardized load surge condition is applied in the simulation, such as a sudden application of 100% rated load from no-load at t=0, and the DC bus voltage response curve is recorded. Key performance indicators are extracted from this curve: maximum voltage undershoot ΔV1 (negative deviation relative to the setpoint), recovery time Tr (time required from the start of the surge to the voltage entering and remaining within the setpoint ± regulation accuracy range), and potential overshoot ΔV2. In this embodiment, the fitness function f is calculated using a weighted summation formula, for example, f = αΔV1 + βTr + γΔV2. The weight coefficients α, β, and γ can be set according to the design priority (e.g., α = 0.5, β = 0.4, γ = 0.1), and all indicators need to be normalized to the same dimension. The goal of the artificial intelligence model is to minimize this fitness function. Next, this embodiment uses a genetic algorithm to automatically search for the optimal parameter combination. During algorithm initialization, N individuals (each corresponding to a set of parameter combinations) are randomly generated within a preset range, serving as the initial population. Simulation is performed on each individual, and its fitness value is calculated. Then, the next generation population is generated through selection, crossover, and mutation operations. This process is repeated iteratively until the maximum number of generations is reached or the calculated fitness function converges. The optimal individual obtained is the best combination of adjustment coefficient and timeout adjustment threshold for that specification parameter. To reduce simulation computation, parallel simulation can be used for acceleration, and typical specification parameter combinations can be sampled in a gridded manner (e.g., setpoints in 50V steps, power in 25kW steps, etc.) to build a tag database covering the product series. If an accurate simulation model is lacking, automated testing can also be performed on a physical prototype. The system automatically adjusts the regulation coefficient and timeout threshold by writing a test program and records the voltage response. Then, the same optimization algorithm is used to search for the optimal regulation coefficient and timeout threshold, thereby generating the corresponding optimal regulation coefficient and timeout threshold for each set of input standard operating parameters. In another optional embodiment, the best parameters are recorded through physical experiments using engineer experience or an automated testing platform. The collected thousands of sets of input-output data constitute the training set. Let the input standard operating parameter set be X, and the combination of regulation coefficient and timeout threshold be Y. The training process uses mean squared error as the loss function, and the network weights are updated through backpropagation using the Adam optimizer until the prediction accuracy of the artificial intelligence model reaches the required level (i.e., the fitness function calculation results converge).

[0031] After the AI ​​model has been trained and verified to be qualified, its structure and weight parameters are solidified and burned into the microcontroller or digital signal processor of the rectifier module in a form suitable for embedded platforms. When the system is powered on for initialization or parameter configuration, the controller first reads the pre-stored standard operating parameter set, processes it using the same normalization method as during training, and then inputs it into the model. The model performs one forward inference, calculating the corresponding adjustment coefficient and timeout adjustment threshold within microseconds, and then writes them into the corresponding register of the control algorithm as fixed parameters for the dynamic suppression process.

[0032] The aforementioned intelligent tuning operation automates and intelligently transforms the traditional process of determining key controller parameters through extensive trial and error and relying on engineers' experience into an instantaneous calculation process based on the module's own specifications. This ensures that rectifier modules of different voltage levels and power levels can obtain regulation coefficients and timeout thresholds that precisely match their characteristics, achieving optimal performance configuration while maintaining a unified control architecture. For example, when the input vector (i.e., the standard operating parameter set) is represented as "±1%, 750V, 15%, 125kW", the model outputs a regulation coefficient k=5 and a timeout threshold of 700ms after forward inference.

[0033] Simultaneously, the parameters related to the timeout recovery mechanism are set. First, the safety margin and the target DC voltage setting are multiplied to obtain the safety regulation DC voltage threshold. For example, 750V × 15% = 112.5V. The safety regulation DC voltage threshold quantifies the theoretical value of the maximum voltage deviation allowed based on the system safety margin. Next, the maximum expected reset deviation is set according to this safety regulation DC voltage threshold using a preset hardware safety regulation strategy. The core principle of this strategy is to ensure that the timeout recovery mechanism has the ability to pull the voltage back from the most severe abnormal state to a steady state; therefore, the maximum expected reset deviation should cover and slightly exceed the safety regulation DC voltage threshold. For example, it can be set to 128V, which is greater than 112.5V, providing additional recovery margin for possible overshoot or extreme situations. Then, the total number of reset steps is calculated based on the preset total reset completion time and the preset unit control cycle duration. Assuming the total reset time is set to 200ms and the unit control cycle (i.e., PWM switching cycle) is 62.5μs, the total number of reset steps is 200,000μs / 62.5μs = 3200 steps. Finally, based on the maximum expected reset deviation and the total number of reset steps, the voltage reset adjustment step size within each unit control cycle is calculated using the formula: Voltage reset adjustment step size = Maximum expected reset deviation ÷ Total number of reset steps. Substituting the values, we get 128V / 3200 = 0.04V / cycle. The significance of setting this small fixed step size is that when dynamic adjustment times out, the system needs to smoothly reset the virtual voltage target setpoint back to the original setpoint in an extremely gentle and shock-free manner. The voltage reset adjustment step size ensures that during the reset process within the entire unit control cycle, the outer voltage loop experiences a slowly changing ramp command, thus preventing new power and current surges and achieving a smooth and safe transition from abnormal regulation to normal steady state. This is a crucial guarantee for the robustness of the entire suppression method.

[0034] Step S1: Real-time acquisition of the actual voltage of the output DC bus of the target rectifier module, and calculation of the deviation voltage value between the actual voltage and the preset DC voltage target setting value.

[0035] Accurate, rapid, and reliable acquisition of voltage deviation information reflecting the instantaneous state of the system provides a unique and quantified input basis for subsequent control logic. The calculation of the deviation voltage value in this application is tightly embedded in the existing digital control system of the target rectifier module, relying on its inherent hardware sampling circuit and timed interrupt service routine to complete the task periodically. Its execution frequency is strictly synchronized with the switching frequency and control cycle of the control system. For example, in a system with a switching frequency of 16kHz, this step is triggered every 62.5μs. First, it relies on a preset hardware acquisition link, which starts from a voltage divider resistor network connected between the positive and negative terminals of the DC bus. This network proportionally attenuates the bus voltage, which can reach hundreds of volts, to a lower voltage level suitable for the input range of the measurement chip. The attenuated voltage signal is buffered by a voltage follower composed of operational amplifiers to enhance the driving capability and isolate the preceding and following circuits, preventing interference from the measurement stage to the power circuit. The signal then enters an anti-aliasing low-pass filter. The cutoff frequency of this filter needs to be scientifically set according to the sampling frequency of the control system. Its purpose is to filter out high-frequency ripples generated by PWM switching actions and high-frequency noise coupled from the environment, while retaining the true low-frequency voltage changes reflecting energy balance, thus avoiding signal distortion caused by high-frequency noise during sampling. The conditioned analog voltage signal is then connected to the input channel of the analog-to-digital converter (ADC) of a microcontroller or dedicated digital signal processor. The ADC typically has a resolution of twelve bits or higher, and its reference voltage must remain highly stable to ensure the absolute accuracy of the conversion result. The ADC is automatically triggered by a timer hardware, strictly aligned with the start point of the control cycle, to ensure consistency in each sampling moment and eliminate calculation errors introduced by sampling jitter. After the ADC is completed, a digital code representing the instantaneous value of the current bus voltage is generated. This digital code needs to be converted into a physically meaningful voltage value using a calibration formula. The calibration formula is determined during system initialization through a calibration program and is used to compensate for system measurement deviations caused by voltage divider network resistor tolerance, operational amplifier offset, and ADC gain error, thereby ensuring an accurate mapping from the digital code to the actual voltage value. The voltage value obtained in this process is the total voltage between the positive and negative terminals of the bus (hereinafter referred to as Vbus), which is the real-time potential difference across the capacitor storing electrical energy on the DC bus.

[0036] After obtaining the accurate actual voltage value, the system immediately enters the deviation calculation stage. Another key input required for this stage is the preset DC voltage target setpoint. The deviation voltage value is calculated by performing an algebraic subtraction operation between the real-time acquired actual voltage value and this preset DC voltage target setpoint. The formula is: Deviation Voltage Value = DC Voltage Target Setpoint - Actual Voltage Value. This subtraction operation can be completed within one instruction cycle in the arithmetic logic unit of the digital controller. The calculated deviation voltage value is a signed scalar, and its sign and magnitude carry complete system state information: when the deviation voltage value is positive, it indicates that the actual voltage is lower than the target setpoint, and the system is in an undervoltage state, usually corresponding to a sudden increase in load or insufficient input power; when the deviation voltage value is negative, it indicates that the actual voltage is higher than the target setpoint, and the system is in an overvoltage state, usually corresponding to a sudden decrease in load or excessive input power. The absolute value of the deviation voltage value directly quantifies the severity of the current voltage deviation from the ideal target. For example, if the actual voltage value obtained from sampling and calculation in a certain control cycle is 730V, then the deviation voltage value is 750V-730V=20V. The deviation voltage value clearly indicates that the current system voltage is 20V lower than the target value, and the deviation direction is positive. The real-time nature of this deviation value is crucial because power imbalances caused by sudden load changes can lead to drastic voltage changes in milliseconds or even less. Only by continuously updating this deviation value at the same frequency as the control cycle (i.e., 62.5μs) can the control algorithm capture the initial trend and instantaneous rate of voltage fluctuations, creating the possibility for early and enhanced intervention.

[0037] Step S2: When the deviation voltage value reaches a preset mutation threshold set, the DC voltage target setting value is mutated and corrected according to the preset adjustment coefficient and the deviation voltage value to generate a voltage target setpoint.

[0038] The mutation threshold set includes a first mutation threshold (e.g., +12V) and a second mutation threshold (e.g., -12V). The mutation judgment logic of this application is as follows: The real-time calculated deviation voltage value is compared with the first mutation threshold. If the deviation voltage value is greater than or equal to the first mutation threshold, a positive over-limit is determined, corresponding to a voltage drop exceeding the allowable range caused by a sudden load increase. The real-time calculated deviation voltage value is compared with the second mutation threshold. If the deviation voltage value is less than or equal to the second mutation threshold, a negative over-limit is determined, corresponding to a voltage surge exceeding the allowable range caused by a sudden load unload. The mutation judgment of this application needs to be completed within one control cycle. For example, in a system with a target setpoint of 750V, if the deviation voltage value is calculated to be 20V at a certain moment, which is greater than the first mutation threshold of +12V, the trigger condition is immediately met; if the deviation voltage value is -20V, which is less than the second mutation threshold of -12V, the trigger condition is also met.

[0039] Once the deviation voltage value is determined to exceed the mutation threshold set, the system immediately enters the correction calculation operation. The first step is to determine the mutation compensation direction sign according to the preset compensation control direction mapping strategy. The essence of this mapping strategy is a simple sign function: when the triggering condition is that the deviation voltage value is greater than or equal to the first mutation threshold (positive deviation exceeding the limit), it means that the actual voltage is too low, and the voltage target value needs to be raised to generate a stronger boost command. Therefore, the mapping strategy stipulates that the mutation compensation direction sign is "positive" at this time; when the triggering condition is that the deviation voltage value is less than or equal to the second mutation threshold (negative deviation exceeding the limit), it means that the actual voltage is too high, and the voltage target value needs to be lowered to generate a stronger lowering command. Therefore, the mapping strategy stipulates that the mutation compensation direction sign is "negative" at this time. The above sign determination operation lays the foundation for the reverse regulation of this application—to suppress voltage drop, the control target needs to be temporarily and significantly increased; to suppress voltage surge, the control target needs to be temporarily and significantly decreased. This is essentially injecting a feedforward signal opposite to the current disturbance trend at the input of the voltage outer loop, thereby physically offsetting the effect of power imbalance in advance. For example, when a sudden increase in load causes a voltage drop with a deviation of +20V, the compensation direction sign is positive, indicating that a positive additive correction will be performed on the original target setting value.

[0040] Next, the voltage compensation amount is calculated. In this application, this calculation operation uses the adjustment coefficient obtained above and the absolute value of the current deviation voltage value for product operation, where the adjustment coefficient is a dimensionless amplification factor. The absolute value of the deviation voltage value directly quantifies the severity of the current voltage deviation; taking a deviation of +20V as an example, its absolute value is 20. The product calculation can be expressed as: Voltage compensation amount = Adjustment coefficient × |Deviation voltage value|. Substituting the values, we get: Voltage compensation amount = 5 × 20 = 100V. Through the above calculation operation, a sensing signal reflecting the magnitude of the deviation is amplified by a pre-optimized gain into a powerful compensation command with voltage dimensions, used to directly correct the target setpoint. It should be understood that the adjustment coefficient k must be greater than 1 to ensure that the compensation is amplified rather than proportional. For example, k=5 results in a 100V compensation for a 20V deviation. This amplification effect is crucial, as it allows the outer-loop voltage controller to instantly acquire a deliberately amplified error, thereby unleashing its maximum potential for rapid response. This results in an output current command that is much larger than the conventional ratio, instructing the rectifier to draw or feed back a massive amount of instantaneous power from the grid to powerfully counteract load surges. This is the key mathematical manifestation of how this method overcomes the slow response and insufficient power of traditional proportional-integral controllers.

[0041] Finally, based on the determined sign of the abrupt change compensation direction and the calculated voltage compensation amount, the preset DC voltage target setpoint is corrected to generate the final voltage target setpoint. The correction process used in this application is algebraic addition: if the sign of the abrupt change compensation direction is positive, then the voltage target setpoint = DC voltage target setpoint + voltage compensation amount; if the sign is negative, then the voltage target setpoint = DC voltage target setpoint - voltage compensation amount. This operation combines direction and magnitude, completing the dynamic reconstruction of the original constant target value. Using the previous example, if the DC voltage target setpoint is 750V, the compensation direction sign is positive, and the voltage compensation amount is 100V, then the generated voltage target setpoint = 750V + 100V = 850V. This 850V value will replace the original 750V as the input target for the voltage outer loop controller in the next moment. The control system no longer attempts to pull the output voltage back to 750V, but instead assumes the system should operate at 850V. This artificially high target forces the rectifier to maximize its output power, thereby quickly filling the power gap caused by the sudden load increase. The actual effect is to curb further voltage drops and accelerate their recovery. Similarly, if there is a sudden load unloading with a deviation of -20V, the compensation direction is negative, and the calculated voltage compensation is also 100V. The voltage target setpoint = 750V - 100V = 650V. This low target value prompts the rectifier to significantly reduce input power, absorb excess energy from the bus, and suppress voltage surges.

[0042] Through the operation of step S2 above, an intelligent and predictive compensation strategy is successfully transformed into a simple setpoint change that can be directly understood and executed by the existing dual-loop control architecture. This allows this application to achieve a leap in the dynamic performance of the control loop without modifying the underlying mature proportional-integral controller structure and parameters. It only requires applying a dynamic and inverse offset to the outermost target value, perfectly matching the core objective of "significantly suppressing fluctuations in a simple and effective manner while retaining the existing mature architecture".

[0043] Step S3: Adjust the input voltage of the outer loop controller in the target rectifier module according to the target voltage setpoint to suppress the voltage of the output DC bus.

[0044] Step S3 of this application starts with the successful triggering of step S2, marking the formal entry of the system into a managed dynamic adjustment cycle. Its internal logic is clearly divided into two stages: one is the active inhibition stage based on dynamic target values, and the other is the timeout reset stage to ensure the safe return of the system.

[0045] First, the preset timeout timer is reset and started. The timeout timer is a software counter or hardware timer function whose counting unit is synchronized with the system's control cycle, for example, incrementing once every 62.5 μs. The significance of resetting and starting it is to establish an independent time scale for this dynamic adjustment process, beginning to measure the time consumed from the initiation to completion of the suppression action. Simultaneously, the obtained voltage target setpoint (e.g., 850V) is input to the setpoint port of the voltage outer loop controller in the target rectifier module. The voltage outer loop controller is the outer loop proportional-integral regulator of the dual closed-loop control architecture described in the operating environment. It originally received a fixed DC voltage target setpoint (e.g., 750V), but now receives this dynamically corrected new target value. This input operation directly changes the reference reference of the entire control loop. The proportional-integral regulator immediately calculates based on the new, larger error (e.g., the error of 120V between the current actual voltage of 730V and the target 850V), outputting a correspondingly significantly enhanced direct-axis current reference command. This instruction, via rapid tracking through the inner current loop, ultimately drives the insulated-gate bipolar transistor to operate at a higher duty cycle, drawing significantly increased active power from the grid side. This exerts a strong reverse pull on the declining DC bus voltage, curbing its downward trend and prompting a recovery (as referenced). Figure 5 (As shown).

[0046] Subsequently, the system enters a cyclic judgment and execution process. This involves real-time reading of the current value of the counting timeout timer to obtain the elapsed adjustment duration since the start of the current cycle, while simultaneously acquiring the actual voltage of the DC bus in real time. Reading the adjustment duration provides a time basis for process management, while acquiring the actual voltage allows for continuous evaluation of the suppression effect and updates to the feedback. Next, the system performs a crucial judgment: comparing whether the current adjustment duration has reached a preset timeout adjustment threshold (e.g., 700ms). This timeout adjustment threshold, obtained through intelligent tuning based on module specifications during the initialization phase, represents the maximum duration for which the system allows dynamic suppression attempts. If the adjustment duration has not reached this threshold, the system is within the normal dynamic adjustment window, and steps S1 to S32 will be repeated, forming a high-speed closed loop. The specific operation process of the high-speed closed loop will not be elaborated further here. The suppression process achieves dynamic adaptability through a dynamic cyclic adjustment process: as the suppression action takes effect, the actual voltage begins to rise (in the case of a sudden load increase), and the deviation voltage value gradually decreases. The voltage target setpoint calculated according to the formula in step S2 (e.g., starting from 850V) also dynamically decreases accordingly, forming a gradually weakening feedforward compensation signal until the voltage rises to the point where the absolute value of the deviation voltage value is less than the absolute value of the sudden change threshold (e.g., the absolute value of the deviation voltage value < |±12V|). Taking a sudden load increase as an example, when the actual voltage rises from 730V to above 742V, the deviation voltage value will be less than |-12V|, meeting the judgment condition for exiting the active suppression stage. The system determines that the active suppression has successfully controlled the voltage fluctuation to an acceptable range, and the purpose of dynamic adjustment has been achieved. Therefore, it exits the loop and forcibly restores the voltage target setpoint to the original DC voltage target setpoint (e.g., 750V), and the voltage outer loop controller returns to the steady-state control mode. The above-described cyclic active suppression mechanism ensures that the suppression intensity can smoothly decay with the improvement of the system state, avoids overcompensation, and achieves fast and accurate dynamic recovery.

[0047] However, if during the cycle, the adjustment time reaches the timeout adjustment threshold, and the real-time calculated deviation voltage value is still greater than or equal to the first mutation threshold (positive deviation has not fallen back), or less than or equal to the second mutation threshold (negative deviation has not fallen back), it indicates that the dynamic suppression process has failed to stabilize the system within the allowable time as expected. This may be due to abnormally severe or continuous load disturbances, or the presence of unmodeled dynamics in the system. At this time, the system will be forced to switch from the dynamic adjustment phase to the timeout recovery phase. The operation logic of this phase is to first stop the dynamic target value update based on the formula in step S2, and then perform a unidirectional reset adjustment on the current voltage target setpoint according to the preset voltage reset adjustment step size. The voltage reset adjustment step size is a very small fixed value (e.g., 0.04V / cycle), which is calculated during the initialization phase based on the safety margin and reset time requirements. The adjustment direction is determined by the relationship between the current voltage target setpoint and the DC voltage target setpoint: if the voltage target setpoint is higher than the setpoint (e.g., it remains high after a sudden load increase), it is reduced by one step per cycle; if it is lower than the setpoint (e.g., it becomes low after a sudden load decrease), it is increased by one step per cycle. It should be understood that during the timeout recovery phase, each adjustment is small in magnitude and constant in direction, no longer dependent on real-time deviation. Subsequently, the adjusted new voltage target setpoint is input to the outer voltage loop controller for adjustment. This process is repeated in each control cycle to implement a conservative, safe, and absolutely convergent exit strategy. The timeout recovery mechanism no longer attempts to forcefully suppress fluctuations, but instead acknowledges that the current dynamic adjustment strategy may be inapplicable or ineffective, and instead uses a soft-landing adjustment method to gently pull back the artificially raised or lowered voltage target value to the original setpoint at an extremely slow speed, without impacting the system. For example, if the target voltage setpoint is 800V at the timeout, the system will gradually restore it to 750V by decreasing it by 0.04V every 62.5μs over a calculated period. During this slow recovery, the actual DC bus voltage is adjusted by the underlying proportional-integral controller based on this slowly changing setpoint, without causing large power jumps. The system essentially returns to its inherent, slower but stable natural recovery characteristics. This timeout recovery phase continues until the target voltage setpoint finally equals the DC voltage target setpoint. At this point, the entire suppression process is complete, all system state variables return to their normal positions, and the system is ready to respond to the next event.

[0048] The above step S3, by integrating dynamic adjustment loop and timeout safety reset, not only achieves rapid and proactive suppression of load mutations, but also ensures that the control strategy can reliably and smoothly exit under any abnormal conditions. Thus, while improving dynamic performance, it strictly guarantees the long-term operational robustness and safety of the system.

[0049] Please see Figure 2 , Figure 2This is a schematic diagram of a load-sudden change output DC bus voltage fluctuation suppression device provided in an embodiment of this application. Figure 2 As shown, the output DC bus voltage fluctuation suppression device 2 for load sudden changes includes: deviation calculation module 21, sudden change judgment module 22, sudden change suppression module 23, threshold calculation module 24, adjustment setting module 25, and reset step size module 26.

[0050] The deviation calculation module 21 is used to collect the actual voltage of the output DC bus of the target rectifier module in real time, and calculate the deviation voltage value between the actual voltage and the preset DC voltage target setting value. The mutation judgment module 22 is used to perform mutation correction on the DC voltage target set value according to the preset adjustment coefficient and the deviation voltage value when the deviation voltage value reaches the preset mutation threshold set, and generate a voltage target set value. The mutation suppression module 23 is used to adjust the input voltage of the voltage outer loop controller in the target rectifier module according to the voltage target given value, so as to suppress the voltage of the output DC bus.

[0051] In one possible implementation, the mutation determination module 22 is specifically used for: The sign of the abrupt compensation direction is determined based on the sign of the deviation voltage value using a preset compensation control direction mapping strategy. The voltage compensation amount is generated by multiplying the preset adjustment coefficient and the absolute value of the deviation voltage value. Based on the mutation compensation direction sign and the voltage compensation amount, the DC voltage target setpoint is corrected to generate the voltage target given value.

[0052] In one possible implementation, the mutation suppression module 23 is specifically used for: Step S31: Reset and start the preset timeout timer, and adjust the input voltage of the voltage outer loop controller in the target rectifier module according to the voltage target given value; Step S32: Read the adjustment duration of the timeout timer in real time, and collect the actual voltage of the output DC bus of the target rectifier module in real time; When the adjustment duration does not reach the timeout adjustment threshold, repeat steps S1 to S32 until the deviation voltage value is less than the first mutation threshold and the deviation voltage value is greater than the second mutation threshold. When the adjustment duration reaches the timeout adjustment threshold, and the deviation voltage value is greater than or equal to the first sudden change threshold, or the deviation voltage value is less than or equal to the second sudden change threshold, the voltage target setpoint is unidirectionally reset and adjusted according to the voltage reset adjustment step size to update the voltage target setpoint, and the input voltage of the voltage outer loop controller in the target rectifier module is adjusted according to the voltage target setpoint until the voltage target setpoint returns to the DC voltage target setpoint.

[0053] In one possible implementation, the output DC bus voltage fluctuation suppression device 2 for load abrupt changes further includes a threshold calculation module 24, which is specifically used for: Based on the received voltage regulation accuracy requirement data and the DC voltage target setting value, calculate the upper limit and lower limit of voltage fluctuation allowed for voltage regulation operation; The received adjustment safety margin and the upper limit of voltage fluctuation are multiplied to calculate the first sudden change threshold; The adjustment safety margin and the lower limit of voltage fluctuation are multiplied to calculate the second mutation threshold.

[0054] In one possible implementation, the output DC bus voltage fluctuation suppression device 2 for load surges further includes an adjustment setting module 25, which is specifically used for: According to the preset data format, the voltage regulation accuracy requirement data, the DC voltage target set value, the adjustment safety margin, and the preset maximum full-load power are aggregated into the standard operating parameter set of the target rectifier module; The standard operating parameter set is subjected to multi-level forward nonlinear transformation to obtain the adjustment coefficient and the timeout adjustment threshold.

[0055] In one possible implementation, the output DC bus voltage fluctuation suppression device 2 for load surges further includes a reset step module 26, which is specifically used for: The safe adjustment safety margin and the DC voltage target set value are multiplied to obtain the safe adjustment DC voltage threshold. The maximum expected reset deviation is set according to the safety regulation DC voltage threshold by using a preset hardware safety regulation strategy; Calculate the total number of reset steps based on the preset total reset completion time and the preset unit control cycle duration; Calculate the voltage reset adjustment step size within each unit control cycle based on the maximum expected reset deviation and the total number of reset steps.

[0056] The deviation calculation module 21, mutation judgment module 22, mutation suppression module 23, threshold calculation module 24, adjustment setting module 25, and reset step size module 26 can all be implemented in software or hardware. For example, the implementation of the deviation calculation module 21 will be described below. Similarly, the implementation of the mutation judgment module 22, mutation suppression module 23, threshold calculation module 24, adjustment setting module 25, and reset step size module 26 can refer to the implementation of the deviation calculation module 21.

[0057] As an example of a software functional unit, the deviation calculation module 21 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Further, the aforementioned computing instance may be one or more. For example, the deviation calculation module 21 may include code running on multiple hosts, virtual machines, or containers. It should be noted that the multiple hosts, virtual machines, or containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts, virtual machines, or containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0058] Similarly, multiple hosts, virtual machines, or containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0059] As an example of a hardware functional unit, the deviation calculation module 21 may include at least one computing device, such as a server. Alternatively, the deviation calculation module 21 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0060] The deviation calculation module 21 includes multiple computing devices that can be distributed in the same region or in different regions. Similarly, the deviation calculation module 21 can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the deviation calculation module 21 can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0061] See Figure 3 As shown, Figure 3 This is a schematic diagram of a computing device provided in this application. The computing device 100 includes: a processor 104, a communication interface 108, a bus 102, and a memory 106. The processor 104, the communication interface 108, and the memory 106 communicate via the bus 102. In practical applications, communication can also be achieved through other means such as wireless transmission; however, this is not limited here.

[0062] The computing device 100 may be a server or a terminal device. It should be understood that this application does not limit the number of processors and memory in the computing device 100.

[0063] The processor 104 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0064] The communication interface 108 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 100 and other devices or communication networks.

[0065] Bus 102 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 3 The bus 102 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 102 may include a path for transmitting information between various components of the computing device 100 (e.g., memory 106, processor 104, communication interface 108).

[0066] Memory 106 may include volatile memory, such as random access memory (RAM). Memory 106 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0067] The memory 106 stores executable program code, and the processor 104 executes the executable program code to implement the functions of the aforementioned deviation calculation module 21, mutation judgment module 22, mutation suppression module 23, threshold calculation module 24, adjustment setting module 25 and reset step size module 26 respectively, thereby realizing the output DC bus voltage fluctuation suppression method for load mutation. That is, the memory 106 stores instructions for executing the output DC bus voltage fluctuation suppression method for load mutation.

[0068] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform a method for suppressing output DC bus voltage fluctuations due to load changes, or instruct the computing device to perform a method for suppressing output DC bus voltage fluctuations due to load changes.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for suppressing output DC bus voltage fluctuations due to load changes, characterized in that, The method includes: Step S1: Real-time acquisition of the actual voltage of the output DC bus of the target rectifier module, and calculation of the deviation voltage value between the actual voltage and the preset DC voltage target setting value; Step S2: When the deviation voltage value reaches a preset mutation threshold set, the mutation compensation direction sign is determined according to the positive or negative sign of the deviation voltage value through a preset compensation control direction mapping strategy. The voltage compensation amount is generated by multiplying the preset adjustment coefficient and the absolute value of the deviation voltage value. The DC voltage target set value is corrected according to the mutation compensation direction sign and the voltage compensation amount to generate the voltage target set value. The mutation threshold set includes a first mutation threshold and a second mutation threshold. Based on the received voltage regulation accuracy requirement data and the DC voltage target setting value, the upper limit and lower limit of voltage fluctuation allowed for voltage regulation operation are calculated. The received adjustment safety margin and the upper limit of voltage fluctuation are multiplied to set the first mutation threshold. The adjustment safety margin and the lower limit of voltage fluctuation are multiplied to set the second mutation threshold. Step S3: Adjust the input voltage of the outer loop controller in the target rectifier module according to the target voltage setpoint to suppress the voltage of the output DC bus, including: Step S31: Reset and start the preset timeout timer, and adjust the input voltage of the voltage outer loop controller in the target rectifier module according to the voltage target given value; Step S32: Read the adjustment duration of the timeout timer in real time, and collect the actual voltage of the output DC bus of the target rectifier module in real time; When the adjustment duration does not reach the preset timeout adjustment threshold, repeat steps S1 to S32 until the deviation voltage value is less than the first mutation threshold and the deviation voltage value is greater than the second mutation threshold. When the adjustment duration reaches the timeout adjustment threshold, and the deviation voltage value is greater than or equal to the first sudden change threshold, or the deviation voltage value is less than or equal to the second sudden change threshold, the voltage target setpoint is unidirectionally reset and adjusted according to a preset voltage reset adjustment step size to update the voltage target setpoint, and the input voltage of the voltage outer loop controller in the target rectifier module is adjusted according to the voltage target setpoint until the voltage target setpoint returns to the DC voltage target setpoint; it also includes: according to a preset data format, the voltage regulation accuracy requirement data, the DC voltage target setpoint, the adjustment safety margin, and the preset maximum Full-load power is aggregated into a standard operating parameter set for the target rectifier module; the standard operating parameter set is subjected to multi-layer forward nonlinear transformation processing to obtain the adjustment coefficient and timeout adjustment threshold; the adjustment safety margin and the DC voltage target set value are multiplied to obtain a safe adjustment DC voltage threshold; based on the safe adjustment DC voltage threshold, a maximum expected reset deviation is set according to a preset hardware safety adjustment strategy; the total number of reset steps is calculated based on the preset total reset completion time and the preset unit control cycle duration; the voltage reset adjustment step size within each unit control cycle is calculated based on the maximum expected reset deviation and the total number of reset steps.

2. A device for suppressing output DC bus voltage fluctuations due to load changes, applied to the method for suppressing output DC bus voltage fluctuations due to load changes as described in claim 1, characterized in that, The device includes: The deviation calculation module is used to collect the actual voltage of the output DC bus of the target rectifier module in real time, and calculate the deviation voltage value between the actual voltage and the preset DC voltage target setting value. The mutation judgment module is used to perform mutation correction on the DC voltage target set value according to the preset adjustment coefficient and the deviation voltage value when the deviation voltage value reaches the preset mutation threshold set, and generate the voltage target set value. A sudden change suppression module is used to adjust the input voltage of the outer loop controller in the target rectifier module according to the voltage target given value, so as to suppress the voltage of the output DC bus.

3. A computing device, characterized in that, The computing device includes: At least one processor; and, A memory and a communication interface that are communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the output DC bus voltage fluctuation suppression method according to claim 1 by executing the instructions stored in the memory.

4. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for suppressing output DC bus voltage fluctuations according to claim 1, which describes a method for suppressing load mutations.

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