Gate drive circuit and gate drive method for hybrid buck converter

Abstract

The application discloses a gate driving circuit and a gate driving method of a hybrid buck converter, and belongs to the technical field of circuits. When the hybrid buck converter comprises a high-side power tube and a low-side power tube, the gate driving circuit converts a gate driving signal in a low-voltage domain into a high-side driving signal and a low-side driving signal in a high-voltage domain through isolation, alternately outputs the high-side driving signal and the low-side driving signal, so that the high-side driving signal drives the high-side power tube to switch, and the low-side driving signal drives the low-side power tube to switch; when the hybrid buck converter comprises the high-side power tube and does not comprise the low-side power tube, the gate driving circuit converts the gate driving signal in the low-voltage domain into the high-side driving signal in the high-voltage domain through isolation and outputs the high-side driving signal, so that the high-side driving signal drives the high-side power tube to switch. The application realizes the isolation of a low-voltage circuit module and a high-voltage driving module and the transmission of a gate driving signal between different voltage domains, and ensures the normal work of the hybrid buck converter.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a gate drive circuit and gate drive method for a hybrid buck converter. Background Technology

[0002] Switching power supplies are rapidly developing towards higher frequencies and smaller sizes. However, in Figure 1 In the conventional buck converter shown, the high-side power switch M... H During the switching process, the input current I IN It exhibits a discontinuous pulse pattern, accompanied by extremely high di / dt transient noise, resulting in an input voltage V IN Significant voltage ripple appeared on the bus, causing severe electromagnetic interference (EMI) noise. This noise interfered with the power supply circuitry of the preceding stage and other sensitive circuits on the same input bus, especially when operating at high switching frequencies, where the di / dt transient noise during switching transients was even higher, making the EMI problem more prominent. Although increasing the input capacitor C... IN While large-capacity capacitors can suppress noise to some extent, they occupy a large area of ​​printed circuit boards (PCBs), which contradicts the goal of miniaturizing power supply systems.

[0003] To improve input current I IN To address the discontinuities and suppress voltage ripple, various buck converter architectures with continuous input current characteristics have been developed in related technologies.

[0004] Figure 2 The Cuk converter shown can achieve continuous current on both the input and output sides, which helps reduce ripple and EMI noise, but its output voltage V OUT Relative to input voltage V IN It is an inverted output (i.e., negative voltage output), therefore, it is mainly suitable for negative power supply applications, and its application range is greatly limited.

[0005] Figure 3 Although the passive-stacked third-order buck converter shown can achieve continuous output and input current, the drive module of this architecture can only withstand low voltage. Therefore, the input and output voltages of this buck converter are very low, and the entire architecture cannot be applied to the high-voltage domain. Summary of the Invention

[0006] This application provides a gate driving circuit and gate driving method for a hybrid buck converter, which solves the output inversion problem of Cuk converters and the problem that passively stacked third-order buck converters cannot be applied to high voltage. The technical solution is as follows:

[0007] According to a first aspect of this application, a gate drive circuit for a hybrid buck converter is provided.

[0008] The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage.

[0009] When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter, and the low-side output terminal of the gate drive circuit is connected to the gate of the low-side power transistor in the hybrid buck converter. The gate drive circuit is used to convert the gate drive signal into a high-side drive signal and a low-side drive signal in the high-voltage domain through isolation, and alternately output the high-side drive signal and the low-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal, and drive the low-side power transistor to turn on and off through the low-side drive signal.

[0010] When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter, and the gate drive circuit is used to convert the gate drive signal into a high-side drive signal in the high-voltage domain through isolation, and output the high-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal.

[0011] The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage. The voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. The isolation types include chip junction isolation and capacitor isolation.

[0012] In one possible implementation, when the hybrid buck converter includes a high-side power transistor and a low-side power transistor, and the isolation type is capacitive isolation, the gate drive circuit includes a dead-time controller, a first isolator, a second isolator, a first gate driver, and a second gate driver.

[0013] The input terminal of the dead time controller serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module; the first output terminal of the dead time controller is connected to the first input terminal of the first isolator, and the second output terminal of the dead time controller is connected to the first input terminal of the second isolator.

[0014] The second input terminal of the first isolator and the bias terminal of the first gate driver are connected to the output terminal of the external first bootstrap circuit. The output terminal of the first isolator is connected to the first input terminal of the first gate driver. The second input terminal of the first gate driver is connected to the output terminal of the hybrid buck converter. The output terminal of the first gate driver serves as the high-side output terminal of the gate drive circuit and is connected to the gate of the high-side power transistor. The voltage at the bias terminal of the first gate driver is the sum of the output voltage and the power supply voltage.

[0015] The second input terminal of the second isolator and the bias terminal of the second gate driver are connected to the output terminal of the external second bootstrap circuit. The output terminal of the second isolator is connected to the first input terminal of the second gate driver. The second input terminal of the second gate driver is connected to the low-side switching node. The output terminal of the second gate driver serves as the low-side output terminal of the gate drive circuit and is connected to the gate of the low-side power transistor. The voltage at the bias terminal of the second gate driver is the sum of the low-side switching node voltage and the power supply voltage.

[0016] In one possible implementation, the first isolator includes a first modulation circuit, a first isolation capacitor assembly, and a first demodulation circuit connected in sequence.

[0017] The second isolator includes a second modulation circuit, a second isolation capacitor assembly, and a second demodulation circuit connected in sequence.

[0018] In one possible implementation, when the hybrid buck converter includes high-side power transistors and low-side power transistors, and the isolation type is chip junction isolation, the gate drive circuit includes a first pull-up level shifter, a pull-down level shifter, a rising edge dead time controller, a falling edge dead time controller, a third gate driver, and a fourth gate driver; wherein, the first pull-up level shifter includes a first low-voltage module, a first high-voltage module, a first high common-mode transient compensation module, a second high common-mode transient compensation module, and a first isolation module, and the pull-down level shifter includes a second high-voltage module, a third high-voltage module, a third high common-mode transient compensation module, a fourth high common-mode transient compensation module, and a second isolation module;

[0019] The input terminal of the first low-voltage module serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the first low-voltage module is connected to the first input terminal of the first high-voltage module through the first isolation module. The second output terminal of the first low-voltage module is connected to the second input terminal of the first high-voltage module through the first isolation module. The third input terminal of the first high-voltage module is connected to the first output terminal of the second high common-mode transient compensation module. The fourth input terminal of the first high-voltage module is connected to the second output terminal of the second high common-mode transient compensation circuit. The output terminal of the first high-voltage module serves as the output terminal of the first pull-up level shifter and is connected to the input terminal of the rising edge dead time controller and the input terminal of the second high-voltage module. The output terminal of the rising edge dead time controller is connected to the gate of the high-side power transistor through the third gate driver. The input terminal of the first high common-mode transient compensation module is grounded. The output terminal of the first high common-mode transient compensation module is connected to the input terminal of the second high common-mode transient compensation module through the first isolation module.

[0020] The input terminal of the second high-voltage module serves as the input terminal of the pull-down level shifter and is connected to the output terminal of the first pull-up level shifter. The first output terminal of the second high-voltage module is connected to the first input terminal of the third high-voltage module through the second isolation module. The second output terminal of the second high-voltage module is connected to the second input terminal of the third high-voltage module through the second isolation module. The third input terminal of the third high-voltage module is connected to the first output terminal of the fourth high common-mode transient compensation module. The fourth input terminal of the third high-voltage module is connected to the second output terminal of the fourth high common-mode transient compensation circuit. The output terminal of the third high-voltage module serves as the output terminal of the pull-down level shifter and is connected to the input terminal of the falling edge dead-time controller. The output terminal of the falling edge dead-time controller is connected to the gate of the low-side power transistor through the fourth gate driver. The input terminal of the third high common-mode transient compensation module is connected to the high-side bootstrap voltage rail. The output terminal of the third high common-mode transient compensation module is connected to the input terminal of the fourth high common-mode transient compensation module through the second isolation module.

[0021] The chip containing the gate drive circuit includes a first high-voltage N-type doped region N Tub, a second high-voltage NTub, and a first low-voltage N Tub. The first low-voltage module and the first high common-mode transient compensation module are located in the first P-well of the first low-voltage N Tub. The first high-voltage module, the second high-voltage module, the second high common-mode transient compensation module, the third high common-mode transient compensation module, the rising edge dead-time controller, and the third gate driver are located in the second P-well of the first high-voltage N Tub. The third high-voltage module, the fourth high common-mode transient compensation module, the falling edge dead-time controller, and the fourth gate driver are located in the third P-well of the second high-voltage N Tub. The first high-voltage N Tub and the second high-voltage N Tub are connected to the high-side bootstrap voltage rail. The first low-voltage N Tub is connected to the power supply voltage. The second P-well is connected to the output voltage. The third P-well is connected to the low-side switching node voltage. The first P-well is grounded.

[0022] In one possible implementation, the first low-voltage module includes a first inverter, a second inverter, a third inverter, a first pulse generating circuit, a second pulse generating circuit, a first switching transistor, and a second switching transistor; the input terminals of the first inverter and the second inverter serve as the input terminals of the first low-voltage module; the output terminal of the first inverter is connected to the input terminal of the first pulse generating circuit; the output terminal of the first pulse generating circuit is connected to the gate of the first switching transistor; the source of the first switching transistor is grounded; the drain of the first switching transistor is the first output terminal of the first low-voltage module; the output terminal of the second inverter is connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the second pulse generating circuit; the output terminal of the second pulse generating circuit is connected to the gate of the second switching transistor; the source of the second switching transistor is grounded; and the drain of the second switching transistor is the second output terminal of the first low-voltage module.

[0023] The second high-voltage module includes a fourth inverter, a fifth inverter, a sixth inverter, a third pulse generation circuit, a fourth pulse generation circuit, a third switch, and a fourth switch. The input terminals of the fourth and fifth inverters serve as the input terminals of the second high-voltage module. The output terminal of the fourth inverter is connected to the input terminal of the third pulse generation circuit. The output terminal of the third pulse generation circuit is connected to the gate of the third switch. The source of the third switch is connected to the high-side bootstrap voltage rail, and the drain of the third switch is the first output terminal of the second high-voltage module. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the input terminal of the fourth pulse generation circuit. The output terminal of the fourth pulse generation circuit is connected to the gate of the fourth switch. The source of the fourth switch is connected to the high-side bootstrap voltage rail, and the drain of the fourth switch is the second output terminal of the second high-voltage module.

[0024] In one possible implementation, the first high-voltage module includes a first damping resistor, a second damping resistor, first to sixth current mirrors, and a first RS latch; the first end of the first damping resistor is the first input terminal of the first high-voltage module, the second end of the first damping resistor is connected to the input terminal of the first current mirror, the output terminal of the first current mirror is connected to the input terminal of the second current mirror, the first output terminal of the second current mirror is connected to the input terminal of the third current mirror, the second output terminal of the second current mirror is connected to the set terminal of the first RS latch, the output terminal of the third current mirror is connected to the reset terminal of the first RS latch, the first end of the second damping resistor is the second input terminal of the first high-voltage module, the second end of the second damping resistor is connected to the input terminal of the fourth current mirror, the output terminal of the fourth current mirror is connected to the input terminal of the fifth current mirror, the first output terminal of the fifth current mirror is connected to the input terminal of the sixth current mirror, the second output terminal of the fifth current mirror is connected to the reset terminal of the first RS latch, the output terminal of the sixth current mirror is connected to the set terminal of the first RS latch, and the output terminal of the first RS latch is the output terminal of the first high-voltage module.

[0025] The third high-voltage module includes a third damping resistor, a fourth damping resistor, seventh to twelfth current mirrors, and a second RS latch. The first end of the third damping resistor is the first input terminal of the third high-voltage module. The second end of the third damping resistor is connected to the input terminal of the seventh current mirror. The output terminal of the seventh current mirror is connected to the input terminal of the eighth current mirror. The first output terminal of the eighth current mirror is connected to the input terminal of the ninth current mirror. The second output terminal of the eighth current mirror is connected to the set terminal of the second RS latch. The output terminal of the ninth current mirror is connected to the reset terminal of the second RS latch. The first end of the fourth damping resistor is the second input terminal of the third high-voltage module. The second end of the fourth damping resistor is connected to the input terminal of the tenth current mirror. The output terminal of the tenth current mirror is connected to the input terminal of the eleventh current mirror. The first output terminal of the eleventh current mirror is connected to the input terminal of the twelfth current mirror. The second output terminal of the eleventh current mirror is connected to the reset terminal of the second RS latch. The output terminal of the twelfth current mirror is connected to the set terminal of the second RS latch. The output terminal of the second RS latch is the output terminal of the third high-voltage module.

[0026] In one possible implementation, the first high common-mode transient compensation module includes a fifth switching transistor, and the second high common-mode transient compensation module includes a fifth damping resistor and a thirteenth current mirror; the gate and source of the fifth switching transistor are the input terminals of the first high common-mode transient compensation module and grounded, the drain of the fifth switching transistor is connected to the first terminal of the fifth damping resistor through the first isolation module, the second terminal of the fifth damping resistor is connected to the input terminal of the thirteenth current mirror, the first output terminal of the thirteenth current mirror serves as the first output terminal of the second high common-mode transient compensation module and is connected to the third input terminal of the first high voltage module, and the second output terminal of the thirteenth current mirror serves as the second output terminal of the second high common-mode transient compensation module and is connected to the fourth input terminal of the first high voltage module;

[0027] The third high common-mode transient compensation module includes a sixth switching transistor, and the fourth high common-mode transient compensation module includes a sixth damping resistor and a fourteenth current mirror. The gate and source of the sixth switching transistor are the input terminals of the third high common-mode transient compensation module and connected in parallel to the high-side bootstrap voltage rail. The drain of the sixth switching transistor is connected to the first terminal of the sixth damping resistor through the second isolation module. The second terminal of the sixth damping resistor is connected to the input terminal of the fourteenth current mirror. The first output terminal of the fourteenth current mirror serves as the first output terminal of the fourth high common-mode transient compensation module and is connected to the third input terminal of the third high-voltage module. The second output terminal of the fourteenth current mirror serves as the second output terminal of the fourth high common-mode transient compensation module and is connected to the fourth input terminal of the third high-voltage module.

[0028] In one possible implementation, when the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, and the isolation type is capacitive isolation, the gate drive circuit includes a third isolator and a fifth gate driver.

[0029] The first input terminal of the third isolator serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The second input terminal of the third isolator and the bias terminal of the fifth gate driver are connected to the output terminal of the external third bootstrap circuit. The output terminal of the third isolator is connected to the first input terminal of the fifth gate driver, and the second input terminal of the fifth gate driver is connected to the output terminal of the hybrid buck converter. The output terminal of the fifth gate driver serves as the high-side output terminal of the gate drive circuit and is connected to the gate of the high-side power transistor. The voltage at the bias terminal of the fifth gate driver is the sum of the output voltage and the power supply voltage.

[0030] In one possible implementation, when the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, and the isolation type is chip junction isolation, the gate drive circuit includes a second pull-up level shifter and a sixth gate driver; wherein the second pull-up level shifter includes a second low-voltage module, a fourth high-voltage module, a fifth high common-mode transient compensation module, a sixth high common-mode transient compensation module, and a third isolation module;

[0031] The input terminal of the second low-voltage module serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the second low-voltage module is connected to the first input terminal of the fourth high-voltage module through the third isolation module. The second output terminal of the second low-voltage module is connected to the second input terminal of the fourth high-voltage module through the third isolation module. The third input terminal of the fourth high-voltage module is connected to the first output terminal of the sixth high common-mode transient compensation module. The fourth input terminal of the fourth high-voltage module is connected to the second output terminal of the sixth high common-mode transient compensation circuit. The output terminal of the fourth high-voltage module serves as the output terminal of the second pull-up level shifter and is connected to the gate of the high-side power transistor through the sixth gate driver. The input terminal of the fifth high common-mode transient compensation module is grounded, and the output terminal of the fifth high common-mode transient compensation module is connected to the input terminal of the sixth high common-mode transient compensation module through the third isolation module.

[0032] The chip containing the gate drive circuit includes a third high-voltage N-Tub and a second low-voltage N-Tub. The second low-voltage module and the fifth high common-mode transient compensation module are located in the fourth P-well of the second low-voltage N-Tub. The fourth high-voltage module, the sixth high common-mode transient compensation module, and the sixth gate driver are located in the fifth P-well of the third high-voltage N-Tub. The third high-voltage N-Tub is connected to the high-side bootstrap voltage rail, the second low-voltage N-Tub is connected to the power supply voltage, the fifth P-well is connected to the output voltage, and the fourth P-well is grounded.

[0033] According to a second aspect of this application, a gate driving method for a hybrid buck converter is provided for use in a gate driving circuit as described above, the method comprising:

[0034] The gate drive circuit receives a low-voltage gate drive signal output by the current control module, and the voltage range of the gate drive signal is from 0 to the power supply voltage.

[0035] When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal and a low-side drive signal in the high-voltage domain through isolation, and alternately outputs the high-side drive signal and the low-side drive signal so that the high-side power transistor is driven to turn on and off by the high-side drive signal, and the low-side power transistor is driven to turn on and off by the low-side drive signal.

[0036] When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal in the high-voltage domain through isolation, and outputs the high-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal.

[0037] The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage. The voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. The isolation types include chip junction isolation and capacitor isolation.

[0038] The beneficial effects of the technical solution provided in this application include at least the following:

[0039] Whether it is a hybrid buck converter that includes both high-side and low-side power transistors, or a hybrid buck converter that includes high-side power transistors but not low-side power transistors, the gate drive circuit can convert the gate drive signal in the low-voltage domain into the gate drive signal in the high-voltage domain through chip junction isolation or capacitor isolation. This achieves isolation between the low-voltage circuit module and the high-voltage drive module, as well as the correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 It is a circuit diagram of a traditional buck converter provided by related technologies;

[0042] Figure 2 This is a circuit diagram of a Cuk converter provided by relevant technology;

[0043] Figure 3 This is a circuit diagram of a passive stacked third-order buck converter provided by related technologies;

[0044] Figure 4 This is a circuit diagram of the first hybrid buck converter provided in this application;

[0045] Figure 5 This is a circuit diagram of the second hybrid buck converter provided in this application;

[0046] Figure 6 This is a schematic diagram of the working principle of the first hybrid buck topology provided in this application;

[0047] Figure 7 This is a circuit diagram of the capacitor-isolated gate drive circuit in the first hybrid buck converter provided in this application;

[0048] Figure 8 This is a circuit diagram of the chip junction isolated gate drive circuit in the first hybrid buck converter provided in this application;

[0049] Figure 9 This is a circuit diagram of the capacitor-isolated gate drive circuit in the second type of hybrid buck converter provided in this application;

[0050] Figure 10 This is a circuit diagram of the chip junction isolated gate drive circuit in the second type of hybrid buck converter provided in this application;

[0051] Figure 11 This is a flowchart of a gate driving method for a hybrid buck converter provided in one embodiment of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0053] This application provides a hybrid buck converter, which includes a hybrid buck topology and an input / output topology. The hybrid buck topology has various structures, such as... Figure 4 As shown, the first structure is a hybrid buck topology, including high-side power transistors and low-side power transistors, such as... Figure 5 As shown, the second structure is a hybrid buck topology that includes a high-side power transistor and a diode, which means that the low-side power transistor in the first structure is replaced with a diode. Figure 4 and 5 In the diagram, the part within the dashed box represents the hybrid buck topology, while the part outside the dashed box represents the input / output topology.

[0054] The following section uses the first type of hybrid buck topology as an example to explain the structure and working principle of the hybrid buck topology.

[0055] like Figure 4 As shown, the hybrid buck topology includes a high-side inductor L H Low-side inductance L L Flying capacitor C F High-side power transistor M H Low-side power transistor M L The gate drive circuit, the structure of which is described in detail below. High-side inductor L H The first terminal is the first input terminal of the hybrid buck topology, and the high-side inductor L H The second terminal is connected to the flying capacitor C F The first terminal and the high-side power transistor M H The drains are connected to form a high-side switching node, and the low-side inductance L L The first terminal is grounded, and the low-side inductance L L The second terminal is connected to the flying capacitor C F The second terminal, one input terminal of the gate drive circuit and the low-side power transistor M L The sources are connected to form a low-side switching node, and the high-side power transistor M... H The source and low-side power transistor M L The drain of the circuit is connected to serve as the output terminal of the hybrid buck topology, and the other input terminal of the gate drive circuit serves as the second input terminal of the hybrid buck topology. The high-side output terminal of the gate drive circuit is connected to the high-side power transistor M. H The gate is connected to the gate, and the low-side output of the gate drive circuit is connected to the low-side power transistor M.L The gate is connected.

[0056] Figure 6 This illustrates the working principle of the hybrid buck topology. In steady-state operation, the flying capacitor C... F Charged to input voltage V IN When the high-side power switch M H When turned on, the high-side switch node voltage V SWH Equal to output voltage V OUT The low-side switching node voltage V SWL The equilibrium is at (V) OUT -V IN ), making the high-side inductance L H and low-side inductance L L Both ends bear (V) IN -V OUT The voltage difference causes the high-side current I to... LH and low-side current I LL From V IN To V OUT Continuing to increase. When the low-side power switch M... L When turned on, the low-side switch node voltage V SWL Change to V OUT The high-side switching node voltage V SWH Then rise to (V) OUT +V IN At this time, the output voltage V OUT Voltage applied to the high-side inductor L H and low-side inductance L L At both ends, this causes the high-side current I. LH and low-side current I LL Gradually decrease, while always maintaining the input current I. IN With continuous output current I OUT continuous.

[0057] The voltage conversion ratio of the above hybrid buck topology is consistent with that of a traditional buck converter, i.e., V OUT =D×V IN D is the high-side power switch M H The duty cycle of the drive signal, but its significant advantage lies in its ability to simultaneously maintain a continuous input current I. IN With continuous output current I OUT This eliminates the need for large input and output capacitors and significantly suppresses EMI noise on the input bus.

[0058] The first point that needs to be explained is that the high-side power transistor M... H and low-side power transistor M LIt can be a silicon metal-oxide-semiconductor field-effect transistor (Silicon MOSFET), a gallium nitride field-effect transistor (GaN FET), or a silicon carbide field-effect transistor (SiC FET), but this embodiment is not limited to any particular type.

[0059] The second point to note is that the control mode of the current control module in the input-output topology can be peak current mode control, valley current mode control, average current mode control, hysteresis mode control, etc.

[0060] The third point to note is that the isolation types of isolators in the gate drive circuit include chip junction isolation and capacitor isolation. Figure 7 The diagram shows a capacitor-isolated gate drive circuit in the first type of hybrid buck converter. Figure 8 The diagram shows the chip junction isolated gate drive circuit in the first type of hybrid buck converter. Figure 9 The diagram shows the capacitor-isolated gate drive circuit in the second type of hybrid buck converter. Figure 10 The diagram shows the chip junction isolated gate drive circuit in the second type of hybrid buck converter.

[0061] like Figure 7 The diagram illustrates a structural block diagram of the gate drive circuit of a hybrid buck converter according to an embodiment of this application. The gate drive circuit of this hybrid buck converter may include:

[0062] The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage V. DD In one example, the power supply voltage V DD It is 5V.

[0063] The high-side output of the gate drive circuit and the high-side power transistor M in the hybrid buck converter H The gate is connected to the gate, and the low-side output of the gate drive circuit is connected to the low-side power transistor M in the hybrid buck converter. L The gates are connected, and the gate drive circuit is used to convert the gate drive signal into a high-side drive signal V in the high-voltage domain through isolation. GH and low-side drive signal V GL Alternately output high-side drive signal VGH and low-side drive signal V GL So that the high-side drive signal V can be used. GH Drive high-side power transistor M H To turn the circuit on and off, a low-side drive signal V is used. GL Drive low-side power transistor M L Perform on / off switching.

[0064] Among them, the high-side driving signal V GH The voltage range is the output voltage V OUT To the output voltage V OUT With power supply voltage V DD The sum of the low-side drive signal V GL The voltage range is the low-side switching node voltage V. SWL to low-side switching node voltage V SWL With power supply voltage V DD The sum of the low-side switching node voltages V SWL It is the low-side power transistor M L The voltage of the connected low-side switch node.

[0065] In simple terms, for the high-side switching transistor M H gate signal V DH From 0 to V DD Low-voltage domain conversion to V OUT ~V DD1 The high-voltage domain, where V DD1 =V OUT +V DD For the low-side switching transistor M L gate signal V DL From 0 to V DD Low-voltage domain conversion to V SWL ~V DD2 The high-voltage domain, where V DD2 =V SWL +V DD By using isolators, isolation between the low-voltage circuit module and the high-voltage drive module is achieved, as well as the correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0066] Specifically, the gate drive circuit includes a dead-time controller 710, a first isolator 720, a second isolator 730, a first gate driver 740, and a second gate driver 750. The input terminal of the dead-time controller 710 serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the dead-time controller 710 is connected to the first input terminal of the first isolator 720, and the second output terminal of the dead-time controller 710 is connected to the first input terminal of the second isolator 730. The second input terminal of the first isolator 720 and the bias terminal V of the first gate driver 740 are connected. DD1 The output of the first external bootstrap circuit is connected to the output of the first isolator 720, the output of the first isolator 720 is connected to the first input of the first gate driver 740, and the second input of the first gate driver 740 is connected to the output of the hybrid buck converter V. OUT Connected, the output of the first gate driver 740 serves as the high-side output V of the gate drive circuit. GH With high-side power transistor M H The gates are connected, and the bias terminal V of the first gate driver 740 is connected. DD1 The voltage is the output voltage V. OUT With power supply voltage V DD The sum; the second input terminal of the second isolator 730 and the bias terminal V of the second gate driver 750. DD2 The output of the second bootstrap circuit is connected to the output of the second isolator 730, the output of the second isolator 730 is connected to the first input of the second gate driver 750, and the second input of the second gate driver 750 is connected to the low-side switching node V. SWL Connected, the output of the second gate driver 750 serves as the low-side output V of the gate drive circuit. GL With low-side power transistor M L The gate is connected to the second gate driver 750, and the bias terminal V is connected to the second gate driver 750. DD2 The voltage is the low-side switching node voltage V. SWL With power supply voltage V DD sum.

[0067] In this embodiment, the first isolator 720 includes a first modulation circuit 721, a first isolation capacitor assembly 722 and a first demodulation circuit 723 connected in sequence; the second isolator 730 includes a second modulation circuit 731, a second isolation capacitor assembly 732 and a second demodulation circuit 733 connected in sequence.

[0068] like Figure 7 As shown, the first isolation capacitor assembly 722 includes two sets of series capacitors connected in parallel, and the second isolation capacitor assembly 732 includes two sets of series capacitors connected in parallel. The first isolation capacitor assembly 722 and the second capacitor isolation assembly 732 can be replaced with other components capable of providing isolation.

[0069] In summary, the gate drive circuit of the hybrid buck converter provided in this application embodiment, for a hybrid buck converter including high-side power transistors and low-side power transistors, can convert the gate drive signal in the low-voltage domain into the gate drive signal in the high-voltage domain through chip junction isolation or capacitor isolation, thereby realizing the isolation between the low-voltage circuit module and the high-voltage drive module and the correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0070] like Figure 8 The diagram illustrates a structural block diagram of the gate drive circuit of a hybrid buck converter according to an embodiment of this application. The gate drive circuit of this hybrid buck converter may include:

[0071] The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage V. DD In one example, the power supply voltage V DD It is 5V.

[0072] The high-side output of the gate drive circuit and the high-side power transistor M in the hybrid buck converter H The gate is connected to the gate, and the low-side output of the gate drive circuit is connected to the low-side power transistor M in the hybrid buck converter. L The gates are connected, and the gate drive circuit is used to convert the gate drive signal into a high-side drive signal V in the high-voltage domain through isolation. GH and low-side drive signal V GL Alternately output high-side drive signal V GH and low-side drive signal V GL So that the high-side drive signal V can be used. GH Drive high-side power transistor M H To turn the circuit on and off, a low-side drive signal V is used. GL Drive low-side power transistor M L Perform on / off switching.

[0073] Among them, the high-side driving signal V GH The voltage range is the output voltage V OUT To the output voltage V OUT With power supply voltage V DD The sum of the low-side drive signal V GL The voltage range is the low-side switching node voltage V. SWL to low-side switching node voltage V SWL With power supply voltage V DD The sum of the low-side switching node voltages V SWL It is the low-side power transistor ML The voltage of the connected low-side switch node.

[0074] In simple terms, for the high-side switching transistor M H gate signal V DH From 0 to V DD Low-voltage domain conversion to V OUT ~V BSTH The high-voltage domain, where V BSTH =V OUT +V DD For the low-side switching transistor M L gate signal V DL From 0 to V DD Low-voltage domain conversion to V SWL ~V BSTL The high-voltage domain, where V BSTL =V SWL +V DD .

[0075] Specifically, the gate drive circuit includes a first pull-up level shifter 810, a pull-down level shifter 820, a rising edge dead time controller 830, a falling edge dead time controller 840, a third gate driver 850, and a fourth gate driver 860; wherein, the first pull-up level shifter 810 includes a first low-voltage module 811, a first high-voltage module 812, a first high common-mode transient compensation module 813, a second high common-mode transient compensation module 814, and a first isolation module 815, and the pull-down level shifter 820 includes a second high-voltage module 821, a third high-voltage module 822, a third high common-mode transient compensation module 823, a fourth high common-mode transient compensation module 824, and a second isolation module 825.

[0076] The input terminal of the first low-voltage module 811 serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the first low-voltage module 811 is connected to the first input terminal of the first high-voltage module 812 through the first isolation module 815. The second output terminal of the first low-voltage module 811 is connected to the second input terminal of the first high-voltage module 812 through the first isolation module 815. The third input terminal of the first high-voltage module 812 is connected to the first output terminal of the second high common-mode transient compensation module 814. The fourth input terminal of the first high-voltage module 812 is connected to the second output terminal of the second high common-mode transient compensation module 814. The output terminal of the first high-voltage module 812 serves as the output terminal of the first pull-up level shifter 810 and is connected to the input terminal of the rising edge dead time controller 830 and the input terminal of the second high-voltage module 821. The output terminal of the rising edge dead time controller 830 is connected to the high-side power transistor M through the third gate driver 850. HThe gate of the first high common-mode transient compensation module 813 is connected to ground AGND, and the output of the first high common-mode transient compensation module 813 is connected to the input of the second high common-mode transient compensation module 814 through the first isolation module 815.

[0077] The input terminal of the second high-voltage module 821 serves as the input terminal of the pull-down level shifter 820 and is connected to the output terminal of the first pull-up level shifter 810. The first output terminal of the second high-voltage module 821 is connected to the first input terminal of the third high-voltage module 822 through the second isolation module 825. The second output terminal of the second high-voltage module 821 is connected to the second input terminal of the third high-voltage module 822 through the second isolation module 825. The third input terminal of the third high-voltage module 822 is connected to the first output terminal of the fourth high common-mode transient compensation module 824. The fourth input terminal of the third high-voltage module 822 is connected to the second output terminal of the fourth high common-mode transient compensation circuit 824. The output terminal of the third high-voltage module 822 serves as the output terminal of the pull-down level shifter 820 and is connected to the input terminal of the falling edge dead-time controller 840. The output terminal of the falling edge dead-time controller 840 is connected to the low-side power transistor M through the fourth gate driver 860. L The gate is connected, and the input terminal of the third high common-mode transient compensation module 823 is connected to the high-side bootstrap voltage rail V. BSTH The output of the third high common-mode transient compensation module 823 is connected to the input of the fourth high common-mode transient compensation module 824 through the second isolation module 825.

[0078] The chip containing the gate drive circuit includes a first high-voltage N-type doped region N Tub, a second high-voltage N Tub, and a first low-voltage N Tub. The first low-voltage module 811 and the first high common-mode transient compensation module 813 are located within the first P-well of the first low-voltage N Tub. The first high-voltage module 812, the second high-voltage module 821, the second high common-mode transient compensation module 814, the third high common-mode transient compensation module 823, the rising edge dead-time controller 830, and the third gate driver 850 are located within the second P-well of the first high-voltage N Tub. The third high-voltage module 822, the fourth high common-mode transient compensation module 824, the falling edge dead-time controller 840, and the fourth gate driver 860 are located within the third P-well of the second high-voltage N Tub. The first high-voltage N Tub and the second high-voltage N Tub are connected to the high-side bootstrap voltage rail V. BSTH The first low-voltage N-tube is connected to the power supply voltage V. DD The second P-well is connected to the output voltage V. OUT The third P-well is connected to the low-side switching node voltage V. SWL The first P-well is grounded to AGND.

[0079] (1) First pull-up level shifter 810

[0080] The first low-voltage module 811 includes a first inverter N1, a second inverter N2, a third inverter N3, a first pulse generating circuit, a second pulse generating circuit, and a first switching transistor M. N1 Second switch M N2 The input terminals of the first inverter N1 and the second inverter N2 serve as the input terminals of the first low-voltage module 811. The output terminal of the first inverter N1 is connected to the input terminal of the first pulse generation circuit, and the output terminal of the first pulse generation circuit is connected to the first switching transistor M. N1 The gate is connected, and the first switching transistor M N1 The source is grounded, and the first switching transistor M N1 The drain of the first low-voltage module 811 is the first output terminal. The output terminal of the second inverter N2 is connected to the input terminal of the third inverter N3. The output terminal of the third inverter N3 is connected to the input terminal of the second pulse generation circuit. The output terminal of the second pulse generation circuit is connected to the second switching transistor M. N2 The gate of the second switch M is connected to the gate of the second switch M. N2 The source is grounded, and the second switch M N2 The drain is the second output terminal of the first low-voltage module 811.

[0081] The first high-voltage module 812 includes a first damping resistor R. D1 Second damping resistor R D2 The first to sixth current mirrors and the first RS latch; the first damping resistor R D1 The first terminal is the first input terminal of the first high-voltage module 812, and the first damping resistor R D1 The second terminal is connected to the input terminal of the first current mirror CM1, the output terminal of the first current mirror CM1 is connected to the input terminal of the second current mirror CM2, the first output terminal of the second current mirror CM2 is connected to the input terminal of the third current mirror CM3, and the second output terminal of the second current mirror CM2 is connected to the set terminal S of the first RS latch. LS Connected, the output terminal of the third current mirror CM3 is connected to the reset terminal R of the first RS latch. LS Connected, the second damping resistor R D2 The first terminal is the second input terminal of the first high-voltage module 812, and the second damping resistor R D2 The second terminal is connected to the input terminal of the fourth current mirror CM4. The output terminal of the fourth current mirror CM4 is connected to the input terminal of the fifth current mirror CM5. The first output terminal of the fifth current mirror CM5 is connected to the input terminal of the sixth current mirror CM6. The second output terminal of the fifth current mirror CM5 is connected to the reset terminal R of the first RS latch. LS Connected, the output terminal of the sixth current mirror CM6 is connected to the set terminal S of the first RS latch. LS The first RS latch is connected to the output of the first high-voltage module 812.

[0082] The first low-voltage module 811 and the first high-voltage module 812 are connected by a first isolation module 815. The first isolation module 815 includes a first high-voltage MOSFET M. HV1 Second high voltage MOSFET M HV2 The first high-voltage MOSFET M HV1 Second high voltage MOSFET M HV2 The gate of the first high-voltage MOSFET is connected to the gate of the first high-voltage MOSFET. HV1 The source and the first switch M N1 The drains of the first high-voltage MOSFET M are connected. HV1 The drain and the first damping resistor R D1 The first terminal is connected to the second high-voltage MOSFET M. HV2 The source and the second switch M N2 The drain of the second high-voltage MOSFET is connected to the drain of the second high-voltage MOSFET. HV2 The drain and the second damping resistor R D2 Connect the first end.

[0083] The first high common-mode transient compensation module 813 includes a fifth switching transistor M. N3 The second high common-mode transient compensation module 814 includes a fifth damping resistor R. D5 and the thirteenth current mirror CM 13 Fifth switch M N3 The gate and source of the first high common-mode transient compensation module 813 are grounded, and the fifth switch M N3 The drain is connected to the fifth damping resistor R through the first isolation module 815. D5 The first end is connected, and the fifth damping resistor R D5 The second end and the thirteenth current mirror CM 13 Connect the input terminal to the thirteenth current mirror CM. 13 The first output terminal serves as the first output terminal of the second high common-mode transient compensation module 814, and is connected to the third input terminal of the first high-voltage module 812. The thirteenth current mirror CM... 13 The second output terminal serves as the second output terminal of the second high common-mode transient compensation module 814, and is connected to the fourth input terminal of the first high-voltage module 812. Among them, the thirteenth current mirror CM... 13 Including three power transistors M connected in parallel P4 ~M P6 power transistor M P6 The drain and gate of the transistor are connected together to form the input terminal, and the power transistor M... P4 The drain of the device is used as the first output terminal to transfer current I. N3 Copy as I N1C The output is then used to offset the common-mode transient current I. N1 Power transistor MP5 The drain of the device is used as the second output terminal to transfer current I. N3 Copy as I N2C The output is then used to offset the common-mode transient current I. N2 .

[0084] The first high common-mode transient compensation module 813 and the second high common-mode transient compensation module 814 are connected by a first isolation module 815. The first isolation module 815 includes a fifth high-voltage MOSFET M. HV5 The fifth high-voltage MOSFET M HV5 The gate of the first high-voltage MOSFET M HV1 Second high voltage MOSFET M HV2 The gate of the fifth high-voltage MOSFET is connected to the gate of the MOSFET. HV5 The source and the fifth switch M N3 The drains of the fifth high-voltage MOSFET are connected. HV5 The drain and the fifth damping resistor R D5 The first terminal is connected. Among them, the first high-voltage MOSFET M... HV1 Second high-voltage MOSFET M HV2 and the fifth high-voltage MOSFET M HV5 The dimensions are the same to ensure that the common-mode transient current I during high dv / dt transients is constant. N1 ~I N3 match.

[0085] In this embodiment, the first damping resistor R D1 Second damping resistor R D2 and the fifth damping resistor R D5 It can limit the injection of transient current caused by dv / dt into the first SR latch, further improving the common-mode transient immunity performance.

[0086] The working principle of the first pull-up level shifter 810 is explained below. When the low-side power transistor M... L When turned off, the input signal V DH The voltage increases, causing the second switch M to... N2 The signal is turned on, and the set signal S is transmitted through the three current mirrors: the fourth current mirror CM4, the fifth current mirror CM5, and the sixth current mirror CM6. LS The voltage level changes to high, which in turn sets the first RS latch to enable the high-side power transistor M. H When the low-side power transistor M L When turned on, the input signal V DH The value decreases, causing the first switching transistor M to... N1 When the circuit is turned on, the reset signal R is transmitted through the three current mirrors: the first current mirror CM1, the second current mirror CM2, and the third current mirror CM3. LSThe signal goes high, which in turn resets the first RS latch to turn off the high-side power transistor M. H .

[0087] (2) Pull-down level shifter 820

[0088] The second high-voltage module 821 includes a fourth inverter N4, a fifth inverter N5, a sixth inverter N6, a third pulse generation circuit, a fourth pulse generation circuit, and a third switching transistor M. P1 and the fourth switch M P2 The input terminals of the fourth inverter N4 and the fifth inverter N5 serve as the input terminals of the second high-voltage module 821. The output terminal of the fourth inverter N4 is connected to the input terminal of the third pulse generation circuit, and the output terminal of the third pulse generation circuit is connected to the third switching transistor M. P1 The gate is connected to the third switch M. P1 The source is connected to the high-side bootstrap voltage rail V BSTH The third switch M P1 The drain of the circuit is the first output terminal of the second high-voltage module 821. The output terminal of the fifth inverter N5 is connected to the input terminal of the sixth inverter N6. The output terminal of the sixth inverter N6 is connected to the input terminal of the fourth pulse generation circuit. The output terminal of the fourth pulse generation circuit is connected to the fourth switching transistor M. P2 The gate is connected, and the fourth switch M is connected. P2 The source is connected to the high-side bootstrap voltage rail V BSTH The fourth switch M P2 The drain terminal is the second output terminal of the second high-voltage module 821.

[0089] The third high-voltage module 822 includes a third damping resistor R. D3 Fourth damping resistor R D4 The seventh to twelfth current mirrors and the second RS latch; the third damping resistor R D3 The first terminal is the first input terminal of the third high-voltage module 822, and the third damping resistor R D3 The second terminal is connected to the input terminal of the seventh current mirror CM7. The output terminal of the seventh current mirror CM7 is connected to the input terminal of the eighth current mirror CM8. The first output terminal of the eighth current mirror CM8 is connected to the input terminal of the ninth current mirror CM9. The second output terminal of the eighth current mirror CM8 is connected to the set terminal S of the second RS latch. LS Connected, the output terminal of the ninth current mirror CM9 is connected to the reset terminal R of the second RS latch. LS Connected, fourth damping resistor R D4 The first terminal is the second input terminal of the third high-voltage module 822, and the fourth damping resistor R D4 The second end and the tenth current mirror CM 10 Connect the input terminal to the tenth current mirror CM. 10The output terminal is connected to the eleventh current mirror CM 11 Connect the input terminal to the eleventh current mirror CM. 11 The first output terminal and the twelfth current mirror CM 12 Connect the input terminal to the eleventh current mirror CM. 11 The second output terminal and the reset terminal of the second RS latch R LS Connected, the twelfth current mirror CM 12 The output terminal and the set terminal S of the second RS latch LS The output of the second RS latch is connected to the output of the third high-voltage module 822.

[0090] The second high-voltage module 821 and the third high-voltage module 822 are connected by a second isolation module 825, which includes the third high-voltage MOSFET M. HV3 and the fourth high-voltage MOSFET M HV4 The third high-voltage MOSFET M HV3 and the fourth high-voltage MOSFET M HV4 The gate of the third high-voltage MOSFET is connected to the gate of the third high-voltage MOSFET. HV3 The drain and the third switch M P1 The drain of the third high-voltage MOSFET is connected to the drain of the third high-voltage MOSFET. HV3 The source and the third damping resistor R D3 The first terminal is connected to the fourth high-voltage MOSFET M. HV4 The drain and the fourth switch M P2 The drain of the fourth high-voltage MOSFET is connected to the drain of the fourth high-voltage MOSFET. HV4 The source and the fourth damping resistor R D4 Connect the first end.

[0091] The third high common-mode transient compensation module 823 includes the sixth switch M. N6 The fourth high common-mode transient compensation module 824 includes the sixth damping resistor R. D6 and the fourteenth current mirror CM 14 Sixth switch M N6 The gate and source terminals are the input terminals of the third high common-mode transient compensation module 823 and connected in parallel to the high-side bootstrap voltage rail V. BSTH The sixth switch M N6 The drain is connected to the sixth damping resistor R through the second isolation module 825. D6 The first end is connected, and the sixth damping resistor R D6 The second end and the fourteenth current mirror CM 14 Connect the input terminal to the fourteenth current mirror CM. 14 The first output terminal serves as the first output terminal of the fourth high common-mode transient compensation module 824, and is connected to the third input terminal of the third high-voltage module 822. The fourteenth current mirror CM 14The second output terminal serves as the second output terminal of the fourth high common-mode transient compensation module 824 and is connected to the fourth input terminal of the third high voltage module 822.

[0092] The third high common-mode transient compensation module 823 and the fourth high common-mode transient compensation module 824 are connected via a second isolation module 825. This second isolation module 825 includes a sixth high-voltage MOSFET M. HV6 The sixth high-voltage MOSFET M HV6 The gate of the third high-voltage MOSFET M HV3 and the fourth high-voltage MOSFET M HV4 The gate of the sixth high-voltage MOSFET is connected to the gate of the MOSFET. HV6 The drain of the sixth switch M N6 The drain of the sixth high-voltage MOSFET is connected to the drain of the MOSFET. HV6 The source and the sixth damping resistor R D6 The first terminal is connected. Among them, the third high-voltage MOSFET M... HV3 The fourth high-voltage MOSFET M HV4 and the sixth high-voltage MOSFET M HV6 The dimensions are the same to ensure that the common-mode transient current I during high dv / dt transients is constant. N4 ~I N6 match.

[0093] In this embodiment, the third damping resistor R D3 Fourth damping resistor R D4 and the sixth damping resistor R D6 It can limit the injection of transient current caused by dv / dt into the second SR latch, further improving the common-mode transient immunity performance.

[0094] The working principle of the pull-down level shifter 820 is explained below. When the low-side power transistor M... L When turned on, the input signal V DHU The value decreases, causing the fourth switch M to... P2 Conduction occurs through the tenth current mirror CM. 10 11th Current Mirror CM 11 and the twelfth current mirror CM 12 This three-stage current mirror transmission enables the set signal S LS The signal goes high, which in turn sets the second RS latch to enable the low-side power transistor M. L When the low-side power transistor M L When turned off, the input signal V DHU The voltage increases, causing the third switch M to... P1 The circuit is turned on, and the reset signal R is transmitted through the three current mirrors: the seventh current mirror CM7, the eighth current mirror CM8, and the ninth current mirror CM9. LSThe signal goes high, which in turn resets the second RS latch to turn off the low-side power transistor M. L .

[0095] In this embodiment, different N-tubs are used internally to isolate the P-wells, thereby separating the low-voltage circuit module from the high-voltage drive module. The working principle of the gate drive circuit is as follows: the input signal V... DH Transmitted to the high-side drive voltage domain V OUT ~V BSTH V BSTH Voltage is V OUT +V DD To drive the high-side power transistor M H Subsequently, signal V DHU Transmitted to the low-side drive voltage domain V SWL ~V BSTL V BSTL Voltage is V SWL +V DD To drive the low-side power transistor M L The rising edge dead time control module 830 and the falling edge dead time control module 840 ensure that the high-side power transistor M... H With low-side power transistor M L The gate signals are non-overlapping to prevent shoot-through.

[0096] High-side bootstrap voltage rail V BSTH Simultaneously, bias is provided for the first pull-up level shifter 810 and the third gate driver 850, enabling the V of the first high voltage N tub to... TUBH In V OUT +V DD Its P-well is connected to the output voltage V. OUT However, the V of the second high-voltage Ntub TUBL Although it is also connected to V OUT +V DD However, its P-well is connected to the low-side switching node voltage V. SWL Low-side switching node voltage V SWL In (V) OUT -V IN ) to V OUT The high-side power transistor M oscillates between these states. H With low-side power transistor M L The driver stages are located in different P-wells, which are isolated from each other by a high-voltage N-Tub, while the low-voltage circuit modules are housed within a low-voltage N-Tub for isolation. Therefore, in a hybrid buck converter, on-chip ground isolation must be achieved between the high-voltage driver module and the low-voltage circuit module to drive the high-side power transistor M. H With low-side power transistor M LProvide a suitable trap potential.

[0097] In summary, the gate drive circuit of the hybrid buck converter provided in this application embodiment, for a hybrid buck converter including high-side power transistors and low-side power transistors, can convert the gate drive signal in the low-voltage domain into the gate drive signal in the high-voltage domain through chip junction isolation or capacitor isolation, thereby realizing the isolation between the low-voltage circuit module and the high-voltage drive module and the correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0098] like Figure 9 The diagram illustrates a structural block diagram of the gate drive circuit of a hybrid buck converter according to an embodiment of this application. The gate drive circuit of this hybrid buck converter may include:

[0099] The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage V. DD In one example, the power supply voltage V DD It is 5V.

[0100] The high-side output of the gate drive circuit and the high-side power transistor M in the hybrid buck converter H The gates are connected, and the gate drive circuit is used to convert the gate drive signal into a high-side drive signal V in the high-voltage domain through isolation. GH Output high-side drive signal V GH So that the high-side drive signal V can be used. GH Drive high-side power transistor M H Perform on / off switching.

[0101] Among them, the high-side driving signal V GH The voltage range is the output voltage V OUT To the output voltage V OUT With power supply voltage V DD The sum. Simply put, for the high-side switch M... H gate signal V DH From 0 to V DD Low-voltage domain conversion to V OUT ~V DD1 The high-voltage domain, where V DD1 =V OUT +V DD .

[0102] Specifically, the gate drive circuit includes a third isolator 910 and a fifth gate driver 920; the first input terminal of the third isolator 910 serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module; the second input terminal of the third isolator 910 is connected to the bias terminal V of the fifth gate driver 920. DD1 The output of the third bootstrap circuit is connected to the external third isolator 910, the output of the third isolator 910 is connected to the first input of the fifth gate driver 920, and the second input of the fifth gate driver 920 is connected to the output of the hybrid buck converter V. OUT Connected, the output of the fifth gate driver 920 serves as the high-side output V of the gate drive circuit. GH With high-side power transistor M H The gate is connected to the fifth gate driver 920, and the bias terminal V is connected to it. DD1 The voltage is the output voltage V. OUT With power supply voltage V DD sum.

[0103] In this embodiment, the third isolator 910 includes a third modulation circuit 911, a third isolation capacitor assembly 912, and a third demodulation circuit 913 connected in sequence.

[0104] like Figure 9 As shown, the third isolation capacitor assembly 912 includes two sets of series capacitors connected in parallel. The third isolation capacitor assembly 912 can be replaced with other components capable of providing isolation.

[0105] In summary, the gate drive circuit of the hybrid buck converter provided in this application embodiment, for a hybrid buck converter that includes a high-side power transistor but does not include a low-side power transistor, can convert the gate drive signal in the low-voltage domain into a gate drive signal in the high-voltage domain through chip junction isolation or capacitor isolation. This achieves isolation between the low-voltage circuit module and the high-voltage drive module, as well as correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0106] like Figure 10 The diagram illustrates a structural block diagram of the gate drive circuit of a hybrid buck converter according to an embodiment of this application. The gate drive circuit of this hybrid buck converter may include:

[0107] The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage V. DD In one example, the power supply voltage V DD It is 5V.

[0108] The high-side output of the gate drive circuit and the high-side power transistor M in the hybrid buck converter H The gates are connected, and the gate drive circuit is used to convert the gate drive signal into a high-side drive signal V in the high-voltage domain through isolation. GH Output high-side drive signal V GH So that the high-side drive signal V can be used. GH Drive high-side power transistor M H Perform on / off switching.

[0109] Among them, the high-side driving signal V GH The voltage range is the output voltage V OUT To the output voltage V OUT With power supply voltage V DD The sum. Simply put, for the high-side switch M... H gate signal V DH From 0 to V DD Low-voltage domain conversion to V OUT ~V BSTH The high-voltage domain, where V BSTH =V OUT +V DD .

[0110] Specifically, the gate drive circuit includes a second pull-up level shifter 1010 and a sixth gate driver 1020; wherein, the second pull-up level shifter 1010 includes a second low-voltage module 1011, a fourth high-voltage module 1012, a fifth high common-mode transient compensation module 1013, a sixth high common-mode transient compensation module 1014 and a third isolation module 1015.

[0111] The input terminal of the second low-voltage module 1011 serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the second low-voltage module 1011 is connected to the first input terminal of the fourth high-voltage module 1012 through the third isolation module 1015. The second output terminal of the second low-voltage module 1011 is connected to the second input terminal of the fourth high-voltage module 1012 through the third isolation module 1015. The third input terminal of the fourth high-voltage module 1012 is connected to the first output terminal of the sixth high common-mode transient compensation module 1014. The fourth input terminal of the fourth high-voltage module 1012 is connected to the second output terminal of the sixth high common-mode transient compensation module 1014. The output terminal of the fourth high-voltage module 1012 serves as the output terminal of the second pull-up level shifter 1010 and is connected to the high-side power transistor M through the sixth gate driver 1020. H The gate of the fifth high common-mode transient compensation module 1013 is connected to the ground, and the output of the fifth high common-mode transient compensation module 1013 is connected to the input of the sixth high common-mode transient compensation module 1014 through the third isolation module 1015.

[0112] The chip containing the gate drive circuit includes a third high-voltage N-Tub and a second low-voltage N-Tub. The second low-voltage module 1011 and the fifth high common-mode transient compensation module 1013 are located in the fourth P-well of the second low-voltage N-Tub. The fourth high-voltage module 1012, the sixth high common-mode transient compensation module 1014, and the sixth gate driver 1020 are located in the fifth P-well of the third high-voltage N-Tub. The third high-voltage N-Tub is connected to the high-side bootstrap voltage rail V. BSTH The second low-voltage N-tube is connected to the power supply voltage V. DD The fifth P-well is connected to the output voltage V. OUT The fourth P-well is grounded to AGND.

[0113] Among them, the second low-voltage module 1011 has the same structure as the first low-voltage module 811, the fourth high-voltage module 1012 has the same structure as the first high-voltage module 812, the fifth high common-mode transient compensation module 1013 has the same structure as the first high common-mode transient compensation module 813, the sixth high common-mode transient compensation module 1014 has the same structure as the second high common-mode transient compensation module 814, and the third isolation module 1015 has the same structure as the first isolation module 815. These will not be described in detail here.

[0114] In summary, the gate drive circuit of the hybrid buck converter provided in this application embodiment, for a hybrid buck converter that includes a high-side power transistor but does not include a low-side power transistor, can convert the gate drive signal in the low-voltage domain into a gate drive signal in the high-voltage domain through chip junction isolation or capacitor isolation. This achieves isolation between the low-voltage circuit module and the high-voltage drive module, as well as correct transmission of the gate drive signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0115] like Figure 11 The diagram illustrates a flowchart of a gate driving method for a hybrid buck converter according to an embodiment of this application. The gate driving method for the hybrid buck converter includes:

[0116] Step 1101: The gate drive circuit receives the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is from 0 to the power supply voltage.

[0117] Step 1102: When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal and a low-side drive signal in the high-voltage domain through isolation, and alternately outputs the high-side drive signal and the low-side drive signal so that the high-side power transistor is driven to turn on and off by the high-side drive signal, and the low-side power transistor is driven to turn on and off by the low-side drive signal.

[0118] Step 1103: When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal in the high-voltage domain through isolation, and outputs the high-side drive signal so as to drive the high-side power transistor to turn on and off.

[0119] The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage. The voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. The isolation types include chip junction isolation and capacitor isolation.

[0120] The working principle of the gate drive circuit is described in detail above and will not be repeated here.

[0121] In summary, the gate driving method for the hybrid buck converter provided in this application, whether it is a hybrid buck converter including both high-side and low-side power transistors or a hybrid buck converter including high-side power transistors but not low-side power transistors, allows the gate driving circuit to convert the gate driving signal in the low-voltage domain into the gate driving signal in the high-voltage domain through chip junction isolation or capacitor isolation. This achieves isolation between the low-voltage circuit module and the high-voltage driving module, as well as correct transmission of the gate driving signal between different voltage domains, ensuring the normal operation of the hybrid buck converter.

[0122] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0123] The above description is not intended to limit the embodiments of this application. Any adjustments, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A gate drive circuit for a hybrid buck converter, characterized in that, The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage. When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter, and the low-side output terminal of the gate drive circuit is connected to the gate of the low-side power transistor in the hybrid buck converter. The gate drive circuit is used to convert the gate drive signal into a high-voltage domain high-side drive signal and a low-side drive signal through isolation, and alternately outputs the high-side drive signal and the low-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal, and drive the low-side power transistor to turn on and off through the low-side drive signal. The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage, and the voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. When the isolation type is capacitive isolation, the gate drive circuit includes a dead-time controller, a first isolator, a second isolator, a first gate driver, and a second gate driver. The input terminal of the dead time controller serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module; the first output terminal of the dead time controller is connected to the first input terminal of the first isolator, and the second output terminal of the dead time controller is connected to the first input terminal of the second isolator. The second input terminal of the first isolator and the bias terminal of the first gate driver are connected to the output terminal of the external first bootstrap circuit. The output terminal of the first isolator is connected to the first input terminal of the first gate driver. The second input terminal of the first gate driver is connected to the output terminal of the hybrid buck converter. The output terminal of the first gate driver serves as the high-side output terminal of the gate drive circuit and is connected to the gate of the high-side power transistor. The voltage at the bias terminal of the first gate driver is the sum of the output voltage and the power supply voltage. The second input terminal of the second isolator and the bias terminal of the second gate driver are connected to the output terminal of the external second bootstrap circuit. The output terminal of the second isolator is connected to the first input terminal of the second gate driver. The second input terminal of the second gate driver is connected to the low-side switching node. The output terminal of the second gate driver serves as the low-side output terminal of the gate drive circuit and is connected to the gate of the low-side power transistor. The voltage at the bias terminal of the second gate driver is the sum of the low-side switching node voltage and the power supply voltage.

2. The gate drive circuit of the hybrid buck converter according to claim 1, characterized in that, The first isolator includes a first modulation circuit, a first isolation capacitor assembly, and a first demodulation circuit connected in sequence; The second isolator includes a second modulation circuit, a second isolation capacitor assembly, and a second demodulation circuit connected in sequence.

3. A gate drive circuit for a hybrid buck converter, characterized in that, The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage. When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter, and the low-side output terminal of the gate drive circuit is connected to the gate of the low-side power transistor in the hybrid buck converter. The gate drive circuit is used to convert the gate drive signal into a high-voltage domain high-side drive signal and a low-side drive signal through isolation, and alternately outputs the high-side drive signal and the low-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal, and drive the low-side power transistor to turn on and off through the low-side drive signal. The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage, and the voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. When the isolation type is chip junction isolation, the gate drive circuit includes a first pull-up level shifter, a pull-down level shifter, a rising edge dead time controller, a falling edge dead time controller, a third gate driver, and a fourth gate driver; wherein, the first pull-up level shifter includes a first low-voltage module, a first high-voltage module, a first high common-mode transient compensation module, a second high common-mode transient compensation module, and a first isolation module, and the pull-down level shifter includes a second high-voltage module, a third high-voltage module, a third high common-mode transient compensation module, a fourth high common-mode transient compensation module, and a second isolation module; The input terminal of the first low-voltage module serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the first low-voltage module is connected to the first input terminal of the first high-voltage module through the first isolation module. The second output terminal of the first low-voltage module is connected to the second input terminal of the first high-voltage module through the first isolation module. The third input terminal of the first high-voltage module is connected to the first output terminal of the second high common-mode transient compensation module. The fourth input terminal of the first high-voltage module is connected to the second output terminal of the second high common-mode transient compensation module. The output terminal of the first high-voltage module serves as the output terminal of the first pull-up level shifter and is connected to the input terminal of the rising edge dead time controller and the input terminal of the second high-voltage module. The output terminal of the rising edge dead time controller is connected to the gate of the high-side power transistor through the third gate driver. The input terminal of the first high common-mode transient compensation module is grounded. The output terminal of the first high common-mode transient compensation module is connected to the input terminal of the second high common-mode transient compensation module through the first isolation module. The input terminal of the second high-voltage module serves as the input terminal of the pull-down level shifter and is connected to the output terminal of the first pull-up level shifter. The first output terminal of the second high-voltage module is connected to the first input terminal of the third high-voltage module through the second isolation module. The second output terminal of the second high-voltage module is connected to the second input terminal of the third high-voltage module through the second isolation module. The third input terminal of the third high-voltage module is connected to the first output terminal of the fourth high common-mode transient compensation module. The fourth input terminal of the third high-voltage module is connected to the second output terminal of the fourth high common-mode transient compensation module. The output terminal of the third high-voltage module serves as the output terminal of the pull-down level shifter and is connected to the input terminal of the falling edge dead-time controller. The output terminal of the falling edge dead-time controller is connected to the gate of the low-side power transistor through the fourth gate driver. The input terminal of the third high common-mode transient compensation module is connected to the high-side bootstrap voltage rail. The output terminal of the third high common-mode transient compensation module is connected to the input terminal of the fourth high common-mode transient compensation module through the second isolation module. The chip containing the gate drive circuit includes a first high-voltage N-type doped region N Tub, a second high-voltage N Tub, and a first low-voltage N Tub. The first low-voltage module and the first high common-mode transient compensation module are located in the first P-well within the first low-voltage N Tub. The first high-voltage module, the second high-voltage module, the second high common-mode transient compensation module, the third high common-mode transient compensation module, the rising edge dead-time controller, and the third gate driver are located in the second P-well within the first high-voltage N Tub. The third high-voltage module, the fourth high common-mode transient compensation module, the falling edge dead-time controller, and the fourth gate driver are located in the third P-well within the second high-voltage N Tub. The first high-voltage N Tub and the second high-voltage N Tub are connected to the high-side bootstrap voltage rail. The first low-voltage N Tub is connected to the power supply voltage. The second P-well is connected to the output voltage. The third P-well is connected to the low-side switching node voltage. The first P-well is grounded.

4. The gate drive circuit of the hybrid buck converter according to claim 3, characterized in that, The first low-voltage module includes a first inverter, a second inverter, a third inverter, a first pulse generating circuit, a second pulse generating circuit, a first switching transistor, and a second switching transistor. The input terminals of the first inverter and the second inverter serve as the input terminals of the first low-voltage module. The output terminal of the first inverter is connected to the input terminal of the first pulse generating circuit. The output terminal of the first pulse generating circuit is connected to the gate of the first switching transistor. The source of the first switching transistor is grounded, and the drain of the first switching transistor is the first output terminal of the first low-voltage module. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the input terminal of the second pulse generating circuit. The output terminal of the second pulse generating circuit is connected to the gate of the second switching transistor. The source of the second switching transistor is grounded, and the drain of the second switching transistor is the second output terminal of the first low-voltage module. The second high-voltage module includes a fourth inverter, a fifth inverter, a sixth inverter, a third pulse generation circuit, a fourth pulse generation circuit, a third switch, and a fourth switch. The input terminals of the fourth and fifth inverters serve as the input terminals of the second high-voltage module. The output terminal of the fourth inverter is connected to the input terminal of the third pulse generation circuit. The output terminal of the third pulse generation circuit is connected to the gate of the third switch. The source of the third switch is connected to the high-side bootstrap voltage rail, and the drain of the third switch is the first output terminal of the second high-voltage module. The output terminal of the fifth inverter is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is connected to the input terminal of the fourth pulse generation circuit. The output terminal of the fourth pulse generation circuit is connected to the gate of the fourth switch. The source of the fourth switch is connected to the high-side bootstrap voltage rail, and the drain of the fourth switch is the second output terminal of the second high-voltage module.

5. The gate drive circuit of the hybrid buck converter according to claim 3, characterized in that, The first high-voltage module includes a first damping resistor, a second damping resistor, first to sixth current mirrors, and a first RS latch. The first end of the first damping resistor is the first input terminal of the first high-voltage module. The second end of the first damping resistor is connected to the input terminal of the first current mirror. The output terminal of the first current mirror is connected to the input terminal of the second current mirror. The first output terminal of the second current mirror is connected to the input terminal of the third current mirror. The second output terminal of the second current mirror is connected to the set terminal of the first RS latch. The output terminal of the third current mirror is connected to the reset terminal of the first RS latch. The first end of the second damping resistor is the second input terminal of the first high-voltage module. The second end of the second damping resistor is connected to the input terminal of the fourth current mirror. The output terminal of the fourth current mirror is connected to the input terminal of the fifth current mirror. The first output terminal of the fifth current mirror is connected to the input terminal of the sixth current mirror. The second output terminal of the fifth current mirror is connected to the reset terminal of the first RS latch. The output terminal of the sixth current mirror is connected to the set terminal of the first RS latch. The output terminal of the first RS latch is the output terminal of the first high-voltage module. The third high-voltage module includes a third damping resistor, a fourth damping resistor, seventh to twelfth current mirrors, and a second RS latch. The first end of the third damping resistor is the first input terminal of the third high-voltage module. The second end of the third damping resistor is connected to the input terminal of the seventh current mirror. The output terminal of the seventh current mirror is connected to the input terminal of the eighth current mirror. The first output terminal of the eighth current mirror is connected to the input terminal of the ninth current mirror. The second output terminal of the eighth current mirror is connected to the set terminal of the second RS latch. The output terminal of the ninth current mirror is connected to the reset terminal of the second RS latch. The first end of the fourth damping resistor is the second input terminal of the third high-voltage module. The second end of the fourth damping resistor is connected to the input terminal of the tenth current mirror. The output terminal of the tenth current mirror is connected to the input terminal of the eleventh current mirror. The first output terminal of the eleventh current mirror is connected to the input terminal of the twelfth current mirror. The second output terminal of the eleventh current mirror is connected to the reset terminal of the second RS latch. The output terminal of the twelfth current mirror is connected to the set terminal of the second RS latch. The output terminal of the second RS latch is the output terminal of the third high-voltage module.

6. The gate drive circuit of the hybrid buck converter according to claim 4, characterized in that, The first high common-mode transient compensation module includes a fifth switching transistor, and the second high common-mode transient compensation module includes a fifth damping resistor and a thirteenth current mirror. The gate and source of the fifth switching transistor are the input terminals of the first high common-mode transient compensation module and are grounded. The drain of the fifth switching transistor is connected to the first terminal of the fifth damping resistor through the first isolation module. The second terminal of the fifth damping resistor is connected to the input terminal of the thirteenth current mirror. The first output terminal of the thirteenth current mirror serves as the first output terminal of the second high common-mode transient compensation module and is connected to the third input terminal of the first high-voltage module. The second output terminal of the thirteenth current mirror serves as the second output terminal of the second high common-mode transient compensation module and is connected to the fourth input terminal of the first high-voltage module. The third high common-mode transient compensation module includes a sixth switching transistor, and the fourth high common-mode transient compensation module includes a sixth damping resistor and a fourteenth current mirror. The gate and source of the sixth switching transistor are the input terminals of the third high common-mode transient compensation module and connected in parallel to the high-side bootstrap voltage rail. The drain of the sixth switching transistor is connected to the first terminal of the sixth damping resistor through the second isolation module. The second terminal of the sixth damping resistor is connected to the input terminal of the fourteenth current mirror. The first output terminal of the fourteenth current mirror serves as the first output terminal of the fourth high common-mode transient compensation module and is connected to the third input terminal of the third high-voltage module. The second output terminal of the fourteenth current mirror serves as the second output terminal of the fourth high common-mode transient compensation module and is connected to the fourth input terminal of the third high-voltage module.

7. A gate drive circuit for a hybrid buck converter, characterized in that, The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage. When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter. The gate drive circuit is used to convert the gate drive signal into a high-voltage domain high-side drive signal through isolation, and output the high-side drive signal so as to drive the high-side power transistor to turn on and off. The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage, and the voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. When the isolation type is capacitive isolation, the gate drive circuit includes a third isolator and a fifth gate driver; The first input terminal of the third isolator serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The second input terminal of the third isolator and the bias terminal of the fifth gate driver are connected to the output terminal of the external third bootstrap circuit. The output terminal of the third isolator is connected to the first input terminal of the fifth gate driver, and the second input terminal of the fifth gate driver is connected to the output terminal of the hybrid buck converter. The output terminal of the fifth gate driver serves as the high-side output terminal of the gate drive circuit and is connected to the gate of the high-side power transistor. The voltage at the bias terminal of the fifth gate driver is the sum of the output voltage and the power supply voltage.

8. A gate drive circuit for a hybrid buck converter, characterized in that, The input terminal of the gate drive circuit is connected to the output terminal of the current control module in the hybrid buck converter, and the gate drive circuit is used to receive the low-voltage gate drive signal output by the current control module. The voltage range of the gate drive signal is 0 to the power supply voltage. When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the high-side output terminal of the gate drive circuit is connected to the gate of the high-side power transistor in the hybrid buck converter. The gate drive circuit is used to convert the gate drive signal into a high-voltage domain high-side drive signal through isolation, and output the high-side drive signal so as to drive the high-side power transistor to turn on and off. The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage, and the voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. When the isolation type is chip junction isolation, the gate drive circuit includes a second pull-up level shifter and a sixth gate driver; wherein, the second pull-up level shifter includes a second low-voltage module, a fourth high-voltage module, a fifth high common-mode transient compensation module, a sixth high common-mode transient compensation module, and a third isolation module; The input terminal of the second low-voltage module serves as the input terminal of the gate drive circuit and is connected to the output terminal of the current control module. The first output terminal of the second low-voltage module is connected to the first input terminal of the fourth high-voltage module through the third isolation module. The second output terminal of the second low-voltage module is connected to the second input terminal of the fourth high-voltage module through the third isolation module. The third input terminal of the fourth high-voltage module is connected to the first output terminal of the sixth high common-mode transient compensation module. The fourth input terminal of the fourth high-voltage module is connected to the second output terminal of the sixth high common-mode transient compensation module. The output terminal of the fourth high-voltage module serves as the output terminal of the second pull-up level shifter and is connected to the gate of the high-side power transistor through the sixth gate driver. The input terminal of the fifth high common-mode transient compensation module is grounded, and the output terminal of the fifth high common-mode transient compensation module is connected to the input terminal of the sixth high common-mode transient compensation module through the third isolation module. The chip containing the gate drive circuit includes a third high-voltage N-Tub and a second low-voltage N-Tub. The second low-voltage module and the fifth high common-mode transient compensation module are located in the fourth P-well of the second low-voltage N-Tub. The fourth high-voltage module, the sixth high common-mode transient compensation module, and the sixth gate driver are located in the fifth P-well of the third high-voltage N-Tub. The third high-voltage N-Tub is connected to the high-side bootstrap voltage rail, the second low-voltage N-Tub is connected to the power supply voltage, the fifth P-well is connected to the output voltage, and the fourth P-well is grounded.

9. A gate driving method for a hybrid buck converter, characterized in that, In a gate drive circuit as described in any one of claims 1 to 8, the method comprises: The gate drive circuit receives a low-voltage gate drive signal output by the current control module, and the voltage range of the gate drive signal is from 0 to the power supply voltage. When the hybrid buck converter includes a high-side power transistor and a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal and a low-side drive signal in the high-voltage domain through isolation, and alternately outputs the high-side drive signal and the low-side drive signal so that the high-side power transistor is driven to turn on and off by the high-side drive signal, and the low-side power transistor is driven to turn on and off by the low-side drive signal. When the hybrid buck converter includes a high-side power transistor but does not include a low-side power transistor, the gate drive circuit converts the gate drive signal into a high-side drive signal in the high-voltage domain through isolation, and outputs the high-side drive signal so as to drive the high-side power transistor to turn on and off through the high-side drive signal. The voltage range of the high-side drive signal is from the output voltage to the sum of the output voltage and the power supply voltage. The voltage range of the low-side drive signal is from the low-side switch node voltage to the sum of the low-side switch node voltage and the power supply voltage. The low-side switch node voltage is the voltage of the low-side switch node connected to the low-side power transistor. The isolation types include chip junction isolation and capacitor isolation.

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