A dynamic pulse width modulation method

Abstract

The application relates to a dynamic pulse width modulation method, comprising: initializing pulse parameters, including setting an initial pulse width, a switching pulse width, a standard pulse width, a switching pulse quantity and a total pulse quantity; counting pulses; when the pulse count is less than the switching pulse quantity, performing first-stage gradual control, the first stage comprising: adopting a binary segmentation algorithm for pulse width modulation, determining a target pulse count value according to the difference between the initial pulse width and the switching pulse width, and adjusting the pulse width based on a current step value; when the pulse count is greater than or equal to the switching pulse quantity and less than the total pulse quantity, performing second-stage gradual control, the second stage comprising: adopting a linear gradual algorithm for pulse width modulation, determining a current step index through cumulative compensation calculation, and adjusting the pulse width based on the current step index; and when the pulse count is greater than or equal to the total pulse quantity, performing stable output control, and outputting the standard pulse width.

Description

Technical Field

[0001] This invention relates to the field of laser control technology, and in particular to a dynamic pulse width modulation method. Background Technology

[0002] In pulsed emission systems such as pulsed lasers and pulsed power supplies, excessive initial pulse energy and slow power escalation are common problems that affect the stability and accuracy of system output.

[0003] When the system starts up, the energy of the first pulse often significantly exceeds that of the pulse under stable operating conditions. This phenomenon can lead to problems such as unstable processing quality and increased risk of equipment damage. Simultaneously, the system typically undergoes a gradual power increase during the initial startup phase, during which the output power is unstable and fails to meet the requirements of high-precision applications. Furthermore, temperature effects also significantly impact the system's output stability; as the operating temperature changes, pulse parameters drift, further exacerbating output instability.

[0004] Existing technologies typically employ static pulse width settings or simple linear compensation methods to address the aforementioned problems, but these methods have significant technical drawbacks:

[0005] First, the static compensation method uses preset fixed parameters for pulse width modulation. This method is difficult to adapt to complex nonlinear temperature effects and power change characteristics, resulting in limited compensation effect and failure to maintain good performance under different working conditions.

[0006] Second, traditional methods usually only address a single problem in first pulse suppression or power ramp-up compensation, lacking a systematic and comprehensive solution. They cannot optimize multiple performance indicators simultaneously, and often end up neglecting one aspect in practical applications.

[0007] Third, existing technologies lack the ability to dynamically adjust according to the actual operating conditions of the system. In real-world operating environments, external conditions such as temperature and humidity change, and the system itself ages over time, all of which affect pulse output characteristics. Because existing technologies use fixed compensation parameters, they cannot respond to these changes in real time, resulting in a decrease in compensation accuracy over time and poor long-term system stability.

[0008] Furthermore, existing simple linear compensation methods have insufficient response speed when dealing with rapidly changing power characteristics, making it difficult to achieve a good balance between the fast convergence requirement for first pulse suppression and the smooth transition requirement for subsequent fine modulation, thus affecting the overall control performance. Summary of the Invention

[0009] This invention discloses a dynamic pulse width modulation method, aiming to solve the technical problems existing in the prior art. The invention adopts the following technical solution:

[0010] This invention provides a dynamic pulse width modulation method, comprising:

[0011] Initialize pulse parameters, including setting the initial pulse width, switching pulse width, standard pulse width, number of switching pulses, and total number of pulses;

[0012] Count the pulses;

[0013] When the pulse count is less than the number of switching pulses, the first stage of gradual control is executed. The first stage of gradual control includes: using a binary segmentation algorithm to perform pulse width modulation, determining the target pulse count value based on the difference between the initial pulse width and the switching pulse width, and adjusting the pulse width based on the current step value.

[0014] When the pulse count is greater than or equal to the number of switching pulses and less than the total number of pulses, the second stage of gradual control is executed. The second stage of gradual control includes: using a linear gradual algorithm to perform pulse width modulation, determining the current step index through cumulative compensation calculation, and adjusting the pulse width based on the current step index.

[0015] When the pulse count is greater than or equal to the total number of pulses, stable output control is executed, and the standard pulse width is output.

[0016] Specifically, a buffering operation is performed when switching between the first stage of gradual control and the second stage of gradual control to ensure a smooth transition of pulse width.

[0017] As a preferred technical solution, the gradual control in the first stage further includes:

[0018] The pulse width adjustment direction is determined based on the relationship between the initial pulse width and the switching pulse width;

[0019] The target pulse count value is determined by performing a binary right shift operation on the number of switching pulses, whereby the number of right shift bits is determined based on the difference between the initial pulse width and the switching pulse width.

[0020] During the first phase, when the pulse count reaches the target pulse count value, the current step value is increased and the target pulse count value is updated.

[0021] As a preferred technical solution, updating the target pulse count value includes:

[0022] The next target pulse count value is dynamically determined based on the difference between the initial pulse width and the switching pulse width and the current step value;

[0023] By decreasing the right shift bit and increasing the next target pulse count value, the update frequency of the current step value is reduced, thereby achieving adaptive adjustment from rapid convergence to smooth transition.

[0024] As a preferred technical solution, the gradual control in the first stage also includes an overmodulation protection mechanism:

[0025] A safety boundary value is set, which is determined based on the difference between the initial pulse width and the switching pulse width;

[0026] The current step value is limited to not exceeding the safety boundary value;

[0027] When the current step value reaches the safety boundary value, the increment of the current step value stops.

[0028] As a preferred technical solution, the gradual control in the second stage also includes:

[0029] The pulse width adjustment direction is determined based on the relationship between the switching pulse width and the standard pulse width;

[0030] The total number of steps in the second stage is determined based on the difference between the switching pulse width and the standard pulse width.

[0031] The step threshold is determined based on the difference between the total number of pulses and the number of switching pulses;

[0032] The update of the current step index is controlled by the cumulative compensation calculation and the step threshold.

[0033] As a preferred technical solution, controlling the update of the current step index through the cumulative compensation calculation and the step threshold includes:

[0034] In each pulse cycle, the total number of steps is cumulatively counted;

[0035] When the cumulative count reaches or exceeds the step threshold, the current step index is incremented, and the step threshold is subtracted from the cumulative count.

[0036] As a preferred technical solution, the second-stage gradual control also includes an overmodulation protection mechanism:

[0037] A safety boundary value is set, which is determined based on the difference between the switching pulse width and the standard pulse width;

[0038] The current step index is limited to not exceeding the safety boundary value;

[0039] When the current step index reaches or exceeds the safety boundary value, the current step index is restricted to the safety boundary value.

[0040] As a preferred technical solution, the switching between the first-stage gradual control and the second-stage gradual control satisfies the following conditions:

[0041] Based on the preset relationship between the pulse count and the number of switching pulses, it is determined that the stage switching condition is met;

[0042] The phase switching is performed at the pulse period boundary to ensure that the switching operation is synchronized with the pulse output.

[0043] Before switching to the execution phase, complete the output of the current pulse cycle.

[0044] As a preferred technical solution, the buffering operation includes:

[0045] Reset the counting state of the first stage;

[0046] The pulse width of the second stage is initialized to the switching pulse width;

[0047] Initialize the step index and cumulative count for the second phase;

[0048] Update the pulse count to bring it into the second-stage counting range.

[0049] As a preferred technical solution, the method is adapted to multiple triggering modes, including internal triggering mode, GATE external triggering mode and PRF_EXT external triggering mode;

[0050] In GATE external trigger mode, calculate the delay compensation parameter to limit the trigger delay to within the preset total delay range;

[0051] In PRF_EXT external trigger mode, the frequency of the external trigger signal is monitored, and the deviation between the actual trigger period and the preset trigger period is calculated. When the deviation exceeds the preset tolerance range, the overload protection flag is triggered and the pulse output is prohibited.

[0052] As a preferred technical solution, real-time status monitoring is also included:

[0053] Monitor the pulse repetition frequency and determine whether a frequency abnormality has occurred by comparing the actual pulse period with the preset pulse period;

[0054] Monitor system temperature changes and dynamically adjust delay parameters to compensate for temperature effects;

[0055] When an abnormal frequency or temperature is detected, the protection mechanism is triggered.

[0056] One embodiment of the above invention has the following advantages or beneficial effects:

[0057] This invention provides a dynamic pulse width modulation method that achieves precise control of the pulse width by dividing the pulse output process into two independent gradual control stages and a stable output stage. In the first stage, a binary segmentation algorithm is used to quickly converge to the vicinity of the target pulse width. In the second stage, a linear gradual algorithm is used to achieve a smooth transition through cumulative compensation calculation. The switching points between the two stages can be flexibly configured, and a buffer operation is performed during the switching to ensure a smooth pulse width transition, achieving a good balance between fast response and precise control.

[0058] Specifically, in the first stage of gradual control, the target pulse count is determined by performing a binary right shift operation on the number of switching pulses. The number of right shift bits is determined based on the difference between the initial pulse width and the switching pulse width. When the pulse count reaches the target pulse count, the current step value is increased and the target pulse count is updated. By gradually decreasing the number of right shift bits, the update frequency of the step value is reduced, achieving adaptive adjustment from rapid convergence to smooth transition. In the second stage, the update of the current step index is controlled by cumulative compensation calculation to ensure that the pulse width adjustment is synchronized with the pulse output, achieving a uniform and smooth linear gradual change effect.

[0059] The technical solution of this invention incorporates overmodulation protection mechanisms in both gradual control stages. By setting safety boundary values ​​and limiting the current step value or step index to not exceed these boundary values, pulse width overshoot is effectively prevented, improving the system's robustness. Furthermore, the technical solution of this invention possesses multi-trigger mode adaptability, supporting internal triggering, GATE external triggering, and PRF_EXT external triggering modes. In external triggering mode, delay compensation and frequency monitoring mechanisms ensure the accuracy of the trigger timing, and a protection mechanism is promptly triggered upon detecting anomalies, thereby ensuring reliable system operation under various operating conditions. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below, forming part of the present invention. The illustrative embodiments of the present invention and their descriptions explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0061] Figure 1 This is a flowchart of a dynamic pulse width modulation method disclosed in one embodiment of the present invention;

[0062] Figure 2 This is a schematic diagram illustrating the specific steps of a dynamic pulse width modulation method disclosed in one embodiment of the present invention;

[0063] Figure 3 This is a structural block diagram of a pulsed laser drive control device disclosed in one embodiment of the present invention. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. In the description of this invention, it should be noted that the term "or" is generally used to include the meaning of "and / or," unless otherwise expressly indicated.

[0065] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. Furthermore, in the description of this application, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0066] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0067] To address the problems existing in the prior art, embodiments of the present invention provide a dynamic pulse width modulation method, such as... Figure 1 The method includes at least the following steps:

[0068] Step S110: Initialize pulse parameters, including setting the initial pulse width, switching pulse width, standard pulse width, number of switching pulses, and total number of pulses.

[0069] Step S120: Count the pulses.

[0070] Step S130: When the pulse count is less than the number of switching pulses, the first stage of gradual control is executed. The first stage of gradual control includes: using a binary segmentation algorithm to perform pulse width modulation, determining the target pulse count value based on the difference between the initial pulse width and the switching pulse width, and adjusting the pulse width based on the current step value.

[0071] Step S140: When the pulse count is greater than or equal to the number of switching pulses and less than the total number of pulses, the second stage of gradual control is executed. The second stage of gradual control includes: using a linear gradual algorithm to perform pulse width modulation, determining the current step index through cumulative compensation calculation, and adjusting the pulse width based on the current step index.

[0072] Step S150: When the pulse count is greater than or equal to the total number of pulses, stable output control is executed, and the standard pulse width is output.

[0073] Preferably, between steps S130 and S140, a further step is included: performing a buffering operation when switching between the first stage of gradual control and the second stage of gradual control to ensure a smooth transition of pulse width.

[0074] In a preferred embodiment, step S110 performs the initialization configuration of the pulse parameters, which lays the foundation for subsequent multi-stage gradual control. Specifically, this step includes setting the following parameters:

[0075] The initial pulse width (init_pulse_width) defines the pulse width value of the first pulse in the pulse sequence. During the startup phase of the pulse transmission system, since the system has not yet reached thermal equilibrium and the energy storage element is in the initial charging state, the first pulse often exhibits excessive energy. Therefore, the setting of the initial pulse width needs to take into account both the transient response characteristics of the system and the energy suppression requirements of the first pulse. By properly configuring this parameter, the peak energy of the first pulse can be effectively reduced.

[0076] The switch pulse width (switch_pulse_width) represents the target pulse width value at the end of the first stage of gradual control, and is also the starting pulse width value for the second stage of gradual control. The switch pulse width plays a crucial role in the entire modulation process, directly affecting the smoothness of the transition between the two gradual stages. When setting this parameter, a balance must be struck between fast convergence efficiency and fine modulation accuracy.

[0077] The standard pulse width (pulse_width) defines the target pulse width value output by the system after it enters a stable operating state. Once the pulse count exceeds the preset total number of pulses, the system will continuously output this standard pulse width to ensure long-term stability and consistency. The determination of the standard pulse width should be based on the specific application scenario's requirements for output power, energy density, and pulse characteristics.

[0078] The number of switching pulses (switch_pulse_num) specifies the number of pulses required from startup to the end of the first phase, i.e., the dividing point between the first and second phases.

[0079] The total number of pulses (init_pulse_num) defines the total number of pulses required from system startup to reaching a stable output state, marking the end point of the second stage of gradual control.

[0080] The proper configuration of the above parameters is a prerequisite for achieving accurate pulse width modulation. In practical applications, the optimal configuration of each parameter should be determined through experimental testing and iterative optimization based on the specific characteristics of the pulse transmission system, the operating environment conditions, and the output performance requirements. No specific limitations are made in this embodiment.

[0081] In a preferred embodiment, step S120 performs a pulse counting operation, which counts the pulse signals output by the system in real time to provide a basis for stage determination and control strategy switching.

[0082] Specifically, after receiving the delay enable signal, the system starts outputting a pulse sequence. The pulse counter (pulse_cnt) starts from the initial value and automatically increments at the end of each pulse repetition frequency (PRF) cycle. This count value reflects the execution progress of the current pulse sequence in real time. By comparing it with the preset number of switching pulses and the total number of pulses, the system can accurately determine the current control stage.

[0083] In this embodiment, the pulse counting operation is strictly synchronized with the PRF cycle to ensure that the count update and pulse output are consistent in timing, thus avoiding control errors caused by counting delay or advance.

[0084] In a preferred embodiment, in step S130, the switching between the first-stage gradual control and the second-stage gradual control satisfies the following condition:

[0085] When the pulse count reaches a preset relationship with the number of switching pulses, the stage switching condition is determined to be met.

[0086] The phase switching is performed at the pulse period boundary to ensure that the switching operation is synchronized with the pulse output.

[0087] Before switching to the execution phase, complete the output of the current pulse cycle.

[0088] Specifically, the stage switching condition is determined by comparing the real-time value of the pulse counter with the number of switching pulses. When the pulse count reaches the preset number of switching pulses minus 1, the system recognizes that it is about to enter the last pulse cycle of the first stage. At this time, the system does not immediately execute the switch, but waits for the current PRF cycle to complete, ensuring that the last pulse of the first stage can be output with a full pulse width, avoiding pulse truncation or waveform distortion caused by improper switching timing. Furthermore, the stage switching is strictly triggered at the boundary of the PRF cycle, using the cycle end signal as the switching enable, ensuring the continuity of pulse output and the determinism of timing.

[0089] In a preferred embodiment, the buffering operation in step S130 includes:

[0090] Reset the counting state of the first stage;

[0091] Initialize the pulse width of the second stage to the switching pulse width;

[0092] Initialize the step index and cumulative count for the second phase;

[0093] Update the pulse count to bring it into the second-stage counting range.

[0094] Specifically, the buffering operation is executed during the interval between the end of the last pulse cycle of the first stage and the start of the first PRF cycle of the second stage. Within this time window, the internal counting states of the first and second stages are first reset, clearing the accumulated state of the first stage and allowing the second stage to start execution from the initial counting state, preventing historical data from interfering with the control logic of the second stage. Subsequently, the pulse width of the second stage is set to the switching pulse width value, which follows the end width of the first stage, ensuring a smooth transition between the starting pulse width of the second stage and the ending pulse width of the first stage, avoiding waveform distortion caused by sudden pulse width changes at the stage switching point. At the start of the first PRF cycle after entering the second stage, the system resets the step index of the second stage to zero, allowing the second stage to execute linear gradual control from the initial step state, while simultaneously initializing the relevant counting states to establish initial conditions for subsequent gradual control. After the buffering operation is completed, the pulse counter is updated to the count value corresponding to the number of switching pulses, ensuring that the count value accurately reflects the state of the system entering the second stage, enabling subsequent PRF cycles to correctly execute the control logic of the second stage.

[0095] In a preferred embodiment, step S130, the first stage of gradual control specifically includes: determining the pulse width adjustment direction based on the relationship between the initial pulse width and the switching pulse width; determining the target pulse count value by performing a binary right shift operation on the number of switching pulses, wherein the number of right shifts is determined based on the difference between the initial pulse width and the switching pulse width; and within the first stage, when the pulse count reaches the target pulse count value, increasing the current step value and updating the target pulse count value. Preferably, updating the target pulse count value includes: dynamically determining the next target pulse count value based on the difference between the initial pulse width and the switching pulse width and the current step value; increasing the next target pulse count value by decreasing the number of right shifts to reduce the update frequency of the current step value, thereby achieving adaptive adjustment from rapid convergence to smooth transition.

[0096] Specifically, in the first stage of gradual control, the initial pulse width and the switching pulse width are compared to determine the direction of pulse width adjustment. When the initial pulse width is greater than the switching pulse width, the increment or decrement flag (is_increasing_1) is set to 0, indicating that the pulse width needs to be decreased; when the initial pulse width is less than or equal to the switching pulse width, the increment or decrement flag is set to 1, indicating that the pulse width needs to be increased. This flag remains unchanged throughout the first stage, providing a directional basis for subsequent pulse width calculations.

[0097] Furthermore, when the delay completion signal (delay_done) is valid, the system triggers a one-time initialization calculation. First, the pulse width difference (width_diff_1) of the first stage is calculated. Its calculation formula is the absolute value of the difference between the initial pulse width (init_pulse_width) and the switching pulse width minus 1 (switch_pulse_width-1). This difference represents the overall pulse width range that needs to be adjusted in the first stage.

[0098] Based on this width difference, the system dynamically determines the initial target pulse count value (target_pulse_cnt), according to the following rules:

[0099] When the width difference is greater than or equal to 31, in order to prevent the binary right shift operation from overflowing, the system does not perform the right shift operation and directly sets the target pulse count value to 1. At this time, the system will update the step value in each pulse cycle to achieve the fastest convergence.

[0100] When the width difference is equal to 0, it indicates that the initial pulse width is equal to the switching pulse width. No pulse width adjustment is needed. The system does not perform a right shift operation and directly sets the target pulse count value to the number of switching pulses (switch_pulse_num). The first stage is completed using all pulse counts.

[0101] When the width difference is greater than 0 and less than 31, the system sets the right shift bit to the width difference itself. The target pulse count value is obtained by performing a binary right shift operation on the number of switching pulses. The calculation formula is: the target pulse count value is equal to the number of switching pulses shifted right by the width difference bit.

[0102] Simultaneously, the system pre-calculates the right shift number of the next target pulse count value (next_target_cnt). If the width difference is greater than 1, the right shift number of the next target pulse count value is equal to the width difference minus 1, and the next target pulse count value is obtained by performing a corresponding right shift operation on the number of switching pulses; if the width difference is less than or equal to 1, no right shift operation is performed, and the next target pulse count value is directly set as the number of switching pulses.

[0103] To track the execution progress of the first phase, the system maintains a dedicated transition counter (trans_pulse_cnt), which increments with each pulse cycle during the first phase and is used to compare with the target pulse count value to determine whether the step value needs to be updated.

[0104] The trigger condition for updating the step value is: the transition counter is greater than or equal to the target pulse count value, and the current step value (current_step) is less than the width difference. When the trigger condition is met, the following operations are performed:

[0105] First, increment the current step value by 1, that is, execute current_step = current_step + 1;

[0106] Then, update the target pulse count value to the next target pulse count value, that is, execute target_pulse_cnt = next_target_cnt;

[0107] Simultaneously, the next target pulse count value is recalculated, and the calculation method is dynamically determined based on the relationship between the current step value and the width difference:

[0108] When the width difference is greater than the current step value plus 2, the system sets the right shift number to the width difference minus the current step value minus 2. The next target pulse count value is obtained by performing a corresponding right shift operation on the number of switching pulses. The calculation formula is: next_target_cnt = switch_pulse_num >> (width_diff_1 - current_step - 2). This mechanism makes the right shift number gradually decrease as the step value accumulates, the target pulse count value interval increases accordingly, and the step value update frequency decreases.

[0109] When the width difference is less than or equal to the current step value plus 2, it indicates that the remaining adjustment range is close to the range of the step value. The system stops the right shift operation, directly sets the next target pulse count value as the number of switching pulses, and uses all remaining pulse counts to complete the gradual adjustment, ensuring that the pulse width at the end of the first stage can be smoothly connected to the switching pulse width.

[0110] In each pulse cycle, the system calculates the pulse width (phase1_width) for the first stage based on an increment or decrement flag and the current step value. When the increment or decrement flag is 1, it indicates that the pulse width is increasing, and the pulse width for the first stage is calculated as the initial pulse width plus the current step value, i.e., phase1_width = init_pulse_width + current_step; when the increment or decrement flag is 0, it indicates that the pulse width is decreasing, and the pulse width for the first stage is calculated as the initial pulse width minus the current step value, i.e., phase1_width = init_pulse_width - current_step.

[0111] The core of this binary right shift operation mechanism lies in controlling the dynamic balance between convergence speed and transition smoothness by controlling the number of bits shifted. The following relationship exists between the number of bits shifted and system performance: the larger the number of bits shifted, the smaller the target pulse count, the higher the step value update frequency, the faster the pulse width adjustment speed, and the faster the system achieves convergence; the smaller the number of bits shifted, the larger the target pulse count, the lower the step value update frequency, the slower the pulse width adjustment speed, but the smoother the pulse width transition.

[0112] The system achieves optimized control strategy by adaptively adjusting the right shift bit: In the initial stage of gradual transition, the right shift bit is set to a larger width difference, making the target pulse count value smaller and the step value update frequency higher, so that the system quickly converges to near the target pulse width; as the current step value increases, the system dynamically reduces the right shift bit, making the target pulse count value gradually increase, the step value update frequency gradually decrease, and the pulse width adjustment speed slows down accordingly; when the remaining difference is small, that is, when the width difference is less than or equal to the current step value plus 2, the system stops the right shift operation and uses all remaining pulse counts to complete the final smooth transition.

[0113] This adaptive mechanism enables the system to automatically adjust the modulation strategy according to the magnitude of the target pulse width difference: when the difference is large, the first stage achieves rapid convergence; when the difference is small or close to the end of the first stage, the system automatically reduces the adjustment frequency to ensure a smooth transition to the second stage and establish stable initial conditions for subsequent fine modulation.

[0114] In a preferred embodiment, step S130 further includes: determining the pulse width adjustment direction based on the relationship between the switching pulse width and the standard pulse width; determining the total number of steps in the second stage based on the difference between the switching pulse width and the standard pulse width; determining the step threshold based on the difference between the total number of pulses and the number of switching pulses; and controlling the update of the current step index through cumulative compensation calculation and the step threshold.

[0115] Specifically, in the second stage of gradual control, the switching pulse width is first compared with the standard pulse width to determine the direction of pulse width adjustment. When the switching pulse width is less than the standard pulse width, the increment or decrement flag (is_increasing_2) is set to 1, indicating that the pulse width needs to be increased; when the switching pulse width is greater than or equal to the standard pulse width, the increment or decrement flag is set to 0, indicating that the pulse width needs to be decreased. This flag remains unchanged throughout the second stage, providing a directional basis for subsequent pulse width calculations.

[0116] After the buffering operation of the phase switching is completed, the system performs the initialization calculation for the second phase. First, the pulse width difference (width_diff_2) of the second phase is calculated. The calculation formula is the absolute value of the difference between the switching pulse width (switch_pulse_width) and the standard pulse width (pulse_width). This difference represents the overall pulse width range that needs to be adjusted in the second phase.

[0117] Based on this width difference, the system determines the total number of steps in the second stage (total_stage2_steps), according to the following rules:

[0118] When the switching pulse width is less than the standard pulse width, the total number of steps is equal to the standard pulse width minus the switching pulse width, that is, total_stage2_steps = pulse_width - switch_pulse_width;

[0119] When the switching pulse width is greater than or equal to the standard pulse width, the total number of steps is equal to the switching pulse width minus the standard pulse width, that is, total_stage2_steps = switch_pulse_width - pulse_width.

[0120] The total number of steps represents the pulse width difference that needs to be adjusted from the switching pulse width to the standard pulse width, and its value directly determines the granularity of the second stage.

[0121] Furthermore, the system calculates the step threshold (step_threshold), which is equal to the total number of pulses (init_pulse_num) minus the number of switching pulses (switch_pulse_num), i.e., step_threshold = init_pulse_num - switch_pulse_num, representing the number of pulse counters available in the second stage. The step threshold controls the update frequency of the step index: when the step threshold is large, the step index update frequency is low, and the pulse width change is smoother; when the step threshold is small, the step index update frequency is high, and the pulse width change is faster.

[0122] To track the execution progress of the second stage and achieve fine-grained linear gradual control, the system maintains a dedicated fine-tuning counter (stage2_pulse_cnt), which increments with each pulse cycle during the second stage. Simultaneously, the system maintains a pulse counter (pulse_counter) for cumulative compensation calculations, with an initial value of 0.

[0123] The triggering mechanism for the step index update employs a cumulative compensation algorithm. Its core idea is to evenly distribute the total number of steps across each pulse cycle of the second stage. Accurate calculation of the step index is achieved through accumulation and threshold comparison, avoiding division operations and ensuring a uniform distribution of step index updates. The specific execution process is as follows:

[0124] At the beginning of each pulse repetition frequency (PRF) cycle, i.e. when the PRF cycle counter (prf_cnt) equals 0, the system triggers the cumulative compensation calculation;

[0125] First, the pulse counter is accumulated by executing pulse_counter = pulse_counter + total_stage2_steps, which means the total number of steps is added to the pulse counter;

[0126] Then, determine whether the pulse counter has reached or exceeded the step threshold, that is, check if pulse_counter ≥ step_threshold;

[0127] When the cumulative count reaches or exceeds the step threshold, the system performs a step index update operation: incrementing the current step index (current_step_idx) by 1, i.e., executing current_step_idx = current_step_idx + 1; and subtracting the step threshold from the cumulative count, i.e., executing pulse_counter = pulse_counter - step_threshold, to keep the cumulative error within a controllable range.

[0128] When the cumulative count has not reached the step threshold, the system does not update the step index, but only maintains the cumulative value of the pulse counter, which will continue to accumulate in the next PRF cycle.

[0129] Furthermore, in each pulse cycle, the system calculates the pulse width (phase2_width) for the second stage based on the increment or decrement flag and the current step index. When the increment or decrement flag is 1, it indicates that the pulse width is increasing, and the second-stage pulse width is calculated as the switching pulse width plus the current step index, i.e., phase2_width = switch_pulse_width + current_step_idx; when the increment or decrement flag is 0, it indicates that the pulse width is decreasing, and the second-stage pulse width is calculated as the switching pulse width minus the current step index, i.e., phase2_width = switch_pulse_width - current_step_idx.

[0130] The cumulative compensation algorithm achieves uniform distribution through accumulation and threshold comparison, avoiding floating-point and division operations, thus ensuring computational efficiency and accuracy. The algorithm works as follows: In each PRF cycle of the second stage, the system accumulates the total number of steps into the pulse counter. This accumulation operation is equivalent to accumulating the step demand. When the accumulated value reaches or exceeds the step threshold, it indicates that the accumulated step demand is sufficient to support one step index update. At this time, the system increments the step index by 1 and subtracts the step threshold from the accumulated value. The remaining accumulated value will continue to accumulate in the next cycle. Through this accumulation and compensation mechanism, the system can evenly distribute the total number of steps across all pulse cycles of the second stage, ensuring that the time interval for step index updates is as uniform as possible.

[0131] The algorithm has the following synchronization characteristics: the step index update is strictly triggered at the PRF cycle boundary, that is, when prf_cnt equals 0, ensuring that the update operation is synchronized with the pulse output; the cumulative compensation calculation is performed at the beginning of each PRF cycle, so that the pulse width adjustment and the pulse output maintain a consistent timing relationship; by setting the update trigger condition to prf_cnt equals 0, the system ensures that the step index update occurs before the start of the new pulse cycle, avoiding timing misalignment caused by update delay.

[0132] This synchronization mechanism enables the second stage to achieve a uniform and smooth linear gradient effect: the pulse width changes by only 1 unit in each adjustment period, minimizing the adjustment amplitude and ensuring the smoothest transition; the step index update is evenly distributed throughout the second stage, avoiding waveform discontinuities caused by adjustments concentrated in certain time periods; through the cumulative compensation mechanism, even if the total number of steps cannot be divided by the step threshold, the system can achieve a near-ideal uniform distribution through the distribution of accumulated errors, ensuring a precise and smooth transition from switching pulse widths to standard pulse widths, and establishing the foundation for stable output of subsequent pulse sequences.

[0133] In a preferred embodiment, step S130 further includes an overmodulation protection mechanism. The overmodulation protection mechanism prevents the pulse width adjustment from exceeding the target range by setting a safety boundary value and limiting the range of the step parameters, thus ensuring system stability.

[0134] In a preferred embodiment, the overmodulation protection mechanism in the first stage includes: setting a safety boundary value, which is determined based on the difference between the initial pulse width and the switching pulse width; limiting the current step value to not exceed the safety boundary value; and stopping the increase of the current step value when the current step value reaches the safety boundary value.

[0135] In a preferred embodiment, the overmodulation protection mechanism in the second stage includes: setting a safety boundary value, which is determined based on the difference between the switching pulse width and the standard pulse width; limiting the current step index to not exceed the safety boundary value; and limiting the current step index to the safety boundary value when the current step index reaches or exceeds the safety boundary value.

[0136] Specifically, in the first stage, the overmodulation protection mechanism first establishes clear judgment criteria. When the current step value is greater than or equal to the target pulse width difference, that is, when the current step value is greater than or equal to the absolute value of the difference between the initial pulse width and the switching pulse width minus 1, the system determines that it is in an overmodulation state, indicating that the actual pulse width adjustment exceeds the target difference. At the same time, the system sets the target pulse width range for the first stage. When the initial pulse width is greater than the switching pulse width minus 1, the target range is the interval from the switching pulse width minus 1 to the initial pulse width. When the initial pulse width is less than or equal to the switching pulse width minus 1, the target range is the interval from the initial pulse width to the switching pulse width minus 1. When the calculated pulse width value exceeds this range, it is determined to be overmodulation.

[0137] Based on the above judgment criteria, the first phase implements multiple protection measures. In the step value update condition, the system must simultaneously meet the conditions that the current pulse count has reached the target count value and the current step value is less than the pulse width difference. By forcibly requiring the current step value to be less than the pulse width difference in the update condition, it ensures that the step value does not exceed the safety boundary value. During the pulse width calculation process, since the current step value is limited by the pulse width difference, when the increment or decrement flag (is_increasing_1) is 1, the first-stage pulse width (phase1_width) equals the initial pulse width plus the current step value; when the increment or decrement flag is 0, the first-stage pulse width equals the initial pulse width minus the current step value. This calculation method ensures that the pulse width is always within the target range. Furthermore, when the pulse width difference is greater than or equal to 31, the system sets the target pulse count value to 1 to prevent right-shift operation overflow, thereby avoiding the risk of overmodulation due to overflow. The safety boundary value for the first stage is set to the pulse width difference itself. This value represents the maximum allowable range of pulse width adjustment in the first stage and is calculated and determined during initialization. If the pulse width difference is equal to 0, it means that no adjustment is needed. If the pulse width difference is greater than or equal to 31, special handling is used to prevent overflow.

[0138] Specifically, the second-stage overmodulation protection mechanism also establishes clear judgment criteria. When the current step index is greater than the total number of steps in the second stage, the system determines it to be in an overmodulation state, indicating that the step index exceeds the maximum allowed number of steps. The target pulse width range in the second stage is determined based on the relationship between the switching pulse width and the standard pulse width. When the switching pulse width is less than the standard pulse width, the target range is the interval from the switching pulse width to the standard pulse width. When the switching pulse width is greater than or equal to the standard pulse width, the target range is the interval from the standard pulse width to the switching pulse width. When the calculated pulse width value exceeds this range, it is determined to be overmodulation.

[0139] The second phase of the protective measures also features multiple protection characteristics. After the step index is updated, the system immediately checks whether the current step index is greater than or equal to the total number of steps. If this condition is met, the system limits the current step index to the total number of steps to prevent the step index from exceeding the allowable range. Through threshold judgment in the cumulative compensation algorithm, the step index is only increased when the pulse counter is greater than or equal to the step threshold. This ensures that the increment of the step index is controlled within one PRF cycle, avoiding overmodulation caused by excessively large single updates. During pulse width calculation, since the current step index is limited by the total number of steps, when the increment or decrement flag (is_increasing_2) is 1, the second-phase pulse width (phase2_width) equals the switching pulse width plus the current step index; when the increment or decrement flag is 0, the second-phase pulse width equals the switching pulse width minus the current step index. This calculation method ensures that the pulse width is always within the target range. The safety boundary value for the second stage is set as the total number of steps. This value is equal to the absolute value of the difference between the switching pulse width and the standard pulse width, representing the maximum allowable number of steps for pulse width adjustment in the second stage. It is calculated and determined during initialization. If the difference is equal to 0, it means that no adjustment is needed and the system directly outputs the standard pulse width.

[0140] Through the aforementioned multiple protection mechanisms, the system forms a complete overmodulation protection system: the safety boundary value is calculated once during initialization and remains unchanged throughout the entire operation, providing a stable reference benchmark for the protection mechanism; protection checks are performed in every clock cycle to ensure real-time monitoring and limitation; and the effectiveness of the protection mechanism is guaranteed from both mathematical and timing dimensions through multiple measures such as updating condition limits, upper limit limits, and pulse width calculation limits. This layered protection strategy not only prevents system loss of control due to single-point failures but also provides targeted protection at different control stages, ensuring stable system operation under various operating conditions.

[0141] In a preferred embodiment, the above-described dynamic pulse width modulation method further includes implementing state monitoring, including: monitoring the pulse repetition frequency and determining whether a frequency abnormality has occurred by comparing the actual pulse period with a preset pulse period; monitoring system temperature changes and dynamically adjusting the delay parameter according to the temperature changes to compensate for the temperature effect; and triggering a protection mechanism when a frequency abnormality or temperature abnormality is detected.

[0142] In a preferred embodiment, frequency anomaly detection is achieved by comparing the actual pulse period with a preset pulse period. Specifically, the system maintains a real-time pulse period counter, sampling at the rising or falling edge of each pulse and recording the number of clock cycles between two adjacent pulses as the actual pulse period. The preset pulse period is calculated based on the system clock frequency and the target pulse repetition frequency and serves as a standard reference value. The system sets a frequency anomaly judgment threshold; when the absolute value of the difference between the actual pulse period and the preset pulse period exceeds the judgment threshold, the system determines that there is a frequency anomaly.

[0143] In some preferred embodiments, when a frequency anomaly is detected, the system can take measures such as reducing the pulse repetition frequency, pausing pulse width adjustment, and issuing an alarm signal to prevent the frequency deviation from accumulating and causing the system to run away with control. When a temperature anomaly is detected, the system can take measures such as pausing high-power operations, initiating heat dissipation measures, and limiting pulse energy to prevent overheating and damage to devices.

[0144] In a preferred embodiment, the above-described dynamic pulse width modulation method is adapted to multiple trigger modes, including an internal trigger mode, a GATE external trigger mode, and a PRF_EXT external trigger mode. Different trigger modes are switched through a mode selection signal to suit different application scenarios and control requirements, giving the system flexible adaptability and a wide range of applications.

[0145] Preferably, in the GATE external trigger mode, the delay compensation parameter is calculated to limit the trigger delay to within the preset total delay range; in the PRF_EXT external trigger mode, the frequency of the external trigger signal is monitored, the deviation between the actual trigger period and the preset trigger period is calculated, and when the deviation exceeds the preset tolerance range, the overload protection flag is triggered and the pulse output is prohibited.

[0146] In a preferred embodiment, the delay compensation parameter calculation method under the GATE external trigger mode is as follows:

[0147] The delay compensation parameter `trigger_delay_n` (the actual delay value after compensation) is calculated according to the following rules: when the trigger delay input value `trigger_delay` (the trigger delay input value in GATE mode) is greater than the preset total delay `TotalDelay`, `trigger_delay_n` equals `TotalDelay`; when `trigger_delay` is less than or equal to `TotalDelay`, `trigger_delay_n` equals `trigger_delay`. Through this calculation method, the system limits the actual delay value to within the preset total delay range, ensuring that the delay value is within the system's allowable range and preventing excessive delay from causing abnormal system response or timing errors.

[0148] During the high level of the GATE signal, the system maintains a GATE delay counter, `gate_delay_counter`, to count the delay. When `gate_delay_counter` is greater than or equal to `TotalDelay` minus `trigger_delay_n`, i.e., when the condition `gate_delay_counter >= (TotalDelay - trigger_delay_n)` is met, the system outputs a delay enable signal, `delay_en`, at a high level, realizing trigger control after delay compensation. This mechanism ensures that the total delay from detecting the GATE trigger signal to the actual start of pulse output is precisely controllable, meeting the accuracy requirements of trigger timing in different application scenarios.

[0149] In a preferred embodiment, the frequency monitoring and overload protection method under the PRF_EXT external trigger mode is as follows:

[0150] The system calculates the frequency deviation by measuring the number of clock cycles (prf_counter) between the rising edges of two adjacent external trigger signals. The formula for calculating the frequency deviation is: Frequency Deviation = |prf_counter - prf_period|, where prf_counter is the actual measured PRF cycle count, and prf_period is the expected PRF cycle value. This deviation reflects the degree of difference between the actual frequency of the external trigger signal and the preset frequency.

[0151] The tolerance range setting comprehensively considers the frequency stability of the external trigger signal source, system clock accuracy, signal transmission delay, the impact of temperature changes on frequency, and system safety margin requirements. The lower limit of the tolerance range is `prf_period` minus `prf_period right-shifted by 4 bits` minus `prf_period right-shifted by 6 bits`, i.e., lower limit = `prf_period` - (`prf_period>>4`) - (`prf_period>>6`); the upper limit of the tolerance range is `prf_period` plus `prf_period right-shifted by 4 bits` plus `prf_period right-shifted by 6 bits`, i.e., upper limit = `prf_period` + (`prf_period>>4`) + (`prf_period>>6`). Here, `prf_period right-shifted by 4 bits` is equal to `prf_period` divided by 16, and `prf_period right-shifted by 6 bits` is equal to `prf_period` divided by 64. This tolerance range, achieved through displacement calculation, is approximately 7.8%. This tolerance range can accommodate frequency jitter of external trigger signals under normal operating conditions, and can also effectively identify overload conditions caused by frequency anomalies.

[0152] When prf_counter is less than the lower limit of the tolerance range or greater than the upper limit of the tolerance range, i.e., when the conditions prf_counter < (prf_period - (prf_period>>4) - (prf_period>>6)) or prf_counter > (prf_period + (prf_period>>4) + (prf_period>>6)) are met, the system triggers the overload protection flag prf_overrun_flag to be set to 1; when prf_counter is within the tolerance range, prf_overrun_flag is set to 0.

[0153] When pref_overrun_flag is 1, the system disables the delay_en signal output to prevent erroneous pulse output under abnormal frequency conditions, ensuring safe and stable system operation. This overload protection mechanism can respond promptly to abnormal changes in external trigger frequency, avoiding system failures or output errors caused by excessively high or low trigger frequencies, providing a reliable protection barrier for the system.

[0154] refer to Figure 2 In a specific embodiment of the present invention, a specific example of a dynamic pulse width modulation method is provided as follows:

[0155] Step S201: System initialization. Set the initial pulse width as init_pulse_width, the number of switching pulses as switch_pulse_num, the total number of pulses as init_pulse_num, the switching pulse width as switch_pulse_width, the standard pulse width as pulse_width, and initialize various control parameters.

[0156] Furthermore, the parameter setting method is as follows:

[0157] (1) Value range and determination method of the number of switching pulses switch_pulse_num:

[0158] The value range of switch_pulse_num is: 1 ≤ switch_pulse_num < init_pulse_num, and switch_pulse_num is a positive integer;

[0159] The determination method of switch_pulse_num is determined according to the actual light output effect and application scenarios. The specific considerations include:

[0160] a) Requirement for suppressing the energy of the first pulse: When the energy of the first pulse is too large and needs to be quickly suppressed, the value of switch_pulse_num is relatively small, which is 10% to 30% of the total number of pulses, to achieve rapid convergence;

[0161] b) Requirement for compensating the slow power rise: When the slow power rise process is long, the value of switch_pulse_num is relatively large, which is 30% to 50% of the total number of pulses, to ensure that there are enough pulses for fine modulation;

[0162] c) Requirement for system stability: When the system has high requirements for stability, the value of switch_pulse_num is moderate, which is 20% to 40% of the total number of pulses, to balance rapid convergence and smooth transition;

[0163] d) Characteristics of the application scenario: According to the characteristics of the application scenarios such as the type of pulsed laser, operating frequency, temperature characteristics, etc., determine the optimal value of switch_pulse_num through experimental tests to make the light output effect reach the best state.

[0164] (2) Determination method of the total number of pulses init_pulse_num:

[0165] The value of init_pulse_num is determined according to the actual light output effect and application scenarios. The specific considerations include:

[0166] a) Power stabilization time: init_pulse_num is greater than or equal to the time required for the system to reach power stabilization, and is 1.5 to 2 times the system stabilization time;

[0167] b) Temperature effect compensation: Considering the impact of temperature changes on the system, init_pulse_num can cover the power change cycle caused by temperature effects;

[0168] c) Application scenario requirements: Based on different application scenarios, including material processing, medical equipment, scientific research experiments, etc., the optimal value of init_pulse_num will be determined through actual testing.

[0169] Step S202: Start the pulse sequence. Upon receiving the delay enable signal delay_en, pulse sequence control begins.

[0170] Step S203: Determine the current stage. Based on the relationship between the current pulse count pulse_cnt and the number of switching pulses switch_pulse_num, determine whether the current stage is the first stage or the second stage.

[0171] Step S204: Execute the first stage of control. When pulse_cnt is less than switch_pulse_num, execute the binary segmentation algorithm:

[0172] (1) Calculate the pulse width difference: width_diff_1 = |init_pulse_width - (switch_pulse_width - 1)|;

[0173] (2) The target pulse count is determined by a right shift operation: target_pulse_cnt = switch_pulse_num >> width_diff_1, where ">>" represents a binary right shift operation, shifting right by width_diff_1 bits;

[0174] (3) Adjust the current pulse width according to the increment or decrement flag is_increasing_1. When is_increasing_1 is 1, phase1_width = init_pulse_width + current_step. When is_increasing_1 is 0, phase1_width = init_pulse_width - current_step.

[0175] Step S205: Execute the second stage of control. When pulse_cnt is greater than or equal to switch_pulse_num and less than init_pulse_num, execute the linear gradient algorithm:

[0176] (1) Calculate the pulse width difference in the second stage: width_diff_2 = |switch_pulse_width - pulse_width|;

[0177] (2) Calculate the total number of steps in the second stage, total_stage2_steps. The total number of steps is calculated as follows: when switch_pulse_width is less than pulse_width, total_stage2_steps = pulse_width - switch_pulse_width; when switch_pulse_width is greater than or equal to pulse_width, total_stage2_steps = switch_pulse_width - pulse_width. The total number of steps represents the pulse width difference that needs to be adjusted from the switching pulse width to the target pulse width. Its value is determined according to the actual light output effect and application scenario. The optimal value is determined through experimental testing to make the pulse width gradual change process smooth and reach the target pulse width.

[0178] (3) Calculate the step threshold step_threshold = init_pulse_num - switch_pulse_num. The step threshold is determined based on the following: step_threshold represents the number of pulses available in the second stage, which is used to control the update frequency of the step index. Its value is determined according to the actual light output effect and application scenario. When step_threshold is large, the step index update frequency is low and the pulse width change is smoother. When step_threshold is small, the step index update frequency is high and the pulse width change is faster. The determination of the step threshold needs to consider the following factors: the absolute value of the pulse width difference, the system's requirements for smoothness, and the application scenario's requirements for response speed. The optimal step_threshold value is determined through actual testing so that the light output effect reaches the best state.

[0179] (4) Calculate the current step index current_step_idx using the cumulative error compensation algorithm: at the beginning of each PRF cycle, execute pulse_counter = pulse_counter + total_stage2_steps. When pulse_counter is greater than or equal to step_threshold, execute current_step_idx = current_step_idx + 1, pulse_counter = pulse_counter - step_threshold. This algorithm avoids division operations and achieves accurate calculation of the step index through accumulation and comparison.

[0180] (5) Adjust the current pulse width according to the increment or decrement flag is_increasing_2. When is_increasing_2 is 1, phase2_width = switch_pulse_width + current_step_idx. When is_increasing_2 is 0, phase2_width = switch_pulse_width - current_step_idx.

[0181] Step S206: Output a stable pulse. When pulse_cnt is greater than or equal to init_pulse_num, output the standard pulse width pulse_width.

[0182] Step S207: Real-time monitoring and protection. Continuously monitor the system status, including frequency overload detection and temperature compensation.

[0183] Furthermore, specific applications of the parameter determination method include:

[0184] (1) For application scenarios with high requirements for first pulse energy suppression, including high-precision material processing, set switch_pulse_num = 8 and init_pulse_num = 20 to quickly suppress the first pulse energy while ensuring sufficient stabilization time;

[0185] (2) For application scenarios with high power sag compensation requirements, including medical laser equipment, set switch_pulse_num = 15 and init_pulse_num = 30 to ensure smooth compensation during the power sag process;

[0186] (3) For application scenarios with high system stability requirements, including scientific research experimental equipment, set switch_pulse_num = 10 and init_pulse_num = 25 to balance fast convergence and smooth transition, and ensure stable system operation.

[0187] The specific values ​​of the above parameters are determined through experimental testing based on the actual light output effect and application scenario to achieve the best pulse width modulation effect.

[0188] refer to Figure 3 In one embodiment of the present invention, a pulsed laser driving control device is also provided. This device is implemented using a field-programmable gate array (FPGA) and includes the following main modules:

[0189] The pulse control module 310 implements the two-stage algorithm control logic. This module receives the clock signal clk and the reset signal rst_n, and controls the pulse output according to the delay enable signal delay_en. The pulse control module internally contains the two-stage algorithm control logic, which manages the entire pulse generation process through a state machine, ensuring that the pulse sequence is output accurately according to preset parameters.

[0190] The parameter calculation module 320 is used to maintain and manage multiple hierarchical counters, including the total pulse counter `pulse_cnt`, the first-stage transition counter `trans_pulse_cnt`, and the second-stage fine modulation counter `stage2_pulse_cnt`. The total pulse counter tracks the output progress of the entire pulse sequence, the first-stage transition counter performs state transitions between pulse width control and pulse interval control, and the second-stage fine modulation counter achieves precise timing of the pulse interval. These counters work together to achieve precise stage control, ensuring high accuracy in pulse output timing.

[0191] The trigger adaptation module 330 supports flexible switching between multiple operating modes, including: Mode 0 is a static test mode used for system debugging and verification; Mode 1 is an internal trigger mode controlled by the communication enable signal comm_enable, which generates periodic trigger signals through an internal pulse repetition frequency generator; Mode 2 is a GATE external trigger mode with delay compensation, suitable for applications requiring precise trigger timing alignment; and Mode 3 is a PRF_EXT external trigger mode with frequency monitoring, suitable for application environments where the frequency of the external trigger signal may fluctuate. The trigger adaptation module dynamically switches its operating state according to the mode selection signal, providing an adaptive trigger mechanism for different application scenarios.

[0192] The status monitoring module 340 is used to monitor the system's operating status in real time, including a frequency monitoring unit and a temperature compensation unit. The frequency monitoring unit determines whether a frequency overload has occurred by comparing the actual period count value `prf_counter` with the preset period `prf_period`. When `prf_counter` exceeds the tolerance range calculated based on `prf_period`, it is determined to be a frequency anomaly. The temperature compensation unit dynamically adjusts the delay parameter `trigger_delay_n` according to the operating mode to compensate for the impact of temperature changes on system timing, ensuring stable trigger delay under different environmental conditions.

[0193] The protection control module 350 automatically triggers a protection mechanism to disable pulse output and ensure safe and stable system operation when frequency overload or other abnormal conditions are detected. When the frequency monitoring unit detects that pref_counter exceeds the tolerance range, the protection control module immediately sets the overload protection flag and prevents the generation of the delay enable signal delay_en, thereby interrupting the output of the pulse sequence. The protection control module also monitors other abnormal states of the system, such as parameter configuration errors and clock failures, providing comprehensive system protection functions.

[0194] In this embodiment, the modules are interconnected internally to achieve data exchange and coordinated control. The entire device is driven by a 100MHz clock, ensuring the system's real-time performance and accuracy. Through the above technical solution, this device successfully solves the technical problems of insufficient pulse modulation accuracy and poor adaptability in the prior art, providing an effective solution for optimizing the performance of pulse transmission systems.

[0195] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

Claims

1. A dynamic pulse width modulation method, characterized in that, include: Initialize pulse parameters, including setting the initial pulse width, switching pulse width, standard pulse width, number of switching pulses, and total number of pulses; Count the pulses; When the pulse count is less than the number of switching pulses, the first stage of gradual control is executed. The first stage of gradual control includes: using a binary segmentation algorithm to perform pulse width modulation, determining the target pulse count value based on the difference between the initial pulse width and the switching pulse width, and adjusting the pulse width based on the current step value. When the pulse count is greater than or equal to the number of switching pulses and less than the total number of pulses, the second stage of gradual control is executed. The second stage of gradual control includes: using a linear gradual algorithm to perform pulse width modulation, determining the current step index through cumulative compensation calculation, and adjusting the pulse width based on the current step index. When the pulse count is greater than or equal to the total number of pulses, stable output control is executed, and the standard pulse width is output. Specifically, a buffering operation is performed when switching between the first stage of gradual control and the second stage of gradual control to ensure a smooth transition of pulse width.

2. The dynamic pulse width modulation method according to claim 1, characterized in that, The first stage of gradual control also includes: The pulse width adjustment direction is determined based on the relationship between the initial pulse width and the switching pulse width; The target pulse count value is determined by performing a binary right shift operation on the number of switching pulses, whereby the number of right shift bits is determined based on the difference between the initial pulse width and the switching pulse width. During the first phase, when the pulse count reaches the target pulse count value, the current step value is increased and the target pulse count value is updated.

3. The dynamic pulse width modulation method according to claim 2, characterized in that, The updating of the target pulse count value includes: The next target pulse count value is dynamically determined based on the difference between the initial pulse width and the switching pulse width and the current step value; By decreasing the right shift bit and increasing the next target pulse count value, the update frequency of the current step value is reduced, thereby achieving adaptive adjustment from rapid convergence to smooth transition.

4. The dynamic pulse width modulation method according to claim 2, characterized in that, The first stage of gradual control also includes an overmodulation protection mechanism: A safety boundary value is set, which is determined based on the difference between the initial pulse width and the switching pulse width; The current step value is limited to not exceeding the safety boundary value; When the current step value reaches the safety boundary value, the increment of the current step value stops.

5. The dynamic pulse width modulation method according to claim 1, characterized in that, The second stage of gradual control also includes: The pulse width adjustment direction is determined based on the relationship between the switching pulse width and the standard pulse width; The total number of steps in the second stage is determined based on the difference between the switching pulse width and the standard pulse width. The step threshold is determined based on the difference between the total number of pulses and the number of switching pulses; The update of the current step index is controlled by the cumulative compensation calculation and the step threshold.

6. The dynamic pulse width modulation method according to claim 5, characterized in that, The step of controlling the update of the current step index through the cumulative compensation calculation and the step threshold includes: In each pulse cycle, the total number of steps is cumulatively counted; When the cumulative count reaches or exceeds the step threshold, the current step index is incremented, and the step threshold is subtracted from the cumulative count.

7. The dynamic pulse width modulation method according to claim 5, characterized in that, The second stage of gradual control also includes an overmodulation protection mechanism: A safety boundary value is set, which is determined based on the difference between the switching pulse width and the standard pulse width; The current step index is limited to not exceeding the safety boundary value; When the current step index reaches or exceeds the safety boundary value, the current step index is restricted to the safety boundary value.

8. The dynamic pulse width modulation method according to claim 1, characterized in that, The switching between the first-stage gradual control and the second-stage gradual control satisfies the following conditions: Based on the preset relationship between the pulse count and the number of switching pulses, it is determined that the stage switching condition is met; The phase switching is performed at the pulse period boundary to ensure that the switching operation is synchronized with the pulse output. Before switching to the execution phase, complete the output of the current pulse cycle.

9. The dynamic pulse width modulation method according to claim 1, characterized in that, The buffering operation includes: Reset the counting state of the first stage; The pulse width of the second stage is initialized to the switching pulse width; Initialize the step index and cumulative count for the second phase; Update the pulse count to bring it into the second-stage counting range.

10. The dynamic pulse width modulation method according to claim 1, characterized in that, The method is adapted to multiple triggering modes, including internal triggering mode, GATE external triggering mode, and PRF_EXT external triggering mode. In GATE external trigger mode, calculate the delay compensation parameter to limit the trigger delay to within the preset total delay range; In PRF_EXT external trigger mode, the frequency of the external trigger signal is monitored, and the deviation between the actual trigger period and the preset trigger period is calculated. When the deviation exceeds the preset tolerance range, the overload protection flag is triggered and the pulse output is prohibited.

11. The dynamic pulse width modulation method according to claim 1, characterized in that, It also includes real-time status monitoring: Monitor the pulse repetition frequency and determine whether a frequency abnormality has occurred by comparing the actual pulse period with the preset pulse period; Monitor system temperature changes and dynamically adjust delay parameters to compensate for temperature effects; When an abnormal frequency or temperature is detected, the protection mechanism is triggered.

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