A true complement-based tsv efficient testing and diagnosis method and circuit

Abstract

The present application belongs to the field of integrated circuit design for testability, and discloses a TSV efficient test and diagnosis method and circuit based on true complement codes, which comprises the following steps: dividing a TSV array into G groups, generating a test sequence based on true complement codes, taking each group as a victim and the rest as attackers in turn, respectively applying "001" and "010" excitations, and exciting and identifying ten types of faults through multiple rounds of testing; adopting time division multiplexing identification logic to compress 6-bit responses into 4-bit fault codes to realize unique determination of fault types. The corresponding circuit comprises a finite state control machine, a test data generator, a boundary register and a reusable identification module, supports full built-in self-test, and does not require external equipment intervention. The present application significantly shortens the test time and reduces the hardware overhead while ensuring high fault coverage, is suitable for high-density TSV interconnection arrays arranged in any manner, and has the advantages of high test efficiency, low cost and wide application range.

Description

Technical Field

[0001] This invention belongs to the field of design testability technology for very large-scale integrated circuits, and particularly relates to an efficient TSV testing and diagnostic method and circuit based on true two's complement. Background Technology

[0002] As integrated circuit manufacturing processes approach their physical limits, integrated chip technology has become a new path to improve chip performance and integration. Through chip-to-chip interconnect technology, integrated chips achieve functional integration of individual chips, overcoming the yield and cost limitations of existing chip manufacturing while increasing system integration and performance optimization potential. Among these technologies, through-silicon vias (TSVs) used in 3D packaging, characterized by their large number, high space density, and complex manufacturing processes, have become a key challenge for improving integrated chip yield.

[0003] During the bonding process of core-to-chip interconnects, TSV interconnects may develop various process defects due to process and environmental factors, leading to interconnect communication failures. To effectively perform post-bonding testing, it is necessary to model different defect types.

[0004] Currently, mainstream TSV testing and diagnostic solutions are mainly divided into two methods: scan chain technology and built-in self-test (BIST). These aim to quickly and accurately locate TSV interconnects with process defects. The key components of the test are as follows: ① Test algorithm design; ② Testability design circuit scheme.

[0005] A test algorithm based on true / inverse codes was first used for interconnect testing, capable of identifying all potential open-circuit and short-circuit faults. Extensive research has also been conducted on the problem of excessively long test times for large-scale interconnect testing. To reduce test application time, some algorithms have considered the two-dimensional arrangement of interconnects, proposing a self-test scheme using alternating row and column stripe test patterns, compressing the 2D test mode into a 1D test mode. However, due to the increasing interconnect communication frequency and the application of TSVs, this scheme cannot cover and identify all fault types; increasing test time at the expense of test coverage is unacceptable. The KAF grouping test scheme is considered an effective solution to the crosstalk problem in TSV interconnects. First, based on the global arrangement of the TSV interconnects under test, they are grouped using the KAF grouping algorithm. Then, testing is performed according to the group number, iterating sequentially until each group of interconnects has been tested. By adjusting the grouping and multiple rounds of test iterations, test coverage can be ensured; however, the total number of test rounds is also positively correlated with the number of groups, often leading to an extension of test time.

[0006] In the area of ​​Design for Testability (DTV) circuits, the IEEE released the IEEE 1838 test standard for chip-level devices in 2019, compatible with existing DTV standards. Within this standard, IEEE proposed a chip-level package register (DWR) scheme, using scan-chain technology to perform chip interconnect testing. Comparatively, scan-chain-based DTV solutions are more versatile, allowing for design independent of the test algorithm and flexible adjustment of the test flow. However, the serial input / output mechanism of scan-chains and their high dependence on external test equipment lead to increasing testing costs as TSV density and quantity increase. To ensure coverage while reducing test time, most integrated circuit manufacturers currently choose the Built-in Self-Test (BIST) scheme for TSV testing because BIST can perform interconnect testing in parallel, resulting in higher efficiency and lower demand for external test equipment. However, traditional TSV testing methods still have significant shortcomings. Some schemes do not support a comprehensive range of defect types, while others require full consideration of various defect types, leading to hardware design difficulties and lower testing efficiency. Furthermore, the dependence on external test equipment results in a cost burden.

[0007] In summary, existing TSV rapid testing and diagnostic technologies still have the following shortcomings:

[0008] Dependence on external testing equipment: Most testing solutions require external testing equipment to provide test vectors or to analyze interconnect defects based on test results, resulting in considerable time and resource costs.

[0009] Relying on complex algorithms and making hardware design difficult: In order to deal with the defects of TSV that may be caused by crosstalk, the latest works have adopted complex algorithms to test TSV. While this can ensure test coverage, it also increases the additional test time and hardware design cost.

[0010] Limited applicability: In order to optimize testing time and conduct tests efficiently, some technologies are designed only for interconnect arrays with specific layouts (rectangular or hexagonal), which to some extent limits the application scope of the technology.

[0011] Therefore, how to accurately and quickly test chip interconnects while controlling costs is a critical issue that urgently needs to be addressed. Summary of the Invention

[0012] This invention provides a high-efficiency TSV testing and diagnostic method and circuit based on true two's complement, aiming to solve the problems of long testing time, complex hardware design, strong dependence on external devices, and limited applicability in existing TSV testing technologies. Through innovative testing algorithms and circuit structures, this invention significantly improves testing efficiency and reduces testing costs and hardware overhead while ensuring high fault coverage.

[0013] To address the aforementioned technical problems, the present invention provides a specific technical solution for an efficient TSV testing and diagnosis method and circuit based on true two's complement, as follows:

[0014] An efficient TSV testing and diagnostic method based on true two's complement includes the following steps:

[0015] Step 1: Divide the TSV interconnect array under test into G groups, where G is an integer greater than or equal to 2;

[0016] Step 2: Generate a test stimulus sequence based on the true complement test algorithm, and treat each group as the victim and the remaining groups as the attackers in turn;

[0017] Step 3: Apply the first incentive vector to the victim group and the second incentive vector to the attacker group;

[0018] Step 4: Collect the response signals of each TSV in multiple test rounds;

[0019] Step 5: Compress the response signal into a fault type code using time-division multiplexing identification logic;

[0020] Step 6: Repeat the above steps and invert all activation vectors to complete the full sequence test.

[0021] Furthermore, the first excitation vector is "001" and the second excitation vector is "010".

[0022] Furthermore, the test stimulus sequence includes a three-round stimulus pattern to cover crosstalk faults, adjacent rounds of stimulus to trigger delay faults, and supplementary stimulus to ensure that the last set of tests covers delay faults.

[0023] Furthermore, the fault type is encoded as 4 bits, which is obtained by compressing a 6-bit response signal through negative feedback logic.

[0024] The present invention also discloses a high-efficiency TSV testing and diagnostic circuit for implementing the method, comprising:

[0025] Finite state control machine, used to control test procedures and mode switching;

[0026] A test data generator is used to store and output the test stimulus sequence;

[0027] Boundary registers are used to switch data paths between functional mode and test mode, and to compare test responses;

[0028] The identification module is used to realize time-division multiplexing identification and compressed storage of fault types, including a linear shift register, negative feedback logic circuit and multiplexer.

[0029] Furthermore, the identification module supports multiplexing among G groups of TSVs, with each group of TSVs corresponding to a 4-bit linear shift register.

[0030] Furthermore, the boundary register is equipped with a 2:1 multiplexer at the transmitting end and an XOR logic comparator at the receiving end.

[0031] Furthermore, the test data generator uses ROM or hardwired logic to store the test sequence.

[0032] Furthermore, the circuit has a built-in self-test structure, eliminating the need for external testing equipment during the post-silicon testing phase.

[0033] Furthermore, the circuit supports TSV interconnect arrays with arbitrary arrangements.

[0034] The efficient TSV testing and diagnostic method and circuit based on true two's complement of the present invention has the following advantages:

[0035] 1. Significantly improved testing efficiency

[0036] By employing a grouping test algorithm based on true complement, combined with a victim-attacker model and a multi-round incentive strategy, ten common TSV fault types (including fixed faults, bridging faults, delay faults, and coupling faults) can be fully covered in fewer test rounds.

[0037] Compared to the traditional KAF grouping test scheme, the test sequence length is shortened by about 10.2%, and the test time is significantly reduced, making it suitable for high-density, large-scale TSV interconnect arrays.

[0038] 2. Low hardware overhead, supports time-division multiplexing

[0039] The identification module adopts a time-division multiplexing mechanism, sharing the same set of negative feedback logic and shift registers among different groups of TSVs, which greatly reduces the circuit area.

[0040] The boundary register only adds a 2:1 multiplexer and an XOR comparator, which has a minimal impact on functional path delay and hardly affects the normal performance of the chip.

[0041] 3. High fault identification accuracy

[0042] By compressing the 6-bit response signal into a 4-bit fault type code, ten types of faults can be uniquely identified without aliasing.

[0043] It supports real-time diagnosis and storage of fault types during testing, without the need for external device intervention, and has a high diagnostic accuracy.

[0044] 4. Strong applicability and scalability

[0045] The algorithm and circuit design are independent of the TSV layout and support rectangular, hexagonal and arbitrary topology interconnect arrays.

[0046] The test sequence can be flexibly expanded according to the number of groups G, making it suitable for chip interconnect systems of different sizes.

[0047] 5. Reduce reliance on external testing equipment

[0048] It adopts a fully built-in self-test (BIST) architecture, where test stimulus generation, response collection, and fault diagnosis are all completed inside the chip.

[0049] The post-silicon testing stage does not require the participation of high-end testing equipment, significantly reducing testing costs and equipment dependence.

[0050] 6. Compatible with existing standards and processes

[0051] The boundary register design is compatible with the IEEE 1838 standard and can be seamlessly integrated into existing chip test frameworks.

[0052] The circuit structure is simple and easy to implement and verify in existing design processes.

[0053] In summary, this invention achieves significant breakthroughs in four aspects: testing speed, diagnostic accuracy, hardware cost, and scope of application. It is particularly suitable for rapid and reliable testing and diagnosis of high-density TSV interconnects in 3D integrated chips, and has important engineering application value and industrialization prospects. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of a test algorithm based on true two's complement.

[0055] Figure 2 A schematic diagram showing the test stimulus coverage for ten fault types;

[0056] Figure 3 A sample diagram of the test sequence list when the number of groups G=2, 3, and 4;

[0057] Figure 4 This is a schematic diagram of the test response for ten fault types when G=2;

[0058] Figure 5 This is a schematic diagram of the overall circuit architecture of the present invention;

[0059] Figure 6 This is the state transition diagram of the finite state control machine of the present invention;

[0060] Figure 7 This is a schematic diagram showing the test verification results and compression results;

[0061] Figure 8 This is a time-division multiplexing circuit structure diagram of the identification module of the present invention. Detailed Implementation

[0062] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an efficient TSV testing and diagnostic method and circuit based on true two's complement.

[0063] The present invention provides an efficient TSV testing and diagnosis method based on true two's complement, comprising the following steps:

[0064] Step 1: Construct a grouping test algorithm based on true two's complement.

[0065] The TSV interconnect array under test is divided into G groups, and a test stimulus sequence is generated using the true two's complement test principle. During the test, each group of TSVs takes turns as the "victim" and the other groups take turns as the "attackers". Different test vectors ("001" and "010") are applied to each group. Through multiple rounds of testing, ten common TSV fault types are stimulated and distinguished, including fixed faults, bridging faults, delay faults and coupling faults.

[0066] Definition and characteristics of true two's complement:

[0067] like Figure 1 As shown, True / Complement Code is a testing algorithm based on several encoding methods for representing signed integers in computers. True / Complement Code, also known as sign-magnitude representation, is the most intuitive binary representation method. The sign-magnitude representation of a positive number is its binary form, while the sign-magnitude representation of a negative number is obtained by changing the sign bit to 1. The two's complement of a positive number is the same as its sign-magnitude representation, while the two's complement of a negative number is obtained by inverting each bit and adding 1.

[0068] The test algorithm based on true complement takes the idea of ​​inverting the encoding method and divides the test algorithm into two parts: original code and complement code.

[0069] This algorithm has several advantages: First, fault-free interconnects always have the same number of 0s and 1s, while interconnects with more 0s or more 1s are faulty; second, for fixed faults and bridging faults, the test algorithm based on true complement can avoid aliasing of test results, ensuring the algorithm's recognition capability; finally, the algorithm is more efficient, with a test time complexity of O(log₂n) for n pairs of interconnects.

[0070] like Figure 2 As shown, the test algorithm based on true complement cannot effectively stimulate and distinguish between delay faults and coupling faults, and cannot meet the test requirements of the current high-density and high-speed TSV interconnects.

[0071] To accomplish the tasks of testing and defect identification, the test stimulus must excite all possible faults of each TSV, and the responses to different faults must be distinct. The KAF testing algorithm divides the interconnection into attacker and victim, focusing only on and analyzing the victim's response anomalies during testing, while ignoring the attacker's test response. However, since the test input stimulus is parallel, the attacker is also affected by the crosstalk effect of the victim, and its input itself can also excite specific defects. If the stimulus can simultaneously test the current TSV and attack adjacent TSVs, the testing time should be further reduced. Therefore, this invention proposes a grouping test algorithm based on true complement, including the following steps:

[0072] Step 1.1: Divide the TSV interconnect array under test into G groups, where G is an integer greater than or equal to 2;

[0073] Step 1.2: Generate a test stimulus sequence based on the true complement test algorithm, and treat each group as the victim and the remaining groups as the attackers in turn;

[0074] Step 1.3: Apply a first stimulus vector to the victim group and a second stimulus vector to the attacker group; the first stimulus vector is “001” and the second stimulus vector is “010”.

[0075] Step 1.4: Collect the response signals of each TSV in multiple test rounds;

[0076] Step 1.5: Compress the response signal into a fault type code using time-division multiplexing identification logic;

[0077] Step 1.6: Repeat the above steps and invert all activation vectors to complete the full sequence test.

[0078] Step 2: Design the stimulus sequence

[0079] The test sequence is divided into two parts:

[0080] The first part covers the faults caused by crosstalk by using a three-round excitation mode;

[0081] Adjacent round excitations are used to trigger delayed faults;

[0082] The remaining supplementary incentives ensure that the last set of tests also fully covers latency faults.

[0083] The entire test sequence supports flexible expansion to adapt to different numbers of groups and interconnection arrangements.

[0084] Step 3: Construct a fault identification and compression mechanism

[0085] During the testing process, the response signals of each TSV in key test rounds are collected, and the 6-bit response is compressed into a 4-bit fault type code through negative feedback logic to achieve unique identification and storage of fault types.

[0086] like Figure 5 As shown, the present invention provides a high-efficiency TSV test and diagnostic circuit based on true complement, comprising a finite state control machine (FSM), a diagnosis module, a die wrapper register, and a test pattern generator.

[0087] We use a finite state machine for self-test process control. For example... Figure 6 As shown, the test procedure is as follows: After system reset, the state machine enters the reset state, waiting for the function selection signal TM / TDM (test mode / test and diagnosis mode) and the test start signal START. All signals need to be transmitted through D flip-flops to avoid CDC problems caused by cross-clock domains. Based on the provided instructions, the state machine will enter the test or identification state. In the test state, the system will enable the TPG to output test data and control the identification module to record faults until all test rounds are completed. In the identification state, the system will also enable the TPG and control the identification module to reuse its function across current test rounds until all test rounds are completed. Finally, the system enters the result shift state, waiting for the external test equipment to shift out the test results.

[0088] Identification Module: The identification module is responsible for identifying the defect type. Observation Figure 4 It can be observed that the test rounds corresponding to each group of TSVs do not overlap in time, which means that the test identification logic can be time-division multiplexed between different groups of TSVs to save area. Compared with the existing technology (a BIST-based TSV test and diagnostic circuit and method), the test sequence length (i.e., the number of clock cycles required for the test) of the present invention can be shortened by about 10.2%. The identification module can be divided into the following parts:

[0089] Each TSV requires a 4-bit linear shift register (to store the results of the ten identified fault types).

[0090] A set of negative feedback logic for compressing a 6-bit fault response into a 4-bit response (which can be multiplexed within different groups of TSVs in different test cycles) is used. This logic is a pure combinational logic circuit without clock and reset signals. The input signals are the current error type data and the correct / incorrect flag of the current cycle test verification. The module selects different interconnected fault type registers and performs calculations based on the finite state machine signals and the test verification results. The compressed diagnostic data is then fed back to the fault type register. Figure 8 As shown, the finite state machine provides the Diag_en[G-1:0] enable signal, controlling the input of the fault type register to switch between the correct / incorrect flag signal Fail_flag[G-1:0] of the current cycle test and the negative feedback output signal of the fault identification combinational logic. In the identification state, the finite state machine provides the selection signal Group_sel according to the current test round, controlling the identification module to perform time-division multiplexing, and simultaneously serving as the shift enable signal for each of the different linear shift registers. The input signals of the fault identification combinational logic are the current error type data (derived from the linear shift register of each TSV) and the correct / incorrect flag Fail_flag[G-1:0] of the current cycle test. Finally, the module selects different interconnected fault type registers and performs calculations based on the finite state machine signals and the test results; the compressed diagnostic data is then fed back to the fault type register. The specific correspondence is as follows: Figure 7 As shown.

[0091] A set of selectors. In the identification state, the finite state machine will provide selection signals according to the current test round, controlling the identification module to perform time-division multiplexing, and also serving as the shift enable signal for the linear shift register.

[0092] Boundary Register: The boundary register is responsible for transmitting and receiving test stimuli. Based on the transmission and reception direction of the test data, we make the following modifications: A multiplexer is added to the transmitting boundary register, switching to BIST input in test mode. The output of the receiving boundary register is XORed with the TPG output. In test mode, fault signals are locked through negative feedback. In identification mode, fault signals are sequentially input to the identification module, finally obtaining the identification result. After adding the BIST circuit, the critical path of the functional circuit only needs to pass through an additional 2:1 selector, and the resulting performance impact is almost negligible.

[0093] Test data generator: The test data generator is responsible for generating and sending test data. The test data sequence can be stored directly in it in the form of values ​​because its total data length is quite limited.

[0094] The above modules work together to form a complete BIST testing system, which requires virtually no external equipment intervention during the post-silicon testing stage, enabling efficient autonomous testing and diagnosis.

[0095] Algorithm Example:

[0096] The steps for constructing the grouping test algorithm based on true two's complement in this invention are as follows:

[0097] 1. Input and Initialization:

[0098] Input the TSV interconnect array to be tested and its grouping scheme G (G is the total number of groups, G≥2).

[0099] Initialize the loop variable i = 1.

[0100] 2. Outer loop: Iterate through each group as the victim:

[0101] When i ≤ G, perform the following steps:

[0102] a. Set j = 1.

[0103] b. Enter the inner loop: Iterate through all groups (including the current group itself).

[0104] 3. Inner loop: Differentiate between victim and attacker and apply incentives:

[0105] When j ≤ G, execute:

[0106] If i == j: This means that the current j-th group is the "victim" group.

[0107] Apply test stimulus "001" to all TSVs in the group.

[0108] The diagnostic module collects the response values ​​of the group of TSVs in the second and third bits (i.e., the second and third clock cycles) during this round of testing and stores them as test results.

[0109] If i ≠ j: it means that the current j-th group is the "attacker" group.

[0110] Apply test stimulus "010" to all TSVs in the group.

[0111] The diagnostic module collects the response value of the group of TSVs in the first bit (i.e. the first clock cycle) during this round of testing and stores it as the test result.

[0112] j = j + 1, continue processing the next group.

[0113] The inner loop ends.

[0114] 4. Iterative loop:

[0115] i = i + 1, select the next group as the victim, repeat steps 2-3 until all groups have completed one test as victims.

[0116] 5. Supplement with stable incentives:

[0117] After completing the above double loop, apply an excitation of "0" to all TSVs to ensure that the test state is stable.

[0118] 6. Complete test of true complement:

[0119] Repeat steps 2-5, but logically invert each bit of all test stimuli (i.e., 0→1, 1→0) to form a complete true complement test sequence.

[0120] 7. Fault Identification:

[0121] Based on the response values ​​of each TSV in key rounds collected during the above process, the 6-bit response is compressed into a 4-bit fault type code through a preset negative feedback logic circuit, thereby realizing the automatic identification and diagnosis of ten types of TSV faults.

[0122] Figure 3 Test sequence examples are given for cases G=2, 3, and 4. In test mode, the stimulus is input at the operating clock frequency. Figure 3 As shown, the test data can be roughly divided into two parts: the portion marked with a bold black box consists of groups of three rounds, covering all fault types caused by crosstalk. Two adjacent rounds of test data can trigger delay faults. The remaining portion serves as a supplement, ensuring that the last group of tests also covers delay faults. This algorithm can be easily extended to meet the testing needs of different grouping schemes.

[0123] Figure 4 The test responses for ten fault types are given under the condition of G=2. For each TSV, we arranged eight rounds of test stimuli. However, as can be seen from the table, it is only necessary to collect the response values ​​of six of these rounds to uniquely determine the type of defect. As marked by the red box in the figure, the response of each fault is different from each other, and the ten defect types can be identified.

[0124] Circuit structure example:

[0125] (1) Finite state control machine

[0126] A four-state machine design is adopted:

[0127] IDLE: Waiting for the test start signal;

[0128] TEST: Enables the test data generator to apply test stimuli;

[0129] DIAG: Enables the identification module for fault diagnosis;

[0130] SHIFT_OUT: Moves the diagnostic results to an external interface.

[0131] (2) Time-division multiplexing implementation of the identification module

[0132] Each TSV group corresponds to a 4-bit shift register, which is used to store the fault code of each TSV in the group.

[0133] The negative feedback logic is a pure combinational circuit that calculates the fault type and updates the register in real time based on the current test round and response signal.

[0134] The multiplexer is controlled by a state machine, which allocates the identification logic to different groups of TSVs according to time slices, thereby realizing hardware multiplexing.

[0135] (3) Boundary register integration

[0136] Insert a 2:1 multiplexer before the DWR at the transmitting end, and switch to TPG output during testing.

[0137] At the receiving end, the DWR output is XORed with the expected TPG output to generate a fault flag signal.

[0138] The fault flag is latched in test mode and sent to the identification module in diagnostic mode.

[0139] (4) Test data generator

[0140] Test sequences are stored using small ROMs or hardwired logic, resulting in short sequence lengths and eliminating the need for complex generation logic.

[0141] It supports adjusting the number of groups G by configuring signals to adapt to different test scenarios.

[0142] The TSV fast testing method proposed in this invention shows significant advantages in both algorithm design and circuit design.

[0143] In terms of algorithm design, this invention specifically optimizes the testing algorithm and designs a general TSV testing algorithm based on true two's complement. Compared with the traditional TSV algorithm, this strategy can significantly shorten the testing time, providing a faster and lower-cost testing solution for chips. Compared with the traditional BIST scheme, the test sequence length (i.e., the number of clock cycles required for testing) of this invention can be shortened by approximately 10.2%.

[0144] In terms of circuit design, this solution innovatively uses a time-division multiplexing test and defect automatic identification circuit. By designing a testability circuit specifically for this algorithm, it can effectively save circuit area while ensuring high-efficiency, high-resolution interconnect defect identification, reducing dependence on external test equipment, and improving product reliability while saving test costs. Furthermore, compared to solutions limited to rectangular TSV arrays, this solution has a wider range of applicability, and can test TSV arrays with any arrangement.

[0145] In summary, this solution has significant advantages over existing solutions in terms of testing speed, defect resolution accuracy, utilization of external design resources, and external testing equipment requirements, and can better meet the stringent requirements of high-performance chips for the reliability of chip interconnects.

[0146] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-efficiency TSV testing and diagnosis method based on true two's complement, characterized in that, Includes the following steps: Step 1: Divide the TSV interconnect array under test into G groups, where G is an integer greater than or equal to 2; Step 2: Generate a test stimulus sequence based on the true complement test algorithm, and treat each group as the victim and the remaining groups as the attackers in turn; Step 3: Apply a first stimulus vector to the victim group and a second stimulus vector to the attacker group; the first stimulus vector is "001" and the second stimulus vector is "010"; Step 4: Collect the response signals of each TSV in multiple test rounds; Step 5: Compress the response signal into a fault type code using time-division multiplexing identification logic; Step 6: Repeat the above steps and invert all activation vectors to complete the full sequence test.

2. The method according to claim 1, characterized in that, The test stimulus sequence includes a three-round stimulus pattern to cover crosstalk faults, adjacent rounds of stimulus to trigger delay faults, and supplementary stimulus to ensure that the last set of tests covers delay faults.

3. The method according to claim 1, characterized in that, The fault type is encoded in 4 bits, which is obtained by compressing a 6-bit response signal through negative feedback logic. The negative feedback logic is a pure combinational logic circuit without clock and reset signals. The input signal is the current error type data and the correct / incorrect flag of the current cycle test verification. Based on the finite state machine signal, different interconnected fault type registers and test verification results are selected for calculation. The compressed diagnostic data is then fed back to the fault type register.

4. A high-efficiency TSV testing and diagnostic circuit for implementing the method of any one of claims 1-3, characterized in that, include: Finite state control machine, used to control test procedures and mode switching; A test data generator is used to store and output the test stimulus sequence; Boundary registers are used to switch data paths between functional mode and test mode, and to compare test responses; The identification module is used to realize time-division multiplexing identification and compressed storage of fault types, including a linear shift register, negative feedback logic circuit and multiplexer.

5. The circuit according to claim 4, characterized in that, The identification module supports multiplexing among G groups of TSVs, with each group of TSVs corresponding to a 4-bit linear shift register.

6. The circuit according to claim 4, characterized in that, The boundary register has a 2:1 multiplexer at the transmitting end and an XOR logic comparator at the receiving end.

7. The circuit according to claim 4, characterized in that, The test data generator uses ROM or hardwired logic to store the test sequence.

8. The circuit according to claim 4, characterized in that, The circuit has a built-in self-test structure, which does not require the intervention of external test equipment during the post-silicon testing stage.

9. The circuit according to claim 4, characterized in that, The circuit supports TSV interconnect arrays with arbitrary arrangement.

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