An ultra-high-speed FPGA logic acquisition device and a data management method thereof

Abstract

The application relates to a super-high-speed FPGA logic acquisition device and a data management method thereof. The device comprises an FPGA chip connected with two DDR memory chips and an Ethernet physical layer chip. The FPGA chip comprises a sampling logic module for capturing data to be sampled and converting the data into a fixed bit-width data stream; a ring buffer control module for ring buffering the data stream; a trigger control module for setting software triggering and hardware triggering and generating corresponding trigger signals; an acquisition main control module for linearly buffering the ring buffer data when the trigger signals are detected, generating data packets, recording ring buffer head and tail pointers, and continuously waiting for the trigger signals; and an asynchronous first-in-first-out buffer module for uploading target-length data packets in a specific data packet format to an upper computer when the data packets meet target acquisition quantity.

Description

Technical Field

[0001] This invention relates to the field of data acquisition technology, and in particular to an ultra-high-speed FPGA logic acquisition device and its data management method. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs), as a highly flexible and parallel hardware platform, are widely used in fields with extremely high requirements for real-time performance and processing speed, such as communications, signal processing, image recognition, and industrial control. With the increasing complexity of systems, high-performance logic acquisition tools are urgently needed when developing and verifying FPGA systems to accurately capture and analyze internal signals or I / O interface data. In typical applications, to troubleshoot logic errors or verify the correctness of protocol execution, developers usually rely on inserting debug logic, using on-chip logic analyzers (such as Xilinx ILA), or observing through external logic analysis devices. However, these traditional methods have gradually shown significant limitations when facing scenarios with high speed, large data volumes, and complex logic paths.

[0003] With the rapid development of electronic technology, data transmission rates have experienced explosive growth. Taking FPGA applications in 5G communication base stations as an example, their data processing rates have increased from hundreds of megabits per second in the early days to several gigabits per second or even higher. Traditional FPGA logic acquisition devices have gradually revealed many shortcomings when faced with such high-speed data deluges. In terms of acquisition speed, traditional acquisition devices, limited by hardware architecture and caching mechanisms, struggle to keep up with the speed of data generation, leading to frequent data loss. Regarding data caching capabilities, a single caching method cannot simultaneously capture complete data before and after the trigger point, resulting in missing key data segments and severely impacting the accuracy and completeness of subsequent data analysis. On the other hand, most existing acquisition tools employ linear caching, which can only record data after the trigger point and cannot effectively cover key historical information before the trigger, severely limiting problem localization and timing tracing. Furthermore, during high-speed acquisition, cache bandwidth, trigger response mechanisms, and data transmission efficiency become bottlenecks restricting acquisition performance. Especially in scenarios with multiple trigger sources and high-speed burst data streams, acquisition devices need flexible trigger logic support and high-bandwidth caching structures to achieve complete and continuous data recording.

[0004] Furthermore, while some acquisition systems support remote data interaction, they often rely on highly complex protocols like TCP, making it difficult to balance reliability and transmission efficiency in low-latency, high-throughput scenarios. Although Ethernet-based UDP data transmission offers high performance, its inherent unreliability makes it highly susceptible to packet loss during transmission, leading to data gaps and analytical distortion. The lack of effective retransmission mechanisms and packet reassembly logic severely impacts data availability and the practical value of the acquisition system. Simultaneously, with the continuous expansion of FPGA data path width, traditional acquisition devices face challenges in bit width configuration and data parsing toolchain compatibility, making it difficult to meet users' requirements for flexibility, scalability, and high-resolution sampling in different application scenarios.

[0005] Therefore, there is an urgent need for an FPGA logic acquisition system that features a high-bandwidth cache structure, supports pre-triggered acquisition, is compatible with multi-source triggering logic, has a highly reliable data interaction mechanism, and can adapt to variable bit width requirements, in order to meet the multiple requirements of modern high-performance digital systems for logic observability, debugging accuracy, and acquisition efficiency. Summary of the Invention

[0006] To address the problems existing in the prior art, the present invention aims to provide an ultra-high-speed FPGA logic acquisition device and its data management method, which features a flexible pre-trigger function, an efficient multi-trigger data storage management mechanism, and a reliable data transmission scheme based on the UDP protocol.

[0007] To achieve the above objectives, the present invention provides the following solution: An ultra-high-speed FPGA logic acquisition device includes: an FPGA chip, wherein the FPGA chip is connected to two DDR memory chips and an Ethernet physical layer chip through a DDR high-speed interface and an RGMII interface, respectively; The FPGA chip includes: The sampling logic module is used to capture the data to be sampled and convert it into a data stream of fixed bit width; A ring buffer control module is used to perform ring buffering of the data stream using a ring buffer controller; The trigger control module is used to set software triggers and hardware triggers, and generate corresponding trigger signals; The main control module of the data collector is used to transfer the circular buffer data to the linear buffer controller for linear buffering when the trigger signal is detected, generate data packets, record the head and tail pointers of the circular buffer, and continue to wait for the trigger signal. An asynchronous first-in-first-out (FIFO) buffer module is used to notify the host computer via an Ethernet communicator that the target number of data packets has been collected when the data packets meet the target collection quantity. The module then uploads data packets of the target length to the host computer in a specific data packet format. During the upload process, the data packets are accompanied by an index value.

[0008] Optionally, the ring buffer control module includes: A ring cache control unit is used to perform ring cache on the data stream using the ring cache controller. The ring cache adopts a circular overwrite write mechanism, forming a ring structure through an address pointer counter to continuously write to the data stream.

[0009] Optionally, the address pointer in the address pointer counter includes a cache head pointer and a cache tail pointer. When the sampling logic module has not started collecting data, the cache head pointer and the cache tail pointer point to the same address. When the sampling logic module starts collecting data, pre-caching is performed first, that is, the cache head pointer starts to move. When the pre-caching ratio is reached, the cache tail pointer starts to move synchronously with the cache head pointer, thereby continuously overwriting early data to perform a constant-length sliding window buffer.

[0010] Optionally, setting the pre-cache ratio includes: defining the pre-cache ratio as the proportion of the total cache length used to record data before the trigger point, that is, when the trigger signal is detected, the cache tail pointer immediately stops moving, the cache head pointer continues to move, and then the remaining proportion of data continues to be collected and written.

[0011] Optionally, the trigger control module includes: The trigger control unit is used to set the software trigger and the hardware trigger, and generate corresponding trigger signals; the software trigger is obtained by the host computer sending instructions via Ethernet, and the hardware trigger is obtained by detecting level changes or edge changes of multiple configurable trigger source signals; The configurable trigger source signal includes: a plurality of signals to be triggered, which are combinations of logical AND, OR, and logical OR operations.

[0012] Optionally, the main control module of the data collector includes: The main control unit of the collector is used to transfer the circular buffer data to the linear buffer controller for linear buffering when the trigger signal is detected, generate the data packet, record and count the current buffer head and tail pointers, and update the current buffer tail pointer to the current value of the buffer head pointer, roll back the pre-buffer length value, and continue to wait for the trigger signal.

[0013] Optionally, the linear cache of the linear cache controller is written in an address incrementing manner. If multiple trigger signals are detected during the acquisition process of the sampling logic module, it is determined whether there is time or address overlap between the data segments. If there is no time or address overlap between the data segments, a special identifier data frame is inserted between the non-overlapping data segments for the host computer to distinguish different trigger data. If there is time or address overlap between the data segments, the overlapping data segments are merged.

[0014] Optionally, the specific data packet format includes: a dedicated identification field, used to exclude data packets not collected by the sampling logic module in the Ethernet; The dedicated identification fields include: packet header, command, length, data payload, and packet trailer; The data payload includes: the index field of the target byte and the data field of the target byte.

[0015] To achieve the above objectives, the present invention also provides a data management method for an ultra-high-speed FPGA logic acquisition device, comprising: Acquire an FPGA logic acquisition device and configure the parameters of the FPGA logic acquisition device; the parameter configuration includes: data bit width, trigger condition and pre-buffer ratio. The configured FPGA logic acquisition device is used to capture the data to be sampled, and circular and linear buffers are used for buffering. When the target number of data to be collected is met, the data in the linear buffer is converted into data packets and an incrementing index value is appended. The packets are then sent to the host computer via the UDP protocol. The host computer verifies the continuity of the index value. If any data packets are missing, a retransmission request is sent until all data packets are complete. The missing data packets are reassembled according to the index value to form a complete data stream, and the complete data stream is stored in a hard disk file.

[0016] The beneficial effects of this invention are as follows: Ultra-high-speed data acquisition: The high bandwidth of the DDR memory in this invention endows the data acquisition unit with powerful data throughput capabilities, enabling it to achieve ultra-high-speed data acquisition and easily meet the stringent requirements of high-speed data acquisition scenarios. Whether in 5G communication base station testing scenarios with extremely high data transmission rate requirements, or in cloud computing scenarios for real-time big data processing, it can complete data acquisition tasks with ease, providing a solid data foundation for the efficient operation of the system.

[0017] Flexible caching methods: This invention employs a collaborative working mode of circular and linear caching. The circular cache ensures complete data acquisition before and after the trigger point, guaranteeing no critical data is missed; the linear cache's ordered data storage method greatly improves the standardization of data storage and the convenience of subsequent processing. In data acquisition and analysis scenarios on industrial automated production lines, this flexible caching method can accurately record key data changes during the production process, providing strong support for production optimization.

[0018] Diverse Triggering Methods: The dual support for software and hardware triggering, along with a rich array of hardware trigger source configuration options, gives the data acquisition unit extremely high flexibility in triggering methods. Whether it's an intelligent monitoring system requiring remote software control or a real-time system that responds in real time to changes in hardware signals, the data acquisition unit can provide precise triggering mechanisms according to the needs of different scenarios, meeting diverse application requirements.

[0019] Reliable data transmission: This invention adopts an Ethernet UDP transmission scheme and improves the packet loss management mechanism to ensure data integrity under UDP transmission. Compared with complex communication transmission mechanisms, it has high flexibility, high bandwidth, low complexity and low cost, effectively ensuring data transmission efficiency.

[0020] Dedicated Data Packet Format: The dedicated data packet format of this invention effectively excludes packets from other non-collector interactions in the Ethernet network, greatly improving the accuracy of data exchange. In complex IoT data transmission environments, it ensures that data exchange between the collector and the host computer is undisturbed and proceeds stably and reliably.

[0021] Compatible with mainstream analysis tools, this invention can improve the visualization and post-processing efficiency of collected data, supports data widths of up to thousands of bits, and is suitable for data capture tasks in large-scale parallel systems. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a hardware architecture diagram of an ultra-high-speed FPGA logic acquisition device according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the working principle of the ring cache structure in an embodiment of the present invention; Figure 3 This is a structural diagram of the data packet format based on the UDP protocol in an embodiment of the present invention; Figure 4 This is a structural diagram of the data upload packet format based on the UDP protocol according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a trigger circuit structure that supports multi-source logic combination according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like Figure 1 As shown, this embodiment discloses an ultra-high-speed FPGA logic acquisition device, including: an FPGA chip, which is connected to two DDR memory chips and an Ethernet physical layer chip through a DDR high-speed interface and an RGMII interface, respectively; The FPGA chip includes: a sampling logic module for capturing data to be sampled and converting it into a fixed-width data stream; a ring buffer control module for using a ring buffer controller to perform ring buffering of the data stream; a trigger control module for setting software and hardware triggers and generating corresponding trigger signals; a main control module for the data acquisition unit, which, when a trigger signal is detected, moves the ring buffer data to a linear buffer controller for linear buffering, generates data packets, records the head and tail pointers of the ring buffer, and continues to wait for a trigger signal; and an asynchronous first-in-first-out buffer module, which, when the data packets meet the target acquisition quantity, uses an Ethernet communicator to notify the host computer that the target acquisition quantity has been completed and uploads data packets of the target length in a specific data packet format to the host computer; during the upload process, the data packets are accompanied by index values.

[0027] Specifically, this embodiment discloses an ultra-high-speed FPGA logic acquisition device, including: a data sampling module, a dual DDR cache management module, a trigger control module, and a data processing and transmission module. The data sampling module is responsible for capturing the logic signal under test in real time according to a configurable data bit width. The dual DDR cache management module is connected to two independent DDR memories. The first DDR memory is configured as a ring cache to support temporary high-speed data writing and pre-triggering functions, while the second DDR memory serves as a linear cache for the final processing and storage of data after triggering. The trigger control module generates the trigger signal for data acquisition. It can not only receive and execute software trigger instructions from the host computer but also monitor the changing edges of one or more hardware trigger source signals to achieve hardware triggering. When multiple hardware trigger sources are configured, the final trigger signal can be generated through combined operations of AND and OR logic. The data processing and transmission module responds to the trigger signal and, according to the user-preset pre-caching ratio, completes the acquisition of a complete data block containing data before and after the trigger point in the ring cache. The data block is then transferred and written to the linear cache. In managing the linear cache, this module can effectively handle multiple triggered events. If the data from two events do not overlap in time, special marker data is filled between the data segments. If there is overlap, the data is merged and stored to ensure temporal continuity. Finally, the module packages the data in the linear cache and sends it to the host computer via Ethernet interface using the UDP protocol. To ensure communication reliability, this invention designs a specific data packet format and a set of acknowledgment and retransmission mechanisms. By attaching a unique index to the data packet, the host computer verifies the index continuity and actively requests the collector to retransmit single packets or batches when missing data is detected, thereby ensuring the integrity of the data stream.

[0028] In one embodiment, the present invention provides an ultra-high-speed FPGA logic acquisition device, the hardware structure of which mainly includes acquisition logic integrated inside the FPGA chip, a DDR memory chip (DDR RAM) and an Ethernet physical layer chip (ETH PHY) outside the FPGA chip. The acquisition logic integrated inside the FPGA includes: an acquisition main control module (DAQ_CTRL), a ring buffer controller (RingBuf), a linear buffer controller (LineBuf), a trigger control module (DAQ_Trigger), an Ethernet communication module (ETH), a sampling logic module (DAQ_Sampling), and an asynchronous first-in-first-out buffer (AsyncFIFO).

[0029] The FPGA chip acts as the core controller, coordinating data flow and logic control between modules. Two DDR memory chips are connected to the FPGA via a high-speed DDR interface. The Ethernet physical layer chip is connected to the FPGA via an RGMII interface. The ring cache controller and linear cache controller share the same internal structure, including a read / write control unit (DDR_RDWR), an asynchronous FIFO buffer, and a DDR controller IP core (DDR IP). The read / write control unit controls data reading and writing to the DDR memory, the asynchronous FIFO buffer is used for temporary storage of write data, and the DDR controller IP core interacts with the DDR memory chips to control their interface. When data needs to be written, the read / write control unit first allocates the data to the asynchronous FIFO buffer, then waits for the DDR memory to become idle before writing the data from the asynchronous FIFO buffer to the DDR controller IP core, and then further writing it to the DDR memory. When data needs to be read from the DDR memory, the DDR controller IP core is directly controlled to read the data from the DDR memory and output it directly. In a circular cache, the write address pointer increments during data writing, returns to 0 when the maximum address value is reached, and then continues incrementing. Similarly, during data reading, the address pointer increments, returns to 0 when the set address value is reached, and then continues incrementing. In contrast, the linear cache's read and write addresses start from 0, and the address pointer increments during read and write operations, stopping when the set address value is reached. The read and write address pointer maintenance for both the circular and linear caches is handled by their respective read and write control units. The capacities of the two DDR memories are adjustable. In the embodiment provided by this invention, the circular cache size is set to 4 GByte, and the linear cache size is set to 8 GByte. Larger capacities allow for larger data acquisition lengths, supporting acquisition throughput rates of up to 12 GB / s and above.

[0030] like Figure 2As shown, the circular buffer employs a cyclic overwrite write mechanism, forming a ring structure through an address pointer counter to continuously write collected data. The address pointers are designed as a head pointer and a tail pointer. Before collection begins, both point to the same address. Upon start-up, pre-buffering occurs, the head pointer moves, and when the pre-buffering ratio is reached, the tail pointer moves synchronously with the head pointer. The collector continuously overwrites the oldest data, achieving a constant-length sliding window buffer. The collector supports setting the pre-buffering ratio P, defined as the proportion of the total buffer length used to record data before the trigger point. P ranges from 0% to 100%. Once a trigger event is detected, the tail pointer immediately stops moving, while the head pointer continues moving, subsequently collecting and writing the remaining proportion (1-P) of data. After collection is complete, the collector's main controller records and counts the current head and tail pointers, and simultaneously initiates the data transfer from the circular buffer to the linear buffer. Notably, at this point, the circular buffer tail pointer is updated to the current value of the head pointer, reverting to the pre-buffering length, and continues the operation of waiting for triggers. This ensures that no data packets that meet the triggering conditions are missed, thus ensuring the completeness of the data collection.

[0031] The linear cache data structure uses an incrementing address starting from 0 for writing. If multiple trigger events occur during data acquisition, the system determines whether there is time or address overlap between the data segments. For non-overlapping data segments, special identifier data frames (such as continuous alternating binary 0s and 1s) are inserted between them for the host computer to distinguish different trigger data. If data segments overlap, the system merges the overlapping areas to ensure that the same data is not stored repeatedly. The linear cache features high integrity and a clear read order, facilitating subsequent transmission and parsing.

[0032] like Figure 3 As shown, this invention designs a dedicated UDP packet format. This format includes a header (a fixed two-byte hexadecimal data: 0x4C55), a command field (two bytes), a length field (two bytes), a payload field (the length is the byte length specified in the length field), and a trailer (a fixed two-byte hexadecimal data: 0x5A45). All packets interacting with the collector conform to this format, avoiding interference from other types of packets in Ethernet. Here, the data upload packet format is taken as an example, such as... Figure 4As shown, the packet format described above has been extended. The Payload field contains two parts: a 4-byte index value (Index) and a 1408-byte data field (Data). The index field is addressed according to the address of the linear buffer, and the 1408 bytes correspond to the 1 in the index field. During data upload, the host computer reassembles the data based on the address of the data corresponding to the index. If packet loss occurs during UDP transmission, the host computer initiates a retransmission request based on the missing index number, and the collector retransmits the specified data packet after responding. If the number of consecutive packet losses exceeds a threshold, the host computer will request batch retransmission to improve efficiency. Finally, the host computer reassembles the data packets according to the index order, removes duplicates, fills in missing data, and stores the valid data in the hard disk file.

[0033] like Figure 5 As shown, the trigger control module supports multiple independent hardware trigger source inputs, such as those from internal FPGA logic units, external I / O pins, voltage comparators, etc. Each trigger source can be configured with valid level, rising edge, or falling edge detection. Multiple trigger sources are combined using an internal logic combiner to perform AND or OR operations to obtain the final trigger signal. This trigger logic can be configured via registers, allowing users to flexibly define trigger conditions according to actual applications. Here, cfg_trigval represents the trigger level setting, cfg_andor indicates the AND or OR operation between trigger sources, cfg_trigen is the trigger source enable configuration, trig_src is the connected hardware trigger signal, and trig_vld is the output trigger pulse signal.

[0034] The data acquisition unit of this invention has a configurable bit width, supporting expansion from 32-bit and 64-bit to 1024-bit or even higher, adapting to the data acquisition requirements of high-speed parallel signal buses. The system supports remote communication using a standard Ethernet interface, and the data is compatible with mainstream analysis software such as MATLAB and RTL simulation tools, enabling various analysis operations such as waveform viewing, protocol parsing, and anomaly localization.

[0035] Thanks to its high-bandwidth DDR cache design, local real-time trigger response mechanism, and highly reliable UDP data management strategy, the logic acquisition unit provided by this invention has the technical advantages of high speed, completeness, reconfigurability, and easy analysis, and is particularly suitable for scenarios such as debugging complex SOC systems, verifying communication protocols, and acquiring high-speed data links.

[0036] This invention also provides a data management method for an ultra-high-speed FPGA logic acquisition device, comprising: acquiring the FPGA logic acquisition device and configuring its parameters; the parameter configuration includes: data bit width, trigger conditions, and pre-buffering ratio; using the configured FPGA logic acquisition device to capture data to be sampled, and performing circular buffering and linear buffering; when the target acquisition quantity is met, converting the data in the linear buffer into data packets and attaching an incrementing index value, and sending them to the host computer via UDP protocol; the host computer verifies the continuity of the index values, and if any data packets are missing, sends a retransmission request until all data packets are complete; reassembling the data packets without missing values ​​according to the index values ​​to form a complete data stream, and storing the complete data stream in a hard disk file.

[0037] Specifically, this invention also provides a data management method for an ultra-high-speed FPGA logic acquisition device. This method begins with the host computer configuring parameters for the acquisition device, including data bit width, trigger conditions, and pre-buffering ratio. Subsequently, the system enters a ready-to-trigger state, continuously writing acquired data into a circular buffer. Once the trigger condition is met, the system accurately captures a complete data block before and after the trigger point according to the preset pre-buffering ratio. This data block is then transferred from the circular buffer to a linear buffer and stored in ascending order of address. Next, the data in the linear buffer is packaged and appended with an ascending index, then sent to the host computer via the UDP protocol. The host computer receiving end is responsible for verifying the continuity of the index and initiating retransmission requests for any missing data packets until all data packets are correctly received. Finally, the host computer reassembles the data packets according to the index, forming a complete data stream without errors or omissions, and stores it in a hard disk file for subsequent in-depth analysis using MATLAB or RTL simulation tools.

[0038] In one embodiment, the system first connects to the FPGA board where the data acquisition unit is located via Ethernet and performs system initialization, configuring parameters such as bit width, trigger conditions, trigger acquisition quantity, and pre-buffer ratio. Then, it enters the acquisition state, continuously acquiring and writing data to the circular buffer. When a trigger signal is detected, the head and tail pointers of the circular buffer are immediately recorded, and the data is moved to the linear buffer while waiting for another trigger signal. When the acquired data packets meet the trigger acquisition quantity, the host computer is notified that acquisition is complete, and the host computer initiates the data upload process. During the upload process, the host computer uploads data of a specified length from the linear buffer according to the user settings, i.e., uploads data packets of fixed length. An index value is attached during upload, and the host computer performs data reassembly and retransmission operations based on the index value, finally writing the data to the hard drive. Throughout the entire process, data acquisition is fully automatically controlled by the internal logic of the FPGA, exhibiting high real-time performance, while data upload is completed jointly by the data acquisition unit and the host computer.

[0039] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A high-speed FPGA logic acquisition device, characterized in that, include: The FPGA chip is connected to two DDR memory chips and an Ethernet physical layer chip via a DDR high-speed interface and an RGMII interface, respectively. The FPGA chip includes: The sampling logic module is used to capture the data to be sampled and convert it into a data stream of fixed bit width; A ring buffer control module is used to perform ring buffering of the data stream using a ring buffer controller; The trigger control module is used to set software triggers and hardware triggers, and generate corresponding trigger signals; The main control module of the data collector is used to identify the software trigger conditions and detect the hardware trigger conditions of the host computer. When the trigger signal is detected, the circular buffer data is transferred to the linear buffer controller for linear buffering, a data packet is generated, and the head and tail pointers of the circular buffer are recorded. At the same time, it continues to wait for the trigger signal. An asynchronous first-in-first-out (FIFO) buffer module is used to facilitate data interaction between the main control module of the data collector and the Ethernet network. When the data packet meets the target collection quantity, the main control module of the data collector buffers the data packet into the asynchronous FIFO buffer and notifies the host computer through the Ethernet communicator that the target collection quantity has been completed. The data packet of the target length is then uploaded to the host computer in a specific data packet format. During the upload process, the data packet is accompanied by an index value.

2. The ultra-high-speed FPGA logic acquisition device according to claim 1, characterized in that, The ring cache control module includes: A ring cache control unit is used to perform ring cache on the data stream using the ring cache controller. The ring cache adopts a circular overwrite write mechanism, forming a ring structure through an address pointer counter to continuously write to the data stream.

3. The ultra-high-speed FPGA logic acquisition device according to claim 2, characterized in that, The address pointer counter includes a cache head pointer and a cache tail pointer. When the sampling logic module has not started collecting data, the cache head pointer and the cache tail pointer point to the same address. When the sampling logic module starts collecting data, pre-caching is performed first, that is, the cache head pointer starts to move. When the pre-caching ratio is reached, the cache tail pointer starts to move synchronously with the cache head pointer, thereby continuously overwriting early data to perform a constant-length sliding window buffer.

4. The ultra-high-speed FPGA logic acquisition device according to claim 3, characterized in that, Setting the pre-cache ratio includes defining the pre-cache ratio as the proportion of the total cache length used to record data before the trigger point. That is, when the trigger signal is detected, the cache tail pointer immediately stops moving, the cache head pointer continues to move, and then the remaining proportion of data continues to be collected and written.

5. The ultra-high-speed FPGA logic acquisition device according to claim 1, characterized in that, The trigger control module includes: The trigger control unit is used to set the software trigger and the hardware trigger, and generate corresponding trigger signals; the software trigger is obtained by the host computer sending instructions via Ethernet, and the hardware trigger is obtained by detecting level changes or edge changes of multiple configurable trigger source signals; The configurable trigger source signal includes: a plurality of signals to be triggered, which are combinations of logical AND, OR, and logical OR operations.

6. The ultra-high-speed FPGA logic acquisition device according to claim 1, characterized in that, The main control module of the data collector includes: The main control unit of the collector is used to transfer the circular buffer data to the linear buffer controller for linear buffering when the trigger signal is detected, generate the data packet, record and count the current buffer head and tail pointers, and update the current buffer tail pointer to the current value of the buffer head pointer, roll back the pre-buffer length value, and continue to wait for the trigger signal.

7. The ultra-high-speed FPGA logic acquisition device according to claim 6, characterized in that, The linear cache controller writes to the linear cache in an address incrementing manner. If multiple trigger signals are detected during the acquisition process of the sampling logic module, it is determined whether there is time or address overlap between the data segments. If there is no time or address overlap between the data segments, a special identifier data frame is inserted between the non-overlapping data segments for the host computer to distinguish different trigger data. If there is time or address overlap between the data segments, the overlapping data segments are merged.

8. The ultra-high-speed FPGA logic acquisition device according to claim 1, characterized in that, The specific data packet format includes: a dedicated identification field, used to exclude data packets not collected by the sampling logic module in the Ethernet; The dedicated identification fields include: packet header, command, length, data payload, and packet trailer; The data payload includes: the index field of the target byte and the data field of the target byte.

9. A data management method for an ultra-high-speed FPGA logic acquisition device implemented according to any one of claims 1-8, characterized in that, include: Obtain the FPGA logic acquisition device and configure its parameters. The parameter configuration includes: data bit width, trigger condition, and pre-buffer ratio; The configured FPGA logic acquisition device is used to capture the data to be sampled, and circular and linear buffers are used for buffering. When the target number of data to be collected is met, the data in the linear buffer is converted into data packets and an incrementing index value is appended. The packets are then sent to the host computer via the UDP protocol. The host computer verifies the continuity of the index value. If any data packets are missing, a retransmission request is sent until all data packets are complete. The missing data packets are reassembled according to the index value to form a complete data stream, and the complete data stream is stored in a hard disk file.

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