Access processing method and chip system

Abstract

The embodiment of the application is suitable for the chip technical field, and provides an access processing method and a chip system. The method is applied to a chip system, the chip system comprises a core particle and a plurality of storage units, at least one transmission channel is arranged between the core particle and each storage unit, and the method comprises the following steps: monitoring a fault condition of the storage unit; in the case that the storage unit has a fault, determining information of available storage units, the information of the available storage units comprising the number of available storage units; in the case that an access request is received, selectively adjusting a first interleaving parameter based on the access request and the information of the available storage units, and performing first interleaving conversion according to the first interleaving parameter to obtain a target memory address; and transmitting the access request to a target storage unit through a corresponding transmission channel according to the target memory address. The embodiment of the application can ensure that the chip system can still be used in the case of partial failure, thereby improving the yield and availability of the chip system.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an access processing method and a chip system. Background Technology

[0002] As chip system scale continues to expand and applications such as artificial intelligence and high-performance computing become more widespread, the storage architecture within chips is gradually evolving from the traditional single storage unit model to a complex structure with multiple storage units and multi-channel parallel access.

[0003] Due to the complexity of chip manufacturing processes, many factors can cause memory cells or corresponding access channels to fail. Current technologies often employ a Partial Good (PBO) approach, typically involving redundant backup memory cells / channels and detection mechanisms. When a fault is detected, the backup memory cell / channel is used as a replacement. This approach not only increases the chip's material cost but also places higher demands on the chip manufacturing process as the number of cells increases. Furthermore, the redundant backup cells can also fail. If the redundant backup memory cell fails again, the entire chip system may malfunction, rendering the chip unusable.

[0004] There is an urgent need for a fault handling mechanism that allows chips to still be used even when they are partially faulty, thereby improving the yield and availability of chip systems. Summary of the Invention

[0005] In view of this, embodiments of this application provide an access processing method and a chip system, which enable the chip system to still be used in the event of partial failure, thereby improving the yield and availability of the chip system.

[0006] A first aspect of this application provides an access processing method applied to a chip system, the chip system including a die and a plurality of memory cells, wherein at least one transmission channel is provided between the die and each memory cell, the method comprising: Monitor storage unit failures; In the event of a storage unit failure, information on available storage units can be determined, including the number of available storage units. Upon receiving an access request, the first interleaving parameters are selectively adjusted based on the access request and information about available storage units, and a first interleaving transformation is performed according to the first interleaving parameters to obtain the target memory address. The access request is transmitted to the target storage unit through the corresponding transmission channel based on the target memory address.

[0007] In some implementations of the first aspect, the first interleaving parameter includes the number of available storage units and the storage unit identifier; The first interleaving transformation is performed based on the first interleaving parameters to obtain the target memory address, including: Extract the address information of the access request; The first interleaving transformation is performed based on the address information and the number of available storage units to obtain the target memory address; The method also includes: The target memory unit is determined based on the target memory address and the memory unit identifier.

[0008] In some implementations of the first aspect, the storage cell identifier is generated in an incrementing manner before a storage cell fails; the target memory address includes the target memory identifier; determining the target storage cell based on the target memory address and the storage cell identifier includes: The identifiers of each storage unit are sorted in ascending order to obtain the first sorting information; The first correction offset corresponding to each storage cell identifier is determined according to the size of each storage cell identifier and the order of the storage cell identifiers in the first sorting information. The target storage unit is determined based on the storage unit identifier, the first correction offset, and the target memory identifier; The difference between the memory cell identifier corresponding to the target memory cell and the first correction offset is equal to the target memory identifier.

[0009] In some implementations of the first aspect, the target memory address includes the target memory identifier; Determining the target memory unit based on the target memory address and the memory unit identifier includes: Update the storage cell identifier in the first interleaving parameter in an incremental manner; The target storage unit is determined by identifying the available storage unit whose updated storage unit identifier matches the target memory identifier.

[0010] In some implementations of the first aspect, multiple parallel transmission channels are included between the die and one or more memory cells; the method further includes: Monitor transmission channel for faults; In the event of a transmission channel failure, determine the information of the available transmission channels between the target storage unit and the chip corresponding to the access request. The information of the available transmission channels includes the number of available transmission channels. The second interleaving parameters are selectively adjusted based on the information of the available transmission channels to perform the second interleaving transformation and determine the target transmission channel for the access request. The access request is transmitted to the target storage unit according to the target transmission channel.

[0011] In some implementations of the first aspect, the transmission channel includes a memory channel and an interconnect channel, where the memory channel is the channel for accessing storage units and the interconnect channel is the channel between chips.

[0012] In some implementations of the first aspect, the chip system includes a master chip and slave chips. The master chip is connected to multiple interconnected master memory cells, and the slave chips are connected to multiple fully interconnected slave memory cells. Each slave chip is connected to the master chip through multiple interconnect channels. The method further includes: For a slave chip with a faulty connected slave storage unit, perform the following steps: Determine the total available bandwidth from the storage units, the number of available interconnect channels, and the interconnect channel bandwidth of a single interconnect channel; The expected number of interconnect channels is determined based on the total available bandwidth from storage units and the interconnect channel bandwidth. If the number of available interconnect channels does not match the expected number of interconnect channels, some interconnect channels will be disabled based on the expected number of interconnect channels.

[0013] In some implementations of the first aspect, the chip system includes a master chip and slave chips. The master chip is connected to multiple interconnected master memory cells, and the slave chips are connected to multiple fully interconnected slave memory cells. Each slave chip is connected to the master chip through multiple interconnect channels. The method further includes: Determine the number of interconnect channels corresponding to the total bandwidth of different storage units; Generate first mapping relationship information based on the total bandwidth of the corresponding storage units and the number of interconnect channels; For a slave chip that has failed in its storage cell, perform the following steps: Determine the total available bandwidth from the storage units and the number of available interconnect channels; Based on the total available bandwidth from the storage units and the first mapping relationship information, determine the expected number of interconnect channels; If the number of available interconnect channels does not match the expected number of interconnect channels, some interconnect channels will be disabled based on the expected number of interconnect channels.

[0014] In some implementations of the first aspect, the method also includes: Determine the load status of the chip system; When the load condition meets the preset threshold and the expected number of interconnect channels corresponding to each slave chip is inconsistent, determine the minimum value among the expected number of interconnect channels; The available interconnect channels for each slave core are determined according to the minimum expected number of interconnect channels, so that the number of available interconnect channels for each slave core is the same.

[0015] In some implementations of the first aspect, before performing a first interleaving transformation based on the first interleaving parameters to obtain the target memory address, the method further includes: Determine the business type of the access request; Determine the set of storage units to be interleaved corresponding to the business type; the set of storage units to be interleaved includes one of the global storage unit set and the local storage unit set. The first interleaving parameters are determined according to the set of memory cells to be interleaved.

[0016] A second aspect of the present application provides a chip system including a chip, a plurality of memory cells, and a monitoring unit, wherein at least one transmission channel is provided between the chip and each memory cell; The monitoring unit is configured to: monitor the failure status of storage units; and, in the event of a storage unit failure, determine the information of available storage units, including the number of available storage units. The chip is configured to, upon receiving an access request, selectively adjust the first interleaving parameters based on the access request and information about available storage units, and perform a first interleaving transformation based on the first interleaving parameters to obtain the target memory address; and transmit the access request to the target storage unit through the corresponding transmission channel based on the target memory address.

[0017] A third aspect of this application provides a computer program product, including a computer program that, when run, causes the access processing method as described in the first aspect above to be executed.

[0018] Compared with the prior art, the embodiments of this application have the following beneficial effects: This application embodiment monitors the fault status of the memory cells. When a memory cell is faulty, it determines information about the number of available memory cells. Upon receiving an access request, it selectively adjusts the first interleaving parameters based on the access request and the available memory cell information, and performs a first interleaving transformation according to the first interleaving parameters to obtain the target memory address. The access request is then transmitted to the target memory cell through the corresponding transmission channel based on the target memory address. This allows for selective adjustment of the first interleaving parameters based on the memory cell corresponding to the access request and the faulty memory cell, ensuring that the first interleaving parameters match the memory cell corresponding to the access request, thus eliminating the influence of the faulty memory cell. The target memory address determined by the first interleaving parameter and the first interleaving transformation can be used to determine the target memory address. The target memory address is an available memory address that corresponds to the access request. Then, the access request is transmitted to the target memory address through the corresponding transmission channel. This allows the chip system to be used without setting up redundant memory addresses or replacing faulty memory addresses. This avoids using a faulty memory address that corresponds to the access request as the target memory address, ensuring the normal operation of the chip system and improving its yield and availability. For chip systems with redundant memory addresses, when the redundant memory addresses also fail or the number of faulty memory addresses exceeds the number of available redundant memory addresses, the solution provided in this application can still be used to maintain the chip system's operation, thereby improving the chip system's yield and availability. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the architecture of a chip system provided in an embodiment of this application; Figure 2 This is a schematic diagram of an access processing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of virtual unit virtual segmentation provided in an embodiment of this application; Figure 4 This is a schematic diagram of another chip system architecture provided in an embodiment of this application; Figure 5 This is a schematic diagram of another chip system architecture provided in an embodiment of this application; Figure 6 This is a schematic diagram of another access processing method provided in the embodiments of this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] It should be noted that the modules and units mentioned in this application may include one or more hardware circuits, including but not limited to: application-specific integrated circuits, digital signal processors, field-programmable gate arrays, discrete logic circuits, state machines, and any combination of the aforementioned circuits; these circuits are specifically designed, configured, and interconnected to perform one or more specific functions disclosed in this application.

[0028] Reference Figure 1 The diagram shows a schematic of a chip system provided in an embodiment of this application. The chip system includes a chip 100 and a plurality of storage units 200. At least one transmission channel 300 is provided between the chip 100 and each storage unit 200. The chip 100 can perform data reading and writing on the storage units 200.

[0029] One of the concepts of this application is that the chip 100 can continuously monitor the fault status of the memory cell 200. When a fault occurs in the memory cell 200, it can combine the received access request and the information of available memory cells to perform interleaving transformation to determine the target memory cell to receive the access request. This provides a Partial Good solution, which ensures that even if some memory cells 200 fail, access to available memory cells 200 can still be guaranteed based on the access request, without the need for redundant memory cells 200. This improves the yield and availability of the chip system and achieves balanced access among available memory cells 200. The technical solution of this application will be described below through specific embodiments.

[0030] First Embodiment Reference Figure 2 The diagram illustrates an access processing method provided in an embodiment of this application, which may specifically include the following steps: Step S21: Monitor the fault status of storage unit 200.

[0031] The chip system containing the chip can monitor each memory cell 200 according to a preset method to determine the fault status of the memory cell 200. The fault status of each memory cell 200 includes either a fault or normal operation.

[0032] The embodiments of this application do not limit the method of determining the fault status of the storage unit 200. For example, a monitoring unit (not shown in the figure, the monitoring unit can be set inside the chip or outside the chip) is set to calculate the error rate (e.g., timeout error or data check code error) of each storage unit 200 within a certain period of time. When the error rate exceeds a certain value, it is determined that the storage unit 200 is faulty. Alternatively, the power-on and power-off status of each storage unit 200 is detected. If the storage unit 200 is abnormally powered off, it is determined that the storage unit 200 is faulty.

[0033] The chip 100 can scan the fault conditions of each memory cell 200 when it is powered on or reset, and continue to monitor the fault conditions of each memory cell 200 after it is powered on, so as to determine the changes in the fault conditions of the memory cell 200 in a timely manner.

[0034] Step S22: In the event of a fault in storage unit 200, determine the information of available storage units.

[0035] The information on available storage units includes the number of available storage units.

[0036] In the event of a fault in storage unit 200, it means that some storage units 200 are unable to respond normally to the data / commands transmitted by the chip 100. In order to ensure that the chip system can work normally, it is necessary to determine that the currently normal storage units 200 are available storage units. The chip 100 interacts with the available storage units and stops interacting with the faulty storage units 200. Therefore, it is necessary to determine the information of available storage units, which may include the number of available storage units.

[0037] Step S23: Upon receiving an access request, selectively adjust the first interleaving parameters based on the access request and information about available storage units, and perform a first interleaving transformation according to the first interleaving parameters to obtain the target memory address.

[0038] The chip 100 can receive or generate access requests and needs to transmit the access requests to available storage units therein. In order to balance access to different storage units 200 to a certain extent, this embodiment of the application determines the storage unit 200 that receives the access request through interleaving. Before performing specific interleaving transformation, the first interleaving parameters need to be determined first.

[0039] In practical applications, different access requests may be processed by one of the storage units 200, rather than by any single storage unit 200 globally. Therefore, the storage unit 200 that can correspond to the access request can be determined first, and a first interleaving parameter can be pre-set for the storage units 200 that can correspond to different access requests. Then, it is determined whether there are any faults in the storage units 200 that can correspond to the access request. If one or more of the storage units 200 that can correspond to the current access request are faulty, the first interleaving parameter can be adjusted based on the information of the access request and the available storage units to match the first interleaving parameter with the available storage units that can correspond to the access request, thus eliminating the influence of the storage units 200 that can correspond to the access request. If the storage unit 200 that can correspond to the access request is not faulty, the first interleaving parameter does not need to be adjusted.

[0040] After determining the first interleaving parameters, a first interleaving transformation is performed based on the first interleaving parameters to obtain the first interleaving result. The target memory address is then determined based on the first interleaving result; the target memory address is the address of the storage unit 200 that receives the access request.

[0041] For example, a chip system has 18 memory cells 200. Access request A corresponds to 6 memory cells 200, corresponding to the first interleaving parameter P1; access request B corresponds to 12 memory cells 200, corresponding to the first interleaving parameter P2. All memory cells 200 corresponding to access request A are in normal condition, while one memory cell 200 corresponding to access request B is in fault condition. If the chip system receives access request A, it can directly use the first interleaving parameter P1 for the first interleaving transformation without adjusting P1. If the chip system receives access request B, it needs to adjust the first interleaving parameter P2 to obtain the first interleaving parameter P2', and then perform the first interleaving transformation based on the first interleaving parameter P2'.

[0042] Step S24: Based on the target memory address, transmit the access request to the target storage unit through the corresponding transmission channel 300.

[0043] The chip 100 communicates with the storage unit 200 through the transmission channel 300. The number of transmission channels 300 between each storage unit 200 and the chip 100 is not limited; there may be one or more.

[0044] The target memory address can be obtained through steps S21 to S23. The storage unit 200 corresponding to the target memory address is determined as the target storage unit. Then, the corresponding transmission channel 300 for transmitting the access request to the target storage unit is determined, and the access request is transmitted to the target storage unit through the transmission channel 300.

[0045] In this embodiment, by monitoring the fault status of the storage unit 200, when a fault exists in the storage unit 200, information about the number of available storage units is determined. Upon receiving an access request, the first interleaving parameter is selectively adjusted based on the access request and the information about available storage units, and a first interleaving transformation is performed according to the first interleaving parameter to obtain the target memory address. The access request is then transmitted to the target storage unit through the corresponding transmission channel 300 according to the target memory address. This allows for selective adjustment of the first interleaving parameter based on the storage unit 200 corresponding to the access request and the faulty storage unit 200 in the chip system, thereby enabling... When the first interleaving parameter matches the memory cell 200 corresponding to the access request, the influence of faulty memory cells 200 is eliminated. This allows the target memory cell to be determined based on the target memory address determined by the first interleaving transformation using the first interleaving parameter. The target memory cell is the available memory cell corresponding to the access request. The access request is then transmitted to the target memory cell through the corresponding transmission channel 300. This eliminates the need for redundant memory cells 200 and the need to replace faulty memory cells 200, allowing the chip to remain operational. This avoids using a faulty memory cell 200 corresponding to the access request as the target memory cell, ensuring the normal operation of the chip system and improving its yield and availability. For chip systems with redundant memory cells, even if redundant memory cells fail or the number of faulty cells exceeds the number of available redundant memory cells, the solution provided in this application can still maintain the chip system's operation, thereby improving its yield and availability. For chip systems, when some memory cells fail, this solution can reduce performance to some extent while continuing operation. If the required performance is met, the entire chip system does not need to be replaced.

[0046] In some implementations of the embodiments of this application, the first interleaving parameter includes the number of available storage units and the identifier of the storage unit; performing a first interleaving transformation based on the first interleaving parameter to obtain the target memory address includes: extracting the address information of the access request; performing a first interleaving transformation based on the address information and the number of available storage units to obtain the target memory address; the method further includes: determining the target storage unit based on the target memory address and the identifier of the storage unit.

[0047] The access request can contain address information and data information. This application can extract the address information of the access request and perform a first interleaving transformation on the address information of the access request based on the number of available storage units to obtain the target memory address. To ensure efficient processing of the address information of the access request and the target memory address at the hardware level, and to avoid information loss or conflict between the address information of the access request and the target memory address, the number of bits in the address information of the access request is the same as the number of bits in the target memory address. The number of bits in the target memory address can be the sum of the maximum capacity of a single storage unit (calculated by taking the logarithm of 2 and rounding it up; one address corresponds to 1 byte of address space, 2 cubed equals 8) and the number of storage units (calculated by taking the logarithm of 2 and rounding it up). That is, the number of bits in the target memory address = log2(C) + log2(N) N represents the number of storage units, and C represents the capacity of the largest storage unit. In this embodiment, N can be the number of available storage units.

[0048] By performing a first interleaving transformation on the address information of the access request based on the number of available storage units, the number of storage units 200 that can be corresponding to the target memory address is consistent with the number of storage units 200. This ensures balanced access between different storage units 200 and avoids the situation where the number of storage units 200 that can be corresponding to the number of available storage units exceeds the number of available storage units, which would cause the access request to be allocated to an unavailable storage unit and affect the normal operation of the chip.

[0049] For example, if the number of available storage units is 6, then any target memory address obtained through the first interleaving transformation corresponds to one of the 6 storage units 200; if the number of available storage units is 5, then any target memory address obtained through the first interleaving transformation corresponds to one of the 5 storage units 200.

[0050] As explained above, each storage unit 200 can be configured with a corresponding storage unit identifier. After obtaining the target memory address, the target storage unit that responds to the access request is determined by using the storage unit identifier contained in the information obtained after interleaving the target memory address and the first interleaving parameter.

[0051] By performing a first interleaving transformation based on address information and the number of available storage units, the target memory address is obtained. The target storage unit is then determined by combining the target memory address with the storage unit identifier in the first interleaving parameters. This achieves balanced access to the storage units 200 when there are multiple storage units 200 that can be corresponding to the access request.

[0052] In some implementations of this application, the storage unit identifier is generated in an incrementing manner before the storage unit 200 fails. Determining the target storage unit based on the target memory address and the storage unit identifier includes: sorting the storage unit identifiers in ascending order to obtain first sorting information; determining a first correction offset corresponding to each storage unit identifier based on the size of each storage unit identifier and its order in the first sorting information; determining the target storage unit based on the storage unit identifier, the first correction offset, and the target memory identifier; the difference between the storage unit identifier corresponding to the target storage unit and the first correction offset is equal to the target memory identifier.

[0053] For different access requests, the corresponding storage unit 200 can be generated in an incremental manner before the storage unit 200 fails. For example, the first storage unit identifier is "0", and each storage unit identifier is generated in increments of 1.

[0054] For example, a chip system has 18 memory cells 200. Access request A can correspond to 6 memory cells 200, so the memory cell identifiers for these 6 memory cells 200 are set to 0~5, and the first interleaving parameter P1 includes memory cell identifiers 0~5. Access request B can correspond to 12 memory cells 200, so the memory cell identifiers for these 12 memory cells 200 are set to 0~11, and the first interleaving parameter P2 includes memory cell identifiers 0~11. The 12 memory cells 200 corresponding to access request B may not include the 6 memory cells 200 corresponding to access request A, or may include at least one of the 6 memory cells 200 corresponding to access request A; neither affects the embodiments of this application. It is only necessary to set the memory cell identifiers for the memory cells 200 corresponding to the access requests in an incremental manner. For a single storage unit 200, its storage unit identifier can be determined according to the access request received by the chip system. For example, for a certain storage unit 200, if the current received access request is A, the storage unit identifier can be 1, and if the current received access request is B, the storage unit identifier can be 7.

[0055] The target memory address includes a target memory identifier. For example, the number of available storage units can be used as the interleaving number to divide the address information of the access request into first computed bits and first reserved bits (the first computed bits are used to determine the target storage unit, and the first reserved bits are used to represent a portion of the access address of the target storage unit). Then, the first computed bits are grouped according to a preset method, with each group including several bits (the target memory identifier in the target memory address includes several bits, and the number of bits in each group is the same as the number of bits in the target memory identifier). The bits of each group are converted into numerical values, and the converted numerical values ​​are summed to obtain a feature value. A modulo operation is performed on the feature value according to the interleaving number to obtain a hash value, and this hash value is used as the target memory identifier. For example: After determining the first calculation bit from the address information, the first calculation bit is grouped into 4 groups:

[0111] ,

[1111] ,

[0011] , and

[1011] . Each group is converted into a value. Taking decimal as an example, the converted values ​​of each group are 7, 15, 3, and 11, respectively. The sum of the values ​​of all groups yields a characteristic value of 36. The corresponding number of storage units is 16. Based on the modulo operation of 16 by 26, the hash value is 10. Therefore, the target memory identifier is 10 (the target memory identifier in the target memory address is 4 bits, i.e.,

[1010] ).

[0056] The first computation bit can be further divided into a first part and a second part, with the number of bits in the first part of the first computation bit matching the number of bits in each group of feature value calculations. The second part of the computation bit can participate in the feature value grouping calculation and also serve as a second reserved bit, passed through to the target memory address. The target memory address is obtained based on the target memory identifier, the second part of the first computation bit, and the first reserved bit, allowing the chip system to generate the target address efficiently and reliably, avoiding information loss or conflict between the address of the access request and the target address. By excluding the first reserved bit from calculation, continuous data can be located in different memory units as much as possible, while data stored in the same memory unit can be kept as continuous as possible. The second part of the computation bit participates in the chip system's feature value grouping calculation and also serves as part of the target memory address, adapting to various large-step access modes. High-bit flipping also allows for balanced access, significantly better than using a power of two with direct interleaving of low bits, which can lead to frequent access to the same memory unit when high bits are flipped and low bits remain unchanged.

[0057] When determining the target storage unit, the storage unit identifiers in the first interleaving parameters corresponding to the access request can be sorted in ascending order to obtain first sorting information. The order of each storage unit identifier within this first sorting information is determined based on its size. Since some storage units 200 corresponding to the current access request may be faulty, the order of the storage unit identifiers of the available storage units needs to be re-determined. For example, the order is determined sequentially starting from "0". For instance, the first sorting information is obtained by sorting four storage unit identifiers, resulting in the sorted order of storage units 200 as "0", "1", "2", and "3".

[0058] After obtaining the order corresponding to each storage cell identifier, a first correction offset is determined based on the difference between each storage cell identifier and its corresponding order. Combining the target memory identifier, storage cell identifier, and first correction offset obtained from the first interleaving, the target storage cell receiving the access request is determined. The storage cell identifier of the target storage cell - the first correction offset = the target memory identifier.

[0059] By determining the target storage unit through this implementation method, it is possible to accurately determine the currently available target storage unit that receives the access request when some storage units 200 are faulty, by using the storage unit identifier obtained before the fault occurred and the target memory address obtained by the first interleaving transformation. This avoids using the faulty storage unit 200 as the target storage unit and achieves access balance between the available storage units corresponding to the access request.

[0060] For example, if the storage unit identifiers in the first sorting information are "0", "1", "3", and "5" respectively, corresponding to the order 0, 1, 2, and 3, then the corresponding first correction offsets are 0, 0, 1, and 2. The differences in the first correction offsets of the storage unit identifiers for each storage unit 200 can be calculated sequentially as 0, 1, 2, and 3. During interleaving, the calculation is performed modulo the available quantity. For example, if 4 is used as the interleaving number, if the target memory identifier is "1", then the storage unit identifier of the target storage unit is "1"; if the target memory identifier is "3", then the storage unit identifier of the target storage unit is 3 + 2 = "5". This means that there is no need to adjust the storage unit identifiers, allowing for more flexible interleaving based on the type of access request, suitable for different request types and different fault / abnormal situations.

[0061] It should be noted that the target memory identifier mentioned above is only an example. The target memory identifier can be composed of several binary bits (or other number systems). For example, the target memory identifier mentioned above is "3", and the specific target memory identifier string can be "000011".

[0062] In practical applications, a chip system may contain storage units 200 of different capacities. The data space of a larger storage unit 200 can be virtually partitioned in parallel to obtain several smaller virtual storage units 200. Then, corresponding storage unit identifiers are generated for each virtual storage unit 200 in the manner described above, further balancing the load on different storage units 200. For example, the capacity of the smallest storage unit 200 in the chip system can be used as the partitioning unit capacity. Storage units 200 with capacities that are integer multiples of this partitioning unit capacity can be used as partitioning objects, and each partitioning object can be virtually partitioned to obtain several virtual storage units 200 with the same capacity as the partitioning unit.

[0063] For example, a chip system contains eight 4GB storage units 200 and four 12GB storage units 200. 4GB can be used as the unit of measurement. The data space of each 12GB storage unit 200 can be divided into three 4GB virtual storage units 200. A corresponding storage unit identifier is generated for each 4GB virtual storage unit 200. Storage unit identifiers are generated for the un-virtually partitioned storage units 200 and each virtual storage unit 200 in an incremental manner. This generates the corresponding first interleaving parameter, thereby maximizing the balanced access of the storage units 200.

[0064] Reference Figure 3 The illustration shows a schematic diagram of a virtual partitioning of a storage unit provided in an embodiment of this application. The data space of a 12GB storage unit 200 can be divided into three 4GB virtual storage units 200. The data spaces of the three virtual storage units 200 correspond to the data spaces of the 12GB storage unit 200 in sequence [0-4GB], [5-8GB] and [9-12GB]. The process of generating the storage unit identifier will not be described here.

[0065] In some other implementations of the first embodiment, determining the target storage unit based on the target memory address and the storage unit identifier includes: updating the storage unit identifier in the first interleaving parameters in an incremental manner; and determining the available storage unit whose updated storage unit identifier matches the target memory identifier as the target storage unit.

[0066] In some other implementations, due to the possibility of failure in some storage units 200 corresponding to the current access request, at least one storage unit identifier may be missing between any two adjacent storage unit identifiers of any size. For example, if the unit identifiers of two adjacent storage units in the first interleaving parameter are "3" and "5" respectively, then storage unit identifier "4" is missing.

[0067] To avoid mismatches between the target memory identifier in the target memory address and all memory cell identifiers in the first interleaving parameters, the memory cell identifiers in the first interleaving parameters can be updated in an incremental manner before determining the target memory cell. Then, the available memory cell whose updated memory cell identifier matches the target memory identifier can be determined as the target memory cell.

[0068] For example: There were originally 6 storage units, labeled 0 to 5. Now, the storage units corresponding to "2" and "4" are faulty. The first interleaving parameter contains 4 storage unit labels: "0", "3", "1", and "5". These 4 storage unit labels can be updated to "0", "1", "2", and "3" respectively. Since the number of available storage units in the first interleaving parameter is 4, the target memory label obtained by taking the modulus of the feature value with 4 as the interleaving number is "0", "1", "2", or "3". At this time, any target memory label can be consistent with one of the updated storage unit labels, so that the available target storage units can be accurately determined.

[0069] In this implementation, by updating the storage unit identifier in the first interleaving parameter in an incremental manner, the available storage unit whose updated storage unit identifier matches the target memory identifier is determined as the target storage unit. This ensures that the target storage unit is an available storage unit identifier and reduces the computational load of the order and first correction offset in the previous implementation. It is more suitable for cases where the access type is relatively fixed and the corresponding storage unit changes little, thus improving the speed of determining the target storage unit.

[0070] In some implementations of this application, the chip 100 and one or more storage units 200 include multiple parallel transmission channels 300; this application may also include: monitoring the failure status of the transmission channels 300; in the event of a failure of the transmission channel 300, determining the information of available transmission channels between the target storage unit corresponding to the access request and the chip 100, the information of available transmission channels including the number of available transmission channels; selectively adjusting the second interleaving parameters according to the information of available transmission channels, performing a second interleaving transformation, and determining the target transmission channel of the access request; and transmitting the access request to the target storage unit according to the target transmission channel.

[0071] like Figure 1As shown, there can be multiple parallel transmission channels 300 between the chip 100 and the storage unit 200. This application can also monitor the fault status of the multiple parallel transmission channels 300.

[0072] In the event of a failure in transmission channel 300, it indicates that some transmission channels 300 are currently transmitting data / commands. To ensure the normal operation of the chip system, it is necessary to determine the currently functioning transmission channels 300 as available transmission channels. The chip 100 interacts with the target memory unit through the available transmission channels, thereby ensuring normal access to the target memory unit. At the same time, in order to avoid frequently using the same transmission channel 300 to transmit access requests / data and to achieve load balancing of multiple parallel transmission channels 300, the embodiments of this application can first determine the information of available transmission channels, including the number of available transmission channels.

[0073] The number of parallel transmission channels 300 corresponding to different storage cells 200 may be different. For example, there are 3 parallel transmission channels 300 between the chip 100 and a certain storage cell 200, and another 3 different parallel transmission channels 300 between the chip 100 and another storage cell 200.

[0074] For each storage cell 200 and the die 100, multiple parallel transmission channels 300 can be established, and a second interleaving parameter can be pre-determined. After determining the target storage cell, it is first determined whether the transmission channel 300 corresponding to the target storage cell is faulty. If the faulty transmission channel 300 is one or more of the multiple parallel transmission channels 300 corresponding to the target storage cell, the second interleaving parameter is adjusted based on the information of the available transmission channels to match the first interleaving parameter with the available transmission channels corresponding to the target storage cell, thus eliminating the influence of the faulty transmission channel 300. If the faulty transmission channel 300 does not correspond to the target storage cell, the second interleaving parameter does not need to be adjusted, thus selectively adjusting the second interleaving parameter for different fault conditions of the transmission channels 300.

[0075] After determining the second interleaving parameters, a second interleaving transformation is performed on the second interleaving parameters to obtain the second interleaving transformation result. Based on the second interleaving result, the target transmission channel for the access request is determined, and the access request is transmitted to the target storage unit through the target transmission channel.

[0076] For example, the second interleaving result includes a target channel identifier, which is used to determine the target transmission channel. A feature value can be calculated based on the address information of the access request (or the feature value can be cached during the first interleaving transformation and directly read during the second interleaving transformation). A hash value is obtained by performing a modulo operation on this feature value according to the number of available transmission channels in the second interleaving parameters. The target channel identifier is then determined based on this hash value. The processing procedure for the second interleaving transformation can refer to the aforementioned processing procedure for the first interleaving transformation. One difference between the second and first interleaving transformations is that the interleaving number in the first interleaving transformation is the number of available storage units, while the interleaving number in the second interleaving transformation is the number of available transmission channels. This will not be elaborated further here. For example, if the feature value is 36 and the number of available transmission channels is 3, then the hash value is 0, and the target channel identifier is 0.

[0077] In this implementation, the fault status of multiple parallel transmission channels 300 between the chip 100 and the storage unit 200 can be monitored. When multiple parallel transmission channels 300 are faulty, the second interleaving parameter is adjusted, and a second interleaving transformation is performed based on the second interleaving parameter to determine the target transmission channel. This achieves load balancing of the multiple parallel transmission channels 300 between the storage unit 200 and the chip 100 while eliminating the influence of faulty available transmission channels. In some implementations of this application, the transmission channel 300 identifiers are generated in an incremental manner before a transmission channel 300 fails. The target transmission channel is determined through the following steps: sorting the transmission channel 300 identifiers in ascending order to obtain second sorting information; determining the second correction offset corresponding to each transmission channel 300 identifier according to the size of each transmission channel 300 identifier and its order in the second sorting information; determining the target transmission channel based on the transmission channel 300 identifier, the second correction offset, and the target channel identifier; the difference between the transmission channel 300 identifier corresponding to the target transmission channel and the second correction offset is equal to the target channel identifier.

[0078] In some other implementations of the first embodiment, the target transmission channel is determined by the following steps: updating the transmission channel 300 identifier in the second interleaving parameters in an incremental manner; and determining the available transmission channel whose updated transmission channel 300 identifier matches the target channel identifier as the target transmission channel.

[0079] The method of determining the target transmission channel based on the channel identifier is similar to that of determining the target storage unit based on the storage unit identifier. The specific process can be found in the description of determining the target storage unit, and will not be repeated here.

[0080] Reference Figure 4This diagram illustrates an architecture of another chip system provided in an embodiment of this application. In some implementations of this application, the transmission channel 300 includes a memory channel 310 and an interconnect channel 320. The memory channel 310 is a channel for accessing the storage unit 200, and the interconnect channel 320 is a channel between chips 100.

[0081] The transmission channel 300 may include a memory channel 310 and an interconnect channel 320. The memory channel 310 is for accessing memory, and the interconnect channel 320 is for communication between chips 100. Upon receiving an access request, the chip receiving the access request or the chip directly connected to the target memory cell can determine the target memory channel between chip 100 and the target memory cell through a second interleaving result, and then send the access request to the target memory cell through this target memory channel. For a chip system containing multiple chips 100, where interconnect channels exist between chips 100 that can transmit access requests, if there are other chips 100 between the target memory cell and the chip 100 that received the access request, the target interconnect channel for sending the access request to the chip containing the target memory cell is determined through the second interleaving result.

[0082] In this implementation, the transmission channel 300 includes a memory channel 310 for accessing the storage unit 200 and an interconnect channel 320 between chips. By determining the target transmission channel, including the target memory channel and the target interconnect channel, as described above, this embodiment can be applied to a chip system with multiple chips 100 and can achieve load balancing between the memory channel 310 and the interconnect channel 320. The second interleaving transformation includes memory channel interleaving, and the second interleaving parameters include the number of available memory channels corresponding to the memory channel interleaving and the identifier of the memory channel 310. For cases where other chips 100 exist between the target storage unit and the received access request, the second interleaving transformation also includes interconnect channel interleaving, and the second interleaving parameters also include the number of available interconnect channels corresponding to the interconnect channel interleaving and the identifier of the interconnect channel 320. For memory channel interleaving and possible interconnect channel interleaving, the steps for determining the target transmission channel described above can be followed, and will not be repeated here.

[0083] Reference Figure 5 This illustration shows an architecture diagram of another chip system provided in an embodiment of this application. In some implementations of this application, the chip system includes a master chip 110 and slave chips 120. The master chip 110 is connected to a plurality of interconnected master memory cells 210, and the slave chips 120 are connected to a plurality of fully interconnected slave memory cells 220. Each slave chip 120 is connected to the master chip 110 through a plurality of interconnect channels 320. The first embodiment may further include: For a slave chip 120 that has failed in its connected slave storage unit 220, perform the following steps: Determine the total available bandwidth of the slave storage units and the number of available interconnect channels, as well as the interconnect channel bandwidth of a single interconnect channel 320; based on the total available bandwidth of the slave storage units and the interconnect channel bandwidth, determine the expected number of interconnect channels; if the number of available interconnect channels is inconsistent with the expected number of interconnect channels, disable some interconnect channels 320 based on the expected number of interconnect channels.

[0084] The chip system includes a master chip 110 and slave chips 120, and the storage unit 200 includes a master storage unit 210 and a slave storage unit 220. Each master storage unit 210 is connected to the master chip 110 in a one-to-one manner, meaning one master storage unit 210 is connected to the master chip 110 through a memory channel 310. The slave chips 120 are connected to multiple fully interconnected slave storage units 220, meaning that each slave chip 120 is fully interconnected to multiple slave storage chips 100 through multiple parallel memory channels 310. The master chip 110 and the slave chips 120 are connected through at least one of the aforementioned interconnect channels 320.

[0085] When the target storage unit is slave storage unit 220, the slave core 120 connected to the target storage unit can receive access requests and the target memory address sent by the master core 110. For slave core 120, in order to avoid wasting bandwidth resources, the sum of the total bandwidth of available interconnect channels must not be less than the total bandwidth of available storage units.

[0086] When any number of slave storage cells 220 connected to the die 120 are faulty, the total available bandwidth of the slave storage cells decreases. In this case, some interconnect channels 320 may be disabled, but the sum of the total available bandwidth of the interconnect channels can still be maintained at a level not less than the total available bandwidth of the storage cells. The total available bandwidth of the slave storage cells can be calculated by summing the bandwidths of the individual slave storage cells 220 connected to the die 120.

[0087] Therefore, in the event of a failure in the slave memory cell 220 connected to the chip 120, the expected number of interconnect channels can be determined based on the total available slave memory cell bandwidth and the interconnect channel bandwidth (bandwidth of a single interconnect channel 320), such that the product of the expected number of interconnect channels and the interconnect channel bandwidth is not less than the total available slave memory cell bandwidth. Expected number of interconnect channels = Available total bandwidth from storage units / interconnect bandwidth , · This indicates rounding up. That is, at least the expected number of interconnect channels (320) is required to ensure that the sum of the total bandwidth of available interconnect channels is not less than the total bandwidth of available storage units. If the number of available interconnect channels does not match the expected number, it means that even disabling some interconnect channels (320) will still ensure that the sum of the total bandwidth of available interconnect channels is not less than the total bandwidth of available storage units. To reduce the data processing volume of the second interleaving transformation (interconnect channel interleaving) and improve the efficiency of determining the target interconnect channels, some interconnect channels (320) can be disabled so that the number of available interconnect channels after disabling is the expected number of interconnect channels.

[0088] For example: If there are a total of 5 interconnect channels 320 connected from core 120 and currently available, the expected number of interconnect channels is 4 based on the above calculation, which means that 1 interconnect channel 320 can be disabled.

[0089] In this implementation, if there is a fault in the slave storage unit 220 connected to the core 120, the expected number of interconnect channels that meet the total bandwidth of the available slave storage units can be determined. If the expected number of interconnect channels is inconsistent with the number of available interconnect channels, some interconnect channels 320 are disabled, thereby reducing the amount of data processing required to determine the target transmission channel and improving the efficiency of determining the target transmission channel.

[0090] In other implementations of the first embodiment, in the event of a failure in the slave memory cell 220 connected to the die 120, a portion of the interconnect channel 320 can be disabled by the following steps: For a slave chip 120 that has failed in its connected slave storage unit 220, perform the following steps: Determine the total available bandwidth of the slave storage units and the number of available interconnect channels, as well as the interconnect channel bandwidth of a single interconnect channel 320; based on the total available bandwidth of the slave storage units and the interconnect channel bandwidth, determine the number of interconnect channels to be disabled; disable a portion of the interconnect channels 320 according to the number of disabled interconnect channels.

[0091] Among them, the number of disabled interconnect channels = Number of available interconnect channels - Total available bandwidth from storage units / Interconnect channel bandwidth , · This indicates rounding down to the nearest integer.

[0092] In some implementations of the embodiments of this application, the embodiments of this application may further include: in the event of a failure of the interconnect channel 320, for the slave chips connected to the faulty interconnect channel 320, performing the following steps: determining the number of available slave storage units, the slave storage unit bandwidth of a single slave storage unit 220, the number of available interconnect channels, and the interconnect channel bandwidth of a single interconnect channel 320; determining the expected number of slave storage units based on the slave storage unit bandwidth, the number of available interconnect channels, and the interconnect channel bandwidth; and disabling some slave storage units 220 based on the expected number of slave storage units if the number of available slave storage units is inconsistent with the expected number of slave storage units.

[0093] When interconnect channel 320 fails, the sum of the available interconnect channel bandwidth may be less than the total available slave memory bandwidth, making it impossible to effectively utilize the total available slave memory bandwidth. The chip system as a whole will be in a state of high capacity but reduced bandwidth. In this case, the expected number of slave memory cells can be determined. If the number of available slave memory cells does not match the expected number, it means that some slave memory cells can be disabled. This ensures that the sum of the available interconnect channel bandwidth is not less than the total available slave memory bandwidth. Therefore, some slave memory cells can be disabled without affecting the performance of the chip system.

[0094] For example, the expected number of storage units = Number of available interconnect channels * interconnect channel bandwidth / slave memory unit bandwidth Or, the expected number of storage units = Number of available interconnect channels * interconnect channel bandwidth / slave memory unit bandwidth Since the interconnect bandwidth is not necessarily an integer multiple of the slave memory cell bandwidth, the expected number of slave memory cells can be determined by rounding up or down based on actual needs. Rounding up allows full utilization of the total interconnect bandwidth, while a portion of the total slave memory cell bandwidth remains unused; conversely, rounding down allows full utilization of the total slave memory cell bandwidth, while the total interconnect bandwidth remains unused. To maximize chip system performance, rounding up is typically used to determine the expected number of slave memory cells, i.e., the expected number of slave memory cells = Number of available interconnect channels * interconnect channel bandwidth / slave memory unit bandwidth .

[0095] For example, if a slave core 120 is connected to 6 slave memory cells 220, and this slave core 120 is connected to 3 interconnect channels 320, and the total bandwidth of the 6 slave memory cells 220 equals the total bandwidth of the 3 interconnect channels 320, and if one interconnect channel 320 fails, then the number of available interconnect channels is 2. In this case, the total bandwidth of the available interconnect channels equals the total bandwidth of the 3 slave memory cells 220. Therefore, the expected number of slave memory cells is 3. Three slave memory cells can be disabled. Based on the "weakest link" principle, the system performance is affected by the faulty interconnect channel 320. By disabling some slave memory cells, the complexity of the first interleaving can be reduced without affecting system performance.

[0096] In some implementations of this application, the chip system includes a master chip 110 and slave chips 120. The master chip 110 is connected to a plurality of interconnected master memory cells 210, and the slave chips 120 are connected to a plurality of fully interconnected slave memory cells 220. Each slave chip 120 is connected to the master chip 110 through a plurality of interconnect channels 320. This application embodiment may also include: Determine the number of interconnect channels corresponding to the total bandwidth of different slave storage units 220; generate first mapping relationship information for the corresponding total bandwidth and number of interconnect channels of slave storage units 220; For a slave chip 120 that has failed in storage cell 220, perform the following steps: Determine the total available bandwidth of the slave storage units; based on the total available bandwidth of the slave storage units and the first mapping relationship information, determine the expected number of interconnect channels; if the total number of interconnect channels 320 is inconsistent with the expected number of interconnect channels, disable some interconnect channels 320 based on the expected number of interconnect channels.

[0097] For each slave chip 120, since the total number of slave storage units 220, the total number of interconnect channels 320, the bandwidth of each slave storage unit 220, and the bandwidth of a single interconnect channel 320 are all known information, the minimum number of interconnect channels required corresponding to the total bandwidth of different slave storage units 220 can be calculated in advance, and the corresponding total bandwidth of slave storage units 220 and the number of interconnect channels can be used to generate a first mapping relationship information and store the first mapping relationship information.

[0098] In the event of a fault in any slave storage cell 220 of the chip 120, the expected number of interconnect channels can be obtained by using the number of interconnect channels corresponding to the total width of the currently available slave storage cells based on the first mapping relationship information. Then, if the total number of interconnect channels 320 is inconsistent with the expected number of interconnect channels, some interconnect channels 320 can be disabled based on the expected number of interconnect channels.

[0099] In this implementation, by determining the total available bandwidth of slave storage units and the number of interconnect channels for each slave core 120, and generating and storing first mapping relationship information, it is possible to quickly disable some interconnect channels 320 in the event of a failure in any slave storage unit 220 of the slave core 120, based on the pre-determined first mapping relationship information and the total available bandwidth of slave storage units. This reduces the amount of data processing required for interconnect channel interleaving and improves the efficiency of determining the target interconnect channel. For example, the disabled interconnect channels 320 can be changed periodically, as long as the number of available interconnect channels after disabling some is consistent with the expected number of interconnect channels. By changing the disabled interconnect channels 320 periodically, the working time among the interconnect channels 320 is balanced. This prevents situations where disabled interconnect channels 320 are idle for a long time, while non-disabled interconnect channels 320 are in working state for a long time, leading to a greater difference in the workload of the interconnect channels 320.

[0100] Similarly, in some implementations of this application, a second mapping relationship information between feature values ​​and target memory identifiers can be generated for each available storage unit quantity. After determining the available storage unit quantity and feature values, the target memory identifier is determined through the second mapping relationship information, thereby improving the processing efficiency of the first interleaving transformation. For each available transmission channel quantity, a third mapping relationship information between feature values ​​and target channel identifiers can be generated. After determining the available channel quantity and feature values, the target channel identifier is determined through the third mapping relationship information, thereby improving the processing efficiency of the second interleaving transformation.

[0101] In some implementations of this application, the chip system further includes an interconnect chip. One side of the interconnect chip is connected to the master chip 110 via an L2C channel, and the other side is connected to a slave chip 120 via one or more interconnect channels 320. The number of L2C (L2 Cache) channels is the same as the number of slave storage units 220 connected to the corresponding slave chip 120, which is beneficial for the overall bandwidth balance of the chip system. In this case, if necessary, a third interleaving transformation can be performed based on the number of L2C channels to determine the target L2C channel for transmitting access requests. The third interleaving transformation is similar to the second interleaving transformation, the main difference being that the third interleaving parameters corresponding to the third interleaving transformation include the number of available L2C channels and the L2C channel identifier. The third interleaving transformation process can be referred to the relevant description of the second interleaving transformation process, and will not be repeated here.

[0102] The L2C channel is a connection channel used to access L2C. In some implementations of this application, interconnect chips can be set in the chip system, and the number of L2C channels is the same as the number of slave memory cells 220. This reduces the bandwidth between the master chip 110 and the slave chip 120, and sets bandwidth redundancy between the slave chips 120. Even if the slave memory cell 220 connected to the slave chip 120 fails, the master chip 110 can still operate with the original bandwidth, thus improving the stability of the chip system.

[0103] The processing procedure for the second interleaving transformation can be referred to the processing procedure for the first interleaving transformation mentioned above. One of the differences between the second interleaving transformation and the first interleaving transformation is that the number of interleavings in the first interleaving transformation is the number of available storage units, while the number of interleavings in the third interleaving transformation is the number of available L2C channels. This will not be elaborated further here.

[0104] In some implementations of this application, for an interconnect chip connected via interconnect channel 320 to a slave chip with a faulty slave storage unit, the following steps are performed: determining the total available bandwidth of the slave storage unit, the number of available L2C channels, and the L2C channel bandwidth of a single L2C channel; determining the expected number of L2C channels based on the total available bandwidth of the slave storage unit and the L2C channel bandwidth; and disabling some of the L2C channels based on the expected number of L2C channels if the number of available L2C channels is inconsistent with the expected number of L2C channels.

[0105] When there is no fault in the slave storage unit 220 of the slave core 120 connected by the interconnect core through the interconnect channel 320, in order to avoid wasting bandwidth resources, the sum of the total bandwidth of the available L2C channels must not be less than the total bandwidth of the available storage units.

[0106] When any number of slave storage cells 220 in the fully interconnected core 120 are faulty, the total available bandwidth of the slave storage cells decreases. In this case, some L2C channels may be disabled, but the sum of the total bandwidth of the available L2C channels can still be maintained at a level not less than the total bandwidth of the available storage cells.

[0107] Therefore, in the event of a failure in the slave storage unit 220 connected to the chip 120, the expected number of L2C channels can be determined based on the total available slave storage unit bandwidth and the L2C channel bandwidth (bandwidth of a single L2C channel), ensuring that the product of the expected number of L2C channels and the L2C channel bandwidth is not less than the total available slave storage unit bandwidth. Expected number of L2C channels = Available total bandwidth from storage cells / L2C channel bandwidth , · This indicates rounding up. It means that at least the expected number of L2C channels are required to ensure that the sum of the total bandwidth of the available L2C channels is not less than the total bandwidth of the available storage units. If the number of available L2C channels does not match the expected number, it means that even disabling some L2C channels will still ensure that the sum of the total bandwidth of the available L2C channels is not less than the total bandwidth of the available storage units. To reduce the data processing volume of the third interleaving transformation (L2C channel interleaving) and improve the efficiency of determining the target L2C channels, some L2C channels can be disabled so that the number of available L2C channels after disabling is the expected number.

[0108] For example, among the interconnecting cores connected from core 120 via interconnecting channel 320, the total number of currently available L2C channels is 4. Based on the above calculation, the expected number of L2C channels is 3, which means that 1 L2C channel can be disabled.

[0109] In this implementation, if there is a fault in the slave storage unit 220 connected to the chip 120, the expected number of L2C channels that meet the total bandwidth of the available slave storage units can be determined. If the expected number of L2C channels is inconsistent with the number of available L2C channels, some L2C channels are disabled, thereby reducing the amount of data processing required to determine the L2C channels and improving the efficiency of determining the L2C channels.

[0110] In some implementations of this application, the method further includes: determining the number of L2C channels corresponding to different total bandwidths of slave storage units; generating fourth mapping relationship information for the corresponding total bandwidths of slave storage units and the number of L2C channels; and performing the following steps for interconnect chips connected through interconnect channel 320 to slave chips with faulty slave storage units: determining the available total bandwidth of slave storage units and the number of available L2C channels; determining the expected number of L2C channels based on the available total bandwidth of slave storage units and the fourth mapping relationship information; and disabling some of the L2C channels based on the expected number of L2C channels if the number of available L2C channels is inconsistent with the expected number of L2C channels.

[0111] In some implementations of this application, the method further includes: determining the number of L2C channels corresponding to different total bandwidths of slave storage units; generating fourth mapping relationship information for the corresponding total bandwidths of slave storage units and the number of L2C channels; and performing the following steps for interconnect chips connected through interconnect channel 320 to slave chips with faulty slave storage units: determining the available total bandwidth of slave storage units and the number of available L2C channels; determining the expected number of L2C channels based on the available total bandwidth of slave storage units and the fourth mapping relationship information; and disabling some of the L2C channels based on the expected number of L2C channels if the number of available L2C channels is inconsistent with the expected number of L2C channels.

[0112] Since the total number of slave storage units 220, the total number of L2C channels, the bandwidth of each slave storage unit 220, and the bandwidth of a single L2C channel are all known information, the minimum number of interconnect channels required corresponding to the total bandwidth of different slave storage units 220 can be calculated in advance, and the corresponding total bandwidth of slave storage units 220 and the number of interconnect channels can be used to generate a fourth mapping relationship information and store the fourth mapping relationship information.

[0113] In the event of a failure in any slave storage cell 220 of the chip 120, the expected number of L2C channels can be obtained by using the fourth mapping relationship information and the number of L2C channels corresponding to the total width of the currently available slave storage cells. Then, if the total number of L2C channels is inconsistent with the expected number of L2C channels, some L2C channels can be disabled based on the expected number of L2C channels.

[0114] It should be noted that disabling some interconnect channels 320 and disabling some L2C channels are independent of each other. You can disable only some interconnect channels 320, or only some L2C channels, or disable both some interconnect channels 320 and some L2C channels at the same time.

[0115] For example, if a slave core 120 is connected to four slave storage units 220, and the slave core 120 is connected to an interconnect core via three interconnect channels 320, and the interconnect core is connected to the master core 110 via four L2C channels, the total bandwidth of the four slave storage units 220 equals the total bandwidth of the three interconnect channels 320 equals the total bandwidth of the four L2C channels. If one of the four slave storage units 220 fails, the interconnect channel 320 is not disabled. Disabling some interconnect channels 320 would result in the total bandwidth of the interconnect channels being less than the total available bandwidth of the slave storage units (the total bandwidth of the three slave storage units 220), making it impossible to effectively utilize the total available bandwidth of the slave storage units. In this case, one L2C channel can be disabled, because disabling one L2C channel still ensures that the total bandwidth of the three L2C channels is not less than the total available bandwidth of the slave storage units, thus still effectively utilizing the total available bandwidth of the slave storage units, while also reducing the data processing volume of the third interleaving process.

[0116] In some implementations of the embodiments of this application, the embodiments of this application may further include: in the event of an L2C channel failure, for the slave chips connected to the interconnect chip of the faulty L2C channel, the following steps are performed: determining the number of available slave storage units, the slave storage unit bandwidth of a single slave storage unit 220, the number of available L2C channels, and the L2C channel bandwidth of a single L2C channel; determining the expected number of slave storage units based on the slave storage unit bandwidth, the number of available L2C channels, and the L2C channel bandwidth; and disabling some slave storage units 220 based on the expected number of slave storage units if the number of available slave storage units is inconsistent with the expected number of slave storage units.

[0117] Similar to the interconnect channel, when the L2C channel of the interconnect chip fails, the slave memory cell may be affected by the total bandwidth of the available L2C channels, resulting in some slave memory cell bandwidth being unusable. Therefore, the expected number of slave memory cells can be determined based on the available L2C channels. If the number of available slave memory cells is inconsistent with the expected number of slave memory cells, some slave memory cells 220 are disabled based on the expected number of slave memory cells. The process is similar to disabling some slave memory cells 220 when the interconnect channel 320 fails. For details, please refer to the relevant descriptions, which will not be repeated here.

[0118] In the case where the L2C channel of the interconnect chip connected to the faulty interconnect channel 320 also fails, based on the barrel principle, we can first determine the total available interconnect channel bandwidth and the total available L2C channel bandwidth, and then determine the expected number of storage cells based on the smaller of the two.

[0119] As one embodiment, the monitoring unit can be located outside the master and slave memory chips and monitor the fault status of each master memory unit 210, slave memory unit 220, interconnect channel 320, and L2C channel.

[0120] As another example, the slave chip 120 can monitor the fault status of its corresponding slave storage unit 220, interconnect channel 320, and L2C channel, and transmit the fault status to a monitoring unit located outside the slave chip 120. The master chip 110 monitors the fault status of each master storage unit 210 and transmits the status to the monitoring unit, which can be located inside or outside the master chip 110.

[0121] In some implementations of the embodiments of this application, the method further includes: determining the load state of the chip system; when the load state meets a preset threshold and the expected interconnect channel numbers corresponding to each slave chip 120 are inconsistent, determining the minimum value among the expected interconnect channel numbers; determining the available interconnect channels of each slave chip 120 according to the minimum value of the expected interconnect channel numbers, so that the expected interconnect channel numbers of each slave chip 120 are the same.

[0122] The load status of the chip system can be determined according to preset methods, such as determining the load status based on the number of access requests processed per unit time, or determining the load status based on the number of target memory units accessed per unit time.

[0123] A preset threshold is set for the load condition to assess whether the chip system is under high load. When the load condition meets the preset threshold, the chip system is determined to be under high load.

[0124] When the chip system is under high load, if the access request received by the master chip 110 corresponds to a parallel computing task, the master chip 110 needs to synchronize with the data returned by all transmission channels 300 before proceeding to the next calculation. If a fault occurs in the processing of the slave storage unit 220, the time required for that slave chip 120 to respond to the access request will increase. This means that even if other slave chips 120 respond quickly to the access request, the master chip 110 will still need to wait for a certain period. Because some slave storage units 220 of the slave chips 120 may malfunction, the expected number of interconnect channels for each slave chip 120 may be inconsistent, meaning the number of interconnect channels required by each slave chip 120 may be inconsistent. In this case, the number of available interconnect channels in each slave chip 120 can be adjusted to make the number of available interconnect channels between each slave chip 120 and the master chip 110 the same, which can greatly reduce the complexity of interconnect channel interleaving without affecting the overall system performance.

[0125] In this implementation, when the chip system is under high load, if the expected number of interconnect channels corresponding to each slave chip 120 is inconsistent, the minimum value among the expected number of interconnect channels of each slave chip 120 can be adjusted to adjust the available interconnect channels of each slave chip 120 so that the number of available interconnect channels of each slave chip 120 is the same, thereby reducing the amount of data processing for interconnect channel interleaving and increasing the speed of interconnect channel interleaving.

[0126] In some implementations of the embodiments of this application, before performing the first interleaving transformation according to the first interleaving parameters to obtain the target memory address, the first embodiment further includes: determining the service type of the access request; determining the set of storage units to be interleaved corresponding to the service type; the set of storage units to be interleaved includes one of a global storage unit set and a local storage unit set; if the set of storage units to be interleaved is a local storage unit set, determining the first interleaving parameters according to the local storage unit set.

[0127] The received access requests from chip 100 may correspond to different service types, and different services have different latency expectations. For example, for low-latency expectation types, the target storage unit needs to be determined from several storage units 200 with the shortest response time between the chip 100 and the receiving access request. For service types with non-low-latency expectations, the target storage unit can be determined from any storage unit 200. Therefore, the service type of the access request is categorized, with different service types corresponding to different sets of storage units to be interleaved. The corresponding target storage unit is requested from the set of storage units to be interleaved for each service type. The set of storage units to be interleaved includes one of a global storage unit set and a local storage unit set. The global storage unit set consists of all storage units 200 in the chip system, while the local storage unit set consists of several pre-determined storage units 200 in the chip system. After determining the set of storage units to be interleaved, the first interleaving parameters can be determined based on the set of storage units to be interleaved. For example: the number of storage cells 200 in the set of storage cells to be interleaved is used as the number of available storage cells in the first interleaving parameter, and the storage cell identifier of the storage cell 200 in the set of storage cells to be interleaved is used as the storage cell identifier in the first interleaving parameter.

[0128] In this implementation, since the service type of the access request corresponds to a specified set of storage units to be interleaved, and this set of storage units to be interleaved is predetermined, the first interleaving parameter can be determined based on the service type of the access request upon receiving the access information. This allows the target storage unit to be one of the storage units in the set of storage units to be interleaved, enabling rapid determination of the first interleaving parameter. Based on the first interleaving parameter, the target storage unit can be determined as one of the storage units 200 in the set of storage units to be interleaved. This allows for the pre-determination of storage units 200 that respond to access requests of different service types, thus meeting the needs of access requests of different service types.

[0129] It should be noted that since different storage units 200 may have different transmission channels 300 with the chip 100 that receives the access request (for example, the transmission channel 300 between some storage units 200 includes the interconnect channel 320, while the transmission channel 300 between some storage units 200 does not include the interconnect channel 320), the time required to respond to the access request includes the time to determine the target storage unit, the time to determine the transmission channel 300, and the time to transmit the access request from the chip 100 to the target storage unit.

[0130] Second Embodiment Reference Figure 6 This illustrates another access processing method provided by an embodiment of this application. The second embodiment can be applied to a chip system, which includes a die and multiple memory cells. At least one transmission channel is provided between the die and each memory cell. The embodiment of this application may include the following steps: Step S61: Upon receiving an access request, determine the service type of the access request.

[0131] Step S62: Determine the set of storage units to be interleaved corresponding to the service type.

[0132] The set of storage cells to be interleaved includes either a global set of storage cells or a local set of storage cells.

[0133] Step S63: Determine the first interleaving parameters according to the set of storage cells to be interleaved.

[0134] Step S64: Perform a first interleaving transformation based on the first interleaving parameters to obtain the target memory address.

[0135] Step S65: Transmit the access request to the target storage unit through the corresponding transmission channel according to the target memory address.

[0136] This application embodiment can determine the service type of the access request upon receiving an access request, and determine the first interleaving parameter based on the interleaving storage unit set corresponding to the service type, thereby achieving rapid determination of the first interleaving parameter. By obtaining the target memory address through the first interleaving transformation, and transmitting the access request to the target storage unit through the corresponding transmission channel based on the target memory address, it is possible to determine the target storage unit as one of the storage units in the set of storage units to be interleaved based on the first interleaving parameter. This allows for the pre-determination of storage units that respond to access requests of different service types, meeting the needs of access requests of different service types. Simultaneously, it enables access balance among the storage units included in the set of storage units to be interleaved corresponding to the service type.

[0137] For example, when the service type is a specific page table access, the set of storage units to be interleaved is a local storage unit; when the service type is a normal data read, the set of storage units to be interleaved is a global storage unit set. For example, specific page table access includes MMU table lookup / write services. This type of service is highly sensitive to latency and is more suitable for accessing storage units closer to the core, thus making local interleaving more suitable.

[0138] The second embodiment can be applied to chip systems including, but not limited to, the architectures mentioned in the first embodiment, including but not limited to, such as Figure 1 , Figure 2 , Figure 4 , Figure 5 The chip system architecture shown.

[0139] The second embodiment can include any implementation of the first embodiment. For example, the second embodiment can be applied to dynamic processing based on storage unit failure and / or dynamic processing based on transmission channel failure. The specific processing procedure is the same as that in the first embodiment and will not be repeated here. For example, for storage unit failure, steps S21-S23 can be used to replace step S64, so that dynamic processing can be performed based on storage unit failure to obtain the target memory address.

[0140] The first embodiment below will be further explained in the case where there are no faults in the memory unit and the transmission channel of the chip system: In some implementations of the second embodiment, the second embodiment may further include the following steps: determining a second interleaving parameter based on the target storage unit; performing a second interleaving transformation based on the second interleaving parameter to determine the target transmission channel of the access request; and transmitting the access request to the target storage unit based on the target transmission channel.

[0141] The difference between this implementation and the first embodiment is that the second interleaving parameters can be determined in advance for each storage cell in the set of storage cells to be interleaved. After the target storage cell is determined, the second interleaving parameters corresponding to the target storage cell are read directly to achieve fast second interleaving transformation processing.

[0142] For cases where there are multiple parallel memory channels between the chip and the target storage cell, the second interleaving transformation includes memory channel interleaving. The second interleaving parameters include the number of available memory channels and memory channel identifiers corresponding to the memory channel interleaving. The number of available memory channels and memory channel identifiers can be determined in advance for each storage cell in the set of storage cells to be interleaved.

[0143] For cases where there are multiple parallel interconnect channels between the chip and the target memory cell, the second interleaving transformation includes interconnect channel interleaving. The second interleaving parameters include the number of available interconnect channels and the interconnect channel identifier corresponding to the interconnect channel interleaving. The number of available interconnect channels and the interconnect channel identifier can be determined in advance for each memory cell in the set of memory cells to be interleaved.

[0144] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0145] Third Embodiment This application also provides a chip system including a chip, multiple memory cells, and a monitoring unit. At least one transmission channel is provided between the chip and each memory cell. The monitoring unit is configured to: monitor the fault status of the memory cells; determine the number of available memory cells in the event of a memory cell fault; and, upon receiving an access request, selectively adjust a first interleaving parameter based on the access request and the information of available memory cells, and perform a first interleaving transformation according to the first interleaving parameter to obtain a target memory address; and transmit the access request to the target memory cell through the corresponding transmission channel according to the target memory address.

[0146] Fourth embodiment This application also provides another chip system, including a chip and multiple memory cells, with at least one transmission channel between the chip and each memory cell; the chip is configured to: upon receiving an access request, determine the service type of the access request; determine a set of memory cells to be interleaved corresponding to the service type; the set of memory cells to be interleaved includes one of a global set of memory cells and a local set of memory cells; determine a first interleaving parameter according to the set of memory cells to be interleaved; perform a first interleaving transformation according to the first interleaving parameter to obtain a target memory address; and transmit the access request to the target memory cell through the corresponding transmission channel according to the target memory address.

[0147] For example, the carrier of the chip system in the third and fourth embodiments can be a computing card that includes two or more chips.

[0148] As the system implementation is basically similar to the method implementation, it is described in a relatively simple way. For relevant details, please refer to the description in the method implementation section.

[0149] This application also discloses a computer program product, including a computer program, which, when run, causes the access processing method as described in the foregoing embodiments to be executed.

[0150] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An access processing method, characterized in that, Applied to a chip system, the chip system including a die and multiple memory cells, wherein at least one transmission channel is provided between the die and each of the memory cells, the method includes: Monitor the fault status of the storage unit; In the event of a failure in the storage unit, information on available storage units is determined, including the number of available storage units. Upon receiving an access request, the first interleaving parameter is selectively adjusted based on the access request and the information of the available storage unit, and a first interleaving transformation is performed according to the first interleaving parameter to obtain the target memory address; The access request is transmitted to the target storage unit through the corresponding transmission channel according to the target memory address; The first interleaving parameter includes the number of available storage units; the step of performing a first interleaving transformation based on the first interleaving parameter to obtain the target memory address includes: extracting the address information of the access request; and performing a first interleaving transformation based on the address information and the number of available storage units to obtain the target memory address.

2. The method according to claim 1, characterized in that, The first interleaving parameter includes a storage cell identifier; the method further includes: The target memory unit is determined based on the target memory address and the storage unit identifier.

3. The method according to claim 2, characterized in that, The storage unit identifier is generated in an incremental manner before the storage unit is in a faulty state; The target memory address includes a target memory identifier; determining the target storage unit based on the target memory address and the storage unit identifier includes: The storage unit identifiers are sorted in ascending order to obtain the first sorting information; Based on the size of each storage cell identifier and the order of the storage cell identifiers in the first sorting information, determine the first correction offset corresponding to each storage cell identifier; The target storage unit is determined based on the storage unit identifier, the first correction offset, and the target memory identifier; The difference between the storage unit identifier corresponding to the target storage unit and the first correction offset is equal to the target memory identifier.

4. The method according to claim 2, characterized in that, The target memory address includes a target memory identifier; Determining the target storage unit based on the target memory address and the storage unit identifier includes: Update the storage cell identifier in the first interleaving parameter in an incremental manner; The available storage unit whose updated storage unit identifier matches the target memory identifier is identified as the target storage unit.

5. The method according to claim 1, characterized in that, The chip and one or more of the memory cells include multiple parallel transmission channels; the method further includes: Monitor the fault status of the transmission channel; In the event of a failure in the transmission channel, information on available transmission channels between the target storage unit and the chip corresponding to the access request is determined, including the number of available transmission channels. Based on the information of the available transmission channels, the second interleaving parameters are selectively adjusted to perform a second interleaving transformation, thereby determining the target transmission channel for the access request. The access request is transmitted to the target storage unit according to the target transmission channel; The second interleaving parameter includes the number of available transmission channels; the second interleaving transformation to determine the target transmission channel of the access request includes: Extract the address information of the access request; perform a second interleaving transformation based on the address information and the number of available transmission channels to determine the target transmission channel.

6. The method according to claim 5, characterized in that, The transmission channel includes a memory channel and an interconnect channel. The memory channel is a channel for accessing storage units, and the interconnect channel is a channel between chips.

7. The method according to claim 6, characterized in that, The chip system includes a master die and slave dies. The master die is connected to multiple interconnected master memory cells, and the slave dies are connected to multiple fully interconnected slave memory cells. Each slave die is connected to the master die through multiple interconnect channels. The method further includes: For a slave chip with a faulty storage unit, perform the following steps: Determine the total available bandwidth from the storage units, the number of available interconnect channels, and the interconnect channel bandwidth of a single said interconnect channel; The expected number of interconnect channels is determined based on the total available bandwidth of the storage units and the interconnect channel bandwidth. If the number of available interconnect channels does not match the expected number of interconnect channels, some of the interconnect channels will be disabled based on the expected number of interconnect channels.

8. The method according to claim 6, characterized in that, The chip system includes a master die and slave dies. The master die is connected to multiple interconnected master memory cells, and the slave dies are connected to multiple fully interconnected slave memory cells. Each slave die is connected to the master die through multiple interconnect channels. The method further includes: Determine the number of interconnect channels corresponding to the total bandwidth of different storage units; A first mapping relationship is generated based on the total bandwidth of the corresponding storage units and the number of interconnect channels; For a slave chip that has failed in the aforementioned storage unit, the following steps are performed: Determine the total available bandwidth from the storage units and the number of available interconnect channels; Based on the total available bandwidth of the storage units and the first mapping relationship information, the expected number of interconnect channels is determined; If the number of available interconnect channels does not match the expected number of interconnect channels, some of the interconnect channels will be disabled based on the expected number of interconnect channels.

9. The method according to claim 7 or 8, characterized in that, The method further includes: Determine the load status of the chip system; If the load condition meets a preset threshold and the expected number of interconnect channels corresponding to each of the slave cores is inconsistent, determine the minimum value among the expected number of interconnect channels. The available interconnect channels for each slave chip are determined according to the minimum of the expected number of interconnect channels, so that the number of available interconnect channels for each slave chip is the same.

10. The method according to claim 1, characterized in that, Before performing the first interleaving transformation based on the first interleaving parameters to obtain the target memory address, the method further includes: Determine the service type of the access request; Determine the set of storage units to be interleaved corresponding to the service type; the set of storage units to be interleaved includes one of a global storage unit set and a local storage unit set. The first interleaving parameters are determined according to the set of storage cells to be interleaved.

11. A chip system, characterized in that, It includes a chip, multiple storage units, and a monitoring unit. At least one transmission channel is provided between the chip and each of the storage units, and the monitoring unit is connected to the storage units. The monitoring unit is configured to: monitor the fault status of the storage unit; and, in the event of a fault in the storage unit, determine information on available storage units, including the number of available storage units. Upon receiving an access request, the chip selectively adjusts the first interleaving parameters based on the access request and the information of the available storage units, and performs a first interleaving transformation according to the first interleaving parameters to obtain the target memory address; and transmits the access request to the target storage unit through the corresponding transmission channel according to the target memory address. The first interleaving parameter includes the number of available storage units; The step of performing a first interleaving transformation based on the first interleaving parameters to obtain the target memory address includes: extracting the address information of the access request; A first interleaving transformation is performed based on the address information and the number of available storage units to obtain the target memory address.

Images