Viterbi decoding method, medium and computer program product for genetic sequencing

Abstract

The present application provides a Viterbi decoding method, medium and computer program product for gene sequencing. The method comprises: obtaining an emission score matrix generated by a recurrent neural network; performing a backward traversal calculation to iteratively calculate a backward probability for each time step, batch and state from the end of a base sequence to the starting end, the backward probability representing an expected cumulative score from the corresponding state to the end of the sequence for the corresponding time step and batch; generating a guide score matrix based on the emission score matrix and the backward probability, the guide score matrix containing a guide score for each time step, batch, state and base type index; and performing forward Viterbi decoding and backtracking using the guide score matrix to obtain a decoded base sequence.

Description

Technical Field

[0001] This disclosure relates to gene sequencing, and more particularly to a Viterbi decoding method used in third-generation gene sequencing to recover base sequences from a fractional matrix output by a recurrent neural network (RNN). Background Technology

[0002] The Viterbi decoding algorithm, a classic method for finding the optimal path in Hidden Markov Models (HMMs), has been widely applied to base calling tasks in gene sequencing. In third-generation gene sequencing technology, Viterbi decoding is used to process the score matrix output by the RNN to recover the base sequence. Summary of the Invention

[0003] In one aspect, this application discloses a Viterbi decoding method for gene sequencing. The method includes: obtaining an emission score matrix generated by a recurrent neural network (RNN) based on sequencing current signals of a base sequence, the emission score matrix being a tensor containing dimensions N, S, and A for each time step (t) of the sequencing current signal, where N is the batch size representing the number of sequences processed simultaneously, S is the number of states, and A is the number of base types; performing a backward traversal computation, iteratively calculating a backward probability for each time step (t), batch (n), and state (s) from the end to the beginning of the base sequence, the backward probability representing the expected cumulative score from the corresponding state (s) to the end for the corresponding time step (t) and batch (n); generating a guiding score matrix based on the emission score matrix and the backward probability, the guiding score matrix containing a guiding score for each time step (t), batch (n), state (s), and base type index (a); and performing forward Viterbi decoding and backtracking using the guiding score matrix to obtain the decoded base sequence.

[0004] In other respects, this application discloses a non-transitory computer-readable medium storing instructions and a computer program product including the instructions. These instructions, when executed by one or more processors, cause the processors to perform the methods described in this application.

[0005] According to embodiments of the present invention, the local greed problem inherent in traditional Viterbi decoding algorithms can be solved. Further embodiments can also improve hardware versatility, computational efficiency, and numerical stability. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the art, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may have been intentionally enlarged or reduced.

[0007] Figure 1 The diagram illustrates an example of the decoding process principle of the traditional Viterbi algorithm.

[0008] Figure 2 This is a schematic diagram of a guided Viterbi decoding algorithm according to an embodiment of the present invention.

[0009] Figure 3 This is a diagram illustrating the traditional method of performing transpose and index operations in the underlying hardware.

[0010] Figure 4 A schematic diagram illustrating the transpose operation implemented by matrix multiplication according to an embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram of mixed precision calculation according to an embodiment of the present invention.

[0012] Figure 6 This is a simplified flowchart of the guided Viterbi decoding algorithm according to an embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram of a computing device that can be implemented according to an embodiment of the present invention. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0015] The purpose of gene sequencing is to read the sequence of the four bases (A, T, C, and G) on a DNA strand. In third-generation sequencing technologies (such as Oxford Nanopore or PacBio SMRT), a single strand of DNA is passed through a nanopore. Different bases (or combinations of bases) passing through induce characteristic changes in electrical signals. These electrical signals are recorded, and a base determination process converts the resulting continuous time-series simulated electrical signals into A, T, C, and G bases, thereby reconstructing the corresponding base sequence and achieving gene sequencing.

[0016] As DNA strands pass through nanopores, different bases or base combinations (called k-mers, where k is a positive integer, typically odd) generate characteristic current blocking levels. Sequencers record continuous current values ​​that fluctuate over time at sampling rates typically a few kHz. The raw current signal is continuous and noisy, containing instrument noise, thermal noise, and is affected by various factors such as temperature and voltage fluctuations. Furthermore, the current values ​​are highly context-dependent. For example, when the same base A passes through a nanopore, the current characteristics may differ depending on whether the previous base combination AA (i.e., the current base is the last A in the AAA sequence) or the previous base combination AC (i.e., the current base is the last A in the ACA sequence). Therefore, the base determination process often employs recurrent neural networks (RNNs) or their variants (such as Long Short-Term Memory (LSTM) networks, gated recurrent units (GRUs), etc.) to process the sequence data. The trained RNN model interprets the current signal segment at each time step t. Instead of directly outputting the base or base combination corresponding to that time step, it outputs a probability distribution (called a "score"). For a single base, there are four possibilities (A, T, C, G). Therefore, the RNN outputs a 4-dimensional vector at each time step t, representing the relative probability of the signal corresponding to these four possibilities at that moment. Typically, for a single base, in addition to A, T, C, and G, an "N" representing an uncertain state is also considered, resulting in a 5-dimensional vector output by the RNN at each time step.

[0017] However, the score matrix output by the RNN is local and independent. The score at each time step is calculated based on the current and previous signals, but the global consistency rules of the entire sequence (e.g., the DNA sequence must conform to reasonable base transition rules) are not explicitly considered when calculating the scores between different time steps. Therefore, the base with the highest score cannot be directly selected as the decision result for each time step t. The actual processing of the score matrix is ​​based on a Hidden Markov Model (HMM), where: the true base state to be determined is the hidden state of the HMM; the score matrix output by the RNN is the observation value; the transition probability from the previous base to the next base is the state transition probability, which can be statistically obtained from known biological data; and the probability of generating a specific observation signal given a true base is the emission probability, provided by the score matrix of the RNN. The base determination process uses the Viterbi algorithm to find the hidden state sequence (i.e., the most likely true base sequence) that is most likely to generate these observation values, given the observed sequence (i.e., the score matrix output by the RNN) and the HMM model parameters (i.e., the state transition probabilities).

[0018] Figure 1 The diagram illustrates an example of the decoding process in the traditional Viterbi algorithm. Figure 1The grid representing the fractional matrix shows four time steps t = 0, 1, 2, 3 on the horizontal axis, and all possible base states s = A, C, T, or G on the vertical axis. The circled grid point represents the corresponding position in the fractional matrix. The score represents the probability of being in state s at time step t. The lines connecting grid points (called "edges") represent the "cost" or "reward" derived from the state transition probability. For example, a transition from A to C is common and has a higher reward; while a transition from A to A is prone to deletion errors in nanopores and has a lower reward (or higher cost). The Viterbi algorithm finds the path with the highest cumulative score in the grid from the first column to the last column by performing forward decoding and backtracking on the score matrix. The traditional Viterbi algorithm is implemented through dynamic programming, recording the best forward path and cumulative score to reach the current state s at each time step t, and finally backtracking to obtain the globally optimal path. The sequence of states corresponding to each node on this path is the base sequence recovered by decoding. For example, for Figure 1 In the example shown, the optimal path represented by the thick arrow yields the base sequence CTTG.

[0019] The above ( The grid model is a simplified model for single bases, based on the assumption that the observed signal at each time step t depends only on the current base. In real nanopore physics, the blocking current is mainly influenced by a small segment of DNA (a k-mer) simultaneously occupying the narrow region of the nanopore. Therefore, in the HMM for base combinations (e.g., for a k-mer model containing 5 bases, k=5), a single base is used as the hidden state, not a single k-mer. Since each base has 4 possibilities (A, T, C, G), the vector dimension of the 5-mer output at each time step t will be... =1024, representing the 1024 possibilities that the blocking current at this moment is mainly influenced by a single 5-mer fragment (e.g., ACTGA, CTGAT, etc.). When the DNA strand moves a base (e.g., T), the hidden state transitions from one k-mer to the next, such as from ACTGA to CTGAT.

[0020] Performing Viterbi decoding on RNN fractional matrices of base combinations involves a large amount of computation and is typically performed in batches on multiple sequences in parallel, usually relying on general-purpose graphics processing units (GPUs). However, traditional Viterbi decoding algorithms suffer from the local greed problem. During the forward traversal, each time step makes a decision based solely on the current state and transition score. This locally greedy strategy leads to suboptimal results in many scenarios. For example, in regions of repetitive sequences, insertion or deletion errors are easily generated when there are consecutive identical bases. In regions of low-quality signals, incorrect paths are easily chosen under noise interference. For long sequences, cumulative errors occur, meaning that locally optimal choices accumulate over long sequences, leading to global suboptimality.

[0021] Furthermore, traditional Viterbi decoding algorithms require extensive use of indexing operations such as gather and scatter in the underlying hardware. These indexing operations are primarily optimized for general-purpose GPUs, while dedicated AI accelerators such as Neural Processing Units (NPUs) and Tensor Processing Units (TPUs) have limited support for gather operations, with performance only 10%-30% of that of general-purpose GPUs. Moreover, due to the irregular memory access patterns, they cannot be efficiently mapped to systolic arrays, making them difficult to implement by field-programmable gate arrays (FPGAs).

[0022] Furthermore, during long sequence decoding, the probability values ​​in the logarithmic space accumulate continuously, easily leading to numerical underflow or overflow. Using high-precision floating-point numbers throughout results in high memory consumption and low throughput; while using low-precision calculations leads to numerical instability. Therefore, traditional techniques struggle to balance numerical stability and computational efficiency.

[0023] Embodiments of this invention provide a guided Viterbi decoding method that achieves globally optimal guidance by deeply integrating backward probability calculation with forward Viterbi decoding. In some embodiments, matrix multiplication and embedding operations are used instead of indexing operations, enabling high hardware versatility. In some embodiments, a mixed-precision calculation strategy is also employed to optimize computational efficiency while ensuring numerical stability.

[0024] For ease of description, the following symbols are used in this article.

[0025] T: Sequence length (number of time steps);

[0026] N: Batch size (number of sequences processed simultaneously);

[0027] S: Number of states (for k-mer gene sequences, ...) );

[0028] A: Alphabet size (number of base types, usually A = 4 or 5);

[0029] : The emission fraction matrix at time step t;

[0030] The backward probability at time step t;

[0031] : Forward probability at time step t;

[0032] : State transition index matrix, elements This represents the target state that can be reached from state s via edge a;

[0033] : Reverse transition index matrix, elements Let represent the source state of the a-th incoming edge leading to state s.

[0034] Figure 2 The illustration shows a schematic diagram of the Viterbi decoding algorithm according to an embodiment of the present invention. Figure 2 The algorithm shown is executed on the acquired emission score matrix, which is generated by the RNN based on the sequencing current of the base sequence. For simplicity, Figure 2 Only the processing procedure for a single batch is shown; however, those skilled in the art will understand that the algorithm can process multiple (N, e.g., hundreds of sequences in parallel) batches simultaneously. The algorithm generally comprises three stages: backward traversal, guided fraction matrix generation, and forward Viterbi decoding and backtracking.

[0035] Backward traversal phase

[0036] In this stage, a traversal is performed from the end of the sequence (time step T) to the beginning of the sequence (time step 0), iteratively calculating the backward probability of each state s. value. The backward probability is the expected cumulative score of all possible future paths from the next time step t+1 to the end of the sequence T, assuming the current time step t is in state s. Therefore, the backward probability characterizes the expected cumulative score from the corresponding state s to the end of the sequence T, quantifying the impact of the current choice on future outcomes.

[0037] In the initialization step of the backward traversal phase, for each batch n and state s, the backward probability value at time step T at the end of the sequence is set to zero:

[0038] For all .

[0039] Then, using equation (1) as the recursive formula, the calculation is performed iteratively for time steps t = T-1, T-2, ..., 0:

[0040] (1)

[0041] In equation (1), It is an index matrix that reflects the state transition, representing the target state reached from state s through edge a. This is the state that was previously calculated for time step t+1, and for batch n at time step t+1. The backward probability represents the expected score of subsequent paths starting from the current node. This is the transposed emission fraction matrix, where the elements are... This represents the matching score of the observed signal at time step t, batch n, if the system is in state s and about to transition out via edge a. The sum of the two terms in square brackets represents the score of a single future path, that is, the total score of the complete future path if edge a is chosen to transition out of state s at time step t.

[0042] In equation (1), The operation is a probability normalization summation operation in the logarithmic space, which can be represented as: Compared to simple summation, using... This operation helps to avoid numerical overflow and ensure numerical stability.

[0043] Through the above operations in the backward traversal phase, the backward probability for each time step t, batch n, and state s can be obtained. .

[0044] Guided fraction matrix generation stage

[0045] At this stage, based on the backward probabilities calculated through backward traversal and the scores in the emission score matrix, a guiding score matrix G is generated, where each guiding score value in matrix G is:

[0046] (2)

[0047] In equation (2):

[0048] It is the raw emission score, representing the likelihood score given by the RNN for the event that "state s at time step t and batch n is reached via incoming edge a (i.e., by consuming base a)".

[0049] The backward probability calculated in the previous stage represents the expected cumulative score for batch n from time step t+1 to the end of the sequence after reaching state s.

[0050] It contains future information (by...) (Reflects) the guiding score.

[0051] Therefore, compared to the original launch score, the guidance score carries global guidance information. It combines local transfer scores with global future expectations, enabling the forward decoding process to "foresee" the long-term consequences of choosing each path, thereby making a globally optimal decision.

[0052] In the above expression, the guiding score is obtained by directly adding the original emission score to the backward probability. In other embodiments, the guiding score matrix can be generated based on the emission score matrix and the backward probability in other ways (e.g., weighted summation).

[0053] Forward Viterbi Decoding and Backtracking Phase

[0054] In this stage, the guiding fraction matrix G is used instead of the emission fraction matrix M in the traditional Viterbi decoding algorithm to perform forward Viterbi decoding and backtracking, so as to obtain the decoded base sequence.

[0055] The forward traversal process of forward Viterbi decoding first performs initialization at time step 0:

[0056] For all .

[0057] Subsequently, the forward traversal process uses the following equations (3) and (4) as recursive formulas to calculate the maximum forward probability and the optimal incoming edge index for time steps t = 0, 1, ..., T-1:

[0058] (3)

[0059] (4)

[0060] In equations (3) and (4):

[0061] It is an index function that represents the source state of the a-th incoming edge leading to state s;

[0062] The optimal incoming edge (i.e., the base a that maximizes the sum of the two terms in the brackets of equation (4)) for reaching state s at time step t and batch n is recorded for subsequent backtracking.

[0063] During the backtracking process, firstly, at the last time step T of the sequence, for the nth sequence in the batch, the state with the highest cumulative forward probability among all states is selected as the endpoint of the optimal path. This final state is determined by the following expression:

[0064] (5)

[0065] In equation (5), Let represent the highest cumulative score among all possible paths from the beginning of the sequence (time step 0) to the end of the sequence (time step T), ultimately ending in state s. Therefore, equation (5) yields the result that... The largest state s is the endpoint state of the globally optimal path. It provides a starting point for the backtracking process.

[0066] Next, the reverse backtracking path is executed, tracing backward step by step from the aforementioned starting point in the opposite time direction. For t = T-1, T-2, ..., 0, the following calculations are performed:

[0067] (6)

[0068] (7)

[0069] In equation (6), at time step t (ranging from T-1 to 0), based on the already determined optimal state for the next time step... Find the optimal inbound edge index stored in the forward traversal calculation shown in equation (4). and save in In the middle. The calculation of equation (6) can recover which edge (i.e. which base) a should be selected at time step t to optimally reach the next state. All Connecting them in chronological order yields the decoded base sequence.

[0070] In equation (7), the optimal transition edge at time step t is determined. Then, using the reverse transition index matrix Find the optimal state at the previous time step t-1 This operation provides the means to continue backtracking forward, thus enabling iterative execution of equations (6) and (7) to trace back earlier transition edges and states.

[0071] When the reverse backtracking path reaches time step t=0, the decoded path can be obtained. This path represents the decoded base sequence.

[0072] The calculation of equation (1) involves the transpose of the emission fraction matrix M. When the transpose operation is performed in the underlying hardware (e.g., GPU, NPU, etc.), it is usually compiled into a series of gather instructions. Figure 3 As illustrated in the diagram, the `gather` operation reads data from different (usually random) memory locations based on the index list `idx` and collects it into a contiguous block of memory. However, since dedicated AI accelerators such as NPUs and TPUs are designed for regular, predictable computational patterns (such as large-scale matrix multiplication and convolution), their core is a systolic array or vector computation unit, requiring a continuous and regular data flow. Irregular operations like `gather` disrupt the data pipeline, leading to a significant performance degradation. Furthermore, implementing a memory controller that supports random address access on an FPGA is also very complex.

[0073] According to an embodiment of the present invention, a permutation matrix is ​​used to implement the matrix transpose operation. First, a permutation matrix is ​​constructed. Its elements are defined as:

[0074] if and only if ;

[0075] Other situations.

[0076] in This is a transpose index mapping based on the state transition index matrix.

[0077] A permutation matrix P has two properties: First, each column of P contains exactly one 1, and the rest are 0; second, P is an orthogonal matrix that satisfies the following condition. .

[0078] Next, the emission fraction matrix is ​​flattened from a tensor of dimensions N, S, A into a tensor of dimensions N, S, A. tensor .

[0079] Subsequently, as Figure 4 As shown in the diagram, the transpose operation can be represented as the following matrix multiplication:

[0080] .

[0081] Matrix multiplication is a fundamental operation in all AI accelerators and is highly hardware optimized. For general-purpose GPUs, it can be efficiently implemented using tensor computing cores. For dedicated AI accelerators, matrix multiplication is typically natively supported, offering optimal performance. For FPGAs, it can be implemented using efficient systolic arrays. Therefore, according to embodiments of the present invention, matrix transposition is achieved by constructing a permutation matrix and performing matrix multiplication, resulting in better hardware versatility and improved performance compared to traditional implementations based on gather instructions.

[0082] As mentioned earlier, indexing operations are required during the forward Viterbi decoding and backtracking process. For example, the forward probability matrix... It is a tensor with dimensions N and S, and a back transition index matrix. It is a tensor with dimensions S and A, and the corresponding indexing operations (common expressions) The result (represented by) will be a tensor with dimensions N, S, and A. Its computation can be understood as: for each sample n (where ":" in the expression means all samples), each target state s, and each incoming edge a in the batch, in... Find the element located in the nth row of the tensor. The column value is then placed into the position of the result tensor. In the underlying hardware implementation, traditional multidimensional indexing operations are usually compiled into a series of gather instructions, which has shortcomings in terms of hardware versatility and performance.

[0083] According to embodiments of the present invention, embedding operations from deep learning are used instead of traditional indexing operations. Natural language processing often uses embedding matrices; given an index (e.g., a word ID), the row corresponding to that index can be obtained, given as a vector representation of the word. According to embodiments of this application, the transposed matrix having dimensions S and N is... If viewed as an embedding matrix, then each row corresponds to a feature vector of length N and state s. The index matrix has dimensions S and A. This serves as the list of indices to be searched. In this way, the embedding operation is performed. This will make for For each index value i in the matrix, go to the matrix Take the i-th row (i.e., the row from source state i) The result of using a vector (of length N) is a tensor with dimensions S, A, and N. The desired N, S, and A tensors can be obtained through simple dimension adjustments. In mainstream deep learning frameworks and hardware, embedding operations have been deeply optimized. On dedicated AI accelerators, they are often implemented as efficient on-chip cache lookups or work in conjunction with matrix multiplication units, with efficiency far exceeding that of the unoptimized general-purpose `gather` operation. Therefore, according to embodiments of the present invention, replacing traditional indexing operations with embedding operations offers better hardware versatility and higher performance compared to traditional `gather` instruction-based implementations.

[0084] like Figure 5 As shown, according to some embodiments, mixed-precision computation can be implemented. Some tensors are stored using lower precision and are temporarily converted to higher precision for computation at some stages. For example, the emission fractional matrix. Guiding score matrix The permutation matrix P can be stored as half-precision floating-point numbers (float16 or bfloat16), thereby reducing memory usage and bandwidth consumption and improving throughput. Before executing the logsumexp operation in equation (1) and the max or argmax operation in equations (3)-(5), the operands involved in these function operations can be temporarily converted to single-precision floating-point numbers (float32) for execution, thereby ensuring numerical stability and avoiding overflow / underflow. Let the input tensor be... The calculation function is The calculation process can be expressed as follows:

[0085]

[0086] in, The operation delegate explicitly converts the data type of the input data D to another data type with precision p, which can be easily achieved, for example, using methods such as .half() and .float32() in PyTorch. According to embodiments of the present invention, precision conversion can reduce memory bandwidth requirements by approximately 50%, and the loss of numerical precision is negligible (because critical calculations still use float32), while also supporting larger batch processing.

[0087] To improve operational efficiency, embodiments of the present invention can perform decoding in a batch processing manner: all operations can be fully parallelized across the batch dimension N, there are no dependencies between different sequences, and simultaneous processing can be achieved using Single Instruction Multiple Data (SIMD) instructions or vectorized instructions. Furthermore, the shape of the input tensor can be changed from... Remodeling The storage method ensures that the innermost dimension A is continuous in memory, which is conducive to the full utilization of cache lines and improves the memory merge access rate.

[0088] Figure 6 This is a simplified flowchart of the guided Viterbi decoding algorithm according to an embodiment of the present invention. Figure 6 As shown, the Viterbi decoding method 100 is used for gene sequencing. Method 100 includes an operation 110 for obtaining an emission score matrix. As previously described, the emission score matrix is ​​generated by a recurrent neural network (RNN) based on the sequencing current signal for the base sequence. For each time step t of the sequencing current signal, the emission score matrix... The tensor contains dimensions N, S, and A, where N is the batch size, representing the number of sequences processed simultaneously; S is the number of states, determined by the number of k-mers k; and A is the number of base types. Method 100 includes an operation 120 of performing backward traversal computation, iteratively calculating the backward probability for each time step t, batch n, and state s from the end of the base sequence to the beginning. Backward probability This characterizes the expected cumulative score from the corresponding state s to the end for the corresponding time step t and batch n. Method 100 includes the operation 130 of generating a pilot score matrix. The pilot score matrix G contains the pilot score for each time step t, batch n, state s, and base type index a. Since the pilot score matrix G is based on the emission score matrix... and backward probability The generated sequence contains future information not found in traditional Viterbi decoding algorithms, guiding subsequent forward decoding and bringing the result closer to the global optimum, thus solving the local greedy problem. Method 100 also includes operations 140 of performing forward Viterbi decoding and backtracking using a guiding score matrix to obtain the decoded base sequence.

[0089] Some embodiments of the present invention provide a non-transitory computer-readable medium. Instructions may be stored on this medium that, when executed by one or more processors, cause the one or more processors to perform the various methods described herein. Some embodiments of the present invention provide a computer program product comprising instructions that, when executed by one or more processors, cause the one or more processors to perform the various methods described herein.

[0090] According to embodiments of the present invention, the guided Viterbi decoding method achieves a significant improvement in accuracy compared to conventional Viterbi decoding methods. In repetitive sequence regions, the accuracy of base determination is improved by 5-15%. In low-quality signal regions, the error rate is reduced by 20-40%. For long sequences exceeding 10,000, cumulative errors are significantly reduced.

[0091] Some embodiments offer better hardware versatility. They can support multiple hardware platforms, including general-purpose GPUs, dedicated AI accelerators (such as NPUs and TPUs), and FPGAs. Traditional gather operations achieve only 10-30% of the performance on dedicated accelerators compared to general-purpose GPUs, while alternative methods such as permutation matrices and embedding operations used in embodiments of this invention can achieve 60-90%.

[0092] Some implementations have higher computational efficiency. Their time complexity is... This is comparable in magnitude to the traditional Viterbi decoding method. The space complexity is O(n). When using mixed-precision computing, actual memory usage is approximately 60% of that of traditional methods. Throughput is increased by 1.8–2.5 times.

[0093] Some implementations exhibit good numerical stability. No numerical overflow occurs on long sequences of T=5,000, and the relative error is less than that of a double-precision floating-point benchmark. .

[0094] Figure 7 This is a schematic diagram of a computing device that can be implemented according to embodiments of the present invention, and can be used to implement the Viterbi decoding method described herein, as well as the corresponding decoding device or gene sequencing device. For example... Figure 7 As shown, the computing device 700 may include a bus 702 or other communication mechanism for transmitting information, and one or more processors 704 coupled to the bus 702 for processing information. The one or more processors 704 may include, for example, one or more general-purpose microprocessors. In some embodiments, the processor 704 may also include one or more AI accelerators, such as GPUs, TPUs, NPUs, FPGAs, etc., and may include corresponding on-chip integrated memory, caches, etc. The architecture, principles, and hardware of AI accelerators are well known in the art and therefore will not be described in detail herein.

[0095] like Figure 7As shown, in some embodiments, computing device 700 may further include main memory 706 coupled to bus 702. Main memory 706 is used to store information and instructions executed by one or more processors 704, such as random access memory (RAM), cache, and / or other dynamic storage devices. Main memory 706 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 704. When these instructions are stored in storage media accessible to one or more processors 704, they can cause computing device 700 to become a dedicated machine customized to perform the operations specified in the instructions. Storage device 708 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or networking versions thereof.

[0096] like Figure 7 As shown, in some embodiments, computing device 700 may further include one or more network interfaces 710 coupled to bus 702. Network interface 710, also referred to as a communication interface, can provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, network interface 710 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. Wireless links may also be implemented.

[0097] The various processes, methods, and algorithms described in the preceding sections can be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by these code modules. The processes and algorithms can be implemented, partially or fully, in dedicated circuit systems.

[0098] When the functions disclosed herein are implemented as software functional units and sold or used as standalone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes instructions to cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0099] Some embodiments further provide a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. Specific embodiments further provide a non-transitory computer-readable storage medium storing instructions executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0100] The embodiments disclosed herein can be implemented via a cloud platform, server, or server cluster (collectively referred to as the “service system”) that interacts with a client. The client can be a terminal device or a client registered by a user at the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device capable of installing platform applications.

[0101] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations should be considered to fall within the scope of this disclosure. Additionally, certain methods or processes may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and the blocks or states associated with them may be executed in other suitable orders. For example, the described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0102] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). The algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly turn the computer into an executable function but may learn from training data to produce a predictive model of the executable function.

[0103] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementations that operate to perform one or more of the operations or functions described herein.

[0104] Similarly, the methods described herein can be implemented at least in part by a processor, where one or more specific processors are instances of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also operate to support the execution of related operations in a “cloud computing” environment or as the execution of related operations in a “Software as a Service” (SaaS) context. For example, at least some operations can be performed by a group of computers (as an example of a machine containing processors), where these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0105] The execution of certain operations can be distributed across processors rather than residing within a single machine, and can be deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In some embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0106] Throughout this specification, multiple examples may be implemented as components, operations, or structures of a single example. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configurations may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as separate components. These and other variations, modifications, additions, and improvements also fall within the scope of this document.

[0107] As used herein, "or" is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, "A, B, or C" means "A, B, A and B, A and C, B and C, or A, B, and C" unless explicitly indicated by the context. Furthermore, "and" is combined and separate unless explicitly indicated by the context. Therefore, in this document, "A and B" means "A and B, combined or separate" unless explicitly indicated by the context. Additionally, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, the boundaries between various resources, operations, engines, and data storage devices are somewhat arbitrary and specific operations are illustrated within the context of a particular illustrative configuration. Other functional assignments are foreseeable and fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as individual resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functions presented as single resources may be implemented as single resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of this disclosure as expressed in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0108] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not preclude the addition of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments require features, components, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, components, and / or steps are included in or performed in any particular embodiment, with or without user input or prompts.

[0109] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0110] The embodiments illustrated herein are described in detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, “implementation” is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their full scope.

Claims

1. A Viterbi decoding method for gene sequencing, comprising: Obtain the emission score matrix generated by the recurrent neural network (RNN) based on the sequencing current signal of the base sequence. The emission score matrix is ​​a tensor containing dimensions N, S, and A for each time step (t) of the sequencing current signal, where N is the batch size representing the number of sequences processed simultaneously, S is the number of states, and A is the number of base types. A backward traversal computation is performed, iteratively calculating the backward probability for each time step (t), batch (n), and state (s) from the end to the beginning of the base sequence. The backward probability represents the expected cumulative score from the corresponding state (s) to the end for the corresponding time step (t) and batch (n). Generate a guiding score matrix based on the emission score matrix and the backward probability, the guiding score matrix containing guiding scores for each time step (t), batch (n), state (s), and base type index (a); as well as The guided fraction matrix is ​​used to perform forward Viterbi decoding and backtracking to obtain the decoded base sequence. The execution of the forward Viterbi decoding and backtracking includes: Based on the guiding score matrix, a forward traversal is performed to calculate the maximum forward probability and the optimal incoming edge index for each time step (t), batch (n), and state (s); and The decoded path is obtained based on the maximum forward probability and the optimal incoming edge index, and the decoded path represents the decoded base sequence.

2. The method according to claim 1, wherein, Calculating the backward probability involves performing a log-space probability normalized summation on the following two: The transposed emission fraction matrix; and The backward probability for the next time step (t+1).

3. The method according to claim 2, wherein, The transpose of the emission fraction matrix includes: Construct an orthogonal permutation matrix based on the state transition index; Perform a flattening operation on the emission fraction matrix; and Perform matrix multiplication on the flattened emission fraction matrix and the orthogonal permutation matrix.

4. The method according to claim 1, wherein, Performing the forward Viterbi decoding and backtracking includes: Based on the reverse transition index matrix ( ) and the transposed forward probability matrix ( Perform the embedding operation. Wherein, the reverse transition index matrix ( ) contains: for each state (s) and the edge represented by the base type index (a), the source state of the edge (a) that is to reach state (s).

5. The method according to claim 3, wherein, The emission fraction matrix, the guidance fraction matrix, and the orthogonal permutation matrix are stored with first precision; Before the probability normalization summation in the logarithmic space, the transposed emission fraction matrix and the orthogonal permutation matrix are temporarily converted to a second precision higher than the first precision; and The result of the probability normalization summation in the logarithmic space is converted into the first precision.

6. The method according to claim 1, wherein, The guiding score matrix is ​​stored with first precision; Before calculating the maximum forward probability, the guiding score matrix is ​​temporarily converted to a second precision higher than the first precision; and The calculation result of the maximum forward probability is converted into the first precision.

7. The method according to claim 5 or 6, wherein, The first precision includes half-precision floating-point numbers, and the second precision includes single-precision floating-point numbers.

8. The method according to claim 1, further comprising: Store the emission fraction matrix such that dimension A is continuous in memory.

9. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 1-8.

10. A computer program product comprising instructions that, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 1-8.

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