High-precision low-temperature drift relaxation oscillation system with symmetrical two-path architecture and calibration method thereof

Abstract

This invention provides a high-precision, low-temperature drift relaxation oscillator system with a symmetrical dual-path architecture and its calibration method. The system includes a symmetrical dual-path relaxation oscillator core architecture, a fine-tuning circuit, a coarse-tuning circuit, and a bandgap reference source module. The method includes: S1, the system acquires the initial operating parameters of the relaxation oscillator and determines the initial frequency value; S2, the coarse-tuning circuit performs coarse-tuning calibration, adjusting the oscillator frequency to a first preset range of the target frequency value; S3, the fine-tuning circuit performs fine-tuning calibration, further adjusting the oscillator frequency to a second preset range of the target frequency value; S4, the bandgap reference source module performs temperature compensation calibration; S5, the system adjusts the ratio of charging current and discharging current, performing duty cycle adjustment; S6, the system performs frequency stability verification; S7, the final calibration configuration is generated and stored for long-term use of the oscillator. This invention is applicable to the field of integrated circuit technology.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and particularly to the field of clock generation circuit technology for system-on-chip (SoC), specifically a high-precision low-temperature drift relaxation oscillation system with a symmetrical dual-path architecture and its calibration method. Background Technology

[0002] In modern integrated circuits, especially in the design of System-on-Chip (SoC), a stable and reliable clock signal is fundamental to ensuring the synchronous operation of the system. To reduce costs, shrink chip size, and increase integration density, on-chip integrated clock sources are gradually replacing solutions that rely on external crystal oscillators. On-chip oscillators such as RC oscillators and relaxation oscillators have become the mainstream choice due to their simple structure and ease of integration.

[0003] Traditional on-chip relaxation oscillators are self-excited oscillation circuits. Their working principle is as follows: a constant current source is used to periodically charge and discharge a timing capacitor. A comparator with hysteresis characteristics monitors the voltage across the capacitor. When the capacitor voltage reaches the upper threshold voltage, the comparator flips to discharge the capacitor. When the capacitor voltage drops to the lower threshold voltage, the comparator flips again to charge the capacitor. This cycle repeats, generating a square wave clock signal at the comparator output. Its oscillation frequency f approximately satisfies f∝I / (C·ΔV), where I is the charging and discharging current, C is the timing capacitor value, and ΔV is the difference between the upper and lower threshold voltages.

[0004] However, traditional on-chip relaxation oscillators have significant technical drawbacks in practical applications, especially in situations where high frequency accuracy and stability are required. These drawbacks are as follows:

[0005] 1. Poor frequency accuracy and high sensitivity to PVT changes: The oscillation frequency directly depends on the absolute parameter values ​​of the on-chip passive components (capacitor C) and active components (transistors). However, process deviations in the manufacturing process of CMOS integrated circuits can cause huge deviations of ±20% or even ±30% in the initial frequency of oscillators in different chips or even different locations on the same chip. At the same time, fluctuations in operating voltage and changes in ambient temperature can significantly change the electrical characteristics of transistors and the parameters of passive components, causing the oscillation frequency to drift with operating conditions. Uncalibrated oscillators cannot meet the frequency accuracy requirements of ±1% to ±5% of modern electronic systems.

[0006] 2. Difficulty in achieving both wide tuning range and high adjustment accuracy: To compensate for frequency deviations caused by PVT variations, oscillators need to have frequency tuning capabilities. However, traditional single adjustment mechanisms present a dilemma: to cover ±30% process deviations, a wide tuning range is required, which usually means a large adjustment step size, making it impossible to achieve high-precision frequency fine-tuning; to achieve high-precision fine-tuning at the kHz level, the tuning range is limited and cannot fully cover the initial frequency distribution caused by process deviations. Existing technologies lack a calibration scheme that simultaneously satisfies both wide range coverage and high-precision adjustment.

[0007] 3. Duty cycle control is difficult and lacks flexibility: Traditional relaxation oscillators use a single asymmetric charging and discharging path. The duty cycle of the output square wave is determined by the ratio of charging time to discharging time. To obtain a precise 50% duty cycle, it is necessary to strictly ensure that the charging current and the net discharging current are equal. In analog circuits, this requires high-precision current mirror matching, which is difficult to achieve and easily affected by component mismatch. In addition, the duty cycle of this structure is a fixed value and cannot be flexibly adjusted according to application requirements.

[0008] Therefore, developing an on-chip relaxation oscillation system and calibration method that can overcome the above-mentioned defects, achieve a wide tuning range, high frequency accuracy, good PVT stability and flexible duty cycle control, and maintain the advantages of low cost, low power consumption and full integration has become an urgent technical problem to be solved in this field. Summary of the Invention

[0009] To address the technical shortcomings of existing on-chip relaxation oscillators, such as poor frequency accuracy, high PVT sensitivity, inability to simultaneously achieve wide tuning range and high precision, and difficulty in duty cycle control, the present invention aims to provide a high-precision, low-temperature drift relaxation oscillator system with a symmetrical dual-path architecture and its calibration method. This system achieves the technical effects of wide-range frequency tuning, high-precision frequency calibration, low PVT sensitivity, and flexible programmable duty cycle, while maintaining the low power consumption and fully integrated characteristics of the oscillator, providing a stable and reliable clock signal for the SoC without the need for an external crystal oscillator.

[0010] The technical solution adopted by the high-precision low-temperature drift relaxation oscillation system with symmetrical dual-path architecture of the present invention is that the high-precision low-temperature drift relaxation oscillation system with symmetrical dual-path architecture includes a symmetrical dual-path relaxation oscillator core architecture, a fine adjustment circuit, a coarse adjustment circuit, and a bandgap reference source module.

[0011] The core architecture of the symmetrical dual-path relaxation oscillator consists of a pair of cross-coupled relaxation comparators, a shared bias module, and an RS latch. The two paths of the relaxation comparators share a timing capacitor or two matched timing capacitors and operate in complementary phases. While one path charges the capacitor, the other path discharges synchronously.

[0012] The bandgap reference source module provides a temperature-independent reference current to the bias module and a temperature-independent reference voltage to the fine adjustment circuit;

[0013] The coarse adjustment circuit is connected to the bias module and is used to adjust the constant current charging and discharging bias current.

[0014] The fine adjustment circuit is connected to the relaxation comparator and is used to adjust the reference voltage of the relaxation comparator.

[0015] Furthermore, the fine adjustment circuit is an 8-bit digital-controlled analog-to-digital converter circuit, with an input 8-bit digital control word OSC_REF_TRIM_DIG<7:0>. This digital control word is divided into high 4 bits and low 4 bits, which are respectively input to two independent 4-to-16 decoders. The fine adjustment circuit adopts a segmented resistor ladder structure, including a main resistor string and a secondary resistor string. The output of the high 4 bits of the decoder controls the main resistor string switch to select a coarse voltage range, and the output of the low 4 bits of the decoder controls the secondary resistor string switch to select a precise tap point. Finally, a high-resolution reference voltage VREF_CMP is output.

[0016] Furthermore, the voltage adjustment step size of the fine adjustment circuit is 1mV / step. By adjusting the reference voltage VREF_CMP, the upper threshold voltage VH and the lower threshold voltage VL of the relaxation comparator are changed, thereby fine-tuning the capacitor charging and discharging time to achieve high-precision frequency adjustment. The frequency adjustment accuracy is 30~50kHz / step.

[0017] Furthermore, the coarse adjustment circuit is a 3-bit digital control circuit. It inputs a 3-bit digital control word OSC_RES_TRIM_DIG<2:0> and changes the mirror ratio or bias resistor of the current mirror by controlling the switch array to achieve 8 different current bias levels. The frequency adjustment step size of the coarse adjustment circuit is 2 to 3 MHz / step, which is used to compensate for the large frequency drift caused by process deviations.

[0018] Furthermore, in the core architecture of the symmetrical dual-path relaxation oscillator, the charging and discharging rates of the two relaxation comparator paths are controlled by the constant current source of the bias module. Under the nominal design, the charging current and discharging current of the two paths are equal in magnitude, so that the rise and fall times of the capacitor voltage are consistent, and the output is a square wave signal with a duty cycle of 50%.

[0019] Furthermore, by independently adjusting the current mirror ratio that controls the magnitude of the charging current and the discharging current in the paths of the two relaxation comparators, the ratio of the capacitor charging time Tcharge to the discharging time Tdischarge is changed, thereby achieving a programmable duty cycle pulse waveform output.

[0020] Furthermore, the bandgap reference source module is designed with temperature compensation, and its output reference current and reference voltage remain stable within the operating temperature range. This eliminates the temperature dependence of the constant current charging and discharging current source Ibias and the reference voltage VREF_CMP, which determine the oscillation frequency, and realizes the low temperature drift characteristic of the oscillator.

[0021] Furthermore, the system's output frequency tuning range covers the SS process corner: 8.5MHz to 29.93MHz, the TT process corner: 10.69MHz to 37.62MHz, and the FF process corner: 13.86MHz to 48.32MHz. It also achieves calibration to the target frequency of 18MHz while retaining adjustment margin at each process corner.

[0022] The calibration method for the above-mentioned high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture includes the following steps:

[0023] S1. The system acquires the initial operating parameters of the relaxation oscillator and determines the initial frequency value of the oscillator based on the initial operating parameters;

[0024] S2. The coarse adjustment circuit performs coarse adjustment calibration based on the initial frequency deviation, adjusting the frequency of the oscillator to a first preset range of the target frequency value;

[0025] S3. Based on the frequency value after coarse adjustment calibration and the remaining deviation, the fine adjustment circuit performs fine adjustment calibration to further adjust the frequency of the oscillator to a second preset range of the target frequency value.

[0026] S4. Based on the finely tuned and calibrated frequency value, the bandgap reference source module performs temperature compensation calibration to reduce the impact of ambient temperature changes on the oscillator frequency.

[0027] S5. Based on the frequency value after temperature compensation calibration, the system adjusts the ratio of charging current and discharging current and performs duty cycle adjustment to meet the needs of specific application scenarios.

[0028] S6. Based on the signal characteristics after duty cycle adjustment, the system performs frequency stability verification to ensure the oscillator's performance under various operating conditions.

[0029] S7. Based on the frequency stability verification results, generate the final calibration configuration and store it for long-term use of the oscillator.

[0030] Furthermore, in step S2, the constant current charge-discharge bias current Ibias is adjusted by inputting the 3-bit digital control word OSC_RES_TRIM_DIG<2:0> through the coarse adjustment circuit, so as to quickly pull the oscillator output frequency back to near the target frequency and compensate for the large frequency drift caused by process deviation.

[0031] In step S3, the reference voltage VREF_CMP of the relaxation comparator is adjusted by inputting the 8-bit digital control word OSC_REF_TRIM_DIG<7:0> through the fine adjustment circuit, and the capacitor charging and discharging time is finely adjusted to accurately calibrate the oscillator output frequency to the target frequency.

[0032] The beneficial effects of this invention are as follows: This invention employs a symmetrical dual-path charging and discharging system to achieve a natural 50% duty cycle, and uses current mirror proportional adjustment to achieve a programmable duty cycle, solving the problem of difficult duty cycle control in traditional structures; it designs a coarse and fine dual-mode digital calibration circuit, enabling wide-range frequency coverage with coarse tuning and high-precision frequency fine-tuning with fine tuning, solving the problem of balancing wide tuning range and high adjustment accuracy; it utilizes a temperature-compensated bandgap reference source to provide a temperature-independent reference for core parameters, suppressing the influence of PVT variations at the source, achieving high accuracy and low temperature drift characteristics; all circuit modules adopt a fully integrated design, requiring no external crystal oscillator or passive components, maintaining the advantages of low power consumption and low cost. This invention achieves the following significant technical effects:

[0033] 1. Achieving a balance between wide tuning range and high adjustment accuracy.

[0034] This invention solves the dilemma of traditional single-mode adjustment through a coarse and fine dual-mode calibration mechanism: the 3-bit coarse adjustment circuit achieves large step size adjustment of 2-3MHz / step by adjusting the bias current, covering a wide frequency range of 8.5MHz-29.93MHz for the SS process corner, 10.69MHz-37.62MHz for the TT process corner, and 13.86MHz-48.32MHz for the FF process corner, ensuring that the target frequency is within the adjustable range at each process corner; the 8-bit fine adjustment circuit achieves high-precision fine adjustment of 30-50kHz / step through a segmented resistor ladder DAC, so that the final output frequency accuracy of the oscillator meets the requirements of ±1% to ±5% of modern electronic systems. The combination of coarse and fine adjustments first quickly compensates for large-range process deviations through coarse adjustment, and then achieves precise calibration through fine adjustment, thus balancing a wide tuning range and high adjustment accuracy.

[0035] 2. Significantly reduces the impact of PVT variations on frequency, improving frequency stability.

[0036] For process deviations, the coarse adjustment circuit can cover ±30% of the initial frequency deviation, and can accurately calibrate the frequency to the target value of 18MHz while retaining adjustment margin under three process angles: SS, TT, and FF. For voltage and temperature changes, this invention eliminates the dependence of core parameters at the source through the bandgap reference source module. The oscillation frequency F is proportional to Ibias and inversely proportional to the threshold voltage difference determined by VREF_CMP. The bandgap reference source provides a stable reference after temperature compensation for Ibias and VREF_CMP, so that the capacitor charging and discharging slope and comparator threshold remain constant when voltage and temperature change, ultimately achieving low sensitivity of the oscillator to PVT changes.

[0037] 3. Achieve precise control and flexible adjustment of duty cycle.

[0038] Traditional single-path asymmetric architectures require high-precision current mirror matching to achieve a 50% duty cycle. However, the symmetrical dual-path charging and discharging path of this invention has naturally equal charging and discharging currents under nominal design, and the capacitor charging and discharging times are consistent. It can output a precise 50% duty cycle square wave without additional current mirror calibration. At the same time, by independently adjusting the current mirror ratio of the two paths, the ratio of charging and discharging times can be flexibly changed to achieve pulse waveform output with arbitrary programmable duty cycles, which greatly improves the functionality and applicability of the oscillator and meets the clock duty cycle requirements of different SoC modules.

[0039] 4. Achieve ultra-low temperature drift characteristics

[0040] The low-temperature drift characteristic of this invention stems from the temperature compensation design of the bandgap reference source and the temperature independence of the core parameters. Within a wide operating temperature range of -40℃ to 130℃, the maximum rate of change of the oscillator output frequency relative to 27℃ is only 0.27%, far superior to traditional relaxation oscillators. The principle is as follows: the reference current and reference voltage output by the bandgap reference source exhibit minimal fluctuations throughout the entire temperature range, keeping Ibias and VREF_CMP stable. The charging and discharging rate of the capacitor and the threshold voltage of the comparator show no significant temperature drift, ultimately ensuring the temperature stability of the oscillation frequency.

[0041] 5. Maintain the advantages of full integration, low power consumption, and low cost.

[0042] All modules of this invention adopt a fully integrated design using standard CMOS technology, eliminating the need for external crystal oscillators, external resistors / capacitors, and other passive components, effectively reducing chip area and cost. Meanwhile, the symmetrical architecture and digital calibration circuit both adopt a low-power design, which reduces the overall power consumption of the system compared to external crystal oscillator solutions, making it more suitable for portable, low-power SoC applications.

[0043] 6. Provide a reliable on-chip clock solution for SoC

[0044] The oscillator system of this invention can achieve high-precision and high-stability clock signal output without the need for an external crystal oscillator, solving the problems of high cost and low integration of external crystal oscillators. At the same time, it overcomes many defects of traditional on-chip oscillators, providing a reliable, cost-effective and highly integrated on-chip clock generation solution for SoCs, which can be widely used in various integrated circuits and on-chip systems. Attached Figure Description

[0045] Figure 1 This is a circuit diagram illustrating the core architecture of the symmetrical dual-channel relaxation oscillator of the present invention.

[0046] Figure 2 This is a circuit diagram illustrating the principle structure of the fine adjustment circuit module of the present invention.

[0047] Figure 3 This is a circuit diagram illustrating the principle structure of the coarse adjustment circuit module of the present invention.

[0048] Figure 4 This is the fine-tuning frequency step diagram of the present invention (TT, 25℃, RES_TRIM=3);

[0049] Figure 5 This is a line graph showing the effect of temperature change on the output frequency of the present invention (RES=5, REF=63, TT).

[0050] Figure 6 This is a line graph (TT) showing the effect of temperature change on the output voltage of the bandgap reference source according to the present invention.

[0051] Explanation of reference numerals in the attached figures:

[0052] Figure 2 In the diagram: DVDD—Power supply voltage, LVSS—Ground, VREF_BIAS—Bandgap reference voltage, RES1—Main resistor string, RES2—Secondary resistor string, Decoder_4to16—4-to-16 decoder, VREF_CMP—Comparator reference voltage;

[0053] Figure 3 In Chinese: TRIM—Digital control word input, Ibias—Bias current output. Detailed Implementation

[0054] The following detailed description, in conjunction with the accompanying drawings and specific test data, illustrates the high-precision low-temperature drift relaxation oscillation system and its calibration method based on the symmetrical dual-path architecture of the present invention. This embodiment is only used to explain the present invention and is not intended to limit the scope of protection of the present invention.

[0055] Example 1: Hardware Structure of a High-Precision Low-Temperature Drift Relaxation Oscillation System with Symmetrical Dual-Path Architecture

[0056] like Figure 1 As shown, the oscillation system in this embodiment includes a symmetrical dual-path relaxation oscillator core architecture, a fine adjustment circuit, a coarse adjustment circuit, and a bandgap reference source module. The symmetrical dual-path relaxation oscillator core architecture consists of a pair of cross-coupled relaxation comparators, a shared bias module, and an RS latch. The two relaxation comparator paths share a timing capacitor or two matched timing capacitors and operate in complementary phases, with one path charging the capacitor while the other path discharges synchronously. The bandgap reference source module provides a temperature-independent reference current to the bias module and a temperature-independent reference voltage to the fine adjustment circuit. The coarse adjustment circuit is connected to the bias module and is used to adjust the constant current charging and discharging bias current. The fine adjustment circuit is connected to the relaxation comparators and is used to adjust the reference voltage of the relaxation comparators. Figure 1 In the middle: two symmetrical analog comparators form a cross-coupled relaxation comparator; the constant current source supplying the charging and discharging current in the middle and the current mirror array form a shared bias module; the logic gate unit on the right forms an RS latch; the capacitor symbol in the charging and discharging path is a timing capacitor; the low temperature drift reference unit on the far left is a bandgap reference source module; the coarse adjustment circuit is located next to the bias module, and the fine adjustment circuit is located next to the relaxation comparator.

[0057] The connection relationships and working methods of each module are as follows:

[0058] like Figure 1 As shown, the core architecture of the symmetrical dual-path relaxation oscillator consists of cross-coupled relaxation comparators, a shared bias module, an RS latch, and a timing capacitor. The two paths of the relaxation comparators operate in complementary phase: when one path charges the capacitor, the other path discharges it synchronously, and vice versa. The charging and discharging rates of both paths are precisely controlled by the constant current source of the bias module. Under nominal design, the charging current Icharge = discharging current Idischarge, ensuring that the capacitor voltage rise (charging) and fall (discharging) times are completely synchronized, naturally generating an 18MHz square wave output signal with a 50% duty cycle. The RS latch shapes the comparator's output signal into a square wave clock signal.

[0059] Meanwhile, by independently adjusting the current mirror ratio that controls the magnitude of the charging current and the discharging current in the two paths, the ratio of the charging time Tcharge to the discharging time Tdischarge can be precisely changed, realizing a programmable duty cycle pulse waveform output to meet the duty cycle requirements of different applications.

[0060] like Figure 2As shown, to achieve high-precision adjustment of the oscillation frequency, an 8-bit digitally controlled fine adjustment circuit is set up. Essentially a digital-to-analog converter (DAC), its core function is to generate a high-resolution reference voltage VREF_CMP for the relaxation comparator. The fine adjustment circuit adopts an 8-bit digital control + segmented resistor ladder structure, with inputs OSC_REF_TRIM_DIG<7:0> (range 0-255). This control word is divided into high 4 bits (MSB) and low 4 bits (LSB), which are input to two independent 4-to-16 decoders. The high 4 bits control the main resistor string RES1 to select the coarse voltage range, and the low 4 bits control the secondary resistor string RES2 to select the precise tap point. The output VREF_CMP is sent to the relaxation comparator. The segmented resistor ladder structure includes a main resistor string (RES1) and a secondary resistor string (RES2). The output of the high 4 bits of the decoder controls the switches on the main resistor string, selecting and generating a coarse voltage range applied across the secondary resistor string. The output of the low 4 bits of the decoder finely controls the switch array inside the secondary resistor string, selecting the precise tap point within this voltage range, and finally outputting a high-resolution reference voltage VREF_CMP. By changing VREF_CMP, the upper and lower threshold voltages VH and VL of the relaxation comparator can be precisely adjusted, thereby fine-tuning the charging and discharging time of the capacitor, achieving small-step, high-precision frequency control. The voltage adjustment step size of this circuit is approximately 1mV / step, and the frequency adjustment accuracy reaches 30–50kHz / step.

[0061] like Figure 3 As shown, to compensate for the large-scale drift of the center frequency caused by process deviations, a coarse adjustment circuit with 3-bit digital control is set up. Its core function is to perform segmented adjustment of the constant current charging / discharging current source (Ibias) of the oscillator core through the 3-bit digital control word OSC_RES_TRIM_DIG<2:0>. The coarse adjustment circuit changes the mirror ratio of the current mirror or the bias resistor by controlling the switch array. The 3-bit control word can select 8 different current bias levels. Since the oscillation frequency is approximately inversely proportional to the charging / discharging time, and the charging / discharging time is inversely proportional to the bias current, adjusting the bias current can directly and effectively change the oscillation frequency, achieving large-step frequency adjustment. Its frequency adjustment step size is approximately 2–3 MHz / step (under the TT process corner), which can quickly pull the oscillation frequency back to near the target frequency, covering the frequency deviation of tens of MHz caused by the process corner.

[0062] To achieve the low temperature drift characteristic of the oscillator, a temperature-compensated bandgap reference source module (BGR) is incorporated. This module provides a temperature-independent reference current to the bias module and a temperature-independent reference voltage to the fine-tuning circuit, ensuring that the two core parameters determining the oscillation frequency—the constant current charge / discharge current source Ibias and the reference voltage VREF_CMP of the relaxation comparator—remain highly stable across the entire operating temperature range. The bandgap reference source module is connected to the bias module and the fine-tuning circuit, outputting temperature-compensated reference current and voltage to provide stable references for Ibias and VREF_CMP, with an operating temperature range of -40℃ to 130℃.

[0063] The oscillation system in this embodiment adopts a fully integrated design using standard CMOS technology, with no external components, small chip area, and low power consumption, making it suitable for on-chip clock generation in SoCs.

[0064] This invention also provides a calibration method for the above system, which employs a combination of coarse and fine dual-mode calibration, specifically as follows:

[0065] Coarse adjustment calibration - Input the 3-digit digital control word OSC_RES_TRIM_DIG<2:0>, and adjust the constant current charge and discharge bias current Ibias through the coarse adjustment circuit. In a step size of 2 to 3 MHz, the oscillator output frequency is quickly pulled back to near the target frequency to compensate for the large frequency drift caused by process deviation.

[0066] Fine-tuning calibration: Input the 8-bit digital control word OSC_REF_TRIM_DIG<7:0>, adjust the reference voltage VREF_CMP through the fine-tuning circuit, and fine-tune the capacitor charging and discharging time with an accuracy of 30 to 50 kHz / step to accurately calibrate the oscillator output frequency to the target frequency;

[0067] Low temperature drift protection – The bandgap reference source module continuously provides temperature-independent reference current and reference voltage to the bias module and fine adjustment circuit throughout the entire calibration and operation process, eliminating the temperature dependence of Ibias and VREF_CMP from the source and suppressing the influence of temperature and voltage changes on the oscillation frequency.

[0068] Example 2 Frequency calibration test of oscillation system

[0069] This embodiment performs frequency calibration tests on the oscillation system of Embodiment 1. The test conditions are 25℃ and the target frequency is 18MHz. The adjustment accuracy of coarse and fine adjustment and the calibration effect under each process angle are tested respectively.

[0070] 1. Fine-tuning accuracy test: With the coarse adjustment control word OSC_RES_TRIM_DIG=3 (TT process angle) fixed, the fine adjustment control word OSC_REF_TRIM_DIG<7:0> was adjusted. The test results are shown in Table 1 and... Figure 4As shown, each change of 1 in the fine-tuning control word results in a frequency change of 0.03 to 0.05 MHz (i.e., 30 to 50 kHz per step), consistent with the design value, achieving high-precision fine-tuning.

[0071] Table 1. Fine-tuning control word adjustment accuracy test (OSC_RES_TRIM_DIG=3, TT, 25℃)

[0072] REF_TRIM<7:0> Freq(MHz) Delta (MHz) 103 17.94 - 104 17.98 0.04 105 18.01 0.03 106 18.05 0.04 107 18.08 0.03 108 18.11 0.03 109 18.15 0.04 110 18.18 0.03 111 18.23 0.05 112 18.27 0.04

[0073] 2. Uncalibrated frequency test for each process corner: The uncalibrated frequencies of the SS, TT, and FF process corners were tested under different coarse and fine adjustment control words. The results are shown in Table 2. Process deviations caused significant differences in uncalibrated frequencies. For example, when RES=0 and REF=255, the frequency of the SS process corner was 14.55MHz and that of the FF process corner was 23.56MHz, with a deviation of 62%.

[0074] Table 2 Output Frequency Control Word Settings (25℃)

[0075] Control words (coarse code, fine code) SS(MHz) TT (MHz) FF (MHz) (0,255) 14.55 18.23 23.56 (3,255) 20.27 25.36 32.74 (7,255) 29.77 37.17 47.85 (0,128) 10.77 13.51 17.49 (3,128) 15.05 18.86 24.39 (7,128) 22.14 27.73 35.80

[0076] 3. Control word setting for each process corner to calibrate to 18MHz: By coarse and fine adjustment, the corresponding control word can be selected under each process corner to accurately calibrate the frequency to 18MHz. The results are shown in Table 3, which proves that the calibration system of the present invention can effectively compensate for process deviations.

[0077] Table 3 Output 18MHz control word settings (25℃)

[0078] Control words (coarse code, fine code) SS(MHz) TT (MHz) FF (MHz) (0,251) - 18.03 - (0,148) - - 17.96 (7,30) 18.05 - -

[0079] Example 3 Temperature Drift Test of Oscillating System

[0080] This embodiment performs a temperature drift test on the oscillation system of Embodiment 1. The test conditions are: coarse adjustment control word RES=5, fine adjustment control word REF=63, TT process angle, test temperature range -40℃~130℃, and test frequency change and bandgap reference source output voltage change.

[0081] 1. Frequency temperature drift test: Results are shown in Table 4 and Figure 5 As shown, within the range of -40℃ to 130℃, the oscillator output frequency fluctuates between 18.76MHz and 18.81MHz, with a maximum change rate of only 0.27% relative to 27℃ (18.81MHz), achieving ultra-low temperature drift.

[0082] Table 4. Effect of temperature change on frequency (RES=5, REF=63, TT)

[0083] Temperature (°C) Freq(MHz) Temperature (°C) Freq(MHz) -40 18.76 40 18.81 -30 18.78 50 18.81 -20 18.78 60 18.81 -10 18.79 70 18.81 0 18.80 80 18.80 10 18.81 90 18.80 20 18.81 100 18.79 27 18.81 110 18.78 30 18.81 120 18.77 - - 130 18.76

[0084] 2. Bandgap reference source voltage temperature drift test: Results are shown in Table 5 and Figure 6 As shown, within the temperature range of -40℃ to 130℃, the output voltage of the bandgap reference source fluctuates between 1.45431V and 1.45575V, with a fluctuation range of only 0.00144V. This demonstrates the excellent temperature compensation effect of the bandgap reference source, providing a stable reference for Ibias and VREF_CMP, which is the core reason for the oscillator's low temperature drift.

[0085] Table 5. Effect of Temperature Change on Output Voltage

[0086] Temperature (°C) Voltage (V) Temperature (°C) Voltage (V) -40 1.45461 40 1.45571 -30 1.45474 50 1.45571 -20 1.45491 60 1.45575 -10 1.45509 70 1.45570 0 1.45526 80 1.45560 10 1.45542 90 1.45542 20 1.45554 100 1.45515 30 1.45564 110 1.45477 - - 120 1.45431

[0087] Comparative Example 1: Traditional Single-Channel Asymmetric Relaxation Oscillator

[0088] A traditional single-channel asymmetric architecture relaxation oscillator was selected as Comparative Example 1. Its structure is a single-channel constant current source charging and discharging + Schmitt trigger, using a single bias current adjustment method with an adjustment step size of 1MHz / step, and a reference source without temperature compensation. Its performance was tested under the same process angle and temperature conditions, and compared with Example 1 of the present invention. The results are shown in Table 6.

[0089] Table 6 Performance Comparison of the Invention and Traditional Oscillators

[0090] Performance indicators Embodiment 1 of the present invention Traditional oscillator (Comparative Example 1) Frequency tuning range 8.5MHz~48.32MHz (all process corners) 12MHz~25MHz (TT process corner) Frequency adjustment accuracy 30–50 kHz / step 1MHz / step Process deviation compensation capability Coverage up to ±30%, full process angle calibration up to 18MHz Covering only ±10%, the SS / FF process corner cannot be calibrated to 18MHz. 50% duty cycle accuracy Naturally achieved, with an error of <0.1%. Error >5% requires additional current mirror calibration. Duty cycle flexibility Programmable adjustment Fixed value, not adjustable Temperature drift (-40~130℃) Maximum 0.27% Maximum 8.5% Integration Fully integrated, with no external components External calibration resistor required

[0091] Comparative conclusion: Traditional single-channel asymmetric relaxation oscillators suffer from drawbacks such as narrow tuning range, low adjustment accuracy, weak process deviation compensation capability, low and non-adjustable duty cycle control accuracy, and large temperature drift, failing to meet the clock requirements of modern SoCs. In contrast, the oscillation system of this invention overcomes these drawbacks comprehensively through a symmetrical dual-channel architecture, coarse and fine dual-mode calibration, and a temperature-compensated bandgap reference source, exhibiting significant advantages in frequency accuracy, stability, duty cycle flexibility, and integration.

[0092] Comparative Example 2: Symmetrical Relaxation Oscillator with Single Modulus Calibration

[0093] A symmetrical dual-channel relaxation oscillator using only 8-bit fine-tuning calibration was selected as Comparative Example 2. Its structure is similar to that of the present invention, but it lacks a 3-bit coarse-tuning circuit. Its process deviation compensation capability was tested and compared with Example 1 of the present invention. The results are as follows: The tuning range of Comparative Example 2 is only 16MHz to 20MHz (TT process angle), which cannot cover the low frequency range of the SS process angle and the high frequency range of the FF process angle. It cannot calibrate the frequency to 18MHz under the SS and FF process angles. However, the present invention, through coarse and fine dual-mode calibration, can cover a wide frequency range across the entire process angle and can accurately calibrate to the target frequency.

[0094] Comparative conclusion: A single high-precision fine-tuning circuit cannot compensate for the large-range frequency drift caused by process deviations, while the coarse and fine dual-mode calibration mechanism of this invention is the key to achieving both a wide tuning range and high adjustment accuracy, and neither can be omitted.

[0095] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture, characterized in that, The system includes a symmetrical dual-channel relaxation oscillator core architecture, fine adjustment circuit, coarse adjustment circuit, and bandgap reference source module; The core architecture of the symmetrical dual-path relaxation oscillator consists of a pair of cross-coupled relaxation comparators, a shared bias module, and an RS latch. The two paths of the relaxation comparators share a timing capacitor or two matched timing capacitors and operate in complementary phases. While one path charges the capacitor, the other path discharges synchronously. The bandgap reference source module provides a temperature-independent reference current to the bias module and a temperature-independent reference voltage to the fine adjustment circuit; The coarse adjustment circuit is connected to the bias module and is used to adjust the constant current charging and discharging bias current. The fine adjustment circuit is connected to the relaxation comparator and is used to adjust the reference voltage of the relaxation comparator.

2. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 1, characterized in that, The fine adjustment circuit is an 8-bit digital-controlled analog-to-digital converter circuit. It receives an 8-bit digital control word, OSC_REF_TRIM_DIG<7:0>, which is divided into high 4 bits and low 4 bits, each input to two independent 4-to-16 decoders. The fine adjustment circuit employs a segmented resistor ladder structure, including a main resistor string and a secondary resistor string. The output of the high 4 bits of the decoder controls the main resistor string switch to select a coarse voltage range, while the output of the low 4 bits controls the secondary resistor string switch to select a precise tap point. The final output is a high-resolution reference voltage, VREF_CMP.

3. The high-precision low-temperature drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 2, characterized in that, The voltage adjustment step size of the fine adjustment circuit is 1mV / step. By adjusting the reference voltage VREF_CMP, the upper and lower threshold voltages VH and VL of the relaxation comparator are changed, thereby fine-tuning the capacitor charging and discharging time to achieve high-precision frequency adjustment with a frequency adjustment accuracy of 30-50kHz / step.

4. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 1, characterized in that, The coarse adjustment circuit is a 3-bit digital control circuit. It inputs a 3-bit digital control word OSC_RES_TRIM_DIG<2:0> and changes the mirror ratio or bias resistor of the current mirror by controlling the switch array to achieve 8 different current bias levels. The frequency adjustment step size of the coarse adjustment circuit is 2 to 3 MHz / step, which is used to compensate for the large frequency drift caused by process deviations.

5. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 1, characterized in that, In the core architecture of the symmetrical dual-path relaxation oscillator, the charging and discharging rates of the two relaxation comparator paths are controlled by the constant current source of the bias module. Under the nominal design, the charging current and discharging current of the two paths are equal in magnitude, so that the rise and fall times of the capacitor voltage are consistent, and the output is a square wave signal with a duty cycle of 50%.

6. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 5, characterized in that, By independently adjusting the current mirror ratio that controls the magnitude of the charging current and discharging current in the paths of the two relaxation comparators, the ratio of the capacitor charging time Tcharge to the discharging time Tdischarge is changed, thereby achieving a programmable duty cycle pulse waveform output.

7. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to claim 1, characterized in that, The bandgap reference source module is designed with temperature compensation, and its output reference current and reference voltage remain stable within the operating temperature range. This eliminates the temperature dependence of the constant current charging and discharging current source Ibias and the reference voltage VREF_CMP, which determine the oscillation frequency, and realizes the low temperature drift characteristic of the oscillator.

8. The high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture according to any one of claims 1 to 7, characterized in that, The system's output frequency tuning range covers the SS process corner: 8.5MHz to 29.93MHz, the TT process corner: 10.69MHz to 37.62MHz, and the FF process corner: 13.86MHz to 48.32MHz. It also achieves calibration to the target frequency of 18MHz at each process corner while retaining adjustment margin.

9. A calibration method for a high-precision cryogenic drift relaxation oscillation system with a symmetrical dual-path architecture as described in claim 8, characterized in that, The method includes the following steps: S1. The system acquires the initial operating parameters of the relaxation oscillator and determines the initial frequency value of the oscillator based on the initial operating parameters; S2. The coarse adjustment circuit performs coarse adjustment calibration based on the initial frequency deviation, adjusting the frequency of the oscillator to a first preset range of the target frequency value; S3. Based on the frequency value after coarse adjustment calibration and the remaining deviation, the fine adjustment circuit performs fine adjustment calibration to further adjust the frequency of the oscillator to a second preset range of the target frequency value. S4. Based on the finely tuned and calibrated frequency value, the bandgap reference source module performs temperature compensation calibration to reduce the impact of ambient temperature changes on the oscillator frequency. S5. Based on the frequency value after temperature compensation calibration, the system adjusts the ratio of charging current and discharging current and performs duty cycle adjustment to meet the needs of specific application scenarios. S6. Based on the signal characteristics after duty cycle adjustment, the system performs frequency stability verification to ensure the oscillator's performance under various operating conditions. S7. Based on the frequency stability verification results, generate the final calibration configuration and store it for long-term use of the oscillator.

10. The method according to claim 9, characterized in that, In step S2, the 3-bit digital control word OSC_RES_TRIM_DIG<2:0> is input through the coarse adjustment circuit to adjust the constant current charge and discharge bias current Ibias, so as to quickly pull the oscillator output frequency back to near the target frequency and compensate for the large frequency drift caused by process deviation. In step S3, the reference voltage VREF_CMP of the relaxation comparator is adjusted by inputting the 8-bit digital control word OSC_REF_TRIM_DIG<7:0> through the fine adjustment circuit, and the capacitor charging and discharging time is finely adjusted to accurately calibrate the oscillator output frequency to the target frequency.

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