A circuit for optimizing the input high-level threshold voltage of a level shifting circuit.

Abstract

This invention discloses a circuit for optimizing the input high-level threshold voltage of a level conversion circuit, comprising resistors R2, R3, and R4, NMOS transistors M4, M5, M6, M7, M8, M9, and M10, a capacitor C1, and a shunt circuit. This invention can significantly improve Vih performance while achieving compatibility with pull-pull and open-drain communication, and the overall solution has a very low power consumption and area cost.

Description

Technical Field

[0001] This invention relates to an optimized circuit, and more particularly to a circuit that optimizes the input high-level threshold voltage of a level conversion circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Level conversion chips / devices are widely used in numerous fields such as chips, integrated circuits, consumer electronics, communications, industrial control, and the Internet of Things. Their core advantage lies in their ability to efficiently adapt to signal conversion requirements between different voltage domains, solving key issues in system interconnection. The input high-level threshold voltage (Vih) refers to the minimum allowed input high level to ensure a logic gate's input is high. Vih is one of the core parameters of a level conversion chip. When the input level is higher than Vih, the level conversion chip recognizes it as a high level and performs the corresponding level conversion operation. In practical applications, circuit architecture, process technology, temperature changes, and power supply voltage fluctuations can all affect this parameter, thus impacting communication reliability.

[0003] Figure 2 and Figure 3 It is a common level shifter architecture. Figure 2 The medium architecture is primarily suitable for push-pull IO communication. Figure 3 The medium architecture is compatible with both pull-pull and open drain; the main difference between the two is whether there is a switching tube. Figure 3 The middle channel switch is connected, and this switch is usually an NMOS device, therefore Figure 3 The architecture in this model has greater applicability. Typically, in low-to-high conversion applications (VCCA is low level), Vih is less than 0.7*VCCA, where VCCA is the high-level voltage of the I / O input. Compared to... Figure 2 The architecture in Figure 3 In mid-architecture circuits, due to the presence of the switching NMOS transistors, Vih is typically limited to VG-VTHN, where VG is the gate bias voltage of the switching NMOS transistor, and VTHN is the threshold voltage of the switching NMOS transistor. Currently, the common VG bias scheme ensures that VG always equals VCCA after the chip is enabled. However, because VTHN varies significantly with process technology and temperature, conventional schemes struggle to meet the requirement of Vih being less than 0.7*VCCA under PVT conditions. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a circuit that optimizes the input high-level threshold voltage of the level conversion circuit, so as to achieve compatibility with pull-pull and open drain communication while significantly improving Vih performance.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A circuit for optimizing the input high-level threshold voltage of a level shifting circuit includes resistors R2, R3, and R4, NMOS transistors M4, M5, M6, M7, M8, M9, and M10, a capacitor C1, and a shunt circuit. One end of resistor R2 and the source of PMOS transistor M8 are connected to the power supply VCCB. The other end of resistor R2 is connected to the input terminal of the shunt circuit and one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the gate of NMOS transistor M4. The other end of resistor R4 is connected to the drain of NMOS transistor M4 and the gate of NMOS transistor M9. The source of NMOS transistor M4... The source of NMOS transistor M5 is connected to the drain of NMOS transistor M5, the gate of NMOS transistor M5, and the gate of NMOS transistor M6. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to the drain of NMOS transistor M7, the gate of NMOS transistor M7, and the gate of NMOS transistor M10. The gate of PMOS transistor M8 is connected to the enable signal OE. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10 and one end of capacitor C1 to generate voltage VB to the gate of switching transistor M11. The source of NMOS transistor M7, the source of NMOS transistor M10, and the other end of capacitor C1 are grounded.

[0006] Furthermore, the shunt circuit includes a resistor R1, a PMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M3. One end of the resistor R1 is connected to the power supply VCCA, and the other end of the resistor R1 is connected to the gate of the PMOS transistor M1. The source of the PMOS transistor M1 serves as the input terminal of the shunt circuit. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2, the gate of the NMOS transistor M2, and the gate of the NMOS transistor M3. The source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded.

[0007] Furthermore, the drain of the switching transistor M11 is connected to one end of resistor R5, and the other end of resistor R5 is connected to node A. The source of the switching transistor M11 is connected to one end of resistor R6, and the other end of resistor R6 is connected to node B.

[0008] Furthermore, the NMOS transistors M7 and M10 constitute an NMOS current mirror.

[0009] Furthermore, the NMOS transistors M7 and M10 are low threshold voltage NMOS transistors, with threshold voltages of 200mV to 400mV.

[0010] Further, the resistors R2 and R3 are megaohm-level resistors, such that the current flowing through the NMOS transistors M4 to M7 is at the microamp level.

[0011] Further, the NMOS transistors M4 to M7 are large-sized NMOS transistors, such that the overdrive voltages of the NMOS transistors M4, M6, and M7 are in the range of several tens of mV.

[0012] Further, the variation range of the power supply VCCA is 0.72V to 1.98V.

[0013] Further, the variation range of the power supply VCCB is 1.62V to 3.63V.

[0014] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a circuit for optimizing the input high-level threshold voltage of a level conversion circuit. The voltage of VB is always maintained within the range of VTHN + VOV < VB < VTHN + m * VCCI. The one-shot circuit at port B only needs to be able to drive the subsequent load, without considering the situation where the input source needs to be driven simultaneously through M11 due to the conduction of M11. Therefore, the Vih index is greatly improved. The present invention can achieve compatibility with pull-pull and open drain communications while significantly improving the Vih performance, and at the same time, the overall power consumption / area cost of the solution is very small. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a circuit for optimizing the input high-level threshold voltage of a level conversion circuit according to the present invention.

[0016] Figure 2 is a schematic diagram of a level shifter architecture suitable for push-pull IO communication in the prior art.

[0017] Figure 3 is a schematic diagram of a level shifter architecture compatible with pull-pull and open drain in the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. And, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0019] As Figure 1 As shown, the present invention provides a circuit for optimizing the input high-level threshold voltage of a level conversion circuit, comprising resistors R2, R3, and R4, NMOS transistors M4, M5, M6, M7, M8, M9, and M10, capacitor C1, and a shunt circuit. One end of resistor R2 and the source of PMOS transistor M8 are connected to the power supply VCCB. The other end of resistor R2 is connected to the input terminal of the shunt circuit and one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the gate of NMOS transistor M4. The other end of resistor R4 is connected to the drain of NMOS transistor M4 and the gate of NMOS transistor M9. The source of transistor 4 is connected to the drain, gate, and gate of NMOS transistor M5 and NMOS transistor M6. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to the drain, gate, and gate of NMOS transistor M7 and NMOS transistor M10. The gate of PMOS transistor M8 is connected to the enable signal OE. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10 and one end of capacitor C1 to generate voltage VB for the gate of switching transistor M11. The source of NMOS transistor M7, the source of NMOS transistor M10, and the other end of capacitor C1 are grounded.

[0020] The shunt circuit includes a resistor R1, a PMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M3. One end of the resistor R1 is connected to the power supply VCCA, and the other end of the resistor R1 is connected to the gate of the PMOS transistor M1. The source of the PMOS transistor M1 serves as the input terminal of the shunt circuit. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2, the gate of the NMOS transistor M2, and the gate of the NMOS transistor M3. The source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded.

[0021] The drain of the switching transistor M11 is connected to one end of resistor R5, and the other end of resistor R5 is connected to node A. The source of the switching transistor M11 is connected to one end of resistor R6, and the other end of resistor R6 is connected to node B.

[0022] NMOS transistors M7 and M10 form an NMOS current mirror. NMOS transistors M7 and M10 are low threshold voltage NMOS transistors, with a threshold voltage of 200mV~400mV.

[0023] Resistors R2 and R3 are megohm-level resistors, ensuring that the current flowing through NMOS transistors M4 to M7 is in the μA range.

[0024] The use of large-size NMOS transistors in NMOS transistors M4 to M7 results in overdrive voltages of tens of mV for NMOS transistors M4, M6, and M7.

[0025] The voltage range of power supply VCCA is 0.72V to 1.98V. The voltage range of power supply VCCB is 1.62V to 3.63V.

[0026] The working principle of the circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to the present invention is as follows: The main objective of this invention is to maintain the following even when the process temperature and power supply VCCA and VCCB are arbitrarily varied: VTHN+VOV <VB<VTHN + m*VCCI Wherein, VTHN is the threshold voltage of NMOS transistors M2, M3, M4, M5, M6 and M11 in the circuit, VTHN + VOV refers to the minimum voltage that can maintain the linear conduction of switch M11 (since the maximum current flowing through switch M11 is fixed and the size of switch M11 is fixed, VOV is equal to 200mV in this embodiment), m*VCCI is Vih, where m is taken as 0.6 in this embodiment, VCCI refers to the logic high level voltage of the input port. For example, when port A is the input port, VCCI is equal to VCCA, and when port B is the input port, VCCI is equal to VCCB.

[0027] The gate voltage of NMOS transistor M9 is equal to VGS7 + VGS6 + VGS4 - I_R4 * R4, where I_R4 is the current flowing through resistor R4, and I_R4 is equal to I_R2 - I_M1, where I_R2 is the current flowing through resistor R2, and I_M1 is the current flowing through PMOS transistor M1.

[0028] When PMOS transistor M1 is not conducting (i.e., when the voltage difference between power supply VCCB and VCCA is small), I_R3 equals I_R2. The value of I_R2 mainly depends on the voltage of power supply VCCB, the resistance values ​​of resistors R2 and R3, and the dimensions of NMOS transistors M4~M7.

[0029] When PMOS transistor M1 is turned on (i.e., when the voltage difference between power supply VCCB and VCCA is large, especially when the power supply VCCA voltage is low), PMOS transistor M1 shunts part of the current flowing through resistor R2, thereby clamping the voltage between resistors R2 and R3, thus reducing I_R3, and thus reducing the VB voltage. This ensures that the circuit maintains the VB voltage no more than VTHN + m*VCCA when the power supply VCCA voltage is relatively low and the power supply VCCB voltage is relatively high, thereby satisfying Vih at node A.

[0030] The voltage of the gate of NMOS transistor M9 is approximately equal to 2*VTHN + VGS7 + VX, and then the VB voltage is VTHN + VGS7 + VY. Here, VX is the sum of the overdrive voltages of NMOS transistors M7, M6, and M4 minus I_R4*R4 (the presence of resistor R4 reduces the VB voltage when the power supply VCCB voltage is high, resulting in an increase in the current flowing through NMOS transistors M4 to M7, thereby reducing the sensitivity of VB to changes in VCCB), and VY is equal to VX minus the overdrive voltage of NMOS transistor M9. In practical applications, NMOS transistors M7 and M10 are low-threshold voltage NMOS transistors, and their threshold voltages vary between 200 mV and 400 mV; in addition, resistors R2 and R3 are megaohm resistors, so the current flowing through NMOS transistors M4 to M7 is only in the μA level. When NMOS transistors M4 to M7 are of a relatively large size, the overdrive voltages of NMOS transistors M4, M6, and M7 are very low, only dozens of mV, so VY can also be controlled to vary within a very small range.

[0031] Other devices not described in the circuit mainly play the role of improving the power-on and power-off reliability of the chip and implementing the enable / disable function of the chip, and will not be described in detail.

[0032] Through the above operations, it can be achieved that under any changes in process temperature and power supplies VCCA and VCCB, the following can be maintained: VTHN + VOV < VB < VTHN + m*VCCI Furthermore, the Vih index under PVT conditions can be satisfied.

[0033] Resistors R2 and R3 mainly play the role of providing DC bias. The resistance values of the two do not need to be particularly precise, and a ±50% change will not affect the actual function of the circuit. Therefore, resistors R2 and R3 can take a smaller length to reduce the area and save costs.

[0034] The present invention provides a circuit for optimizing the input high-level threshold voltage of a level conversion circuit. The voltage of VB is always maintained within the range of VTHN + VOV < VB < VTHN + m*VCCI. The one-shot circuit at port B only needs to be able to drive the subsequent load, and there is no need to consider the situation where the input source needs to be driven simultaneously through M11 due to the conduction of M11. Therefore, the Vih index is greatly improved; the present invention can achieve compatibility with pull-pull and open drain communications while significantly improving the Vih performance, and at the same time, the overall power consumption / area cost of the scheme is very small.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A circuit for optimizing the input high-level threshold voltage of a level conversion circuit, characterized in that: This circuit includes resistors R2, R3, and R4; NMOS transistors M4, M5, M6, and M7; PMOS transistors M8, M9, and M10; capacitor C1; and a shunt circuit. One end of resistor R2 and the source of PMOS transistor M8 are connected to the power supply VCCB. The other end of resistor R2 is connected to the input of the shunt circuit and one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4 and the gate of NMOS transistor M4. The other end of resistor R4 is connected to the drain of NMOS transistor M4 and the gate of NMOS transistor M9. The source of NMOS transistor M4 is connected to the drain of NMOS transistor M5. The gates of NMOS transistors M5 and M6 are connected, the source of NMOS transistor M5 is connected to the drain of NMOS transistor M6, the source of NMOS transistor M6 is connected to the drain of NMOS transistor M7, the gate of NMOS transistor M7 is connected to the gate of NMOS transistor M10, the gate of PMOS transistor M8 is connected to the enable signal OE, the drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9, the source of NMOS transistor M9 is connected to the drain of NMOS transistor M10 and one end of capacitor C1 to generate voltage VB to the gate of switching transistor M11, and the source of NMOS transistor M7, the source of NMOS transistor M10 and the other end of capacitor C1 are grounded.

2. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 1, characterized in that: The shunt circuit includes a resistor R1, a PMOS transistor M1, an NMOS transistor M2, and an NMOS transistor M3. One end of the resistor R1 is connected to the power supply VCCA, and the other end of the resistor R1 is connected to the gate of the PMOS transistor M1. The source of the PMOS transistor M1 serves as the input terminal of the shunt circuit. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M2, the gate of the NMOS transistor M2, and the gate of the NMOS transistor M3. The source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M3, and the source of the NMOS transistor M3 is grounded.

3. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 1, characterized in that: The drain of the switching transistor M11 is connected to one end of resistor R5, and the other end of resistor R5 is connected to node A. The source of the switching transistor M11 is connected to one end of resistor R6, and the other end of resistor R6 is connected to node B.

4. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 1, characterized in that: The NMOS transistors M7 and M10 constitute an NMOS current mirror.

5. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 4, characterized in that: The NMOS transistors M7 and M10 are low threshold voltage NMOS transistors, with threshold voltages ranging from 200mV to 400mV.

6. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 1, characterized in that: The resistors R2 and R3 are megohm-level resistors, so that the current flowing through the NMOS transistors M4 to M7 is in the μA level.

7. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 6, characterized in that: The NMOS transistors M4 to M7 are large-size NMOS transistors, so that the overdrive voltage of NMOS transistors M4, M6 and M7 is tens of mV.

8. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 2, characterized in that: The power supply VCCA varies in the range of 0.72V to 1.98V.

9. The circuit for optimizing the input high-level threshold voltage of the level conversion circuit according to claim 1, characterized in that: The power supply VCCB varies in the range of 1.62V to 3.63V.

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