An IDAC circuit with output current level switchable

Abstract

The application discloses an IDAC circuit with switchable output current grades, which comprises a resistance string module, an interpolation equivalent module, a first-stage BUFFER, a switch S1 and a second-stage BUFFER, the resistance string module outputs a voltage VIH and a voltage VIL to the interpolation equivalent module, the output end of the interpolation equivalent module is connected with the input end of the first-stage BUFFER, the first output end of the first-stage BUFFER is connected with the first input end of the switch S1 and generates a signal V2A, the second output end of the first-stage BUFFER is connected with the second input end of the switch S1 and generates a signal V2B, and the output end of the switch S1 is connected with the input end of the second-stage BUFFER. The application can realize two output current grades of a low current grade and a high current grade, and fully utilize the hardware cost.

Description

Technical Field

[0001] This invention relates to an IDC circuit, and more particularly to an IDC circuit with switchable output current levels, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] An IDAC (current-mode digital-to-analog converter) is a DAC that outputs a current signal. It is suitable for low-impedance or current-sensitive loads and has wide applications in fields such as chips, new energy vehicles, and the Internet of Things.

[0003] Conventional IDC architecture, such as Figure 3 As shown, the specific working principle is as follows: The high-order code controls the resistor string module, outputting voltages VIH and VIL based on the value of the high-order code. The low-order code controls the interpolation equivalent module, outputting an equivalent voltage V_EQ between VIH and VIL based on the value of the low-order code. V_EQ is input to the first-stage buffer circuit composed of op-amps A1, M1, R1, and R2, clamping the voltage drop V1 across R1 to be equal to V_EQ. The voltage value of V1 and the resistance value of R1 determine the current value flowing through resistor R2. This current generates a voltage drop across R2, determining the voltage value V2 at the connection between R2 and the drain terminal of M1. V2 is input to the second-stage buffer circuit composed of op-amps A2, Power MOS, and R3, clamping the voltage value V3 at the connection between R3 and the source terminal of the Power MOS to be equal to V2. When V3 and V2 are equal, the current flowing through R3 is equal to the ratio of R2 to R3 multiplied by the current flowing through R2. The output current of the IDAC is then equal to the current flowing through R3, thus realizing the control of the output current by the input code.

[0004] This type of IDAC architecture only has one output current level. At this current level, the maximum output voltage of the IDAC can reach is PVDD minus the voltage drop across R3 and the absolute value of the Power MOS's VDSat. To ensure a sufficiently large headroom for the output voltage, the Power MOS needs to be large enough. This results in wasted hardware costs, using a large Power MOS but only being able to output a relatively low current range. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an IDAC circuit with switchable output current levels, so as to realize the free switching of high and low output current levels.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An IDAC circuit with switchable output current levels includes a resistor string module, an interpolation equivalent module, a first-stage buffer, a switching switch S1, and a second-stage buffer. The resistor string module outputs voltages VIH and VIL to the interpolation equivalent module. The output terminal of the interpolation equivalent module is connected to the input terminal of the first-stage buffer. The first output terminal of the first-stage buffer is connected to the first input terminal of the switching switch S1 and generates signal V2A. The second output terminal of the first-stage buffer is connected to the second input terminal of the switching switch S1 and generates signal V2B. The output terminal of the switching switch S1 is connected to the input terminal of the second-stage buffer.

[0007] Furthermore, the first-stage buffer includes an operational amplifier A1, an NMOS transistor M1, resistors R1, R2A, and R2B. The non-inverting input of operational amplifier A1 serves as the input of the first-stage buffer. The output of operational amplifier A1 is connected to the gate of NMOS transistor M1. The source of NMOS transistor M1 is connected to one end of resistor R1 and the inverting input of operational amplifier A1. The other end of resistor R1 is grounded. The drain of NMOS transistor M1 is connected to one end of resistor R2B and serves as the second output of the first-stage buffer to generate signal V2B. The other end of resistor R2B is connected to one end of resistor R2A and serves as the first output of the first-stage buffer to generate signal V2A. The other end of resistor R2A is connected to the power supply PVDD.

[0008] Furthermore, the switching switch S1 includes a PMOS transistor M5, an NMOS transistor M4, an inverter INV1, a PMOS transistor M3, and an NMOS transistor M2. The gates of PMOS transistor M5 and NMOS transistor M2 are connected to the input terminal of inverter INV1, which is connected to the enable signal EN_400MA. The source of PMOS transistor M5 is connected to the source of NMOS transistor M4 and serves as the first input terminal of switching switch S1, which is connected to the signal V2A. The gate of NMOS transistor M4 is connected to the output terminal of inverter INV1 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to the gate of NMOS transistor M2 and serves as the second input terminal of switching switch S1, which is connected to the signal V2B. The drain of PMOS transistor M5 is connected to the drains of NMOS transistor M4, PMOS transistor M3, and NMOS transistor M2 and serves as the output terminal of switching switch S1.

[0009] Furthermore, the second-stage buffer includes an operational amplifier A2, a PMOS transistor MP, and a resistor R3. The non-inverting input of the operational amplifier A2 serves as the input of the second-stage buffer. The output of the operational amplifier A2 is connected to the gate of the PMOS transistor MP. The source of the PMOS transistor MP is connected to one end of the resistor R3 and the inverting input of the operational amplifier A2 to generate a signal V3. The other end of the resistor R3 is connected to the power supply PVDD. The drain of the PMOS transistor MP generates an output signal VOUT.

[0010] Furthermore, the operational amplifier A2 includes transistors Q1 and Q2, operational amplifiers AN and AP, NMOS transistors M6, M7, M8, M9, and M10, PMOS transistors M11, M12, M13, M14, and M15, resistors R4 and R5, capacitors C4 and C5, and a current source I1. One end of capacitor C5, one end of resistor R4, and one section of resistor R5 are connected to the power supply VDD, and the other end of capacitor C5... The output of operational amplifier AN and the gate of PMOS transistor M11 are connected together. The other end of resistor R4 is connected to the source of PMOS transistor M14, and the other end of resistor R5 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15. The drain of PMOS transistor M14 is connected to the collector of transistor Q1, the inverting input of operational amplifier AN, the source of PMOS transistors M11 and M12, and the drain of PMOS transistor M15 is connected to the collector of transistor Q2 and the non-inverting input of operational amplifier AN. The source terminal of PMOS transistor M11 is connected to the source terminal of PMOS transistor M13. The gate terminal of PMOS transistor M12 is connected to the gate terminal of PMOS transistor M13. The drain terminal of PMOS transistor M11 is connected to the drain terminal of PMOS transistor M12, the drain terminal of NMOS transistor M8, the drain terminal of NMOS transistor M9, the gate terminal of NMOS transistor M6, and the gate terminal of NMOS transistor M7. The drain terminal of PMOS transistor M13 is connected to the drain terminal of NMOS transistor M10 and serves as the output terminal of operational amplifier A2. The base terminal of transistor Q1 serves as the non-inverting input terminal of operational amplifier A2, and the base terminal of transistor Q2 serves as the inverting input terminal of operational amplifier A2. At the input terminals, the non-inverting input terminal of operational amplifier AP is connected to the source of NMOS transistor M10 and the drain of NMOS transistor M7. The inverting input terminal of operational amplifier AP is connected to the source of NMOS transistor M8, the source of NMOS transistor M9, and the drain of NMOS transistor M6. The output terminal of operational amplifier AP is connected to one end of capacitor C4 and the gate of NMOS transistor M8. The gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10. The other end of current source I1, the other end of capacitor C4, the source of NMOS transistor M6, and the source of NMOS transistor M7 are grounded.

[0011] Furthermore, the operational amplifier AP is a five-transistor operational amplifier with P-type input pairs.

[0012] Furthermore, the operational amplifier AN is a five-transistor operational amplifier with N-type input pairs.

[0013] Furthermore, the operational amplifier A2 also includes NMOS transistors M16, M17, M18, and M19, and inverter INV2. The gates of PMOS transistor M19, NMOS transistor M16, and the input terminal of inverter INV2 are connected to the enable signal EN_400MA. The drain of PMOS transistor M19 is connected to the drains of NMOS transistors M18, M17, and M16, and the base of transistor Q2. The gate of NMOS transistor M18 is connected to the gate of PMOS transistor M17 and the output terminal of inverter INV2. The source of PMOS transistor M19 is connected to the sources of NMOS transistors M18, M17, and M16, and is also connected to signal V3.

[0014] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an IDAC circuit with switchable output current levels, which can arbitrarily switch between two output current levels: low current level and high current level. It can output high current level, and also utilize the hardware configuration that supports high current level to allow low current level to enjoy the output voltage headroom advantage, so as to make full use of hardware costs. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an IDAC circuit with switchable output current levels according to the present invention.

[0016] Figure 2 This is a circuit diagram of an IDAC circuit with switchable output current levels according to the present invention.

[0017] Figure 3 This is a schematic diagram of an existing IDAC circuit. Detailed Implementation

[0018] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 and Figure 2 As shown, an IDAC circuit with switchable output current levels according to the present invention includes a resistor string module, an interpolation equivalent module, a first-stage buffer, a switching switch S1, and a second-stage buffer. The resistor string module outputs voltages VIH and VIL to the interpolation equivalent module. The output terminal of the interpolation equivalent module is connected to the input terminal of the first-stage buffer. The first output terminal of the first-stage buffer is connected to the first input terminal of the switching switch S1 and generates signal V2A. The second output terminal of the first-stage buffer is connected to the second input terminal of the switching switch S1 and generates signal V2B. The output terminal of the switching switch S1 is connected to the input terminal of the second-stage buffer. The switching switch S1 is used to switch the IDAC output current level.

[0020] The first-stage buffer includes operational amplifier A1, NMOS transistor M1, resistors R1, R2A, and R2B. The non-inverting input of operational amplifier A1 serves as the input of the first-stage buffer. The output of operational amplifier A1 is connected to the gate of NMOS transistor M1. The source of NMOS transistor M1 is connected to one end of resistor R1 and the inverting input of operational amplifier A1. The other end of resistor R1 is grounded. The drain of NMOS transistor M1 is connected to one end of resistor R2B and serves as the second output of the first-stage buffer, generating signal V2B. The other end of resistor R2B is connected to one end of resistor R2A and serves as the first output of the first-stage buffer, generating signal V2A. The other end of resistor R2A is connected to the power supply PVDD.

[0021] The switching switch S1 includes a PMOS transistor M5, an NMOS transistor M4, an inverter INV1, a PMOS transistor M3, and an NMOS transistor M2. The gates of PMOS transistor M5 and NMOS transistor M2 are connected to the input of inverter INV1, which is connected to the enable signal EN_400MA. The source of PMOS transistor M5 is connected to the source of NMOS transistor M4 and serves as the first input of switching switch S1, which is connected to the signal V2A. The gate of NMOS transistor M4 is connected to the output of inverter INV1 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to the gate of NMOS transistor M2 and serves as the second input of switching switch S1, which is connected to the signal V2B. The drain of PMOS transistor M5 is connected to the drains of NMOS transistors M4, M3, and M2, and serves as the output of switching switch S1.

[0022] The smaller voltage difference generated between signal V2A and power supply PVDD is used to generate a low-level output current, while the larger voltage difference generated between signal V2B and power supply PVDD is used to generate a high-level output current.

[0023] The second-stage buffer consists of operational amplifier A2, PMOS transistor MP, and resistor R3. The non-inverting input of operational amplifier A2 serves as the input of the second-stage buffer. The output of operational amplifier A2 is connected to the gate of PMOS transistor MP. The source of PMOS transistor MP is connected to one end of resistor R3 and the inverting input of operational amplifier A2 to generate signal V3. The other end of resistor R3 is connected to power supply PVDD. The drain of PMOS transistor MP generates the output signal VOUT.

[0024] like Figure 2 As shown, operational amplifier A2 includes transistors Q1 and Q2, operational amplifiers AN and AP, NMOS transistors M6, M7, M8, M9, and M10, PMOS transistors M11, M12, M13, M14, and M15, resistors R4 and R5, capacitors C4 and C5, and a current source I1. One end of capacitor C5, one end of resistor R4, and one end of resistor R5 are connected to the power supply VDD. The other end of capacitor C5 is connected to the operational amplifier. The output of amplifier AN is connected to the gate of PMOS transistor M11. The other end of resistor R4 is connected to the source of PMOS transistor M14, and the other end of resistor R5 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M14 is connected to the gate of PMOS transistor M15. The drain of PMOS transistor M14 is connected to the collector of transistor Q1, the inverting input of operational amplifier AN, the source of PMOS transistor M11, and the source of PMOS transistor M12. The drain of PMOS transistor M15 is connected to the collector of transistor Q2, the non-inverting input of operational amplifier AN, and... The source of PMOS transistor M13 is connected to the source, the gate of PMOS transistor M12 is connected to the gate of PMOS transistor M13, the drain of PMOS transistor M11 is connected to the drain of PMOS transistor M12, the drain of NMOS transistors M8 and M9, the gate of NMOS transistor M6, and the gate of NMOS transistor M7. The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M10 and serves as the output of operational amplifier A2. The base of transistor Q1 serves as the non-inverting input of operational amplifier A2, and the base of transistor Q2 serves as the inverting input of operational amplifier A2. At the input terminals, the non-inverting input terminal of operational amplifier AP is connected to the source of NMOS transistor M10 and the drain of NMOS transistor M7. The inverting input terminal of operational amplifier AP is connected to the source of NMOS transistor M8, the source of NMOS transistor M9, and the drain of NMOS transistor M6. The output terminal of operational amplifier AP is connected to one end of capacitor C4 and the gate of NMOS transistor M8. The gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10. The other end of current source I1, the other end of capacitor C4, the source of NMOS transistor M6, and the source of NMOS transistor M7 are grounded.

[0025] Transistors Q1 and Q2 are the input pair of operational amplifier A2.

[0026] Operational amplifier AP is a five-transistor operational amplifier with P-type input pairs. Operational amplifier AN is a five-transistor operational amplifier with N-type input pairs. Operational amplifiers AP and AN act as gain boosters, used to increase the loop gain of the second-stage buffer loop.

[0027] Operational amplifier A2 also includes NMOS transistors M16, M17, M18, and M19, and inverter INV2. The gates of PMOS transistor M19, NMOS transistor M16, and the input of inverter INV2 are connected to the enable signal EN_400MA. The drain of PMOS transistor M19 is connected to the drains of NMOS transistors M18, M17, and M16, and the base of transistor Q2. The gate of NMOS transistor M18 is connected to the gate of PMOS transistor M17 and the output of inverter INV2. The source of PMOS transistor M19 is connected to the sources of NMOS transistors M18, M17, and M16, and is also connected to signal V3.

[0028] PMOS transistors M5, M4, M3, M2, M16, M17, M18, and M19 are four pairs of CMOS switches. The switching switch S1, composed of PMOS transistors M5, M4, M3, and M2, switches the voltage input to the second-stage buffer, thereby switching the output current level. The CMOS switch composed of NMOS transistors M16, M17, M18, and M19 cancels out the offset voltage introduced by the differential pair between transistors Q1 and Q2 at the base of the CMOS switch composed of PMOS transistors M5, M4, M3, and M2, thus preventing the input current from introducing offset.

[0029] The working principle of the IDAC circuit with switchable output current levels of the present invention is as follows: The high-order code controls the resistor string module, which outputs voltages VIH and VIL according to the value of the high-order code. The low-order code controls the interpolation equivalent module, which outputs an equivalent voltage V_EQ between voltages VIH and VIL according to the value of the low-order code. V_EQ is input to the first-stage buffer composed of operational amplifier A1, NMOS transistor M1, resistor R1, resistor R2A, and resistor R2B, clamping the voltage drop V1 across resistor R1 to be equal to the equivalent voltage V_EQ. The voltage value of V1 and the resistance value of R1 determine the current value flowing through resistors R2A and R2B. This current generates voltage drops across both resistors R2A and R2B, thereby determining the voltage values ​​of signals V2A and V2B. When a sufficiently large output headroom voltage is required, the enable signal EN_400MA is set low, NMOS transistors M2 and M3 are turned off, while NMOS transistors M4 and M5 are turned on. Signal V2A is input to the second-stage buffer, and the IDAC outputs a low-level current. When a high-level current is required, the enable signal EN_400MA is set high, NMOS transistors M2 and M3 are turned on, while NMOS transistors M4 and M5 are turned off. Signal V2B is input to the second-stage buffer, and the IDAC outputs a high-level current. Whether outputting high-level or low-level current, the base of transistor Q2 is always connected to signal V3. The CMOS switch composed of NMOS transistors M16, M17, M18, and M19 cancels the offset voltage introduced by the differential pair between transistors Q1 and Q2 at the base of the CMOS switch composed of PMOS transistors M5, M4, M3, and M2, thereby preventing the output current from introducing offset.

[0030] This invention provides an IDAC circuit with switchable output current levels, which can arbitrarily switch between two output current levels: low current and high current. It can output high current, and also utilize the hardware configuration that supports high current to allow low current to enjoy the output voltage headroom advantage, thus making full use of hardware costs.

[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An IDAC circuit with switchable output current levels, characterized in that: It includes a resistor string module, an interpolation equivalent module, a first-stage buffer, a switching switch S1, and a second-stage buffer. The resistor string module outputs voltages VIH and VIL to the interpolation equivalent module. The output of the interpolation equivalent module is connected to the input of the first-stage buffer. The first output of the first-stage buffer is connected to the first input of the switching switch S1 and generates signal V2A. The second output of the first-stage buffer is connected to the second input of the switching switch S1 and generates signal V2B. The output of the switching switch S1 is connected to the input of the second-stage buffer. The second-stage buffer includes operational amplifier A2, PMOS transistor MP, and resistor R3. The non-inverting input of operational amplifier A2 serves as the input of the second-stage buffer. The output of operational amplifier A2 is connected to the gate of PMOS transistor MP. The source of PMOS transistor MP is connected to one end of resistor R3 and the inverting input of operational amplifier A2 to generate signal V3. The other end of resistor R3 is connected to power supply PVDD. The drain of PMOS transistor MP generates the output signal VOUT. Operational amplifier A2 includes transistors Q1 and Q2, operational amplifiers AN and AP, NMOS transistors M6, M7, and M8, and NMOS transistors M8 and M9. The circuit consists of transistors M9, M10, M11, M12, M13, M14, and M15; resistors R4 and R5; capacitors C4 and C5; and current source I1. One end of capacitor C5, one end of resistor R4, and one end of resistor R5 are connected to the power supply VDD. The other end of capacitor C5 is connected to the output of operational amplifier AN and the gate of PMOS transistor M11. The other end of resistor R4 is connected to the source of PMOS transistor M14, and the other end of resistor R5 is connected to the source of PMOS transistor M15. The gates of PMOS transistor M14 and M15 are connected. The drain of PMOS transistor M14 is connected to the transistor... The collector of transistor Q1, the inverting input of operational amplifier AN, the source of PMOS transistors M11 and M12 are connected. The drain of PMOS transistor M15 is connected to the collector of transistor Q2, the non-inverting input of operational amplifier AN, and the source of PMOS transistor M13. The gate of PMOS transistor M12 is connected to the gate of PMOS transistor M13. The drain of PMOS transistor M11 is connected to the drain of PMOS transistor M12, the drain of NMOS transistors M8 and M9, the gate of NMOS transistor M6, and the gate of NMOS transistor M7. The drain of PMOS transistor M13 is connected to the drain of NMOS transistor M10 and serves as the output of operational amplifier A2. The base of transistor Q1 serves as the non-inverting input of operational amplifier A2, and the base of transistor Q2 serves as the inverting input of operational amplifier A2. The non-inverting input of operational amplifier AP is connected to the source of NMOS transistor M10 and the drain of NMOS transistor M7. The inverting input of operational amplifier AP is connected to the source of NMOS transistor M8, the source of NMOS transistor M9, and the drain of NMOS transistor M6. The output of operational amplifier AP is connected to one end of capacitor C4 and the gate of NMOS transistor M8. The gate of NMOS transistor M9 is connected to the gate of NMOS transistor M10. The other end of current source I1, the other end of capacitor C4, the source of NMOS transistor M6, and the source of NMOS transistor M7 are grounded.

2. The IDAC circuit with switchable output current levels according to claim 1, characterized in that: The first-stage buffer includes an operational amplifier A1, an NMOS transistor M1, resistors R1, R2A, and R2B. The non-inverting input of operational amplifier A1 serves as the input of the first-stage buffer. The output of operational amplifier A1 is connected to the gate of NMOS transistor M1. The source of NMOS transistor M1 is connected to one end of resistor R1 and the inverting input of operational amplifier A1. The other end of resistor R1 is grounded. The drain of NMOS transistor M1 is connected to one end of resistor R2B and serves as the second output of the first-stage buffer, generating signal V2B. The other end of resistor R2B is connected to one end of resistor R2A and serves as the first output of the first-stage buffer, generating signal V2A. The other end of resistor R2A is connected to the power supply PVDD.

3. The IDAC circuit with switchable output current levels according to claim 1, characterized in that: The switching switch S1 includes a PMOS transistor M5, an NMOS transistor M4, an inverter INV1, a PMOS transistor M3, and an NMOS transistor M2. The gates of PMOS transistor M5 and NMOS transistor M2 are connected to the input of inverter INV1, which is connected to the enable signal EN_400MA. The source of PMOS transistor M5 is connected to the source of NMOS transistor M4 and serves as the first input of switching switch S1, which is connected to the signal V2A. The gate of NMOS transistor M4 is connected to the output of inverter INV1 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to the gate of NMOS transistor M2 and serves as the second input of switching switch S1, which is connected to the signal V2B. The drain of PMOS transistor M5 is connected to the drains of NMOS transistors M4, M3, and M2 and serves as the output of switching switch S1.

4. The IDAC circuit with switchable output current levels according to claim 1, characterized in that: The operational amplifier AP is a five-transistor operational amplifier with P-type input pairs.

5. The IDAC circuit with switchable output current levels according to claim 1, characterized in that: The operational amplifier AN is a five-transistor operational amplifier with N-type input pairs.

6. The IDAC circuit with switchable output current levels according to claim 1, characterized in that: The operational amplifier A2 also includes NMOS transistors M16, M17, M18, and M19, and inverter INV2. The gates of PMOS transistor M19, NMOS transistor M16, and the input of inverter INV2 are connected to the enable signal EN_400MA. The drain of PMOS transistor M19 is connected to the drains of NMOS transistors M18, M17, and M16, and the base of transistor Q2. The gate of NMOS transistor M18 is connected to the gate of PMOS transistor M17 and the output of inverter INV2. The source of PMOS transistor M19 is connected to the sources of NMOS transistors M18, M17, and M16, and is also connected to signal V3.

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