A method for manufacturing a semiconductor structure

Abstract

The application discloses a semiconductor structure manufacturing method, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises at least an interlayer dielectric layer, a hard mask layer, an anti-reflection layer and a photoresist layer which are stacked in sequence; patterning the photoresist layer and etching the anti-reflection layer to form a first recess; taking the photoresist layer and the anti-reflection layer as a mask, etching the exposed part of the hard mask layer in the first recess for the first time to form a second recess; the hard mask layer comprises an amorphous carbon layer; taking the anti-reflection layer as a mask, etching the exposed hard mask layer in the second recess for the second time to form a third recess, and the sidewall of the exposed hard mask layer forms a polymer layer; taking the anti-reflection layer and the hard mask layer or taking the hard mask layer as a mask, etching the exposed interlayer dielectric layer in the third recess to form a through hole; and removing the hard mask layer to form a connecting structure in the through hole. The semiconductor structure manufacturing method provided by the application can ensure the side profile and target size of the through hole and improve the manufacturing yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for fabricating a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuits, the feature size of semiconductor devices is decreasing, and the integration density of integrated circuits is constantly increasing. In integrated devices, different semiconductor devices are interconnected through high-density metal wires. In semiconductor manufacturing processes, via etching is a key technology connecting front-end devices with back-end metal wires and multilayer metal wires, playing a crucial role in bridging the gap between the two. Due to the high aspect ratio of vias, there are strict definitions for the material of the vias and the size of the etched vias.

[0003] As the critical dimension (CD) of vias decreases and the aspect ratio increases, a hard mask layer is introduced during via etching to cooperate with photoresist in forming a mask pattern. The main component of the hard mask layer is, for example, an amorphous carbon layer. During etching, oxygen and sulfur-containing gases are used to passivate the sidewalls and ensure the side profile. However, due to the presence of copper, sulfur-containing gases cannot be used. As a result, the critical dimension of the hard mask layer opening is too large or the side profile is poor during the etching process. This leads to the perpendicularity or dimensional deviation of the etched via, which directly affects the subsequent metal filling, resulting in higher metal resistance and even affecting the product yield. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor structure. The method provided by this invention can ensure the side profile and target size of the via, ensure the quality of the connection structure, reduce the resistance of the connection structure, and improve the device fabrication yield.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided, wherein the substrate comprises at least an interlayer dielectric layer, a hard mask layer, an anti-reflection layer and a photoresist layer stacked sequentially. The photoresist layer is patterned and the anti-reflection layer is etched using the photoresist layer as a mask to form a first recess; Using the photoresist layer and the anti-reflection layer as masks, the exposed portion of the hard mask layer of the first recess is etched for the first time to form the second recess; the hard mask layer includes an amorphous carbon layer; Using the anti-reflective layer as a mask, the hard mask layer exposed by the second recess is etched a second time to form a third recess, and a polymer layer is formed on the sidewall of the hard mask layer exposed by the third recess; Using the anti-reflective layer and the hard mask layer, or using the hard mask layer as a mask, the interlayer dielectric layer exposed in the third recess is etched to form a via; Remove the hard mask layer to form a connection structure within the through-hole.

[0007] In one embodiment of the present invention, the thickness of the hard mask layer etched for the first time is 15% to 45% of the thickness of the hard mask layer.

[0008] In one embodiment of the present invention, the first etching and the second etching are performed using dry etching. The first etching is performed by introducing a first etching gas under a first preset pressure and a first preset power; the second etching is performed by introducing a second etching gas under a second preset pressure and a second preset power.

[0009] In one embodiment of the present invention, the first preset pressure is greater than the second preset pressure, and the first preset power is less than the second preset power.

[0010] In one embodiment of the present invention, the first preset pressure is 100mTorr~130mTorr, and the second preset pressure is 20mTorr~30mTorr.

[0011] In one embodiment of the present invention, the first preset power includes a first high-frequency power and a first low-frequency power, wherein the first high-frequency power is 150W~250W and the first low-frequency power is 550W~650W; the second preset power includes a second high-frequency power and a second low-frequency power, wherein the second high-frequency power is 1800W~2000W and the second low-frequency power is 2900W~3200W.

[0012] In one embodiment of the present invention, the first etching gas includes oxygen, carbon monoxide and fluorocarbon gas, wherein the fluorocarbon gas includes one or more of trifluoromethane, carbon tetrafluoride or hexafluoroethane.

[0013] In one embodiment of the present invention, the flow rate of the oxygen is 300 sccm to 400 sccm, the flow rate ratio of the oxygen to the carbon monoxide is (6 to 8): (4 to 2), and the flow rate of the fluorocarbon gas is 40 sccm to 60 sccm.

[0014] In one embodiment of the present invention, the second etching gas includes a fluorocarbon gas, and the flow rate of the fluorocarbon gas is 15 sccm to 30 sccm.

[0015] In one embodiment of the present invention, when etching the interlayer dielectric layer, the thickness of the polymer layer gradually decreases from the top of the hard mask layer to the interlayer dielectric layer, and the thickness of the polymer layer at the maximum position is 5nm~70nm.

[0016] In summary, this invention provides a method for fabricating a semiconductor structure. By improving this method, the unexpected technical advantages of this invention include ensuring the side profile morphology and target size of vias, ensuring the quality of the interconnect structure, reducing the resistance of the interconnect structure, and improving device fabrication yield. During the etching of the hard mask layer, two etching steps shorten the etching time using fluorocarbon gas, thereby ensuring the final target size of the vias, passivating the sidewalls of the hard mask layer, obtaining a vertical profile, and reducing profile damage. Simultaneously, the use of sulfur-containing gases is avoided during the etching process, thus preventing interference with the first metal layer.

[0017] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an example of forming an interlayer dielectric layer, a hard mask layer, an anti-reflection layer, and a photoresist layer sequentially on a substrate.

[0020] Figure 2 This is a schematic diagram of etching a photoresist layer and an anti-reflection layer to form a first recess in one embodiment.

[0021] Figure 3 This is a schematic diagram of the first etching of the hard mask layer to form the second recess in one embodiment.

[0022] Figure 4 This is a schematic diagram of the third recess formed by the second etching of the hard mask layer in one embodiment.

[0023] Figure 5 This is a schematic diagram of forming a through-hole by etching the interlayer dielectric layer in one embodiment.

[0024] Figure 6 This is a schematic diagram of a connection structure formed in a through hole in one embodiment.

[0025] Label Explanation: 10. Substrate; 101. Semiconductor device; 102. Interconnect structure; 11. Insulating layer; 12. First dielectric layer; 13. First metal layer; 14. Interlayer dielectric layer; 15. Hard mask layer; 16. Anti-reflection layer; 17. Photoresist layer; 171. First recess; 172. Second recess; 173. Third recess; 18. Polymer layer; 19. Through-hole; 20. Connection structure. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0029] This invention provides a method for fabricating a semiconductor structure. During the etching of the hard mask layer, a two-stage etching process shortens the etching time using fluorocarbon gas, thereby ensuring the final target size of the vias. This also passivates the sidewalls of the hard mask layer, resulting in a vertical profile and reducing damage to the profile. Simultaneously, the use of sulfur-containing gases is avoided during the etching process, thus preventing interference with the first metal layer. This ensures the side profile morphology and target size of the vias, guarantees the quality of the interconnect structure, and improves device fabrication yield.

[0030] Please see Figure 1As shown, in one embodiment of the present invention, a substrate 10 is first provided, and the substrate 10 can be any suitable material for formation, such as a silicon wafer, a germanium substrate, silicon-germanium, silicon-on-insulator, or silicon-on-insulator stacked, etc. The present invention does not limit the type and thickness of the substrate 10. In this embodiment, the substrate 10 is selected, for example, as a silicon wafer, and the fabrication method is described, and the substrate 10 is, for example, a P-type silicon wafer.

[0031] Please see Figure 1 As shown, in one embodiment of the present invention, a plurality of semiconductor devices 101 are disposed on the substrate 10. The present invention does not limit the types of semiconductor devices 101. Semiconductor device 101 is, for example, a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), a high-efficiency rectifier diode (HED), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate turn-off thyristor (GTO), a light-triggered thyristor (LTT), a thyristor, a charge-coupled device (CCD image sensor), a digital signal processor (DSP), a photorelay, or a microprocessor. The specific process involves one or more semiconductor devices, such as a processor, and can be manufactured according to the requirements of semiconductor integrated device manufacturing.

[0032] Please see Figure 1As shown, in one embodiment of the present invention, an insulating layer 11 is disposed on a substrate 10, and a plurality of interconnect structures 102 are disposed within the insulating layer 11. The interconnect structures 102 are, for example, metal wires or conductive plugs, and are connected to semiconductor devices 101 on the substrate 10, for example, to the source region, drain region, or gate structure of the semiconductor device. The insulating layer 11 is, for example, an insulating material such as silicon dioxide or silicon nitride, which can isolate the semiconductor device 101 from the metal layer, prevent the diffusion of metal from affecting the semiconductor device 101, and protect the semiconductor device 101 from damage during the fabrication of the metal layer. In this embodiment, the interconnect structures 102 are, for example, low-resistance materials such as tungsten, copper, silver, or gold, ensuring that the resistance is low when the interconnect structures 102 are connected to the subsequently fabricated first metal layer 13, thereby improving the performance of the semiconductor integrated device.

[0033] Please see Figure 1 As shown, in one embodiment of the present invention, a first dielectric layer 12 is disposed on the insulating layer 11, and a plurality of first metal layers 13 are disposed within the first dielectric layer 12. The first metal layers 13 are, for example, aluminum or copper, and are respectively connected to the interconnect structure 102. The first dielectric layer 12 is, for example, an insulating material such as silicon dioxide or silicon nitride, which can reduce the diffusion of the first metal layer 13, prevent the diffusion of metal from affecting the semiconductor device 101, and protect the semiconductor device 101 during the fabrication of the metal layer, preventing damage to the semiconductor device 101. In this embodiment, a barrier layer (not shown in the figure) is also disposed between the first metal layer 13 and the first dielectric layer 12. The barrier layer is, for example, titanium (Ti) or titanium nitride (TiN), and the thickness of the barrier layer is, for example, 2nm~5nm. By providing the barrier layer, the adhesion between the first metal layer 13 and the first dielectric layer 12 is enhanced, electromigration is prevented, and the electrical performance of the semiconductor device is improved.

[0034] Please see Figure 1As shown, in one embodiment of the present invention, an interlayer dielectric layer 14, a hard mask layer 15, an anti-reflection layer 16, and a photoresist layer 17 are sequentially formed on the first dielectric layer 12 and the first metal layer 13. The interlayer dielectric layer 14 is, for example, a silicon oxide layer, and is formed, for example, by chemical vapor deposition (CVD), with a thickness of, for example, 530 nm to 600 nm. Before forming the interlayer dielectric layer 14, a titanium or titanium nitride layer (not shown) is formed on the first dielectric layer 12 and the first metal layer 13 to prevent atoms in the first metal layer 13 from diffusing into the interlayer dielectric layer 14. The hard mask layer 15 is, for example, an amorphous carbon layer (ACL), and is formed, for example, by chemical vapor deposition or physical vapor deposition (PVD), with a thickness of, for example, 250 nm to 300 nm. The anti-reflective layer 16 is, for example, at least one of silicon-based anti-reflective layers such as silicon oxynitride, silicon nitride, or an organic polymer. The organic polymer includes, for example, organopolysilazane, organosilicon resin, or polysiloxane. The anti-reflective layer 16 is formed, for example, by chemical vapor deposition or physical vapor deposition, and its thickness is, for example, 30 nm to 40 nm. The photoresist layer 17 is, for example, a positive photoresist or a negative photoresist layer, and its thickness is not limited, for example, by spin coating, blade coating, or coating processes. In other embodiments, the thicknesses of the interlayer dielectric layer 14, the hard mask layer 15, and the anti-reflective layer 16 may vary depending on performance requirements such as the number and density of vias formed.

[0035] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after forming the photoresist layer 17, the photoresist layer 17 is patterned by processes such as exposure and development, forming an opening (not shown in the figure) within the photoresist layer 17. Then, using the photoresist layer 17 as a mask, the anti-reflective layer 16 exposed by the opening is removed to form a first recess 171. The anti-reflective layer 16 is removed, for example, by dry etching, and the pressure in the etching chamber is, for example, 100 mTorr to 130 mTorr, the high frequency (HF) power is, for example, 150 W to 250 W, the low frequency (LF) power is, for example, 550 W to 650 W, and the etching gas includes, for example, a fluorine-containing gas, or, for example, one or more of carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hexafluoroethane (C2F6), chlorine (Cl2), hydrogen bromide (HBr), trifluoromethane (CHF3), or boron trichloride (BCl3), or a mixture thereof with oxygen (O2). In this embodiment, the etching gas is, for example, a mixture of trifluoromethane and carbon tetrafluoride, and the flow rate of trifluoromethane is, for example, 30 sccm to 50 sccm, and the flow rate of carbon tetrafluoride is, for example, 250 sccm to 300 sccm. By using trifluoromethane, a polymer protective layer can be formed on the sidewall during the etching process to suppress lateral etching and improve anisotropy, thereby obtaining a first recess 171 with a good sidewall morphology. The opening size of the first recess 171 is, for example, 25% to 35% of the target size of the final through hole.

[0036] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the first recess 171, the hard mask layer 15 is etched for the first time using the photoresist layer 17 and the anti-reflection layer 16 as a mask to form the second recess 172. The first etching is, for example, dry etching, and a first etching gas is introduced under a first preset pressure and a first preset power to perform the first etching. The first preset pressure is, for example, 100 mTorr to 130 mTorr; the first preset power includes a first high-frequency power and a first low-frequency power; the first high-frequency power is, for example, 150 W to 250 W; the first low-frequency power is, for example, 550 W to 650 W; and the first etching gas includes, for example, oxygen, carbon monoxide, and fluorocarbon gas (C). x F yThe etching gas includes, for example, one or more of trifluoromethane, carbon tetrafluoride, or hexafluoroethane, and the oxygen flow rate is, for example, 300 sccm to 400 sccm, the oxygen to carbon monoxide flow rate ratio is, for example, (6 to 8):(4 to 2), or for example, 7:3, and the fluorocarbon gas flow rate is, for example, 40 sccm to 60 sccm. Argon is simultaneously introduced as a carrier gas to improve etching uniformity. During the first etching process, adding oxygen and carbon monoxide to the etching gas enables lateral etching, enlarging the opening size of the first recess 171, and controlling the oxygen to carbon monoxide flow rate ratio controls the amount of lateral etching. In this embodiment, when the depth h of the second recess 172 within the hard mask layer 15 is 15% to 45% of the thickness H of the hard mask layer 15, the opening size of the second recess 172 is, for example, 70% to 80% of the target size of the final via. At this point, the photoresist layer 17 is essentially completely etched.

[0037] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after forming the second recess 172, the hard mask layer 15 is etched a second time using the anti-reflection layer 16 as a mask to form the third recess 173. The second etching is performed, for example, in the same etching chamber as the first etching, and the pressure in the etching chamber is adjusted to a second preset pressure. A second etching gas is introduced at a second preset power for the second etching. The first preset pressure is greater than the second preset pressure, and the first preset power is less than the second preset power. In this embodiment, the second preset pressure is, for example, 20 mTorr to 30 mTorr, and the second preset power includes a second high-frequency power and a second low-frequency power. The second high-frequency power is, for example, 1800 W to 2000 W, and the second low-frequency power is, for example, 2900 W to 3200 W. The second etching gas includes, for example, fluorocarbon gas, i.e., oxygen and carbon monoxide are turned off, and the flow rate of the fluorocarbon gas is, for example, 15 sccm to 30 sccm. Argon gas is simultaneously introduced as a carrier gas to improve etching uniformity. During the etching process, the fluorocarbon gas reacts with the material of the hard mask layer 15 to form a polymer that adheres to the sidewalls of the hard mask layer 15. This polymer prevents the etching gas from laterally etching the hard mask layer 15. As time increases, the amount of polymer generated continuously forms a polymer layer 18 on the hard mask layer 15 exposed on the sidewalls of the third recess 173. The thickness of the polymer layer 18 gradually decreases from the top of the hard mask layer 15 to the interlayer dielectric layer 14, ultimately forming a third recess 173 with a high aspect ratio. In this embodiment, the thickness at the thickest point of the polymer layer 18 is, for example, 5 nm to 70 nm, with the specific value influenced by the conditions during the etching process. After forming the third recess 173, the opening size of the third recess 173 is, for example, the target size of the final via. During the etching process, the proportion of etching gas in the first etching can be adjusted so that the opening size of the third recess 173 is, for example, the target size of the final via. After etching is completed, the anti-reflective layer 16 is essentially completely etched or a small amount remains.

[0038] Please see Figures 2 to 4 As shown, in one embodiment of the present invention, the etching of the hard mask layer 15 is performed in two steps: a first etching followed by a second etching. This shortens the etching time using fluorocarbon gas, thereby ensuring the target dimensions. Simultaneously, the second etching process passivates the sidewalls of the hard mask layer 15, resulting in a vertical profile, reducing damage to the profile and improving its quality. Furthermore, the use of sulfur-containing gases is avoided during the etching process, thus preventing any impact on the first metal layer.

[0039] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after the third recess 173 is formed, the interlayer dielectric layer 14 and part of the first metal layer 13 exposed at the bottom of the third recess 173 are etched using a hard mask layer 15 or an anti-reflection layer 16 and a hard mask layer 15 as a mask to form a via 19. The interlayer dielectric layer 14 is, for example, etched by dry etching, and the pressure in the etching chamber is, for example, 35 mTorr to 45 mTorr, the high-frequency power is, for example, 550 W to 650 W, the low-frequency power is, for example, 1450 W to 1600 W, and the etching gas includes, for example, oxygen, carbon tetrafluoride, and argon, with the oxygen flow rate being, for example, 10 sccm to 15 sccm, the carbon tetrafluoride flow rate being, for example, 15 sccm to 20 sccm, and the argon flow rate being, for example, 750 sccm to 900 sccm. During the etching process, because the sidewalls of the third recess 173 are covered with polymer and the cross-sectional damage is minimal, lateral etching can be reduced, ensuring the size of the via 19 and achieving the target via size. Simultaneously, by controlling the etching conditions of the interlayer dielectric layer 14, the morphology of the sidewalls of the via 19 can be improved, resulting in a vertical cross-section. This allows for vias with a diameter less than 100 nm and an aspect ratio greater than 7, achieving a breakthrough in patterning through double-layer photoresist processes. After etching to form the via 19, the remaining portion of the hard mask layer 15 on the interlayer dielectric layer 14 is removed by wet etching or oxygen plasma. In other words, the via formation method of this application ensures the side profile and target size of the via, guarantees the quality of the subsequently formed interconnect structure, reduces the resistance of the interconnect structure, and improves device fabrication yield.

[0040] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after forming the via 19, a barrier layer (not shown in the figure) is formed on the sidewalls and bottom of the via 19. The barrier layer is formed, for example, by physical vapor deposition, and is made of a material with good adhesion, such as tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). The thickness of the barrier layer is, for example, 2 nm to 5 nm. By setting the barrier layer, the adhesion between the subsequently deposited metal layer and the sidewalls of the via 19 is enhanced. Then, a metal layer is deposited on the barrier layer to form a connection structure 20. The material of the connection structure 20 is, for example, a low-resistivity material such as tungsten, copper, silver, or gold. In this embodiment, the connection structure 20 is, for example, tungsten. The connection structure 20 is formed, for example, by physical vapor deposition or electroplating, and the metal layer fills the via 19 until it covers the interlayer dielectric layer 14. Then, a planarization process, such as chemical mechanical polishing, is used to remove the metal layer on the interlayer dielectric layer 14, so that the formed connection structure 20 is flush with the interlayer dielectric layers 14 on both sides. After forming the connection structure 20, multiple wiring layers are fabricated, such as the second metal layer, the third metal layer, and the connection structure between the second metal layer and the third metal layer. The connection structure can be fabricated using the method of this application, which will not be elaborated here.

[0041] In summary, this invention provides a method for fabricating a semiconductor structure. By improving this method, the unexpected technical advantages of this invention include ensuring the side profile and target size of vias, ensuring the quality of the interconnect structure, reducing the resistance of the interconnect structure, and improving device fabrication yield. During the etching of the hard mask layer, two etching steps shorten the etching time using fluorocarbon gas, thereby ensuring the final target size of the vias, passivating the sidewalls of the hard mask layer, obtaining a vertical profile, and reducing profile damage. Simultaneously, the use of sulfur-containing gases is avoided during the etching process, thus preventing interference with the first metal layer.

[0042] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate comprises at least an interlayer dielectric layer, a hard mask layer, an anti-reflection layer and a photoresist layer stacked sequentially. The photoresist layer is patterned and the anti-reflection layer is etched using the photoresist layer as a mask to form a first recess; Using the photoresist layer and the anti-reflective layer as masks, the exposed portion of the hard mask layer in the first etching is etched for the first time, and the hard mask layer is laterally etched during the first etching process to enlarge the opening size of the first recess, forming a second recess; the hard mask layer includes an amorphous carbon layer; the first etching gas used in the first etching includes oxygen, carbon monoxide, and fluorocarbon gas, and the fluorocarbon gas includes one or more of trifluoromethane, carbon tetrafluoride, or hexafluoroethane; the opening size of the second recess is 70% to 80% of the target size of the final via. Using the anti-reflective layer as a mask, the hard mask layer exposed by the second recess is etched a second time to form a third recess. A polymer layer is formed on the sidewall of the hard mask layer exposed by the third recess. The thickness of the polymer layer gradually decreases from the top of the hard mask layer to the interlayer dielectric layer. The second etching gas used in the second etching includes fluorocarbon gas. The opening size of the third recess is the target size of the final via. Using the anti-reflective layer and the hard mask layer, or using the hard mask layer as a mask, the interlayer dielectric layer exposed in the third recess is etched to form a via; Remove the hard mask layer and form a connection structure within the through-hole; The first etching and the second etching are performed using dry etching. The first etching gas is introduced under a first preset pressure and a first preset power to perform the first etching. Under a second preset pressure and a second preset power, the second etching gas is introduced to perform the second etching. The first preset pressure is greater than the second preset pressure, and the first preset power is less than the second preset power.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The thickness of the hard mask layer during the first etching is 15% to 45% of the thickness of the hard mask layer.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first preset pressure is 100mTorr~130mTorr, and the second preset pressure is 20mTorr~30mTorr.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first preset power includes a first high-frequency power and a first low-frequency power, wherein the first high-frequency power is 150W~250W and the first low-frequency power is 550W~650W; the second preset power includes a second high-frequency power and a second low-frequency power, wherein the second high-frequency power is 1800W~2000W and the second low-frequency power is 2900W~3200W.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, In the first etching gas, the flow rate of oxygen is 300 sccm to 400 sccm, the flow rate ratio of oxygen to carbon monoxide is (6 to 8): (4 to 2), and the flow rate of fluorocarbon gas is 40 sccm to 60 sccm.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The flow rate of the second etching gas is 15 sccm to 30 sccm.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, When etching the interlayer dielectric layer, the thickness of the polymer layer at its maximum position is 5 nm to 70 nm.

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