Error correction and recovery in optical communication systems with low power light source devices

Abstract

A first communication device receives a set of bits for transmission over a plurality of channels of an optical communication link. The optical communication link includes a greater number of channels than the number of channels required to support transmissions at a particular clock rate to provide a maximum speed supported by the optical communication link. The first communication device multiplexes a set of data bits for transmission over a corresponding channel, and transmits the multiplexed set of bits over the channel to the second communication device. The first communication device transmits error correction code bits using a larger number of channels in addition to transmitting a set of bits at a particular clock rate through a plurality of channels at a maximum speed supported by the optical communication link, and / or provides one or more redundant channels in the optical communication link using a larger number of channels.

Description

Cross Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 470,428, filed June 1, 2023, entitled “Large Channel Count Active Optical Cable Forward Error Correction Improvements and Error / Redundancy Control,” the disclosure of which is expressly incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to the transmission of data via optical media, and more particularly to error correction and failure recovery when transmitting data via optical cables using low power light source devices. BACKGROUND

[0003] An active optical cable (AOC) is a point-to-point link between two electronic devices (e.g., switches, servers, etc.) in which fiber optic optics are used as the physical medium of communication between the devices. Traditionally, AOCs use one or more lasers as light sources and have a relatively small number of fiber pairs. Some systems use light emitting diodes (LEDs) rather than lasers to save power. Although LEDs typically transmit data at a lower bit rate compared to lasers, the power consumption of LEDs is significantly lower than the ratio of their respective bandwidths. Thus, optical cables with very large counts of fiber pairs for transmission using LEDs provide power savings compared to optical systems that use lasers as light source devices to transmit data over optical communication links. SUMMARY

[0004] In one embodiment, a method for communicating over an optical communication link is provided. The method includes receiving, at a first communication device, a set of bits for transmission over a plurality of lanes of an optical communication link, a respective lane among the plurality of lanes comprising a respective optical fiber driven by a respective light emitting diode (LED), wherein the optical communication link comprises a greater number of lanes than a number of lanes required to support transmission at a maximum speed of the optical communication link to provide a maximum speed supported by the optical communication link; multiplexing, by the first communication device, the set of data bits for transmission over the respective lane among the plurality of lanes, including one or both of: i) using the greater number of lanes for transmission of error correction code bits in addition to transmitting the set of bits at a particular clock rate over the plurality of lanes at the maximum speed supported by the optical communication link, and ii) using the greater number of lanes to provide one or more redundant lanes in the optical communication link; and transmitting, by the first communication device, the multiplexed set of bits over the plurality of lanes of the optical communication link to a second communication device.

[0005] In another embodiment, a first communication device is provided. The first communication device includes a transceiver comprising: a receiver configured to receive a set of bits for transmission over a plurality of lanes of an optical communication link, a respective lane among the plurality of lanes comprising a respective optical fiber driven by a respective light emitting diode (LED), wherein the optical communication link comprises a greater number of lanes than a number of lanes required to support transmission at a maximum speed of the optical communication link to provide a maximum speed supported by the optical communication link; one or more multiplexers configured to multiplex the set of data bits for transmission over the respective lane among the plurality of lanes, including one or both of: i) using the greater number of lanes for transmission of error correction code bits in addition to transmitting the set of bits at a particular clock rate over the plurality of lanes at the maximum speed supported by the optical communication link, and ii) using the greater number of lanes to provide one or more redundant lanes in the optical communication link; and a transmitter configured to transmit the multiplexed set of bits over the plurality of lanes of the optical communication link to a second communication device. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a simplified diagram of an example system in which an optical cable has a greater number of lanes than a number of lanes required to support a maximum speed of a communication link provided via the optical cable, in accordance with one embodiment.

[0007] Figure 2A is a block diagram of portions of an example transmitter device used in a system of Figure 1

[0008] ​Figure 2B is a block diagram of portions of an example receiver device for receiving signals transmitted by Figure 2A a transmitter device of FIG. 1.

[0009] Figure 3A is a block diagram of portions of an example transmitter device for use in a system of Figure 1 FIG. 1.

[0010] Figure 3B is a block diagram of portions of an example receiver device for receiving signals transmitted by Figure 3A a transmitter device of FIG. 1.

[0011] Figure 4 is a block diagram of an example transmit circuitry of a transmitter device of Figure 3A FIG. 1.

[0012] Figure 5A is a block diagram of portions of an example transmitter device for use in a system of Figure 1 FIG. 1.

[0013] Figure 5B is a block diagram of portions of an example receiver device for receiving signals transmitted by Figure 5A a transmitter device of FIG. 1.

[0014] Figure 6 illustrates an example remapping function used by a transmitter device of Figure 5A FIG. 1.

[0015] Figure 7 is a block diagram of an example redundancy controller for use in a system of Figure 1 FIG. 1.

[0016] Figure 8 is a block diagram of an example redundancy controller for use in a system of Figure 1 FIG. 1.

[0017] Figure 9 is a flow diagram of an example method for communicating over a fiber optic cable communication link according to an embodiment. DETAILED DESCRIPTION

[0018] As described above, optical communication systems using low-power semiconductor devices, such as light emitting diodes, are designed with a greater number of lanes or fiber pairs compared to optical communication systems using lasers. In the embodiments described below, optical communication systems utilize optical communication links that include a greater number of lanes than are needed to transmit data at a particular clock rate at the maximum link speed supported by the optical communication link. In one embodiment, the optical system utilizes the additional lanes to encode additional data without increasing the transmission rate per lane. Additionally or alternatively, the optical system utilizes the additional lanes as redundant lanes that are used to repair the optical communication link in the presence of one or more dead or failed lanes in the optical communication link. As discussed in greater detail below, in various embodiments, the inclusion of additional lanes in the optical communication link and the use of the additional lanes for additional encoding and / or redundancy improves the resiliency and reliability of the optical communication link in at least some embodiments. For example, in at least some embodiments, the additional lanes allow the optical communication system to implement hitless recovery to repair the optical communication link in the presence of a failed or dead lane and / or to improve the bit error rate of the optical communication link in the presence of a burst error condition without losing lock and without the need to reinitialize the optical communication link. Because laser devices consume significantly more power compared to low-power semiconductor devices, such as light emitting diodes, typical optical communication links that use lasers for data transmission as the light source device for transmitting data over the optical communication link do not typically include such additional lanes, and typical optical communication devices that use lasers for data transmission are not configured to use additional data lanes. As a result, hitless recovery is typically not possible in optical communication systems that use lasers as the light source device for transmitting data over the optical communication link.

[0019] Figure 1is a simplified diagram of an example system 100 according to one embodiment in which a fiber optic cable includes a greater number of lanes than are needed to support the maximum speed of a communication link provided via the fiber optic cable. The system 100 includes a first communication device 102 coupled to a second communication device 104 via a fiber optic cable 106. In one embodiment, the first communication device 102, the second communication device 104, and the fiber optic cable 106 form an active fiber optic cable used to communicatively couple host devices, such as switches or end host devices. In another embodiment, the first communication device 102 and the second communication device 104 are part of host devices coupled via the fiber optic cable 106. For example, in one embodiment, a first switch device includes or otherwise implements the first communication device 102 and a second switch device includes or otherwise implements the second communication device 104. In the illustrated embodiment, the first communication device 102 includes a transceiver 110 which in turn includes a transmitter 113 and a receiver 115. In the illustrated embodiment, the second communication device 104 includes a transceiver 120 which in turn includes a receiver 123 and a transmitter 125.

[0020] In one embodiment, the fiber optic cable 106 provides an optical communication link 108 including a plurality of lanes 109 (also sometimes referred to herein as "channels"). A respective lane 109 includes a respective optical fiber or a respective pair of optical fibers used to transmit signals in the fiber optic cable 106. The first communication device 102 includes a plurality of light source devices 111 coupled with the plurality of lanes 109. In one embodiment, the light source devices 111 are relatively lower power devices as compared to laser light sources. In one embodiment, the light source devices 111 include light emitting diodes (LEDs). In other embodiments, other suitable light source devices of lower power as compared to laser light sources are used. The second communication device 104 includes a plurality of optical detector devices 121 coupled with the plurality of lanes 109. In one embodiment, the optical detector devices 121 include photodiodes. In other embodiments, other suitable optical detector devices are used. In one embodiment, each light source device 111 is configured to transmit optical signals at a relatively lower bit rate as compared to the bit rate that a laser light source device can transmit. However, in at least some embodiments, the power consumption of each light source device 111 is significantly lower than the ratio of the bandwidth of the light source devices 111 to the bandwidth of a typical laser light source device. Thus, the first communication device 102 includes a significantly greater number of light source devices 111 as compared to a typical communication device that uses laser light for data transmission while utilizing laser light that also operates at a lower power than a typical optical transmitter that uses laser light for data transmission. Thus, the fiber optic cable 106 includes a corresponding greater number of lanes 109 for data transmission as compared to the number of data lanes in a fiber optic cable used with a typical communication device that uses laser light for data transmission.

[0021] In one embodiment, the first communication device 102 is configured to use a larger number of light source devices 111 and channels 109 to transmit data, the data including a number of bits extended due to additional encoding of the data by the transmitter 113 of the first communication device 102. Using additional light source devices 111 and channels 109 to transmit the additionally encoded data allows the transmission of the additionally encoded data without increasing the clock rate relative to the clock rate used to transmit data without additional encoding, while still supporting the maximum speed of the communication link 108. In at least some embodiments, using additional light source devices 111 and channels 109 to transmit the additionally encoded data thus simplifies the design of the transceiver 110 compared to a system that does not provide channels to accommodate the additional encoding. Alternatively or concurrently, the first communication device 102 is configured to use a larger number of light source devices 111 and channels 109 by using one or more channels 109 as redundant channels. For example, the first communication device 102 is configured to determine that a fault or hard fault has occurred on a specific channel 109, which is driven by a specific diode 111 of the first communication device 102 and received by a specific diode 121 of the second communication device 104. In one embodiment, as explained in detail below, the first communication device 102 is configured to determine that a fault or hard fault has occurred on channel 109 in response to receiving an indication from the second communication device 104 that a failed channel or a silent channel has been detected by the receiver 121 of the second communication device 104.

[0022] In one embodiment, the first communication device 102 is configured to transfer data transmission from the specific channel 109 to a redundant channel 109 in response to determining that a fault or hard fault has occurred on the specific channel 109. In one embodiment, the redundant channel 109 is driven by a diode 111 different from the diode 111 driving the faulty channel 109 and received by a diode 121 different from the diode 121 receiving the faulty channel 109. In one embodiment, the first communication device 102 is configured to determine that a fault has occurred and, for example, due to a high bit error rate on the communication link 108 as determined by a higher-level processing unit (e.g., a media access controller (MAC)) included in or coupled to the receiver 123 of the second communication device 104, transfer transmission from the faulty channel to the redundant channel before the link is determined to be downstream via the receiver 123 of the second communication device 104 or a higher-level processing unit coupled to the receiver 123 of the second communication device 104. In this case, transferring transmission from the faulty channel to the redundant channel allows for uninterrupted recovery of the communication link 108, which is repaired in the background without losing lock and without needing to reinitialize the communication link 108.

[0023] The first communication device 102 is configured to receive a deserialized serial bit stream for transmission over optical fiber 106. The deserialized bit stream includes data generated by SERDES at a host clock rate C. host N bits are transmitted. In one embodiment, for example, N is 128 bits, and the clock rate C host It is 880MHz. In one embodiment, the first communication device 102 includes a retimer or gearbox, which is typically configured to convert a data stream of a first bit width, clocked at a first clock rate, into a data stream of a second bit width, clocked at a second clock rate. In one embodiment, the retimer or gearbox is configured to output N bits to a data stream of a line clock rate C. line On the D LED channels controlled by the clock, the line clock rate is C line From host clock rate C host Exported. The number of channels D and the exported clock C. line It is determined that the data stream is transmitted at a total bit rate equal to or greater than the link speed of communication link 108. For example, in an embodiment where the guaranteed useful transmission rate on communication link 108 is 100 GHz, the number of channels is 32 and the clock rate is C. line The clock speed is 3.52 GHz. In this embodiment, the clock rate C line Equal to clock rate C host Multiplying by 4, and with the overall speed of communication link 108 being 112.64 GHz, this is sufficient to guarantee a transmission speed of 100 GHz on optical communication link 108, while allowing the transmission of overhead bits such as Ethernet FEC bits.

[0024] In one embodiment, the transmitter 113 of the first communication device 102 includes a remapper 112, an encoder 114, a redundancy controller 116, and a multiplexer 118. The multiplexer 118 is configured to multiplex bits of a data stream for transmission through a corresponding channel 109 of the optical fiber 106. As described in more detail below, in various embodiments, the remapper 112 is configured to interleave bits of the encoded data stream received by the transmitter 113 for transmission to better distribute them among the channels 109, the encoder 114 is configured to further encode the encoded data stream, and the redundancy controller 116 is configured to control the transfer of data transmission from a failed or faulty channel 109 to a redundant channel 109. Also described in more detail below, in various embodiments, the operations performed by the remapper 112, encoder 114, and redundancy controller 116 improve the resilience to burst errors on the optical communication link 108 and / or enable the repair of failed channels 109 in the optical communication link 108. In some embodiments, transmitter 113 omits one or more of the remapper 112, encoder 114, and redundant controller 116.

[0025] In one embodiment, the receiver 123 of the second communication device 104 includes a demapper 122, a decoder 124, and a redundancy controller 126. The demapper 122 is configured to reverse the interleaving performed by the remapper 112. The decoder 124 is configured to decode the data stream encoded by the encoder 114. In one embodiment, the redundancy controller 126 is configured to detect a faulty or failed channel 109 and coordinate with the redundancy controller 116 to transfer data transmission from the faulty or failed channel 109 to the redundant channel 109. In some embodiments, the receiver 123 may omit one or more of the demapper 122, decoder 124, and redundancy controller 126. In one embodiment, the receiver 115 of the first communication device 102 is typically the same as the receiver 123 of the second communication device 104. Similarly, in one embodiment, the transmitter 125 of the second communication device 104 is typically the same as the transmitter 113 of the first communication device 102.

[0026] In one embodiment, the data stream received by the first communication device 102 is encoded using a specific encoding scheme. For example, the data stream is encoded using the Reed Solomon (RS) block encoding scheme. In one embodiment, the data stream is encoded using the Ethernet RS (544, 514) block encoding scheme. In this scheme, the Reed Solomon block code is used, where 514 10-bit data symbols are amplified using 30 10-bit parity symbols to produce 544 symbol codewords. This RS code can correct 15 erroneous symbols. Because the data stream is multiplexed via a gearbox and is multiplexed to a limited number of data channels, in at least some cases, the data transmission is not resilient to burst errors. For example, directly distributing bits from the data stream between channels 109 may cause bits from multiple symbols of the RS code to be mapped onto the same data channel 109. As a result, burst errors on data channel 109 are distributed across multiple symbols of the RS code and therefore cannot be corrected by the RS code in at least some cases.

[0027] As discussed in more detail below, in one embodiment, the remapper 112 of the first communication device 102 interleaves or remaps the bits in the data stream such that the bits are distributed among channels 109 in a manner that maximizes the mapping of bits of the same symbol from the RS code to the same channel 109, thus minimizing the distribution of burst errors among multiple symbols of the RS code. For example, the remapper 112 interleaves or remaps the bits to ensure that bits of the same symbol of the RS code are mapped to the same channel 109 to the maximum extent or completely. In this case, burst errors on a particular channel 109 affect fewer symbols of the RS code compared to a system that does not perform such remapping. Therefore, in one embodiment, such remapping makes the transmission of the data stream more resilient to burst errors and more easily corrected by the RS code. The data stream is then demapped by the demapper 122 of the second communication device 104 to restore the order of the data bits before providing the data stream decoded according to the Ethernet decoding scheme.

[0028] Alternatively, in some embodiments, the encoder 114 of the first communication device 102 further encodes the data stream before transmission. In one embodiment, the encoder 114 is a block code encoder configured to further encode the data stream using block codes (such as RS codes). In another embodiment, the encoder 114 is configured to use codes different from block codes. For example, in one embodiment, the encoder 114 is configured to encode the data stream using Hamming codes. In another example, the encoder 114 is configured to encode the data stream by adding cyclic redundancy check (CRC) bits generated based on the data bits. The data stream received by the second communication device 104 is then decoded by the decoder 124 of the second communication device 104. In one embodiment, the decoder 124 can therefore correct and detect one or more errors in the received data stream before providing the data stream for decoding according to the Ethernet decoding scheme. In at least some embodiments, the data stream is further encoded to make the data transmission more resilient to burst errors because some errors are detected and corrected at the second communication device 104 before the corrected bit stream is provided for decoding according to the Ethernet decoding scheme.

[0029] In one embodiment, the redundancy controller 116 of the first communication device 102 and the redundancy controller 126 of the second communication device 104 are configured to cooperate with each other to achieve redundant data transmission from the first communication device 102 to the second communication device 104. In one embodiment, the redundancy controller 126 of the second communication device 104 is configured to detect a fault on channel 109 and provide an indication of the faulty channel 109 to the first communication device 102. In one embodiment, the redundancy controller 126 of the second communication device 104 provides the indication of the faulty channel 109 to the first communication device 102 via a sideband channel 130 provided between the first communication device 102 and the second communication device 104. Furthermore, the redundancy controller 126 of the second communication device 104 is configured to reconfigure the receiver 123 of the second communication device 104 to transfer data reception from the faulty channel 109 to the redundant channel 109 in response to detecting a fault on channel 109. The redundancy controller 116 of the first communication device 102 is configured to receive an indication of a faulty channel from the second communication device 104 and transfer data transmission from the faulty channel 109 to the redundant channel 109. In one embodiment, the second communication device 104 is configured to detect a fault before it causes a loss of lock between the first and second communication devices 102 due to a fault. For example, the second communication device 104 is configured to use a "stuckon" detector to monitor channel 109, and the "stuckon" detector is configured to detect a fault in response to detecting that a bit stream received from a particular channel 109 is stuck at bit values ​​of 0 or 1 for a predetermined period of time. In other embodiments, other suitable detection mechanisms are used.

[0030] As described in more detail below, in various embodiments, i) an additional channel is used for transmitting data further encoded by the first communication device 102, ii) an additional channel 109 is used to provide redundancy, iii) a faulty channel 109 is quickly detected at the second communication device 104, iv) a sideband channel is used to transmit an indication of a faulty channel from the second communication device 104 to the first communication device 102, and v) data transmission is efficiently transferred from the faulty channel 109 to one or more of the redundant channels 109, etc., allowing the communication system 100 to perform data transmission and / or achieve uninterrupted recovery from channel failures in a manner resilient to sudden errors.

[0031] Figure 2A This is a block diagram of a portion of an example transmitter device 200 according to one embodiment. Transmitter device 200 corresponds to... Figure 1 The optical first communication device 102 of the communication system 100 or included therein Figure 1 In the optical first communication device 102 of the communication system 100, and for illustrative purposes, the transmitter device 200 refers to Figure 1To describe. However, in some embodiments, the transmitter device 200 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The optical first communication device 102 of the communication system 100 is different from the transmitter device 200.

[0032] Transmitter device 200 includes a SERDES receiver block 202, a first set of triggers 204, a remapper 206, multiple multiplexers 208, a second set of triggers 210, and a line transmitter 212. Transmitter device 200 also includes a phase-locked loop (PLL) 214 and a controller 216. Transmitter device 200 is configured to receive signals for communication via a link supporting a maximum link speed (e.g., 100 GHz). Figure 1 The data stream 220 is transmitted via the optical communication link 108. Data stream 220 corresponds to a serial data stream, which is transmitted by the host SERDES at a clock rate C. host Converted into a parallel data stream of width N, where the clock rate C host Equal to or greater than the maximum link speed divided by N. In one embodiment, the width N of the data stream 220 is 128 bits, and the clock rate C host The clock speed is 880 MHz. In other embodiments, other suitable data stream widths and / or other suitable clock rates are used. Transmitter device 200 is configured to convert the received data stream 220 to a clock rate C via a gearbox. line The clock-controlled data stream has a width of M and a clock rate of C. line With clock rate C host Proportional. In one embodiment, a first set of triggers 204, a remapper 206, multiple multiplexers 208, a second set of triggers 210, a PLL 214, and a controller 216 are configured to implement the gearbox function of the transmitter device 200.

[0033] SERDES receiver block 202 is configured to receive N data bits from a host SERDES device and store the N bits in a first set of triggers 204. In the illustrated embodiment, the first set of triggers 204 includes 128 triggers to store 128 bits of data stream 220. In one embodiment, the data stream 220 received by SERDES receiver block 202 is an encoded data stream encoded according to block codes, which include multiple symbols of codewords forming the block codes. For example, data stream 220 is encoded using Ethernet RS (544, 514) codes. PLL 214 is configured to receive data from the host SERDES device at clock rate C. host The corresponding clock signal and the line clock rate C are derived.line The corresponding clock signal, line clock rate C line Clock rate C of the host device host Proportional. In some embodiments, the clock signal received by PLL 214 is noisy, and PLL 214 is also configured to clean up the clock signal to generate a clock signal proportional to the line clock rate C. line The corresponding clean clock signal. In one embodiment, the clock rate C line From clock rate C host By C host This is obtained by multiplying by a factor N / M (e.g., 4 in the illustrated embodiment). Therefore, in the illustrated embodiment, PLL 214 is configured to generate a clock signal that is the product of a clock signal from the host SERDES device and a factor of four.

[0034] Remapper 206 remaps the bits output from the first set of triggers 204 to maximize the bit mapping from the same symbols of the block code to the same channel 109, thus minimizing the distribution of burst errors across multiple symbols of the block code. For example, remapper 206 interleaves or remaps bits to ensure that bits of the same symbols of the RS code are mapped to the same channel 109 to the maximum or complete extent. In this case, burst errors on a particular channel 109 affect fewer symbols of the RS code compared to a system that does not perform such remapping. Therefore, in one embodiment, such remapping makes the data stream more resilient to burst errors and more easily corrected by the RS code. In one embodiment, remapper 206 is configured to remap bits according to the following mapping function: for i in range ( 8 ): for j in range ( 4 ): for k in range ( 4 ): Equation 1

[0035] The remapping function in Equation 1 maps 128 bits to 32 data channels, such that in most cases, four consecutive bits of the same symbol in an Ethernet RS (544, 514) code are mapped to the same data channel. In other embodiments, other suitable remapping functions are used. The bits remapped by remapping unit 206 are provided to a set of multiplexers 208. In the illustrated embodiment, the set of multiplexers 208 comprises 32 4:1 multiplexers. Multiplexers 208 are controlled by controller 216 at clock rate C. line To control. Each multiplexer in multiplexer 208 is configured to operate at clock rate C. lineOne bit is output per clock cycle. The output of multiplexer 208 is stored in a second set of flip-flops 210. In the illustrated embodiment, the second set of flip-flops 210 comprises 32 flip-flops. The second set of flip-flops 210 is controlled by controller 216 at a clock rate C. line 32 signals are output per clock cycle. The 32 signals drive the corresponding LEDs of the transmitter device 200. In one embodiment, the LEDs convert the signals into optical signals and output the corresponding optical signals to the corresponding data channels of the 32 data channels of the communication link 108 for transmission to the second communication device 104.

[0036] Figure 2B This is a block diagram of an example receiver 250 according to one embodiment, the example receiver 250 being configured to receive signals from... Figure 2A The transmitter 200 transmits the signal. The receiver device 250 corresponds to... Figure 1 The optical second communication device 104 of the communication system 100 or is included Figure 1 In the optical second communication device 104 of the communication system 100, and for illustrative purposes, the receiver device 250 refers to Figure 1 To describe. However, in some embodiments, the receiver device 250 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The optical second communication device 104 of the communication system 100 is different from the receiver device 250.

[0037] Receiver 250 includes a line receiver device 252, a first set of triggers 254, a second set of triggers 256, a demapper 258, and a host SERDES transmitter device 260. Receiver 250 also includes a PLL 268 and a controller 264. Line receiver device 252 is configured to receive optical signals from a communication link (e.g., communication link 108) and convert the optical signals into electrical signals to generate a data stream 251. In one embodiment, receiver device 250 includes a plurality of photodiodes configured to convert signals received from multiple channels of the communication link into electrical signals to generate the data stream 251. In one embodiment, the data stream includes signals received at a line clock rate C. line The clock-controlled data stream has a width of M bits, where M is the number of channels in the communication link and C line It is the clock rate at which data is transmitted through each channel of the communication link. In one embodiment, C line High enough to support the maximum link speed of the communication link, such as 100 GHz. In this embodiment, C lineEqual to or greater than the maximum link speed of the communication link divided by M. Receiver device 250 is configured to convert data stream 251 to a clock rate C. host A data stream 253 with a width of N is controlled by a clock. In one embodiment, the clock rate C host With clock rate C line Proportional. For example, clock rate C host Equals C line Multiply by the ratio M / N. In one embodiment, M is 32, C line It is 3.52 GHz, N is 128 bits, and the clock rate C host It is 880MHz. In other embodiments, other suitable data stream widths and / or other suitable clock rates are used.

[0038] The line receiver device 252 is configured to store bits of the received data stream 251 in a set of flip-flops 254. In one embodiment, the set of flip-flops 254 includes M flip-flops corresponding to the width of the data stream 251. For example, in the illustrated embodiment, the set of flip-flops 254 includes 32 flip-flops. The PLL 268 is configured to receive clock rate C. line The clock signal and convert the clock signal to a clock rate C host The clock signal. For example, the PLL 268 is configured to generate a clock rate C. host The signal, clock rate C host Corresponding to clock rate C line Multiply by M / N (e.g., 1 / 4 in the illustrated embodiment). In some embodiments, the clock signal received by PLL 268 is noisy, and PLL 268 is also configured to clean the clock signal to generate a host clock rate C consistent with the host device. host The corresponding clean clock signal.

[0039] Receiver device 250 is configured to be in C line During each clock cycle, bits stored in the set of flip-flops 254 are transferred to the set of flip-flops 256. In one embodiment, the second set of flip-flops 256 comprises N flip-flops corresponding to the width of the data stream 253. For example, in the illustrated embodiment, the second set of flip-flops 256 comprises 128 bits. In one embodiment, the second set of flip-flops 256 is thus configured to accumulate the N bits transferred from the set of flip-flops 256. Controller 264 is configured to control the set of flip-flops 256 in clock cycle C. hostEach clock cycle outputs N bits. A data stream of width N output from the set of flip-flops 256 is provided to demapping unit 258. Demapping unit 258 deinterleaves the bits to reverse the interleaving performed by remapping unit 206 of transmitter device 200. In one embodiment, the deinterleaved data stream is provided to host SERDES transmitter 260, which then outputs a data stream for serializing the SERDES of the host device.

[0040] Figure 3A According to another embodiment Figure 1 A block diagram of a portion of the example transmitter device 300 used in the system. Transmitter device 300 corresponds to... Figure 1 The optical first communication device 102 of the communication system 100 or included therein Figure 1 In the optical first communication device 102 of the communication system 100, and for illustrative purposes, the transmitter device 300 refers to Figure 1 To describe. However, in some embodiments, the transmitter device 300 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The optical first communication device 102 of the communication system 100 is different from the transmitter device 300.

[0041] Transmitter device 300 is similar to Figure 2A The transmitter device 200 and includes a ... Figure 2A The transmitter device 200 is a similarly numbered element. In one embodiment, with Figure 2A Compared to transmitter device 200, transmitter device 300 is configured to transmit data via a greater number of channels in the communication link, accommodating a wider data width and / or including additional redundant channels. In one embodiment, transmitter device 300 includes a host SERDES receiver device 302, which corresponds to... Figure 2A The host SERDES receiver device 302. The transmitter device 300 also includes a first set of triggers 304, a barrel shifter 305, a remapper 306, a second set of triggers 306, a remapper / redundancy controller 308, a FIFO 310, multiple multiplexers 312, a fourth set of triggers 314, and a line transmitter 316. The transmitter device 300 also includes a PLL 324 and a controller 318. In one embodiment, the host SERDES receiver device 302 is configured to receive signals as referenced above. Figure 2A The discussion is based on a clock rate of C. host The clock-controlled data stream has a width of N, which is 320. Figure 3AIn the illustrated embodiment, N is 128 bits and the clock rate C host The frequency is 880MHz. In one embodiment, the data stream 220 received by the SERDES receiver block 202 is an encoded data stream encoded according to a block code, which includes multiple symbols of codewords forming the block code. For example, the data stream 220 is encoded using Ethernet RS (544, 514) code.

[0042] Transmitter device 300 is configured to convert the received data stream 220 into a clock rate C via a gearbox. line The clock-controlled data stream has a width of M and a clock rate of C. line With clock rate C host Proportional. In one embodiment, a data stream of width M is transmitted through M data channels in optical communication link 108. In one embodiment, the width M is designed to include a sufficient number of data channels to ensure that the entire symbol of the code is used to encode the data stream 220. For example, in one embodiment, the width M is 40. Forty data channels are sufficient to ensure that each symbol of the Ethernet RS (544, 514) code can be mapped to a single data channel. In the illustrated embodiment, transmitter device 300 is configured to convert a 128-bit wide data stream 220 to a 160-bit wide data stream via a gearbox, and then convert the 160-bit wide data stream to a clock rate C. line The clock-controlled data stream is 40 bits wide, and the clock rate is C. line Equal to clock rate C host Multiply by 16 / 5. In one embodiment, a first set of triggers 304, a barrel shifter 305, a second set of triggers 306, a remapper / redundancy controller 308, a FIFO 310, multiple multiplexers 312, a fourth set of triggers 314, a PLL 324, and a controller 318 are configured to implement the gearbox function of the transmitter device 300.

[0043] In one embodiment, the host SERDES receiver device is configured to store a 128-bit wide data stream 220 received during a continuous clock cycle in a subset of triggers 304-1 and 304-2 within a first set of triggers 304. A bucket shifter 305 is configured to read a subset of bits from triggers 304-1 and 304-2 in 160-bit blocks and store the 160 bits in a second set of triggers 306. In one embodiment, a remapper / redundancy controller 308 is configured to remap the 160 bits such that the entire symbol of the code used to encode the data stream 220 is transmitted through the same data channel and redundant bits are added for transmission through a redundant channel. Brief Reference Figure 4According to one embodiment, a circuit 400 for accumulating and reading 160 bits is illustrated. Circuit 400 includes two stages 402 of serial shift registers 404, each set comprising five serial shift registers 404. The five sets of shift registers 404 provide 80 bits of storage. Therefore, stage 402 of the serial shift registers 404 guarantees 160 bits. In one embodiment, circuit 400 thus allows accumulating and reading 160 bits with relatively small delays. (Refer to again...) Figure 3A In one embodiment, the remapper / redundancy controller 308 is configured to add eight redundant bits to the 160-bit array, wherein the eight redundant bits are copies of bits mapped to a faulty data channel and to be transferred to a redundant channel. In the illustrated embodiment, the remapped bits with the added redundant bits are stored in a FIFO 310, which includes 168 triggers.

[0044] PLL 324 is configured to receive data from the host SERDES device at clock rate C. host The corresponding clock signal and the line clock rate C are derived. line The corresponding clock signal, line clock rate C line Clock rate C of the host device host Proportional. In one embodiment, the clock rate C line By C host Multiply by a factor N / M (e.g., 16 / 5 in the illustrated embodiment) from clock rate C host Therefore, in the illustrated embodiment, PLL 324 is configured to generate a clock signal that is the product of a clock signal from the host SERDES device and a factor of 16 / 5. In some embodiments, the clock signal received by PLL 324 is noisy, and PLL 324 is also configured to clean the clock signal to generate a clock signal with line clock rate C. line The corresponding clean clock signal.

[0045] In the illustrated embodiment, the set of multiplexers 312 comprises 42 4:1 multiplexers. Controller 318 is configured to control a third set of triggers 310 to output remapped bits, plus additional bits added for redundancy by the remapper / redundancy controller 308, to the set of multiplexers 312. The multiplexers 312 are controlled by controller 318 at a clock rate derived from a clock signal from the host SERDES by PLL 324. Each multiplexer in the multiplexers 312 corresponds to a channel and is configured to transfer bits input to the multiplexer 312 to the channel in each clock cycle under the control of controller 318. The outputs of the multiplexers 312 are stored in a fourth set of triggers 314. In the illustrated embodiment, the set of triggers 210 comprises 42 triggers. The fourth set of triggers 210 is controlled by controller 318 to output 42 signals in each clock cycle of controller 318. The 42 signals drive corresponding LEDs of transmitter device 300. In one embodiment, the LED thus converts the signal into an optical signal and outputs the optical signal to 32 channels of the communication link 108 for transmission to the second communication device 104.

[0046] Figure 3B This is a block diagram of an example receiver 350 according to one embodiment, the example receiver 350 being configured to receive signals from... Figure 3A The transmitter 300 transmits the signal. The receiver device 350 corresponds to... Figure 1 The optical second communication device 104 of the communication system 100 or is included Figure 1 In the optical second communication device 104 of the communication system 100, and for illustrative purposes, the receiver device 250 refers to Figure 1 To describe. However, in some embodiments, the receiver device 350 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The optical second communication device 104 of the communication system 100 is different from the receiver device 350.

[0047] Receiver 350 includes a line receiver device 352, a first set of triggers 354, a second set of triggers 356, a FIFO 358, a redundancy controller / demapping unit 360, a barrel shifter 362, a third set of triggers 364, and a host SERDES transmitter 368. Receiver 350 also includes a PLL 370, a first controller 372, and a second controller 374. Line receiver device 352 is configured to receive optical signals from optical communication link 108 and convert the optical signals into electrical signals to generate a data stream 351. In one embodiment, receiver device 350 includes a plurality of photodiodes configured to convert signals received from multiple channels of optical communication link 108 into electrical signals to generate data stream 351. In one embodiment, data stream 351 includes signals received at a line clock rate C. line The clock-controlled data stream has a width of M bits, where M corresponds to the number of data channels in the optical communication link 108 and C line This is the clock rate at which data is transmitted through each channel of the optical communication link 108. The receiver device 350 is configured to convert the data stream 351 to a clock rate C. host A data stream 353 with a width of N is controlled by a clock. In one embodiment, the clock rate C host With clock rate C line Proportional. For example, clock rate C host Equals C line Multiply by the ratio M / N. In one embodiment, M is 40, and C... line It is 2.816 GHz, N is 128 bits, and the clock rate C host It is 880MHz. In other embodiments, other suitable data stream widths and / or other suitable clock rates are used.

[0048] The line receiver device 352 is configured to store bits of the received data stream 351 in a first set of triggers 354. In one embodiment, the first set of triggers 354 includes M triggers corresponding to the width of the data stream 351 and an additional R triggers corresponding to redundant channels in the optical communication link 108. For example, in the illustrated embodiment, the first set of triggers 354 includes 42 triggers, of which 40 triggers correspond to the width of the data stream 251 and two additional triggers correspond to two redundant channels in the optical communication link 108. The PLL 370 is configured to receive clock rate C. line The clock signal and convert the clock signal to a clock rate C host The clock signal. For example, the PLL 370 is configured to generate a clock rate C. host The signal, clock rate C hostCorresponding to clock rate C line Multiply by M / N (e.g., 5 / 16 in the illustrated embodiment). In some embodiments, the clock signal received by PLL 370 is noisy, and PLL 370 is also configured to clean up the clock signal to generate a clock rate C consistent with the host clock rate of the host device. host The corresponding clean clock signal.

[0049] In one embodiment, receiver device 350 is configured to, within four consecutive clock cycles, in C line During each clock cycle, the bits stored in the first set of flip-flops 354 are transferred to the second set of flip-flops 356. In one embodiment, the second set of flip-flops 356 includes bits corresponding to the width of the data stream 353 and additional redundant bits. A set of triggers. For example, in the illustrated embodiment, the second set of triggers 356 comprises 168 bits. In one embodiment, the second set of triggers 356 is therefore configured to accumulate. Each bit, plus additional redundant bits transferred from the second set of flip-flops 356. Controller 372 is configured to control the set of flip-flops 356 to operate at clock C. line Output per clock cycle One bit and additional redundant bits. The width of the output from the set of flip-flops 356 is The data stream and additional redundant bits are accumulated in FIFO 358 and provided to the redundancy controller and demapping unit 360. The redundancy controller and demapping unit 360 select suitable channels and deinterleave the bits to reverse the interleaving performed by the remapping unit 308 of the transmitter device 300; the suitable channels include the data channel and / or the redundant channel. The deinterleaved data stream is stored in a third set of flip-flops 364. At clock rate C... host The controller 374 controls the third set of triggers 364 to output per clock cycle. bits, The bits are then read out in N-bit blocks (e.g., 128 bits in the illustrated embodiment) by a bucket shifter to generate data stream 253. In one embodiment, data stream 253 is then transmitted by host SERDES transmitter 368 to host SERDES device.

[0050] Figure 5A According to another embodiment Figure 1 A block diagram of a portion of the example transmitter device 500 used in the system. Transmitter device 500 corresponds to... Figure 1 The optical first communication device 102 of the communication system 100 or included therein Figure 1In the optical first communication device 102 of the communication system 100, and for illustrative purposes, the transmitter device 500 refers to Figure 1 To describe. However, in some embodiments, the transmitter device 500 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The optical first communication device 102 of the communication system 100 is different from the transmitter device 300.

[0051] Transmitter device 500 is similar to Figure 2A The transmitter device 200 and includes a ... Figure 2A The transmitter device 200 is a similarly numbered element. In one embodiment, with Figure 2A Compared to transmitter device 200, transmitter device 500 is configured to transmit data via a greater number of channels of communication link 108. These greater number of channels include additional FEC channels and / or additional redundant channels, which are configured to accommodate additional encoding performed by transmitter device 500. In one embodiment, transmitter device 500 includes a host SERDES receiver device 502, which corresponds to... Figure 2A The host SERDES receiver device 502. The transmitter device 500 also includes a first gearbox 504, a remapper 506, an encoder 508, a second gearbox 510, a redundant copy generator 512, a FIFO 514, a set of multiplexers 516, a set of triggers 518, and a line transmitter 524. The transmitter device 500 also includes a PLL 526 and a controller 528. In one embodiment, the host SERDES receiver device 502 is configured to receive signals at clock rate C. host The clock-controlled data stream has a width of N, which is 520. Figure 5A In the embodiment shown, N is 128 bits and the clock rate C host The frequency is 880MHz. In one embodiment, the data stream 520 received by the SERDES receiver block 502 is an encoded data stream encoded according to a block code, which includes multiple symbols of codewords forming the block code. For example, the data stream 520 is encoded using Ethernet RS (544, 514) code.

[0052] In the illustrated embodiment, gearbox 504 is configured to convert the received 128-bit wide data stream 520 into a clock rate C. hostA clock-controlled data stream 522 is 192 bits wide. In one embodiment, the 192 bits are provided to a remapper 506, which is configured to remap the bits to provide a better distribution of RS (544, 514) code symbols across the data channels, thereby maximizing the mapping of corresponding data symbols to the same data channels. (Brief Reference) Figure 6 In one embodiment, the remapper 506 is configured to... Figure 6 The remapping function 600 shown is used to remap bits. In other embodiments, other suitable remapping functions are used.

[0053] Refer again Figure 5A The data stream remapped by remapper 506 is further encoded by encoder 508. In one embodiment, encoder 508 uses RS (34, 32) codes with a symbol size of six bits or more. In one embodiment, transmitter device 500 is configured to transmit the data stream encoded by encoder 508 such that each symbol of the six-bit or more-bit RS (34, 32) code is transmitted on the same channel of optical communication link 108. In this embodiment, RS (34, 32) codes allow correction of individual symbols out of 34 symbols, thereby allowing receiver device i) to correct single-bit errors within any given clock cycle, ii) to correct burst errors on a single channel (e.g., over multiple clock cycles), and / or iii) to repair failed channels. In other embodiments, encoder 508 uses other suitable encoding schemes.

[0054] PLL 526 is configured to receive clock rate C from the host SERDES device. host The clock signal, and derive the line clock rate C. line The clock signal, line clock rate C line Clock rate C of the host device host Proportional. In one embodiment, the clock rate C line By C host Multiply by N / M (e.g., 4 in the illustrated embodiment) from the clock rate C host Therefore, in the illustrated embodiment, PLL 526 is configured to generate clock rate C. line The clock signal, clock rate C line It is the product of the clock signal from the host SERDES device and a factor of 4. In some embodiments, the clock signal received by the PLL 526 is noisy, and the PLL 526 is also configured to clean the clock signal to generate a clock signal with line clock rate C. line The corresponding clean clock signal.

[0055] The data stream encoded by encoder 508 is converted from 204 bits to 136 bits by a second gearbox 510. In the illustrated embodiment, a redundancy copy generator 512 then adds redundant bits for transmission via two redundant channels of optical communication link 108, thus generating a data stream with a width of 144 bits. In one embodiment, the 144 bits are stored in FIFO 514 and controlled by controller 528 in C... line The clock rate is read from FIFO 514. The bits read from FIFO 514 are provided to a set of multiplexers 516. The set of multiplexers 516 consists of 36 4:1 multiplexers 516, each multiplexer 516 being configured to operate at clock rate C. line Each clock cycle, the multiplexer outputs bits for transmission via the corresponding channel in the optical communication link 108. The output of the multiplexer 516 is stored in a fourth set of flip-flops 518. In the illustrated embodiment, the set of flip-flops 518 comprises 36 flip-flops. The set of flip-flops 518 operates at clock rate C. line Each clock cycle outputs 36 signals. In one embodiment, the 36 signals drive corresponding LEDs of the transmitter device 500. The LEDs thus convert the signals into light signals and output the light signals to 36 channels of the optical communication link 108 for transmission to the second communication device 104.

[0056] Figure 5B This is a block diagram of an example receiver 550 according to one embodiment, the example receiver 550 being configured to receive signals from... Figure 5A The transmitter 500 transmits the signal. The receiver device 550 corresponds to... Figure 1 The second communication device 104 of the communication system 100 or included therein Figure 1 In the second communication device 104 of the communication system 100, and for illustrative purposes, the receiver device 550 refers to Figure 1 To describe. However, in some embodiments, the receiver device 550 is in conjunction with Figure 1 The communication systems are used in different communication systems. Similarly, in some embodiments, Figure 1 The second communication device 104 of the communication system 100 is different from the receiver device 550.

[0057] Receiver 550 includes a line receiver device 552, a first set of triggers 554, a second set of triggers 556, a FIFO 558, a redundancy controller 560, a first gearbox 562, an alignment controller 564, a decoder 566, a demapping unit 568, a second gearbox 570, a second set of triggers 572, and a host SERDES transmitter 574. Receiver 550 also includes a PLL 576, a first controller 578, and a second controller 580. The line receiver device 552 is configured to receive optical signals from optical communication link 108 and convert the optical signals into electrical signals to generate a data stream 551. In one embodiment, receiver device 550 includes a plurality of photodiodes configured to convert signals received from multiple channels of optical communication link 108 into electrical signals to generate data stream 551. In one embodiment, data stream 551 includes signals received at a line clock rate C. line The clock-controlled data stream has a width of M bits, where M corresponds to the number of data channels in the optical communication link 108 and C line This is the clock rate at which data is transmitted through each channel of the optical communication link 108. The receiver device 550 is configured to convert the data stream 551 to a clock rate C. host A data stream 553 with a width of N is controlled by a clock. In one embodiment, the clock rate C host With clock rate C line Proportional. For example, clock rate C host Equals C line Multiply by the ratio M / N. In one embodiment, M is 32, C line It is 3.52GHz, N is 128 bits, and the clock rate C host It is 880MHz. In other embodiments, other suitable data stream widths and / or other suitable clock rates are used. Data stream 551 also includes F (e.g., 2) bits and R (e.g., 2) redundant bits added by encoder 508. Therefore, the width of data stream 551 is M+F+R, which is equal to 36 bits in the illustrated embodiment.

[0058] The line receiver device 552 is configured to store bits of the received data stream 551 in a first set of flip-flops 554. In one embodiment, the first set of flip-flops 554 includes M+F+R (e.g., 36) flip-flops corresponding to the width of the data stream 551. The PLL 576 is configured to receive clock rate C. line The clock signal and convert the clock signal to a clock rate C host The clock signal. For example, the PLL 576 is configured to generate a clock rate C. host The signal, clock rate C hostCorresponding to clock rate C line Multiply by M / N (e.g., 1 / 4 in the illustrated embodiment). In some embodiments, the clock signal received by PLL 576 is noisy, and PLL 576 is also configured to clean up the clock signal to generate a clock rate C consistent with the host clock rate of the host device. host The corresponding clean clock signal.

[0059] In one embodiment, receiver device 550 is configured to, over four consecutive clock cycles, in C line During each clock cycle, the bits stored in the first set of flip-flops 554 are transferred to the second set of flip-flops 556. In one embodiment, the second set of flip-flops 556 includes bits corresponding to the width of the data stream 553. (M+F+R) triggers. For example, in the illustrated embodiment, the second set of triggers 556 includes... Bits. In one embodiment, the second set of triggers 556 is therefore configured to accumulate. (M+F+R) (for example, The controller 578 is configured to control the set of flip-flops 556 to operate at clock C. This includes the first set of flip-flops 556 and additional redundant bits transferred from the second set of flip-flops 556. line Output per clock cycle (M+F+R) bits. The width of the output from the set of 556 flip-flops is... The (M+F+R) data stream is accumulated in FIFO 558 and provided to redundancy controller 560. In one embodiment, redundancy controller 560 selects an appropriate channel, which includes a data channel and / or a redundancy channel. In the illustrated embodiment, data from the selected channel is then converted by first gearbox 562, which converts 136 bits to 204 bits. In one embodiment, alignment controller 564 is configured to implement an alignment scheme to synchronize with transmitter device 500 on incoming data during link startup, thereby eliminating startup-to-start latency variations. Decoder 566 decodes the data based on the encoding scheme of encoder 508 of transmitter device 500 (e.g., RS (34, 32) encoding scheme). In one embodiment, demapper 568 reorders the bits to restore the bit order of Ethernet RS (544, 514) codes. In the illustrated embodiment, second gearbox converts the demapped 192 bits to 128 bits. The converted 128-bit wide data stream is stored in the third set of flip-flops 572. At clock rate C... host The controller 580 controls the third set of triggers 572 to output in each clock cycle. Bit, The bits are then read out in N-bit blocks (e.g., 128 bits in the illustrated embodiment) by a bucket shifter to generate data stream 553. In one embodiment, data stream 553 is then transmitted by host SERDES transmitter 574 to host SERDES device.

[0060] Brief Reference Figure 7 The diagram illustrates a block diagram of an example redundant controller 700 according to one embodiment. The redundant controller 700 is used as a reference in various embodiments. Figure 1 , Figure 2A- Figure 2B , Figure 3A- Figure 3B and Figure 5A- Figure 5B The redundant controller described. In one embodiment, the redundant controller 700 includes a series-arranged... :2 Input multiplexer 702 (Dn, MUXn-1), the output of the final multiplexer 702 in series controls the redundant channel LED. In operation, a configuration signal (CfgReg) is provided to the Dn input on the first multiplexer 702 in series. In one embodiment, although Figure 7 The diagram illustrates only one chain of multiplexer 702; however, note that the redundancy controller 700 includes a chain of multiplexers 702 for each redundant bit. In this redundancy controller architecture, LED outputs other than the redundant LEDs are not switched. Therefore, transferring a faulty channel to a redundant channel does not affect the rest of the communication link. Due to the latency of the serially connected multiplexer 702, pipelined and shutdown timing in the redundancy controller 700 are challenging in some embodiments.

[0061] Figure 8 This is a block diagram of an example redundant controller 800 according to another embodiment. The redundant controller 800 is used as the reference above in various embodiments. Figure 1 , Figure 2A- Figure 2B , Figure 3A- Figure 3B and Figure 5A- Figure 5B The described redundant controller. In one embodiment, the redundant controller 800 includes... (9+2+1) 4-input multiplexers 802, (9+2+1) four-input multiplexers 802 are arranged in three layers, with the output control of the final output multiplexer 802 being redundant LEDs. In the illustrated embodiment, the three layers of multiplexers 802 implement a 34:1 multiplexer. In the illustrated embodiment, during operation, a configuration signal (CfgReg) is provided to the final multiplexer 802 in the first layer. In one embodiment, although... Figure 8 The diagram illustrates only one three-layer arrangement of multiplexer 802; however, note that the redundancy controller 800 includes such a three-layer arrangement of multiplexer 802 for each redundant bit. Figure 7The redundant controller 700 has a similar architecture, except that the LED outputs other than the redundant LEDs are... Figure 8 The redundant controller 800 is not switched in its architecture. Therefore, transferring a failed channel to a redundant channel does not affect the rest of the communication link. In at least some embodiments, in Figure 8 In the architecture of the redundant controller 800, pipelined and timing shutdown are... Figure 8 The redundant controller 800 is easier to implement than the redundant controller 800.

[0062] Figure 9 This is a flowchart of an example method 900 for communication via an optical communication link according to one embodiment. In one embodiment, method 900 is performed by... Figure 1 The first communication device 102 is used to implement this, and method 900 is referenced. Figure 1 To describe in order to facilitate explanation. In other embodiments, method 900 is performed by and Figure 1 The first communication device 102 is implemented using different suitable network devices, and / or in conjunction with... Figure 1 The system has been implemented in 100 different systems.

[0063] At block 902, the bit set is received by the first communication device. The bit set is used to transmit to the second communication device via multiple channels of the optical communication link. In one embodiment, each channel of the multiple channels comprises a corresponding optical fiber driven by a corresponding light-emitting diode (LED). In one embodiment, the optical communication link includes a larger number of channels than are required to support transmission at a specific clock rate, to provide the maximum speed supported by the optical communication link.

[0064] At block 904, the bits of the data bit set are multiplexed for transmission through a corresponding channel among multiple channels of the optical communication link. In one embodiment, transmission through a corresponding channel among multiple channels of the optical communication link includes one or both of the following: i) using a larger number of channels to transmit error correction code bits in addition to transmitting the bit set through multiple channels at a specific clock rate at the maximum speed supported by the optical communication link; and ii) using a larger number of channels to provide one or more redundant channels in the optical communication link. As described above, in various embodiments, one or both of i) using a larger number of channels to transmit error correction code bits in addition to transmitting the bit set through multiple channels at a specific clock rate at the maximum speed supported by the optical communication link and ii) using a larger number of channels to provide one or more redundant channels in the optical communication link improves the resilience of the communication link and / or allows for uninterrupted link recovery without having to reinitialize the communication link.

[0065] At box 906, the multiplexed set of bits is transmitted to the second communication device through multiple channels of the optical communication link.

[0066] Example 1: A method for communicating via an optical communication link, the method comprising: receiving at a first communication device a set of bits for transmission via a plurality of channels of the optical communication link, wherein a corresponding channel of the plurality of channels includes a corresponding optical fiber driven by a corresponding light-emitting diode (LED), wherein the optical communication link includes a larger number of channels than the number of channels required to support transmission at a specific clock rate, to provide a maximum speed supported by the optical communication link; multiplexing the set of data bits by the first communication device for transmission via a corresponding channel of the plurality of channels, including one or both of the following: i) using a larger number of channels for transmitting error correction bits in addition to transmitting the set of bits via the plurality of channels at a specific clock rate at the maximum speed supported by the optical communication link; and ii) using a larger number of channels to provide one or more redundant channels in the optical communication link; and transmitting the multiplexed set of bits by the first communication device to a second communication device via the plurality of channels of the optical communication link.

[0067] Example 2: According to the method of Example 1, wherein: the plurality of channels includes one or more redundant channels; and the method further includes: determining a fault on a first channel among the plurality of channels by a first communication device, the first channel being driven by a first LED; and in response to determining the fault on the first channel among the plurality of channels, transferring transmission from the channel where the fault was detected to a redundant channel among the one or more redundant channels by the first communication device, the redundant channel being driven by a second LED, the second LED being different from the first LED.

[0068] Example 3: According to the method described in Example 2, determining a fault on the first channel includes: receiving an indication of a fault on the first channel from the second communication device via a sideband channel between the first communication device and the second communication device.

[0069] Example 4: According to the method described in Example 3, determining a fault on the first channel includes: receiving an indication of a fault on the first channel in response to the second communication device detecting that the bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period.

[0070] Example 5: The method according to any one of Examples 2 to 5, wherein transferring transmission from a first channel where a fault is detected to a redundant channel includes: generating a copy of the data mapped onto the first channel where the fault is detected; and multiplexing the copy of the data into a redundant channel among one or more redundant channels without shifting data from other channels among the plurality of channels.

[0071] Example 6: The method according to any one of Examples 1 to 5, wherein: receiving the bit set includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and the method further includes: encoding the encoded data stream by a first communication device using a second Reed-Solomon code having a second codeword length, the second codeword length being different from the first codeword length.

[0072] Example 7: According to the method described in Example 6, wherein: receiving the bit set includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first symbol size; and the method further includes: encoding the encoded data stream by a first communication device using a second Reed-Solomon code having a second symbol size, the second symbol size being different from the first symbol size.

[0073] Example 8: The method according to Example 7 further includes: before encoding the data bit set using the second Reed-Solomon code, remapping the data bit set to maximize the mapping of bits corresponding to the same codeword of the first Reed-Solomon code to the same channel among multiple channels of the optical communication link.

[0074] Example 9: The method according to any one of Examples 1 to 8, wherein: receiving the bit set includes: receiving the bit set at a first clock rate; and transmitting the multiplexed bit set through multiple channels includes: transmitting the multiplexed bit set at a specific clock rate, wherein the specific clock rate is an integer multiple of the first clock rate.

[0075] Example 10: The method according to any one of Examples 1 to 9, wherein transmitting a multiplexed set of bits through multiple channels of an optical communication link comprises: modulating a corresponding light-emitting diode (LED) to generate a corresponding optical signal based on a corresponding bit in the set of bits; and transmitting the corresponding optical signal through a corresponding channel of a multiple channel of an optical communication link.

[0076] Example 11: A first communication device includes: a transceiver including a receiver configured to receive a set of bits for transmission via a plurality of channels of an optical communication link, each of the plurality of channels including a corresponding optical fiber driven by a corresponding light-emitting diode (LED), wherein the optical communication link includes a larger number of channels than the number of channels required to support transmission at a specific clock rate to provide a maximum speed supported by the optical communication link; one or more multiplexers configured to multiplex the set of data bits for transmission via a corresponding channel of the plurality of channels, including one or both of the following: i) using a larger number of channels for transmitting error correction bits in addition to transmitting the set of bits via the plurality of channels at a specific clock rate at the maximum speed supported by the optical communication link; and ii) using a larger number of channels to provide one or more redundant channels in the optical communication link; and a transmitter configured to transmit the multiplexed set of bits to a second communication device via the plurality of channels of the optical communication link.

[0077] Example 12: According to the first communication device of Example 11, wherein: the plurality of channels include one or more redundant channels; and the transceiver further includes a redundancy controller configured to determine a fault on a first channel among the plurality of channels, the first channel being driven by a first LED, and in response to determining a fault on the first channel among the plurality of channels, to transfer transmission from the channel where the fault is detected to a redundant channel among the one or more redundant channels, the redundant channel being driven by a second LED, the second LED being different from the first LED.

[0078] Example 13: According to the first communication device of Example 12, the redundancy controller is configured to receive an indication of a fault on a first channel from the second communication device at least through a sideband channel between the first and second communication devices to determine a fault on the first channel among a plurality of channels.

[0079] Example 14: According to the first communication device of Example 13, the redundancy controller is configured to determine a fault on the first channel by receiving an indication at least in response to the second communication device detecting that the bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period.

[0080] Example 15: A first communication device according to any one of Examples 12 to 14, wherein the redundancy controller is configured to transfer transmission from a first channel where a fault is detected to a redundant channel by at least the following: generating a copy of the data mapped to the first channel where the fault is detected; and multiplexing the copy of the data onto the redundant channel without shifting data from other channels among the plurality of channels.

[0081] Example 15: A first communication device according to any one of Examples 11 to 14, wherein the set of bits received by the receiver is an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and the transceiver further includes an encoder configured to encode the encoded data stream using a second Reed-Solomon code having a second codeword length different from the first codeword length.

[0082] Example 16: According to the first communication device of Example 15, wherein: the encoded data stream is encoded by a first Reed-Solomon code having a first symbol size; and the encoder is configured to encode the encoded data stream using a second Reed-Solomon code having a second symbol size different from the first symbol size.

[0083] Example 17: The first communication device according to Example 16, wherein the transceiver further includes a remapper configured to remap the data bit set before encoding the data bit set using the second Reed-Solomon code, so as to maximize the mapping of bits corresponding to the same codeword of the first Reed-Solomon code to the same channel among multiple channels of the optical communication link.

[0084] Example 19: A first communication device according to any one of Examples 11 to 18, wherein the receiver is configured to receive a set of bits at a first clock rate; and the transmitter is configured to transmit a multiplexed set of bits through multiple channels at a specific clock rate, wherein the specific clock rate is an integer multiple of the first clock rate.

[0085] Example 20: A first communication device according to any one of Examples 11 to 19, wherein the transmitter is configured to transmit a multiplexed set of bits through a plurality of channels of an optical communication link by at least the following: modulating a corresponding light-emitting diode (LED) to generate a corresponding optical signal based on a corresponding bit in the set of bits; and transmitting the corresponding optical signal through a corresponding channel of a plurality of channels of the optical communication link.

[0086] At least some of the aforementioned blocks, operations, and techniques can be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any computer-readable storage device coupled to the processor, such as RAM, ROM, flash memory, etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause one or more processors to perform various actions.

[0087] When implemented in hardware, the hardware may include one or more of the following: discrete components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs).

[0088] Although the invention has been described with reference to specific examples, these specific examples are intended to be illustrative only and not to limit the invention. Changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention. Claims (as amended under Article 19 of the Treaty) 1. A method for communicating via an optical communication link, the method comprising: At a first communication device, a host clock is used to receive a set of bits for transmission through multiple channels of the optical communication link, each of the multiple channels comprising a corresponding optical fiber driven by a corresponding light-emitting diode (LED), wherein the set of bits comprises multiple bits received in parallel using the host clock, and wherein the optical communication link comprises a larger number of channels than the number of channels required to support transmission at a specific clock rate, in order to provide the maximum speed supported by the optical communication link. The first communication device uses a line clock to multiplex the bit set for transmission through a set of data channels among the plurality of channels of the optical communication link, wherein i) the number of data channels in the set of data channels is less than the number of bits in the bit set, and ii) the line clock is proportional to the host clock by a factor determined based on a) the number of data channels in the set of data channels and b) the number of bits in the bit set, and wherein multiplexing the bit set includes one or both of the following: i) using a larger number of the channels of the optical communication link to transmit error correction bits in addition to transmitting the bit set through the set of data channels of the optical communication link at the rate of the line clock; and ii) using a larger number of the channels of the optical communication link to provide one or more redundant channels in the optical communication link; and The first communication device transmits the multiplexed set of bits to the second communication device via the optical communication link. 2. The method according to claim 1, wherein: The plurality of channels includes one or more redundant channels; and The method further includes: The first communication device determines a fault on a first channel among the plurality of channels, the first channel being driven by a first LED, and In response to determining a fault on the first channel among the plurality of channels, the first communication device transfers transmission from the first channel where the fault was detected to a redundant channel among the one or more redundant channels, the redundant channel being driven by a second LED, the second LED being different from the first LED. 3. The method of claim 2, wherein determining the fault on the first channel comprises: receiving an indication of the fault on the first channel from the second communication device via a sideband channel between the first communication device and the second communication device. 4. The method of claim 3, wherein determining the fault on the first channel comprises: receiving the indication of the fault on the first channel in response to the second communication device detecting that the bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period. 5. The method of claim 2, wherein transferring transmission from the first channel where the fault was detected to the redundant channel comprises: Generate a copy of the data mapped to the first channel where the fault was detected; and The copy of the data is multiplexed onto one or more redundant channels without shifting data from other channels among the multiple channels. 6. The method according to claim 1, wherein: Receiving the set of bits includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and The method further includes: encoding the encoded data stream by the first communication device using a second Reed-Solomon code having a second codeword length different from the first codeword length. 7. The method of claim 6, wherein: Receiving the set of bits includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first symbol size; and The method further includes: encoding the encoded data stream by the first communication device using a second Reed-Solomon code having a second symbol size different from the first symbol size. 8. The method of claim 7, further comprising: remapping the set of data bits before further encoding the encoded data stream using the second Reed-Solomon code to maximize the mapping of bits corresponding to the same codeword of the first Reed-Solomon code to the same channels of the plurality of channels of the optical communication link. 9. The method according to claim 1, wherein: Receiving the bit set includes: receiving the bit set at the rate of the host clock; and Transmitting the multiplexed set of bits via the optical communication link includes transmitting the multiplexed set of bits at the rate of the line clock. 10. The method of claim 1, wherein transmitting the multiplexed set of bits through the plurality of channels of the optical communication link comprises: The corresponding light-emitting diode (LED) is modulated to generate a corresponding optical signal based on the corresponding bits in the multiplexed bit set; and The corresponding optical signal is transmitted through the corresponding channel in the set of data channels among the plurality of channels of the optical communication link. 11. A first communication device, comprising: Transceiver, the transceiver comprising: A receiver configured to receive, using a host clock, a set of bits for transmission via multiple channels of an optical communication link, each channel comprising a corresponding optical fiber driven by a corresponding light-emitting diode (LED), wherein the set of bits comprises multiple bits received in parallel using the host clock, and wherein the optical communication link comprises a larger number of channels than are required to support transmission at a specific clock rate, to provide the maximum speed supported by the optical communication link. One or more multiplexers are configured to multiplex the bit set using a line clock for transmission through a set of data channels among the plurality of channels of the optical communication link, wherein i) the number of data channels in the set of data channels is less than the number of bits in the bit set, and ii) the line clock is proportional to the host clock by a factor determined based on a) the number of data channels in the set of data channels and b) the number of bits in the bit set, and wherein multiplexing the bit set includes one or both of: i) using a larger number of the channels of the optical communication link to transmit error correction bits in addition to transmitting the bit set through the set of data channels of the optical communication link at the rate of the line clock; and ii) using a larger number of the channels of the optical communication link to provide one or more redundant channels in the optical communication link; and A transmitter configured to transmit the multiplexed set of bits to a second communication device via the optical communication link. 12. The first communication device according to claim 11, wherein: The plurality of channels includes one or more redundant channels; and The transceiver also includes a redundant controller, which is configured to: A fault is identified in the first of the plurality of channels, the first channel being driven by a first LED, and In response to determining a fault on the first channel of the plurality of channels, transmission is transferred from the first channel where the fault was detected to a redundant channel of the one or more redundant channels, the redundant channel being driven by a second LED, the second LED being different from the first LED. 13. The first communication device of claim 12, wherein the redundancy controller is configured to receive an indication of a fault on the first channel from the second communication device at least via a sideband channel between the first communication device and the second communication device, to determine the fault on the first channel among the plurality of channels. 14. The first communication device of claim 13, wherein the redundancy controller is configured to determine the fault on the first channel by receiving the indication at least in response to the second communication device detecting that a bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period. 15. The first communication device of claim 12, wherein the redundancy controller is configured to transfer transmission from the first channel where the fault is detected to the redundant channel by at least the following: Generate a copy of the data mapped to the first channel where the fault was detected; and The copy of the data is multiplexed onto the redundant channel without shifting data from other channels among the plurality of channels. 16. The first communication device according to claim 11, wherein: The set of bits received by the receiver is an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and The transceiver also includes an encoder configured to encode the encoded data stream using a second Reed-Solomon code having a second codeword length different from the first codeword length. 17. The first communication device according to claim 16, wherein: The encoded data stream is encoded using a first Reed-Solomon code having a first symbol size; and The encoder is configured to encode the encoded data stream using a second Reed-Solomon code having a second symbol size different from the first symbol size. 18. The first communication device of claim 16, wherein the transceiver further comprises a remapper configured to remap the set of data bits before encoding the encoded data stream using the second Reed-Solomon code, to maximize the mapping of bits corresponding to the same codeword of the first Reed-Solomon code to the same channels among the plurality of channels of the optical communication link. 19. The first communication device according to claim 11, wherein: The receiver is configured to receive the bit set at the rate of the host clock; and The transmitter is configured to transmit the multiplexed set of bits at the rate of the line clock via the optical communication link. 20. The first communication device of claim 11, wherein the transmitter is configured to transmit a multiplexed set of bits through the plurality of channels of the optical communication link at least by: The corresponding light-emitting diode (LED) is modulated to generate a corresponding optical signal based on the corresponding bits in the multiplexed bit set; and The corresponding optical signal is transmitted through a corresponding channel in the data channel set among the plurality of channels of the optical communication link.

Claims

1. A method for communicating via an optical communication link, the method comprising: A set of bits for transmission via multiple channels of the optical communication link is received at a first communication device, wherein each of the multiple channels includes a corresponding optical fiber driven by a corresponding light-emitting diode (LED), and wherein the optical communication link includes a larger number of channels than the number of channels required to support transmission at a specific clock rate, so as to provide the maximum speed supported by the optical communication link. The first communication device multiplexes the data bit set for transmission through a corresponding channel among the plurality of channels, including one or both of the following: i) using a larger number of the channels to transmit error correction code bits in addition to transmitting the bit set through the plurality of channels at the specific clock rate at the maximum speed supported by the optical communication link; and ii) using a larger number of the channels to provide one or more redundant channels in the optical communication link; as well as The first communication device transmits the multiplexed set of bits to the second communication device through the multiple channels of the optical communication link.

2. The method according to claim 1, wherein: The plurality of channels includes one or more redundant channels; and The method further includes: The first communication device determines a fault on a first channel among the plurality of channels, the first channel being driven by a first LED, and In response to determining a fault on the first channel among the plurality of channels, the first communication device transfers transmission from the channel where the fault was detected to a redundant channel among the one or more redundant channels, the redundant channel being driven by a second LED, the second LED being different from the first LED.

3. The method of claim 2, wherein determining the fault on the first channel comprises: The fault indication on the first channel is received from the second communication device via the sideband channel between the first communication device and the second communication device.

4. The method of claim 3, wherein determining the fault on the first channel comprises: In response to the second communication device detecting that the bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period, the device receives the indication of the fault on the first channel.

5. The method of claim 2, wherein transferring transmission from the first channel where the fault was detected to the redundant channel comprises: Generate a copy of the data mapped to the first channel on which the fault was detected; as well as The copy of the data is multiplexed onto one of the one or more redundant channels without shifting data from other channels among the multiple channels.

6. The method according to claim 1, wherein: Receiving the set of bits includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and The method further includes: encoding the encoded data stream by the first communication device using a second Reed-Solomon code having a second codeword length different from the first codeword length.

7. The method of claim 6, wherein: Receiving the set of bits includes: receiving an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first symbol size; and The method further includes: encoding the encoded data stream by the first communication device using a second Reed-Solomon code having a second symbol size different from the first symbol size.

8. The method according to claim 7, further comprising: Before encoding the data bit set using the second Reed-Solomon code, the data bit set is remapped to maximize the mapping of bits corresponding to the same codewords of the first Reed-Solomon code to the same channels among the plurality of channels of the optical communication link.

9. The method according to claim 1, wherein: Receiving the bit set includes: receiving the bit set at a first clock rate; and Transmitting the multiplexed bit set through the multiple channels includes transmitting the multiplexed bit set at the specific clock rate, wherein the specific clock rate is an integer multiple of the first clock rate.

10. The method of claim 1, wherein transmitting the multiplexed set of bits through the plurality of channels of the optical communication link comprises: The corresponding light-emitting diode (LED) is modulated to generate a corresponding light signal based on the corresponding bit in the bit set; as well as The corresponding optical signal is transmitted through a corresponding channel among the plurality of channels of the optical communication link.

11. A first communication device, comprising: Transceiver, the transceiver comprising: A receiver configured to receive a set of bits for transmission via multiple channels of an optical communication link, each channel comprising a corresponding optical fiber driven by a corresponding light-emitting diode (LED), wherein the optical communication link comprises a larger number of channels than are required to support transmission at a specific clock rate, in order to provide the maximum speed supported by the optical communication link. One or more multiplexers configured to multiplex the data bit set for transmission through a respective channel of the plurality of channels, including one or both of the following: i) using a larger number of the channels to transmit error correction code bits in addition to transmitting the bit set through the plurality of channels at the specific clock rate at the maximum speed supported by the optical communication link; and ii) using a larger number of the channels to provide one or more redundant channels in the optical communication link; and A transmitter configured to transmit the multiplexed set of bits to a second communication device via the plurality of channels of the optical communication link.

12. The first communication device according to claim 11, wherein: The plurality of channels includes one or more redundant channels; and The transceiver also includes a redundant controller, which is configured to: A fault is identified in the first of the plurality of channels, the first channel being driven by a first LED, and In response to determining a fault on the first channel among the plurality of channels, transmission is transferred from the channel where the fault was detected to a redundant channel among the one or more redundant channels, the redundant channel being driven by a second LED, the second LED being different from the first LED.

13. The first communication device of claim 12, wherein the redundancy controller is configured to receive an indication of a fault on the first channel from the second communication device at least via a sideband channel between the first communication device and the second communication device, to determine the fault on the first channel among the plurality of channels.

14. The first communication device of claim 13, wherein the redundancy controller is configured to determine the fault on the first channel by receiving the indication at least in response to the second communication device detecting that a bit stream received from the first channel is stuck at a bit value of 0 or a bit value of 1 for a predetermined time period.

15. The first communication device of claim 12, wherein the redundancy controller is configured to transfer transmission from the first channel where the fault is detected to the redundant channel by at least the following: Generate a copy of the data mapped to the first channel where the fault was detected; and The copy of the data is multiplexed onto the redundant channel without shifting data from other channels among the plurality of channels.

16. The first communication device according to claim 11, wherein: The set of bits received by the receiver is an encoded data stream, wherein the encoded data stream is encoded by a first Reed-Solomon code having a first codeword length; and The transceiver also includes an encoder configured to encode the encoded data stream using a second Reed-Solomon code having a second codeword length different from the first codeword length.

17. The first communication device according to claim 16, wherein: The encoded data stream is encoded using a first Reed-Solomon code having a first symbol size; and The encoder is configured to encode the encoded data stream using a second Reed-Solomon code having a second symbol size different from the first symbol size.

18. The first communication device of claim 16, wherein the transceiver further comprises a remapper configured to remap the data bit set before encoding the data bit set using the second Reed-Solomon code, so as to maximize the mapping of bits corresponding to the same codeword of the first Reed-Solomon code to the same channels among the plurality of channels of the optical communication link.

19. The first communication device according to claim 11, wherein: The receiver is configured to receive the bit set at a first clock rate; and The transmitter is configured to transmit the multiplexed set of bits through the plurality of channels at the specific clock rate, wherein the specific clock rate is an integer multiple of the first clock rate.

20. The first communication device of claim 11, wherein the transmitter is configured to transmit a multiplexed set of bits through the plurality of channels of the optical communication link at least by: The corresponding light-emitting diode (LED) is modulated to generate a corresponding light signal based on the corresponding bit in the bit set; and The corresponding optical signal is transmitted through a corresponding channel among the plurality of channels of the optical communication link.

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