A memory object allocation method and device, electronic equipment and medium

Abstract

Embodiments of the present application provide a memory object allocation method and device, electronic equipment and medium, relating to the technical field of computer, which is applied to a kernel in a multi-core system. The kernel manages a primary cache pool and a backup cache pool corresponding to a plurality of CPUs and a node cache unit corresponding to a plurality of memory nodes. The node cache unit manages a full cache pool and an empty cache pool. The method comprises: obtaining a memory allocation request for a task on a CPU; if the primary cache pool is an empty cache pool and the second cache pool is a full cache pool, swapping the primary and backup cache pools, and allocating an idle memory object to the task from the swapped primary cache pool; obtaining a full cache pool from a node cache unit corresponding to a memory node to which the CPU belongs as a new backup cache pool, and storing the swapped backup cache pool to the node cache unit. The scheme can reduce global lock contention and atomic operation, improve memory node locality and cache efficiency, and reduce allocation delay.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and medium for allocating memory objects. Background Technology

[0002] In multi-core systems such as those with Non-Uniform Memory Access (NUMA), the Linux kernel's memory allocator (such as the SLUB allocator) employs a hybrid management model of static pre-allocation and fixed threshold allocation. A fixed threshold of free memory objects is pre-allocated to each Central Processing Unit (CPU), forming a free object list for each CPU. When the kernel requests memory allocation, it quickly allocates memory objects from the current CPU's free list. If there are no free memory objects in the free list, it enters a slower path, using the memory allocator to migrate memory pages (slabs) from memory nodes to the current CPU.

[0003] In existing SLUB allocators, each CPU maintains only a simple freelist of objects. In high-concurrency scenarios, this architecture suffers from two main bottlenecks: First, when the local freelist is exhausted, the CPU must acquire a global lock to migrate memory pages from a partial slab list of a memory node; this lock contention becomes the primary performance bottleneck. Second, object allocation and deallocation directly interact with slab pages, leading to frequent cache line invalidation and increased fragmentation. Especially in NUMA systems, it is difficult to guarantee the locality of memory access, resulting in increased latency for remote access. Summary of the Invention

[0004] The purpose of this application is to provide a memory object allocation method, apparatus, electronic device, and medium to reduce global lock contention and atomic operations, improve memory node locality and cache efficiency, and reduce allocation latency. The specific technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide a memory object allocation method applied to the kernel of a multi-core system. The kernel manages a primary cache pool and a backup cache pool corresponding to multiple CPUs, and a node cache unit corresponding to multiple memory nodes. The primary cache pool and the backup cache pool manage free memory objects, and the node cache unit manages a full cache pool and an empty cache pool. The full cache pool includes a first preset number of free memory objects, and the empty cache pool does not include free memory objects. The method includes: obtaining a first memory allocation request for a first task on a first CPU; the first CPU corresponds to a first cache pool and a second cache pool, the first cache pool being the primary cache pool and the second cache pool being the backup cache pool; if the first cache pool is an empty cache pool and the second cache pool is a full cache pool, then the second cache pool is switched to the primary cache pool, the first cache pool is switched to the backup cache pool, and a free memory object is allocated from the second cache pool for the first task; obtaining a third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs, the third cache pool being a full cache pool; switching the third cache pool to the backup cache pool corresponding to the first CPU, and storing the first cache pool in the first node cache unit.

[0006] In some embodiments, the method further includes: if the first cache pool is an empty cache pool and the second cache pool is an empty cache pool, then obtaining a free memory object from the free object list of the first CPU and filling the obtained free memory object into the first cache pool; if the first cache pool is not an empty cache pool, then allocating a free memory object for the first task from the first cache pool.

[0007] In some embodiments, the method further includes: if the third cache pool is obtained, then performing the step of switching the third cache pool to the standby cache pool corresponding to the first CPU; if the third cache pool is not obtained, then obtaining a free memory object from the free object list of the first CPU and filling the obtained free memory object into the first cache pool.

[0008] In some embodiments, the method further includes: if the free object list of the first CPU does not contain a free memory object, then calling the memory allocator to migrate memory page blocks from the partial memory page block list of the first memory node; generating a free memory object based on the migrated memory page block, and writing the generated free memory object into the free object list of the first CPU; and re-executing the step of obtaining a free memory object from the free object list of the first CPU.

[0009] In some embodiments, the method further includes: obtaining a first memory release request for the first task on the first CPU; if the first cache pool is a full cache pool, switching the second cache pool to a primary cache pool, switching the first cache pool to a standby cache pool, and writing the memory object included in the first memory release request into the second cache pool; obtaining a fourth cache pool from the first node cache unit, the fourth cache pool being an empty cache pool; switching the fourth cache pool to a standby cache pool corresponding to the first CPU, and storing the first cache pool in the first node cache unit.

[0010] In some embodiments, the method further includes: if the first cache pool is not a full cache pool, then writing the memory object included in the first memory release request into the first cache pool.

[0011] In some embodiments, the method further includes: if the number of free memory objects included in the first node cache unit is greater than a second preset number, then the free memory objects included in the first node cache unit are released to the memory allocator, and the number of free memory objects included in the first node cache unit after release is less than or equal to the second preset number.

[0012] In some embodiments, the kernel further manages multiple CPU-corresponding delayed release cache pools, which manage delayed release memory objects; the method further includes: obtaining a delayed release request for the first task on the first CPU; writing the memory object included in the delayed release request into a fifth cache pool corresponding to the first CPU, the fifth cache pool being a delayed release cache pool corresponding to the first CPU; when the fifth cache pool is a full cache pool, invoking a second CPU to store the fifth cache pool into the first node cache unit, and obtaining a sixth cache pool from the first node cache unit, the sixth cache pool being an empty cache pool; and switching the sixth cache pool to the delayed release cache pool corresponding to the first CPU.

[0013] In some embodiments, the method further includes: obtaining a free memory object from the free object list of the first CPU and filling the obtained free memory object into a dedicated cache pool corresponding to the second task on the first CPU; allocating a free memory object for the second task from the dedicated cache pool after a second memory allocation request for the second task; and writing the memory object included in the second memory release request into the dedicated cache pool after obtaining a second memory release request for the second task.

[0014] In some embodiments, the method further includes: obtaining a third memory release request for a third task on a first CPU, wherein the memory object included in the third memory release request corresponds to a memory page block on a second memory node; and releasing the memory object included in the third memory release request to a memory allocator.

[0015] In some embodiments, the method further includes: configuring the maximum capacity of the cache pool through a cache creation interface; and when the maximum capacity is 0, using the CPU's list of free objects to process free memory objects.

[0016] Secondly, embodiments of this application provide a memory object allocation device applied to the kernel of a multi-core system. The kernel manages a primary cache pool and a backup cache pool corresponding to multiple CPUs, and a node cache unit corresponding to multiple memory nodes. The primary cache pool and the backup cache pool manage free memory objects, and the node cache unit manages a full cache pool and an empty cache pool. The full cache pool includes a first preset number of free memory objects, and the empty cache pool does not include free memory objects. The device includes:

[0017] The first acquisition module is used to acquire the first memory allocation request for the first task on the first CPU; the first CPU corresponds to a first cache pool and a second cache pool, the first cache pool is the primary cache pool, and the second cache pool is the backup cache pool.

[0018] The first switching module is used to switch the second cache pool to the primary cache pool and the first cache pool to the standby cache pool if the first cache pool is empty and the second cache pool is full, and to allocate a free memory object for the first task from the second cache pool.

[0019] The second acquisition module is used to acquire a third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs, wherein the third cache pool is a full cache pool;

[0020] The second switching module is used to switch the third cache pool to the backup cache pool corresponding to the first CPU, and to store the first cache pool in the first node cache unit.

[0021] Thirdly, embodiments of this application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement any of the methods described above when executing the program stored in the memory.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the methods described above.

[0023] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the methods described above.

[0024] Beneficial effects of the embodiments in this application:

[0025] In the technical solution provided in this application, the kernel manages multiple primary and backup cache pools corresponding to CPUs, as well as node cache units corresponding to multiple memory nodes. When allocating memory objects, the kernel first obtains free memory objects from the primary cache pool corresponding to the current CPU, and then obtains full cache pools from the node cache units corresponding to the current CPU to replace empty cache pools (such as backup cache pools) corresponding to the current CPU. By introducing a dedicated cache pool (Pool) for each CPU and a node cache unit (Cell) for each memory node, a two-level cache management system is constructed. This system localizes most memory allocation / release operations within the CPU's cache pool, significantly reducing global lock contention and atomic operations; and by managing the batch transfer of cache pool resources through node-level Cells, it improves memory node locality and cache efficiency. Thus, it not only reduces allocation latency under sudden loads, but also comprehensively improves system throughput and scalability under high concurrency, and effectively controls memory fragmentation.

[0026] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0028] Figure 1 A flowchart illustrating a memory object allocation method provided in an embodiment of this application;

[0029] Figure 2 A flowchart illustrating a memory object release method provided in an embodiment of this application;

[0030] Figure 3 Another flowchart illustrating the memory object release method provided in this application embodiment;

[0031] Figure 4 A schematic diagram of the memory object management mechanism provided in the embodiments of this application;

[0032] Figure 5 A schematic diagram of a memory object allocation device provided in an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0035] For ease of understanding, the terms appearing in the embodiments of this application are explained below.

[0036] Cache pool: A batch object cache maintained by each CPU. The cache pool can be viewed as a coarser-grained version of per-CPU memory slabs, similar to a freelist. It stores a set of free memory objects pulled from slab pages, i.e., memory slabs migrated from memory nodes using a memory allocator (such as SLUB allocation). Free memory objects: Unoccupied memory objects.

[0037] Each CPU's cache pool can include a main pool, a spare pool, and a delayed-release pool (such as the rcu_free pool).

[0038] Primary cache pool: The cache pool that is currently allocated priority for use.

[0039] Backup cache pool: When the primary cache pool is empty or full, it can be replaced by the primary cache pool.

[0040] Delayed Release Cache Pool: A batch cache of memory objects used for delayed release (such as in the kfree_rcu scenario).

[0041] The capacity of a cache pool can be specified by the pool_capacity parameter. For example, a cache pool can cache a maximum of N objects, where N is the first preset number specified by the pool_capacity parameter. A cache pool is considered full if it contains the first preset number of free memory objects, and an empty cache pool is considered empty if it contains zero free memory objects.

[0042] A node cache cell is a management structure attached to each memory node (e.g., `kmem_cache_node`) used to store a list of available cache pools on that memory node. A node cache cell can contain two cache pool lists: a full pool list and an empty pool list. The full pool list contains all full cache pools. The empty pool list contains all empty cache pools. The node cache cell can use spinlocks to protect the full and empty pool lists. Cross-CPU pool resource swapping / reclamation all pass through the node cache cell.

[0043] In this embodiment of the application, the number of full cache pools (such as Max_Full_Pools) or empty cache pools (such as Min_Empty_Pools) retained by the node cache unit can be limited to avoid occupying too much free memory.

[0044] In this embodiment, the cache pool is an immediate cache (per-CPU level) for allocation and release operations. The cache pool is a batch memory object cache held by each CPU to accelerate allocation and release. The node cache unit is the resource manager within a memory node (such as a NUMA node) that schedules these cache pools across CPUs. The node cache unit is the "switching station" for each memory node to manage these cache pools, realizing the recycling and cross-CPU allocation of cache pool resources among multiple CPUs within the memory node.

[0045] To address the issue of delayed replenishment of free memory objects in the local Freelist during sudden load surges, forcing numerous memory allocation requests into slow paths and increasing memory allocation latency, this application provides a memory object allocation method, such as... Figure 1 As shown, the kernel applied to a multi-core system manages multiple primary and secondary cache pools corresponding to CPUs, as well as node cache units corresponding to multiple memory nodes. The primary and secondary cache pools manage free memory objects, and the node cache units manage full and empty cache pools. A full cache pool includes a first preset number of free memory objects, and an empty cache pool does not include free memory objects. The method includes:

[0046] Step S101: Obtain the first memory allocation request for the first task on the first CPU; the first CPU corresponds to the first cache pool and the second cache pool, the first cache pool is the primary cache pool, and the second cache pool is the backup cache pool.

[0047] Step S102: If the first cache pool is an empty cache pool and the second cache pool is a full cache pool, then the second cache pool is switched to the primary cache pool, the first cache pool is switched to the standby cache pool, and a free memory object is allocated for the first task from the second cache pool.

[0048] Step S103: Obtain the third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs. The third cache pool is a full cache pool.

[0049] Step S104: Switch the third cache pool to the backup cache pool corresponding to the first CPU, and store the first cache pool in the first node cache unit.

[0050] In the technical solution provided in this application, the kernel manages multiple primary and backup cache pools corresponding to multiple CPUs, as well as node cache units corresponding to multiple memory nodes. When allocating memory objects, the kernel first obtains free memory objects from the primary cache pool corresponding to the current CPU, and then obtains full cache pools from the node cache units corresponding to the current CPU to replace the empty cache pools (such as backup cache pools) corresponding to the current CPU. In this way, when a sudden load occurs, when all the free memory objects in the primary cache pool are allocated, that is, when the primary cache pool is empty, the kernel quickly completes the replacement between the primary and backup cache pools, omitting the operation of migrating memory page blocks from memory nodes using the memory allocator, thus reducing memory allocation latency.

[0051] In step S101 above, the two cache pools corresponding to the first CPU are the first cache pool and the second cache pool, wherein the first cache pool is the primary cache pool and the second cache pool is the backup cache pool.

[0052] The first task can be any task executed on the first CPU. The first memory allocation request is used to request the allocation of free memory objects for the first task, such as for network packet processing. The number of free memory objects requested in the first memory allocation request can be one or more.

[0053] The kernel can call the first CPU to obtain the first memory allocation request, that is, the first CPU acts as the current CPU and receives the first memory allocation request.

[0054] In step S102 above, after receiving the first memory allocation request, the kernel checks whether the first cache pool, which serves as the primary cache pool, is empty. If the first cache pool is empty and the second cache pool is full, it means that the first cache pool has no free memory objects available for allocation, but the second cache pool is available. The kernel can then call the first CPU to switch between the primary and standby cache pools, that is, to switch the second cache pool to the primary cache pool and the first cache pool to the standby cache pool. In this way, the kernel can call the first CPU to obtain free memory objects from the second cache pool, which serves as the primary cache pool, and allocate the obtained free memory objects to the first task for the first task to cache data.

[0055] In some embodiments, if the first cache pool is an empty cache pool and the second cache pool is an empty cache pool, the kernel obtains free memory objects from the free list of the first CPU and fills the obtained free memory objects into the first cache pool.

[0056] In this embodiment, the application applies to the initial state. When the first cache pool is empty and the second cache pool is empty, it means that neither the first cache pool nor the second cache pool has any free memory objects available for allocation. The kernel can call the first CPU to obtain free memory objects from the first CPU's freelist and fill the obtained free memory objects into the primary cache pool, i.e., the first cache pool, so as to quickly allocate memory objects for tasks.

[0057] In some embodiments, if the first cache pool is not empty, it means that there are still free memory objects available for allocation in the first cache pool. The kernel can allocate free memory objects for the first task from the first cache pool, that is, call the first CPU to directly obtain free memory objects from the first cache pool, which is the primary cache pool, and allocate the obtained free memory objects to the first task for the first task to cache data. In this scheme, there is no need to switch between the primary and backup cache pools, which further reduces memory allocation latency.

[0058] In this embodiment, memory objects are preferentially obtained from the local primary cache pool. Only when the primary cache pool does not contain free memory objects (i.e., a miss) are other slower CPU resources (such as resources in node cache units) or slab pages accessed, thus accelerating memory object allocation.

[0059] In addition, the allocation of some memory objects is restricted to the per-CPU cache pool. In this case, the kernel can use a lightweight local_lock for protection, which reduces lock contention and lock costs.

[0060] In addition, objects can be transferred in batches between cache pools, such as when the kernel switches between primary and standby cache pools. This batch operation reduces the number of atomic operations such as Compare and Swap (CAS), thus reducing the cost of operations and locks.

[0061] In step S103 above, the first memory node is the memory node to which the first CPU belongs, and the node cache unit corresponding to the first memory node is the first node cache unit. After the kernel switches the primary and backup cache pools, the kernel can call the first CPU to obtain a full cache pool from the full pool list included in the first node cache unit. This full cache pool is the third cache pool.

[0062] In step S104 above, the kernel can call the first CPU to replace the backup cache pool, that is, replace the backup cache pool corresponding to the first CPU with the third cache pool, and add the first cache pool, which is the backup cache pool, to the list of empty pools included in the first node cache unit.

[0063] In some embodiments, if a third cache pool is obtained, the kernel executes step S104 to switch the third cache pool to the standby cache pool corresponding to the first CPU; if a third cache pool is not obtained, the kernel can obtain free memory objects from the free object list of the first CPU and fill the obtained free memory objects into the first cache pool.

[0064] In this embodiment, when the primary cache pool corresponding to a CPU on a memory node becomes empty, the kernel retrieves a full cache pool from the node cache unit corresponding to the same memory node to replace the primary cache pool. Each CPU on the memory node can transfer cache pool resources within the node cache unit corresponding to the same memory node, thus achieving cross-CPU resource transfer and avoiding cross-memory node access. Furthermore, cache pools preferentially circulate within the node cache unit corresponding to the memory node. When there is no available full cache pool in the node cache unit, the kernel pulls free memory objects from the CPU's free object list to fill the backup cache pool, facilitating subsequent primary and backup cache pool replacement and improving allocation efficiency. This scheme minimizes the need to access memory objects across memory nodes, such as by using the memory allocator to migrate memory page blocks (slabs) from the underlying layer, reducing remote access latency and ensuring memory node locality.

[0065] In some embodiments, when the free object list of the first CPU does not contain a free memory object, the kernel can invoke the memory allocator to migrate memory pages (slab pages) from the partial slab list of the first memory node; generate a free memory object based on the migrated memory pages, and write the generated free memory object into the free object list of the first CPU. In this way, the kernel can obtain a free memory object from the free object list of the first CPU when the first cache pool is empty, the second cache pool is empty, or when a third cache pool is not available.

[0066] Corresponding to the memory object allocation method, this application embodiment also provides a memory object release method, such as... Figure 2 As shown, the kernel applied to a multi-core system manages primary and secondary cache pools corresponding to multiple CPUs, as well as node cache units corresponding to multiple memory nodes. The primary and secondary cache pools manage free memory objects, and the node cache units manage full and empty cache pools. A full cache pool includes a first preset number of free memory objects, while an empty cache pool does not include any free memory objects. The method may include:

[0067] Step S201: Obtain the first memory release request for the first task on the first CPU;

[0068] Step S202: If the first cache pool is full, then the second cache pool is switched to the primary cache pool, the first cache pool is switched to the standby cache pool, and the memory object included in the first memory release request is written to the second cache pool.

[0069] Step S203: Obtain the fourth cache pool from the first node cache unit. The fourth cache pool is an empty cache pool.

[0070] Step S204: Switch the fourth cache pool to the backup cache pool corresponding to the first CPU, and store the first cache pool in the first node cache unit.

[0071] In the technical solution provided in this application, the kernel manages multiple primary and secondary cache pools corresponding to multiple CPUs, as well as node cache units corresponding to multiple memory nodes. When releasing memory objects, the kernel prioritizes completing the process locally on the current CPU, that is, writing the released free memory objects into the primary cache pool corresponding to the current CPU. When the primary cache pool is full, an empty cache pool is obtained from the node cache unit corresponding to the current CPU to replace the full cache pool (such as the secondary cache pool) corresponding to the current CPU. In this way, when the primary cache pool is full, the kernel can quickly complete the replacement between the primary and secondary cache pools and continue to write the released free memory objects into the primary cache pool corresponding to the current CPU, omitting the operation of releasing free memory objects to the memory allocator and reducing memory release latency.

[0072] In step S201 above, after the first task finishes execution, it needs to release the memory objects allocated to it. A first memory release request is used to request the release of the memory objects allocated to the first task. The number of memory objects requested to be released in the first memory release request can be one or more.

[0073] When releasing a memory object, the kernel can call the first CPU to obtain the first memory release request. That is, the first CPU acts as the current CPU and receives the first memory release request.

[0074] In step S202 above, after receiving the first memory release request, the kernel checks whether the first cache pool, which serves as the primary cache pool, is full. If the first cache pool is full, it means that the first cache pool can no longer store free memory objects. The kernel can then call the first CPU to switch the primary and backup cache pools, that is, to switch the second cache pool to the primary cache pool and switch the first cache pool to the backup cache pool. In this way, the kernel can call the first CPU to write the memory objects included in the first memory release request into the second cache pool, which serves as the primary cache pool.

[0075] In some embodiments, if the first cache pool is not full, it means that the first cache pool can still store free memory objects. The kernel can write the memory objects included in the first memory release request into the first cache pool, that is, call the first CPU to continue storing free memory objects in the first cache pool, which serves as the primary cache pool. In this scheme, there is no need to switch between the primary and backup cache pools, further reducing memory allocation latency.

[0076] In this embodiment, freed memory objects are preferentially written from the local primary cache pool. Only when a free memory object cannot be written to the primary cache pool (i.e., a miss) will other slower CPU resources (such as resources in node cache units) or slab pages be accessed, thereby accelerating the release of memory objects.

[0077] In addition, the release of some memory objects is restricted to the per-CPU cache pool. In this case, the kernel can use a lightweight local_lock for protection, which reduces lock contention and lock costs.

[0078] In addition, objects can be transferred in batches between cache pools, such as when the kernel switches between primary and standby cache pools. This batch operation reduces the number of atomic operations and reduces the cost of operations and locks.

[0079] In step S203 above, after the kernel swaps the primary and backup cache pools, the kernel can call the first CPU to obtain an empty cache pool from the list of empty pools included in the first node cache unit. This empty cache pool is the fourth cache pool.

[0080] In step S204 above, the kernel can call the first CPU to replace the backup cache pool, that is, replace the backup cache pool corresponding to the first CPU with the fourth cache pool, and add the first cache pool, which is the backup cache pool, to the full pool list included in the first node cache unit.

[0081] In some embodiments, if the number of free memory objects included in the first node cache unit is greater than a second preset number, the kernel releases the free memory objects included in the first node cache unit to the memory allocator, and the number of free memory objects included in the first node cache unit after release is less than or equal to the second preset number.

[0082] In this embodiment, the second preset number is the maximum number of free memory objects included in the node cache unit. If the number of free memory objects included in the first node cache unit is greater than the second preset number, the kernel can call the first CPU to release the free memory objects included in the first node cache unit to the memory allocator, so that the number of free memory objects included in the first node cache unit is less than or equal to the second preset number, thus avoiding the occupation of too much free memory.

[0083] In this embodiment, when the primary cache pool corresponding to a CPU on a memory node becomes empty, the kernel retrieves an empty cache pool from the node cache unit corresponding to the same memory node to replace the primary cache pool. Each CPU on the memory node can transfer cache pool resources within the node cache unit corresponding to the same memory node, thus achieving cross-CPU resource transfer and avoiding cross-memory node access. Furthermore, cache pool transfer is preferentially performed within the node cache unit corresponding to the memory node, minimizing the release of memory objects across memory nodes, such as releasing underlying migrated memory pages (slabs), reducing remote access latency and ensuring memory node locality.

[0084] In addition, the node cache unit can be used to return a full cache pool to a node cache unit for use by other CPUs, and to refill an empty cache pool, reducing fragmentation within a single slab.

[0085] In some embodiments, the kernel also manages multiple CPU-specific deferred release cache pools, which manage deferred release memory objects. In this case, such as... Figure 3 As shown, a method for releasing memory objects is also provided, which may include:

[0086] Step S301: Obtain the delayed release request for the first task on the first CPU;

[0087] Step S302: Write the memory object included in the delayed release request into the fifth cache pool corresponding to the first CPU. The fifth cache pool is the delayed release cache pool corresponding to the first CPU.

[0088] Step S303: When the fifth cache pool is full, the second CPU is called to store the fifth cache pool in the first node cache unit and retrieve the sixth cache pool from the first node cache unit. The sixth cache pool is an empty cache pool.

[0089] Step S304: Switch the sixth cache pool to the delayed release cache pool corresponding to the first CPU.

[0090] In the technical solution provided in this application embodiment, the kernel uses a delayed release cache pool to store memory objects that need to be released late. When the delayed release cache pool is full, the kernel releases the delayed release cache pool in batches, that is, it reclaims the memory objects in the delayed release cache pool in batches to the node cache unit, omitting the operation of releasing free memory objects to the memory allocator, further reducing memory release latency and alleviating the latency and overflow problems caused by releasing memory object by object.

[0091] In step S301 above, the delayed release request can be kfree_rcu(), or other types of delayed release requests; this is not limited. The number of memory objects requested to be released in the delayed release request can be one or more. The delayed release request may also include a grace period for delayed release. The grace period represents the duration for which the delayed release of the cache pool is allowed.

[0092] When releasing a memory object, the kernel can call the first CPU to obtain a delayed release request; that is, the first CPU acts as the current CPU and receives the delayed release request.

[0093] In step S302 above, the fifth cache pool is the delayed release cache pool corresponding to the first CPU. After the kernel obtains the delayed release request, it can call the first CPU to write the memory object included in the delayed release request into the fifth cache pool corresponding to the first CPU.

[0094] In step S303 above, the second CPU can be any CPU on the first memory node. The second CPU and the first CPU can be the same or different. The second CPU supports delayed release callbacks. For example, in the kfree_rcu scenario, the second CPU supports Read Copy Update (RCU) callbacks.

[0095] When the fifth cache pool is full, the kernel can submit a message indicating that the fifth cache pool is full to the deferred release subsystem (such as the RCU subsystem), which will then invoke the second CPU to store the fifth cache pool in the full pool list included in the first node cache unit at the end of the grace period. Alternatively, the kernel can also obtain an empty cache pool from the empty pool list included in the first node cache unit; this empty cache pool is the sixth cache pool.

[0096] After obtaining the sixth cache pool, the kernel can execute step S304 to replace the delayed release cache pool corresponding to the first CPU with the sixth cache pool.

[0097] In this embodiment, the kernel configures an independent delayed-release cache pool for each CPU and performs batch buffering and tempering on delayed-release memory objects. After the grace period ends, the delayed-release cache pool is preferentially reused as an allocatable cache, i.e., placed in the node cache unit, rather than being returned to the underlying slab. This measure reduces the overhead of frequent allocation and reclamation, reduces memory object fragmentation, and maintains efficient reclamation capabilities in some CPU memory nodes where delayed release can be called back.

[0098] In some embodiments, the kernel can configure a preallocation interface (Application Programming Interface, API). The kernel can call the preallocation interface to retrieve free memory objects from the free object list of the first CPU and populate the first object pool, which serves as the primary cache pool. This allows for rapid execution of steps S101 to S104 in the initial state to allocate memory objects.

[0099] This application provides an efficient memory object pre-allocation mechanism. The kernel can borrow and fill the cache pool before entering a critical path or restricted context, ensuring that the required allocation is completed without blocking or failure in scenarios with a known worst-case allocation limit. After the task is completed, the memory objects can be quickly returned to the node cache unit, thereby significantly reducing the inefficient process of batch allocation based on the worst-case scenario and centralized release of unused memory objects, which is suitable for operations that require immediate allocation.

[0100] In some embodiments, the kernel can configure a pre-allocation interface. The kernel can call the pre-allocation interface to obtain free memory objects from the free object list of the first CPU and fill the obtained free memory objects into the dedicated cache pool corresponding to the second task on the first CPU; after a second memory allocation request for the second task, the kernel can allocate free memory objects for the second task from the dedicated cache pool; after obtaining a second memory release request for the second task, the kernel can write the memory objects included in the second memory release request into the dedicated cache pool.

[0101] In some embodiments, the kernel may obtain a third memory release request for a third task on a first CPU, wherein the memory object included in the third memory release request corresponds to a memory page block on a second memory node; and release the memory object included in the third memory release request to the memory allocator.

[0102] In this embodiment, the third memory release request is a release request corresponding to a remote memory node, and the released memory object is located on a remote second memory node. In this case, when the release of the object by the remote NUMA node is detected, the kernel bypasses the local cache pool on the first CPU and directly returns the memory object to its slab, thus maintaining the locality of memory access.

[0103] In some embodiments, the kernel can configure the maximum capacity of the cache pool (e.g., the pool_capacity parameter) through a cache creation interface (e.g., the kmem_cache_create interface); when the maximum capacity is 0, the CPU's list of free objects is used to process free memory objects.

[0104] In the technical solution provided in this application embodiment, the kernel can extend the cache creation (kmem_cache_create) parameter to support the pool_capacity parameter. Thus, when the maximum capacity is greater than 0, the technical solution provided in this application embodiment is activated, and memory object processing (such as allocating and releasing memory objects) can be completed in the manner described above when the technical solution is activated. When the maximum capacity is 0, the technical solution provided in this application embodiment is disabled. When the technical solution provided in this application embodiment is not activated, the logic for memory object processing is equivalent to the original memory object allocation and release scheme, that is, using the CPU's free object list to process free memory objects. For example, when the kernel requests memory allocation, it quickly allocates memory objects from the current CPU's Freelist; if there are no free memory objects in the Freelist, it enters the slow path, using the memory allocator to migrate memory page blocks (slabs) from memory nodes to the current CPU. This achieves upward compatibility of the interface.

[0105] This application provides an efficient memory object pre-allocation mechanism. The second task is a task that does not support resource sharing with tasks on the same CPU or other CPUs. For tasks that do not support resource sharing, the kernel can borrow and fill a dedicated cache pool for that task before entering a critical path or restricted context, ensuring that the required allocation is completed without blocking or failures in scenarios with a known worst-case allocation limit. After the task is completed, memory objects can be quickly returned to the dedicated cache pool for that task, thereby significantly reducing the inefficient process of batch allocation based on worst-case scenarios and centralized release of unused memory objects, which is suitable for operations that require immediate allocation.

[0106] The following is combined with Figure 4 The schematic diagram of the memory object management mechanism illustrates the memory object allocation method provided in the embodiments of this application. A multi-core system includes multiple memory nodes, and each memory node includes one or more CPUs1. Figure 4Taking a memory node as an example, and illustrating a CPU1 on that memory node, CPU1 is configured with cache pool 1 as the primary cache pool, cache pool 2 as the backup cache pool, and cache pool 3 as the delayed release cache pool. The memory node is configured with a node cache unit, which includes a full pool list and an empty pool list. In the initial state, CPU1 obtains free memory objects from its corresponding Freelist and stores them in cache pool 1.

[0107] The kernel can also call the pre-allocation interface to configure a dedicated cache pool for task 0 based on the Freelist. The cache pools in the node cache unit (such as the cache pools in the full pool list and the empty pool list) are general-purpose cache pools. These general-purpose cache pools change as tasks on each CPU request to allocate or release memory objects.

[0108] After receiving a task allocation request, CPU1 retrieves a memory object from cache pool 1 and allocates it to the task. When all memory objects in cache pool 1 are allocated (i.e., cache pool 1 becomes empty), CPU1 switches cache pool 2 to the primary cache pool and cache pool 1 to the standby cache pool. Subsequently, upon receiving a task allocation request, CPU1 retrieves a memory object from cache pool 2 and allocates it to the task. When CPU1 detects that the standby cache pool (i.e., cache pool 1) has become empty, it pulls a cache pool (e.g., cache pool 4) from the full pool list included in the node cache unit (i.e., retrieves the full pool), replaces cache pool 1 with cache pool 4 as the CPU's standby cache pool, and adds cache pool 1 to the empty pool list included in the node cache unit.

[0109] After receiving a task's release request, CPU1 places the memory objects included in the release request into cache pool 1. When the number of memory objects in cache pool 1 reaches a first preset number, i.e., cache pool 1 becomes a full cache pool (i.e., primary full), CPU1 switches cache pool 2 to the primary cache pool and cache pool 1 to the standby cache pool. Subsequently, after receiving a task's release request, CPU1 places the memory objects included in the release request into cache pool 2. When CPU1 detects that the standby cache pool (i.e., cache pool 1) has become a full cache pool, it pulls a cache pool (such as cache pool 5) from the list of empty pools included in the node cache unit (i.e., retrieves an empty pool), replaces cache pool 1 with cache pool 5 as the standby cache pool for CPU1, and adds cache pool 1 to the list of full pools included in the node cache unit.

[0110] After CPU1 receives a delayed release request from a task (such as kfree_rcu()), it places the memory objects included in the delayed release request into cache pool 3. When the number of memory objects in cache pool 3 reaches a first preset number, that is, when cache pool 3 becomes a full cache pool, CPU1 submits a message to the RCU subsystem indicating that the delayed release cache pool is full. After the grace period for the delayed release cache pool ends, CPU2 on the memory node ( Figure 4 (Not shown in the image) Pull a cache pool (such as cache pool 6) from the list of empty pools included in the node cache unit, replace cache pool 3 with cache pool 6 as the delayed release cache pool corresponding to CPU1, and put cache pool 3 into the list of full pools included in the node cache unit.

[0111] After receiving the allocation request from Task 0, CPU1 retrieves the memory object from the dedicated cache pool and allocates it to Task 0; after receiving the release request from Task 0, CPU1 puts the memory object included in the release request into the dedicated cache pool.

[0112] When the number of memory objects in a node cache unit exceeds a second preset number, i.e., when the node cache unit is full, the kernel can release the free memory objects in the node cache unit to the underlying memory allocator (such as the SLUB allocator), and then release the free memory objects to the underlying memory page blocks. When the memory objects in a node cache unit are empty, the kernel can pull the underlying memory page blocks from the underlying memory allocator (such as the SLUB allocator) and add the corresponding free memory objects to the node cache unit or the cache pool requesting the allocation of free memory objects (including the primary cache pool and the standby cache pool).

[0113] In the technical solution provided in this application embodiment, the kernel can extend the cache creation (kmem_cache_create) parameter to support the pool_capacity parameter. Thus, when the technical solution provided in this application embodiment is started, memory object allocation and release can be completed in the above manner. When the technical solution provided in this application embodiment is not started, the logic is equivalent to the original memory object allocation and release scheme. When the kernel requests memory allocation, it quickly allocates memory objects from the current CPU's Freelist; if there are no free memory objects in the Freelist, it enters the slow path, using the memory allocator to migrate memory page blocks (slabs) from memory nodes to the current CPU. This achieves upward compatibility of the interface.

[0114] This application provides a hierarchical memory management unit consisting of a per-CPU cache pool and a node cache cell. In a multi-core system, the cache pool can be a logical partition, and the node cache cell can be a physical cache pool. This isolates memory resources at the granularity of memory nodes or thread groups, implementing a locality-first caching strategy and meeting the scalability requirements in high-concurrency scenarios.

[0115] The memory object allocation method under the hierarchical memory management unit provided in this application reduces global resource sharing. Through dynamic load awareness, it converges memory object allocation / reclamation to the local node cache unit, thereby reducing cross-core synchronization overhead. Simultaneously, it optimizes the efficiency of memory object fragment aggregation under high pressure, significantly improving the throughput and determinism of memory allocation in container-intensive deployments or high-frequency memory operation scenarios. Therefore, the hierarchical memory management mechanism optimizes the high-frequency memory operation performance of the Linux kernel.

[0116] In this embodiment, two private local cache pools are maintained on each CPU: a primary cache pool and a backup cache pool. Allocation and release are preferentially performed through the local cache pool to avoid cross-CPU lock contention, thereby avoiding latency jitter caused by cross-CPU lock contention. When the local cache pool is exhausted or full, it interacts with the shared storage at the memory node level (i.e., the node cache unit). The node cache unit stores a global queue of full / empty cache pools, and batch replacement reduces the overhead of directly accessing the global slab. When the node cache unit has no available cache pool, it then follows the traditional slow path processing, i.e., accessing the underlying slab. This reduces access to the memory node's linked list and locks.

[0117] Furthermore, the hierarchical memory management mechanism provided in this application embodiment can be compatible with memory node locality strategies. When remotely releasing memory objects, it bypasses the cache pool and directly returns to the underlying slab (i.e., slow path processing) to avoid remote objects from staying in the local cache for a long time, affecting access locality. This balances efficiency and memory locality, and improves the balance between performance and memory locality.

[0118] In summary, the technical solutions provided in this application can solve the following problems and achieve corresponding beneficial effects:

[0119] (1) Improve memory allocation / release performance and determinism, and reduce latency jitter.

[0120] In this embodiment, a localized caching strategy maintains a primary cache pool and a backup cache pool on each CPU, enabling memory allocation and deallocation operations to be completed locally on the CPU as much as possible. This avoids cross-CPU data interaction and eliminates the need to access shared locks or execute atomic instructions. This approach effectively reduces lock contention and cache migration, improving the execution efficiency of memory allocation / deallocation. Performance is significantly enhanced, especially in critical paths involving frequent allocation and deallocation of fixed-size memory objects, making high-frequency memory allocation / deallocation operations faster and more predictable, and reducing latency fluctuations. This solution addresses the performance bottlenecks and latency jitter issues caused by cross-node access and global lock contention in traditional SLUB allocators in high-concurrency, multi-core (especially NUMA architecture) systems.

[0121] (2) Optimize system resource management and efficiency, and optimize slow path access performance.

[0122] This application's embodiments change the static, passive memory management method in the prior art. In this application's embodiments, when the memory objects (i.e., cache) in the CPU's local cache pool are exhausted or overflow, the node cache unit can provide a full or empty cache pool to replace the current cache pool in the CPU, thereby maintaining high access efficiency even when entering slow paths. Furthermore, by limiting the number of cache pools that a node cache unit can hold and supporting batch reclamation, the system can controllably manage the cache size, avoiding excessive memory resource consumption. Therefore, this application's embodiments, through a dynamic and adaptive caching mechanism, reduce invalid memory usage and proactively prevent the accumulation of memory object fragmentation, thereby improving memory utilization and the long-term stability of the system.

[0123] (3) Enhance the adaptability, scalability and concurrency of the architecture.

[0124] In this embodiment, a hierarchical, topology-aware resource scheduling mechanism, combining localized processing of the cache pool with centralized access to node cache units, reduces interference between multi-cores, improves the overall concurrent processing capability and scalability of the system, and enhances scalability in large-scale concurrent scenarios. This allows the memory management unit provided in this embodiment to better adapt to modern hardware architectures (such as heterogeneous computing big.LITTLE) and cloud computing load characteristics (such as dense container deployment).

[0125] In summary, the technical solution provided in this application constructs a dynamically adaptive SLUB allocator architecture, which achieves higher performance, lower latency, more predictability and better resource utilization memory management in various kernel object allocation scenarios such as latency sensitivity and high throughput. While maintaining the flexibility and maintainability of memory management, it significantly reduces resource consumption and provides an optimized architecture with long-term evolution potential for kernel memory allocation systems.

[0126] Corresponding to the above-described memory object allocation method, this application also provides a memory object allocation apparatus, such as... Figure 5 As shown, a kernel applied in a multi-core system manages primary and secondary cache pools corresponding to multiple CPUs, as well as node cache units corresponding to multiple memory nodes. The primary and secondary cache pools manage free memory objects, and the node cache units manage full and empty cache pools. A full cache pool includes a first preset number of free memory objects, and an empty cache pool does not include free memory objects. The device includes:

[0127] The first acquisition module 501 is used to acquire the first memory allocation request for the first task on the first CPU; the first CPU corresponds to the first cache pool and the second cache pool, the first cache pool is the primary cache pool, and the second cache pool is the backup cache pool.

[0128] The first switching module 502 is used to switch the second cache pool to the primary cache pool and the first cache pool to the standby cache pool if the first cache pool is empty and the second cache pool is full, and to allocate a free memory object for the first task from the second cache pool.

[0129] The second acquisition module 503 is used to acquire the third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs. The third cache pool is a full cache pool.

[0130] The second switching module 504 is used to switch the third cache pool to the backup cache pool corresponding to the first CPU and store the first cache pool in the first node cache unit.

[0131] In the technical solution provided in this application, the kernel manages multiple primary and backup cache pools corresponding to multiple CPUs, as well as node cache units corresponding to multiple memory nodes. When allocating memory objects, the kernel first obtains free memory objects from the primary cache pool corresponding to the current CPU, and then obtains full cache pools from the node cache units corresponding to the current CPU to replace the empty cache pools (such as backup cache pools) corresponding to the current CPU. In this way, when a sudden load occurs, when all the free memory objects in the primary cache pool are allocated, that is, when the primary cache pool is empty, the kernel quickly completes the replacement between the primary and backup cache pools, omitting the operation of migrating memory page blocks from memory nodes using the memory allocator, thus reducing memory allocation latency.

[0132] In some embodiments, the first switching module 502 can also be used to, if the first cache pool is an empty cache pool and the second cache pool is an empty cache pool, obtain a free memory object from the free object list of the first CPU and fill the obtained free memory object into the first cache pool; if the first cache pool is not an empty cache pool, allocate a free memory object for the first task from the first cache pool.

[0133] In some embodiments, the second switching module 504 can also be used to switch the third cache pool to the backup cache pool corresponding to the first CPU if the third cache pool is obtained.

[0134] The second switching module 504 can also be used to obtain free memory objects from the free object list of the first CPU if the third cache pool is not obtained, and fill the obtained free memory objects into the first cache pool.

[0135] In some embodiments, the first switching module 502 can also be used to, if the free object list of the first CPU does not contain a free memory object, call the memory allocator to migrate memory page blocks from the partial memory page block list of the first memory node; generate a free memory object based on the migrated memory page block, and write the generated free memory object into the free object list of the first CPU; and retrieve a free memory object again from the free object list of the first CPU.

[0136] In some embodiments, the first acquisition module 501 can also be used to acquire a first memory release request for a first task on the first CPU; the first switching module 502 can also be used to switch the second cache pool to the primary cache pool and the first cache pool to the standby cache pool if the first cache pool is a full cache pool, and write the memory object included in the first memory release request into the second cache pool; the second acquisition module 503 can also be used to acquire a fourth cache pool from the first node cache unit, the fourth cache pool being an empty cache pool; the second switching module 504 can also be used to switch the fourth cache pool to the standby cache pool corresponding to the first CPU and store the first cache pool in the first node cache unit.

[0137] In some embodiments, the first switching module 502 can also be used to write the memory object included in the first memory release request into the first cache pool if the first cache pool is not a full cache pool.

[0138] In some embodiments, the second switching module 504 can also be used to release the free memory objects included in the first node cache unit to the memory allocator if the number of free memory objects included in the first node cache unit is greater than a second preset number, and the number of free memory objects included in the first node cache unit after release is less than or equal to the second preset number.

[0139] In some embodiments, the kernel also manages multiple CPU-corresponding delayed release cache pools, which manage memory objects that are delayed in release; the first acquisition module 501 can also be used to acquire a delayed release request for a first task on the first CPU; the first switching module 502 can also be used to write the memory object included in the delayed release request into the fifth cache pool corresponding to the first CPU, where the fifth cache pool is the delayed release cache pool corresponding to the first CPU; the second acquisition module 503 can also be used to, when the fifth cache pool is a full cache pool, call the second CPU to store the fifth cache pool into the first node cache unit, and acquire the sixth cache pool from the first node cache unit, where the sixth cache pool is an empty cache pool; the second switching module 504 can also be used to switch the sixth cache pool to the delayed release cache pool corresponding to the first CPU.

[0140] In some embodiments, the memory object allocation device may further include: a pre-allocation module, configured to obtain free memory objects from the free object list of the first CPU and fill the obtained free memory objects into a dedicated cache pool corresponding to the second task on the first CPU; an allocation module, configured to allocate free memory objects for the second task from the dedicated cache pool after a second memory allocation request for the second task; and a first release module, configured to write the memory objects included in the second memory release request into the dedicated cache pool after a second memory release request for the second task is obtained.

[0141] In some embodiments, the memory object allocation device may further include: a third acquisition module, configured to acquire a third memory release request for a third task on a first CPU, wherein the memory object included in the third memory release request corresponds to a memory page block on a second memory node; and a second release module, configured to release the memory object included in the third memory release request to the memory allocator.

[0142] In some embodiments, the memory object allocation device may further include: a configuration module for configuring the maximum capacity of the cache pool through a cache creation interface; and a processing module for processing free memory objects using the CPU's free object list when the maximum capacity is 0.

[0143] Corresponding to the above-described memory object allocation method, this application also provides an electronic device, such as... Figure 6 As shown, the system includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604. The processor 601, communication interface 602, and memory 603 communicate with each other via the communication bus 604. The memory 603 is used to store computer programs; the processor 601, when executing the program stored in the memory 603, implements any of the aforementioned memory object allocation methods.

[0144] The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0145] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0146] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0147] The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0148] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements any of the memory object allocation methods described above.

[0149] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the memory object allocation methods described above.

[0150] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0151] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0152] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, storage media, and program products are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0153] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method for allocating memory objects, characterized in that, A kernel applied to a multi-core system, wherein the kernel manages a primary cache pool and a backup cache pool corresponding to multiple CPUs, and a node cache unit corresponding to multiple memory nodes; the primary cache pool and the backup cache pool manage free memory objects; the node cache unit manages a full cache pool and an empty cache pool; the full cache pool includes a first preset number of free memory objects; the empty cache pool does not include free memory objects; the method includes: Obtain the first memory allocation request for the first task on the first CPU; the first CPU corresponds to a first cache pool and a second cache pool, the first cache pool is the primary cache pool, and the second cache pool is the backup cache pool; If the first cache pool is empty and the second cache pool is full, then the second cache pool is switched to the primary cache pool, the first cache pool is switched to the standby cache pool, and a free memory object is allocated for the first task from the second cache pool. Obtain the third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs, wherein the third cache pool is a full cache pool; If the third cache pool is obtained, the third cache pool is switched to the backup cache pool corresponding to the first CPU, and the first cache pool is stored in the first node cache unit; If the third cache pool is not obtained, a free memory object is obtained from the free object list of the first CPU, and the obtained free memory object is filled into the first cache pool. The free memory objects stored in the free object list of the first CPU are generated by migrating memory page blocks from the partial memory page block list of the first memory node according to the memory allocator.

2. The method according to claim 1, characterized in that, The method further includes: If the first cache pool is an empty cache pool and the second cache pool is an empty cache pool, then a free memory object is obtained from the free object list of the first CPU and the obtained free memory object is filled into the first cache pool. If the first cache pool is not an empty cache pool, then a free memory object is allocated for the first task from the first cache pool.

3. The method according to claim 1 or 2, characterized in that, The method further includes: If the free object list of the first CPU does not contain free memory objects, then the memory allocator is invoked to migrate memory pages from the partial memory page block list of the first memory node; Free memory objects are generated based on the migrated memory page blocks, and the generated free memory objects are written into the free object list of the first CPU; the step of obtaining free memory objects from the free object list of the first CPU is executed again.

4. The method according to claim 1, characterized in that, The method further includes: Obtain the first memory release request for the first task on the first CPU; If the first cache pool is full, then the second cache pool is switched to the primary cache pool, the first cache pool is switched to the standby cache pool, and the memory object included in the first memory release request is written to the second cache pool. Obtain the fourth cache pool from the first node cache unit, wherein the fourth cache pool is an empty cache pool; The fourth cache pool is switched to the backup cache pool corresponding to the first CPU, and the first cache pool is stored in the first node cache unit.

5. The method according to claim 4, characterized in that, The method further includes: If the first cache pool is not full, then the memory object included in the first memory release request is written into the first cache pool.

6. The method according to claim 4 or 5, characterized in that, The method further includes: If the number of free memory objects included in the first node cache unit is greater than the second preset number, then the free memory objects included in the first node cache unit are released to the memory allocator, and the number of free memory objects included in the first node cache unit after release is less than or equal to the second preset number.

7. The method according to claim 1, characterized in that, The kernel also manages multiple CPU-specific delayed-release cache pools, which manage delayed-release memory objects; the method further includes: Obtain the delayed release request for the first task on the first CPU; The memory object included in the delayed release request is written into the fifth cache pool corresponding to the first CPU, and the fifth cache pool is the delayed release cache pool corresponding to the first CPU; When the fifth cache pool is full, the second CPU is invoked to store the fifth cache pool in the first node cache unit, and the sixth cache pool is obtained from the first node cache unit. The sixth cache pool is an empty cache pool. Switch the sixth cache pool to the delayed release cache pool corresponding to the first CPU.

8. The method according to claim 1, characterized in that, The method further includes: Retrieve free memory objects from the list of free objects of the first CPU and fill the retrieved free memory objects into the dedicated cache pool corresponding to the second task on the first CPU; After the second memory allocation request for the second task, a free memory object is allocated for the second task from the dedicated cache pool; After obtaining the second memory release request for the second task, the memory object included in the second memory release request is written to the dedicated cache pool.

9. The method according to claim 1, characterized in that, The method further includes: Obtain a third memory release request for a third task on the first CPU, wherein the memory object included in the third memory release request corresponds to a memory page block on the second memory node; Release the memory object included in the third memory release request to the memory allocator.

10. The method according to claim 1, characterized in that, The method further includes: Configure the maximum capacity of the cache pool through the cache creation interface; When the maximum capacity is 0, free memory objects are handled using the CPU's list of free objects.

11. A memory object allocation device, characterized in that, A kernel applied in a multi-core system, the kernel managing multiple primary and backup cache pools corresponding to multiple CPUs, and node cache units corresponding to multiple memory nodes, the primary and backup cache pools managing free memory objects, the node cache units managing full and empty cache pools, the full cache pool including a first preset number of free memory objects, the empty cache pool not including free memory objects; the device includes: The first acquisition module is used to acquire the first memory allocation request for the first task on the first CPU; the first CPU corresponds to a first cache pool and a second cache pool, the first cache pool is the primary cache pool, and the second cache pool is the backup cache pool. The first switching module is used to switch the second cache pool to the primary cache pool and the first cache pool to the standby cache pool if the first cache pool is empty and the second cache pool is full, and to allocate a free memory object for the first task from the second cache pool. The second acquisition module is used to acquire a third cache pool from the first node cache unit corresponding to the first memory node to which the first CPU belongs, wherein the third cache pool is a full cache pool; The second switching module is used to switch the third cache pool to the backup cache pool corresponding to the first CPU if the third cache pool is obtained, and to store the first cache pool in the first node cache unit. The second switching module is further configured to, if the third cache pool is not obtained, obtain a free memory object from the free object list of the first CPU and fill the obtained free memory object into the first cache pool. The free memory objects stored in the free object list of the first CPU are generated by migrating memory page blocks from the partial memory page block list of the first memory node according to the memory allocator.

12. An electronic device, characterized in that, The system includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; the memory is used to store computer programs; and the processor, when executing the program stored in the memory, implements the method described in any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 1-10.

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