Efficient DDR4 memory debugging system and debugging method for SoC chip

Abstract

This invention relates to the fields of integrated circuits and chip debugging, and provides a high-efficiency DDR4 memory debugging system and method for SoC chips. The system includes: a parameter debugging module, used to adjust the parameters to be adjusted in the register configuration file according to DIMM information, register configuration file and working mode information, and after completing the register parameter configuration, start the DDR4 IP to perform training tasks according to the training parameter settings and training control settings; and a testing module, used to check whether the adjusted register parameters are correct and monitor whether the training results of the DDR4 IP to perform training tasks are correct, and to perform read and write tests on DRAM. When it is determined that the check and training are passed and the read and write tests are passed, the operating system is selected to start. This invention avoids the repetition and confusion of debugging work in the debugging process, can effectively reduce the debugging error rate, speed up the debugging process, and improve the debugging efficiency.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and chip debugging, and in particular to a high-efficiency DDR4 memory debugging system and method for SoC chips. Background Technology

[0002] DDR stands for DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). In high-performance computing systems, the DDR controller is an indispensable and crucial component of high-performance SoC chips. The CPU (Central Processing Unit, the "brain" of the SoC, executing program instructions and computing tasks) accesses main memory (DDR memory, or DDR SDRAM, the hardware that actually stores data, such as the chips on memory modules, which transmit data at double the data rate) through the DDR controller (the "scheduler" within the SoC, responsible for sending read and write commands, managing addresses, and timings to the DDR memory). The DDR controller translates the CPU's access requests into commands and address information that the DRAM (the internal circuitry of the DDR memory chips, responsible for receiving commands and reading / writing data) can recognize, thus completing the data transfer between the CPU and the DDR memory.

[0003] With the development of DDR technology, the maximum transmission rate of DDR4 has reached 3200Mbps, corresponding to a memory clock frequency of 1600MHz. This high clock frequency brings stricter timing requirements and more complex signal integrity issues to DDR4 memory debugging, making it a challenging aspect of the entire chip debugging process. Furthermore, the DDR4 controller and its corresponding PHY (Physical Interface: the "translator and messenger" between the controller and the memory, responsible for electrical signal conversion, such as digital-to-analog conversion) circuitry contain over three thousand registers, and correct register parameter configuration is crucial for the functionality of DDR4 memory. However, the complex register parameters increase the complexity of DDR debugging. Moreover, differences in the routing between the DDR controller and the DDR memory on the PCB (Printed Circuit Board) introduce signal delays, further increasing the difficulty of DDR debugging.

[0004] Current DDR4 memory debugging typically uses hardware interface methods, which suffer from problems such as chaotic debugging processes, unclear parameter settings, and low debugging efficiency. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a high-efficiency DDR4 memory debugging system and debugging method for SoC chips.

[0006] This invention provides a high-efficiency DDR4 memory debugging system for SoC chips. The system includes a parameter debugging module and a testing module, wherein:

[0007] The parameter debugging module is used to acquire DIMM information, register configuration file and working mode information, adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information, and after completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings.

[0008] The testing module is used to check whether the adjusted register parameters are correct and to monitor whether the training results of the DDR4 IP are correct. It also performs read and write tests on the DRAM. Once the check and training are confirmed to be successful and the read and write tests are successful, the operating system is then started.

[0009] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided. The parameter debugging module includes an SPD_info reading module, a frequency selection module, a register initialization module, a register reconfiguration module, and a training module, comprising:

[0010] The SPD_info reading module is used to read DIMM information;

[0011] The frequency selection module is used to obtain the corresponding register configuration file based on the input DIMM operating frequency;

[0012] The register initialization module is used to initialize and configure the register parameters in DDR4 memory according to the obtained register configuration file.

[0013] The register reconfiguration module is used to adjust the parameters to be adjusted in the key register parameters of the initialized DDR4 memory based on different working mode information and read DIMM information, and to configure the selected performance parameters and function control parameters.

[0014] The training module is used to start the DDR4 IP to execute the training task after the register parameters are configured, based on the settings of the training parameters and training control parameters.

[0015] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided. The performance parameters and functional control parameters filtered by the register reconfiguration module include signal quality, timing, DM, parity function, bit width, address mapping, and performance. Accordingly, the register reconfiguration module includes a signal quality adjustment module, a timing parameter optimization module, a mode register configuration module, a DM function control module, a parity function management module, a data bit width adjustment module, an address mapping configuration module, and a performance adjustment module, wherein:

[0016] The signal quality adjustment module is used to adjust the ODT value of key signals at the IP end;

[0017] The timing parameter optimization module is used to adjust the DRAM basic timing parameters, DFI interface timing parameters, DFI update timing parameters, self refresh parameters, IP internal access latency parameters, and mode register timing parameters.

[0018] The mode register configuration module is used to adjust the ODT value in MR under different RANKs;

[0019] The DM function control module is used to adjust whether the data mask DM function is enabled or disabled;

[0020] The verification function management module is used to adjust whether ECC and CRC functions are enabled or disabled;

[0021] The data bit width adjustment module is used to adjust the DIMM bit width information;

[0022] The address mapping configuration module is used to adjust the address mapping parameters within the IP address.

[0023] The performance tuning module is used to adjust the DDR bandwidth utilization.

[0024] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided, wherein the training module includes a training parameter setting module, a training control module, and a training startup module, wherein:

[0025] The training parameter setting module is used to set training parameters;

[0026] The training control module is used to set the training control parameters;

[0027] The training startup module is used to start the DDR4 IP to execute training tasks based on the settings of training parameters and training control.

[0028] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided, wherein the testing module includes a training state monitoring module, a read / write testing module, and a system startup module, wherein:

[0029] The training status monitoring module is used to check whether the adjusted register parameters are correct and to monitor whether the training results of the DDR4 IP are correct after starting the training task.

[0030] The read / write test module is used to perform read / write tests on DRAM according to various preset test patterns and obtain test results.

[0031] The system startup module is used to confirm that the operating system starts after training and testing have passed.

[0032] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided, wherein the training state monitoring module is specifically used for:

[0033] Verify that the adjusted register parameters are set correctly;

[0034] Verify that the register parameters required to start the DDR4 IP to perform the training task are set correctly;

[0035] Verify whether starting the DDR4 IP to execute the training task is successful;

[0036] Determine if the DFI interrupt status bits are normal.

[0037] According to the present invention, a high-efficiency DDR4 memory debugging system for SoC chips is provided, wherein the test module is further configured to: after the training state monitoring module and the read / write test module are executed, execute any one of the training state monitoring module, the read / write test module and the system startup module again.

[0038] This invention also provides an efficient DDR4 memory debugging method for SoC chips, including:

[0039] Obtain DIMM information, register configuration file and working mode information; adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information; and after completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings.

[0040] Check whether the adjusted register parameters are correct and monitor whether the training results of the training task performed on the DDR4 IP are correct. Perform read and write tests on the DRAM. If the check and training are passed and the read and write tests are passed, then select to start the operating system.

[0041] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements any of the above-described efficient DDR4 memory debugging methods for SoC chips.

[0042] This invention provides a high-efficiency DDR4 memory debugging system and method for SoC chips. By streamlining and modularizing the debugging process of the DDR4 memory debugging system, the originally tedious and time-consuming debugging task is divided into several independent and manageable modules, each with its specific debugging objectives and operation procedures. This design avoids repetition and confusion in the debugging process, effectively reducing the debugging error rate, accelerating the debugging progress, and improving debugging efficiency. The streamlined and modular design also makes system maintenance and upgrades easier, allowing for independent modification of specific modules without affecting other functional modules. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of the high-efficiency DDR4 memory debugging system for SoC chips provided by the present invention.

[0045] Figure 2 This is a flowchart illustrating the efficient DDR4 memory debugging method for SoC chips provided by the present invention.

[0046] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0048] The following is combined Figures 1-3 This invention describes a high-efficiency DDR4 memory debugging system and debugging method for SoC chips.

[0049] Figure 1 This diagram illustrates the structure of a high-efficiency DDR4 memory debugging system for SoC chips provided by the present invention. (See attached diagram.) Figure 1 The system includes a parameter debugging module and a testing module, wherein:

[0050] The parameter debugging module is used to obtain DIMM information, register configuration file and working mode information, adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information, and after completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings.

[0051] The testing module is used to check whether the adjusted register parameters are correct and to monitor whether the training results of the DDR4 IP are correct. It also performs read and write tests on the DRAM. Once the check and training are confirmed to be successful and the read and write tests are successful, the operating system is then started.

[0052] It's important to clarify that DDR stands for DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). In high-performance computing systems, the DDR controller is an indispensable and crucial component of high-performance SoC chips. The CPU (Central Processing Unit, the "brain" of the SoC, executing program instructions and computational tasks) accesses main memory (DDR memory, or DDR SDRAM, the hardware that actually stores data, such as the chips on memory modules, which transmit data at double the data rate) through the DDR controller (the "scheduler" within the SoC, responsible for sending read / write commands, managing addresses, and timing). The DDR controller translates the CPU's access requests into commands and address information that the DRAM (the internal circuitry of the DDR memory chips, responsible for receiving commands and reading / writing data) can recognize, thus completing the data transfer between the CPU and the DDR memory.

[0053] With the development of DDR technology, the maximum transmission rate of DDR4 has reached 3200Mbps, corresponding to a memory clock frequency of 1600MHz. This high clock frequency brings stricter timing requirements and more complex signal integrity issues to DDR4 memory debugging, making it a challenging aspect of the entire chip debugging process. Furthermore, the DDR4 controller and its corresponding PHY (Physical Interface: the "translator and messenger" between the controller and the memory, responsible for electrical signal conversion, such as digital-to-analog conversion) circuitry contain over three thousand registers, and correct register parameter configuration is crucial for the functionality of DDR4 memory. However, the complex register parameters increase the complexity of DDR debugging. Moreover, differences in the routing between the DDR controller and the DDR memory on the PCB (Printed Circuit Board) introduce signal delays, further increasing the difficulty of DDR debugging.

[0054] Current DDR4 memory debugging typically employs hardware interface methods, which suffer from problems such as chaotic debugging processes, unclear parameter settings, and low debugging efficiency. Therefore, a high-efficiency DDR4 memory debugging system for SoC chips is needed, which optimizes DDR memory debugging methods through a software interface to accelerate DDR memory debugging. Based on a software interface, this system ensures debugging correctness while achieving efficient, streamlined, and modular debugging processes. This high-efficiency DDR4 memory debugging system not only improves debugging efficiency but also saves debugging manpower and time, thereby shortening the chip debugging cycle.

[0055] When designing an efficient DDR4 memory debugging system, the key is to study flexible parameter setting methods and effective debugging procedures. This allows the DDR memory debugging system to identify and resolve problems more quickly during DDR debugging, improving overall development efficiency and quality.

[0056] This system provides DDR debugging engineers with comprehensive debugging capabilities and flexible configuration options. It streamlines and modularizes the DDR4 memory debugging process and supports features such as training status monitoring. Debugging engineers can quickly locate and resolve debugging issues in DDR4 memory, thereby reducing debugging time, accelerating innovation, and driving technological progress.

[0057] In this invention, the DDR4 memory debugging system streamlines and modularizes the debugging process, simplifying the debugging workflow. Through this streamlined and modular design, debugging personnel can modify debugging parameters more quickly, reducing debugging time. To this end, the parameter debugging module of this invention acquires DIMM information (Dual In-line Memory Module: a "memory module" inserted into the motherboard, composed of multiple DDR chips and auxiliary components), register configuration files, and operating mode information. Based on the DIMM information, register configuration files, and operating mode information, it adjusts the parameters to be adjusted in the register configuration file. After completing the register parameter configuration, it starts the DDR4 IP to execute the training task according to the training parameter settings and training control settings.

[0058] In this invention, the DDR4 memory debugging system also has a testing function, which can monitor the training status and automatically execute a series of test cases, improving the automation level of debugging, helping debugging personnel to quickly locate and solve problems, and reducing their workload. To this end, the testing module of this invention checks whether the adjusted register parameters are correct and monitors whether the training results of the DDR4 IP executing the training task are correct, and performs read and write tests on the DRAM. When it is determined that the checks and training have passed and the read and write tests are consistent, the operating system is then started.

[0059] In summary, the high-efficiency DDR4 memory debugging system of this invention provides debugging personnel with a more convenient, faster, and more accurate debugging tool, greatly improving the efficiency and quality of DDR4 memory debugging.

[0060] Furthermore, the parameter debugging module includes an information reading module, a frequency selection module, a register initialization module, a register reconfiguration module, and a training module, comprising:

[0061] The information reading module is used to read DIMM information. This module, the SPD_info module, is used to read DIMM (Dual Inline Memory Modules) information from the SPD chip, including but not limited to: DDR4 memory manufacturer information, module model, speed class, capacity, data bus width, CAS latency, RAS-to-CAS latency, RAS precharge latency, module voltage, and module temperature sensor data. These parameters are used to adjust some configurations of the DDR4 memory, helping the IP to operate at its best.

[0062] The frequency selection module retrieves the corresponding register configuration file based on the input DIMM operating frequency. Multiple preset register configuration files in various formats can be configured within the system, covering different settings within the range of 1600MHz to 3200MHz. Once the DIMM operating frequency is determined, the system automatically loads the corresponding configuration file. This flexible design allows for timely adjustment of the DIMM operating frequency during debugging without needing to re-import the register configuration file, greatly simplifying the operation process and improving debugging efficiency.

[0063] The register initialization module is used to initialize and configure the register parameters in the DDR4 memory according to the obtained register configuration file. During the initialization and configuration of DDR4 memory, since DDR4 memory involves more than 3,000 registers, the configuration is performed in the order of controller module, physical layer independent module, and physical layer module. The configuration file is derived from the corresponding register configuration file obtained based on the input DIMM operating frequency, ensuring configuration accuracy and efficiency.

[0064] The register reconfiguration module adjusts the parameters to be adjusted in the registers of the initialized DDR4 memory based on the input operating mode information and the read DIMM information, and configures the selected performance parameters and function control parameters. The register reconfiguration module is specifically designed to adjust critical register parameters to adapt to different operating modes. Under the constraints of the input operating mode information, it adjusts the register parameters to be adjusted using parameters such as DIMM capacity, timing parameters, bit width, and DIMM row and column addresses obtained from the SPD_info module. In addition, this register reconfiguration module also controls some important functions, such as enabling and disabling DM (Data Mask), ECC (Error Checking and Correcting), and CRC (Cyclic Redundancy Check) functions, ensuring stable operation of the debugging system under different configurations.

[0065] Furthermore, the performance and functional control parameters selected by the register reconfiguration module include signal quality, timing, DM (Digital Modulation), parity function, bit width, address mapping, and performance. Correspondingly, the register reconfiguration module is subdivided into several key sub-modules: signal quality adjustment module, timing parameter optimization module, mode register configuration module, DM function control module, parity function management module, data bit width adjustment module, address mapping configuration module, and performance adjustment module, as detailed below:

[0066] The signal quality adjustment module is used to adjust the resistance value of the ODT (On-Die Termination, a signal absorber inside the memory chip that reduces signal reflection interference) at the IP end. In this module, the signal driving capability is adjusted by regulating the ODT values ​​of key signals at the IP end, directly affecting signal quality. Correctly set ODT values ​​help obtain a clearer signal eye diagram, thereby improving system stability and performance. This module focuses on centrally processing the ODT adjustments of key signals such as DQ (data signal), DQS (data select signal), and CLK (clock signal) to optimize the signal driving capability of the IP end, thereby effectively improving debugging efficiency and success rate.

[0067] The timing parameter optimization module is used to adjust the DRAM basic timing parameters, DFI interface timing parameters, DFI update timing parameters, self-refresh parameters, IP internal access latency parameters, and mode register timing parameters. The first part of the parameters that the timing parameter adjustment module needs to debug is the DRAM (Dynamic Random Access Memory) basic timing parameters. This part is determined by the corresponding register configuration file obtained based on the input DIMM operating frequency, ensuring that the DRAM works normally.

[0068] Furthermore, the second part of the parameters consists of the DFI (DDR PHY Interface, DDR and PHY physical layer interface protocol) interface timing parameters, ensuring normal interaction between the controller and the physical layer.

[0069] Furthermore, the third part is the DFI update timing.

[0070] Furthermore, the fourth part of the parameters is related to self refresh. These parameters need to be debugged when testing the self refresh function, and the default values ​​can be kept temporarily in the early stage.

[0071] Furthermore, the fifth part of the parameters includes internal IP access latency parameters such as read-to-read, read-to-write, write-to-read, and write-to-write, which require debugging.

[0072] Furthermore, the sixth part, timing parameters, refers to the settings of timing parameters in the mode register.

[0073] The timing parameter adjustment module decomposes different timing parameters and processes them according to functional modules, enabling more flexible debugging and optimization of timing parameters. This setup significantly improves the flexibility and performance of the debugging system, simplifies the debugging process, and allows for rapid adjustments during debugging.

[0074] The Mode Register configuration module is used to adjust the ODT value in the Mode Register (MR) under different RANKs. The Mode Register adjustment module primarily debugs the ODT on the DRAM side. Under different RANKs (DDR physical bank blocks), the ODT in the MR needs to be set with different values, requiring fine-tuning. The parameters involved include MR1 RTT_NOM, MR2 RTT_WR, and MR5 RTT_PARK.

[0075] The DM function control module is used to adjust whether the Data Mask (DM) function is enabled or disabled during write operations. The DM function can be enabled or disabled independently during debugging. To improve debugging efficiency, the DM function can be temporarily disabled during the initial debugging phase.

[0076] The verification function management module is used to adjust whether ECC and CRC functions are enabled or disabled. Verification functions include ECC and CRC, which detect errors occurring during data transmission. These functions can be enabled or disabled during debugging.

[0077] The data bit width adjustment module is used to adjust the DIMM bit width information.

[0078] The address mapping configuration module is used to adjust the address mapping parameters within the IP. Based on the capacity, address, and other information obtained from the DIMM by the SPD_info module, it sets address-related parameters such as column, row, bank, and rank within the IP.

[0079] The performance tuning module is used to adjust DDR bandwidth utilization. It debugs certain special performance modes within the IP to improve DDR bandwidth utilization. This module should be operated without affecting normal functionality and is generally enabled after basic function debugging is completed. During the initial debugging phase, this module can be temporarily disabled to ensure stable system operation.

[0080] The training module is used to start the DDR4 IP to execute the training task after the register parameters are configured, based on the settings of the training parameters and training control parameters.

[0081] The training module is divided into three key parts: the training parameter setting module, which is responsible for setting the training parameters required for debugging; the training control module, which is used to set the training control parameters, supports selectively enabling one or more training tasks, and manages and monitors the training process; and the training startup module, which starts the DDR4 IP to execute training tasks according to the settings of the training parameters and training control, and is designed to be responsible for starting and executing the entire training process.

[0082] In this invention, the training parameter setting module plays a crucial role in the training process. This module is responsible for adjusting various training parameters in a specific order, configuring parameters for ZQ calibration, write balancing, read gate training, read data eye training, write DQ training, read DBI (Data Bus Inverse) training, and VREF DQ (Reference Voltage Data). These parameter settings include adjustment step size, delay compensation, and sampling period, and all training-related parameters are centrally managed within this module.

[0083] The training control module is responsible for enabling various training programs, allowing specific training programs to be selectively turned on or off during a single training session. This flexibility allows for initial debugging phases where a single training program can be tested first, and other training programs can be added gradually after confirmation, resulting in more refined and efficient debugging.

[0084] Once the training startup module is set up, training can begin. This module acts as a switch for training, responsible for initiating the entire training process.

[0085] Furthermore, the testing module includes a training status monitoring module, a read / write testing module, and a system startup module, among which:

[0086] The training status monitoring module is used to check whether the adjusted register parameters are correct and to monitor the training results of the DDR4 IP after starting the training task. Specifically, the training status monitoring module is used for:

[0087] Verify that the adjusted register parameters are set correctly;

[0088] Verify that the register parameters required to start the DDR4 IP to perform the training task are set correctly;

[0089] Verify whether starting the DDR4 IP to execute the training task is successful;

[0090] Determine if the DFI interrupt status bits are normal.

[0091] The above monitoring is used to quickly locate and resolve debugging issues in DDR4 memory.

[0092] The read / write test module performs read / write tests on the DRAM according to various preset test patterns and obtains the test results. The module has multiple built-in test patterns, providing the most direct way to check the training results. This module complements the training status monitoring module, working together to ensure the reliability and stability of the DDR4 memory debugging system.

[0093] The system boot module is used to confirm the operating system startup after successful training and testing. Once training and testing are complete, engineers can choose to boot the system via the system boot module, which is the ultimate goal of debugging. To ensure a smooth system boot, in addition to successful DDR4 memory debugging, the stability of the SOC and other peripheral modules must also be ensured. The system boot module allows engineers to easily boot the system according to their needs.

[0094] In this invention, the training status monitoring module, the testing module, and the system startup module are optional and can be executed in parallel. After the training status monitoring module and the read / write test module are executed, any one of these modules can be executed again. Chip debugging engineers can freely choose to execute any of these modules as needed. For example, after completing the status monitoring module and the testing module, they can choose to execute any one of these modules again, or the system startup module. The debugging system can also be combined with devices such as oscilloscopes and logic analyzers for debugging.

[0095] This invention provides a high-efficiency DDR4 memory debugging system for SoC chips. By streamlining and modularizing the debugging process, the originally tedious and time-consuming debugging task is divided into several independent, manageable modules, each with its specific debugging objectives and operational procedures. This design avoids repetitive and chaotic debugging work, effectively reducing the debugging error rate, accelerating the debugging process, and improving debugging efficiency. The streamlined and modular design also makes system maintenance and upgrades easier, allowing for independent modification of specific modules without affecting other functional modules.

[0096] The following describes the efficient DDR4 memory debugging method for SoC chips provided by the present invention. The efficient DDR4 memory debugging method for SoC chips described below can be referred to in correspondence with the efficient DDR4 memory debugging system for SoC chips described above.

[0097] Figure 2 This diagram illustrates a flowchart of an efficient DDR4 memory debugging method for SoC chips provided by the present invention. (See attached diagram.) Figure 2 The device includes the following steps:

[0098] Step 21: Obtain DIMM information, register configuration file and working mode information. Adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information. After completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings.

[0099] Step 22: Check whether the adjusted register parameters are correct and monitor whether the training results of the training task performed on the DDR4 IP are correct. Perform read and write tests on the DRAM. If the check and training are passed and the read and write tests are passed, then select to start the operating system.

[0100] Since the method in this embodiment of the invention is based on the same principle as the system in the above embodiment, more detailed explanations will not be repeated here.

[0101] This invention provides a high-efficiency DDR4 memory debugging method for SoC chips. By streamlining and modularizing the debugging process of the DDR4 memory debugging system, the originally tedious and time-consuming debugging task is divided into several independent and manageable modules, each with its specific debugging objectives and operation procedures. This design avoids repetition and confusion in the debugging process, effectively reducing the debugging error rate, accelerating the debugging progress, and improving debugging efficiency. The streamlined and modular design also makes system maintenance and upgrades easier, allowing for independent modification of specific modules without affecting other functional modules.

[0102] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 31, a communication interface 32, a memory 33, and a communication bus 34. The processor 31, communication interface 32, and memory 33 communicate with each other via the communication bus 34. The processor 31 can call logical instructions in the memory 33 to execute a high-efficiency DDR4 memory debugging method for SoC chips. This method includes: acquiring DIMM information, register configuration files, and operating mode information; adjusting the parameters to be adjusted in the register configuration file based on the DIMM information, register configuration files, and operating mode information; after completing the register parameter configuration, starting the DDR4 IP to execute a training task based on the training parameter settings and training control settings; checking whether the adjusted register parameters are correct and monitoring whether the training results of the DDR4 IP training task are correct; performing read / write tests on the DRAM; and selecting to start the operating system when the check and training are passed and the read / write test is passed.

[0103] Furthermore, the logical instructions in the aforementioned memory 33 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0104] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the efficient DDR4 memory debugging method for SoC chips provided by the above methods. The method includes: acquiring DIMM information, register configuration file and working mode information; adjusting the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information; and after completing the register parameter configuration, starting the DDR4 IP to perform a training task according to the setting of training parameters and the setting of training control; checking whether the adjusted register parameters are correct and monitoring whether the training result of the DDR4 IP training task is correct, and performing read and write tests on DRAM; and when it is determined that the check and training are passed and the read and write tests are passed, then selecting to start the operating system.

[0105] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the efficient DDR4 memory debugging method for SoC chips provided by the above methods. The method includes: acquiring DIMM information, register configuration file and working mode information; adjusting the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information; and after completing the register parameter configuration, starting the DDR4 IP to perform a training task according to the training parameter settings and training control settings; checking whether the adjusted register parameters are correct and monitoring whether the training result of the DDR4 IP training task is correct, and performing read and write tests on the DRAM; and when it is determined that the check and training have passed and the read and write tests have passed, then selecting to start the operating system.

[0106] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An efficient DDR4 memory debugging system for SoC chips, characterized in that, It includes a parameter debugging module and a testing module, among which: The parameter debugging module is used to acquire DIMM information, register configuration file and working mode information, adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information, and after completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings. The testing module is used to check whether the adjusted register parameters are correct and to monitor whether the training results of the DDR4 IP are correct. It also performs read and write tests on the DRAM. When the check and training are confirmed to be successful and the read and write tests are successful, the operating system is selected to start. The parameter debugging module includes an SPD_info reading module, a frequency selection module, a register initialization module, a register reconfiguration module, and a training module, including: The SPD_info reading module is used to read DIMM information; The frequency selection module is used to obtain the corresponding register configuration file based on the input DIMM operating frequency; The register initialization module is used to initialize and configure the register parameters in DDR4 memory according to the obtained register configuration file. The register reconfiguration module is used to adjust the parameters to be adjusted in the key register parameters of the initialized DDR4 memory according to the different working mode requirements and the read DIMM information, and to configure the selected performance parameters and function control parameters. The training module is used to start the DDR4 IP to execute the training task after the register parameters are configured, based on the settings of the training parameters and training control parameters. The performance and functional control parameters selected by the register reconfiguration module include signal quality, timing, DM (Digital Modulation), parity function, bit width, address mapping, and performance. Correspondingly, the register reconfiguration module includes a signal quality adjustment module, a timing parameter optimization module, a mode register configuration module, a DM function control module, a parity function management module, a data bit width adjustment module, an address mapping configuration module, and a performance adjustment module, wherein: The signal quality adjustment module is used to adjust the ODT value of key signals at the IP end; The timing parameter optimization module is used to adjust the DRAM basic timing parameters, DFI interface timing parameters, DFI update timing parameters, self refresh parameters, IP internal access latency parameters, and mode register timing parameters. The mode register configuration module is used to adjust the ODT value in MR under different RANKs; The DM function control module is used to adjust whether the data mask DM function is enabled or disabled; The verification function management module is used to adjust whether ECC and CRC functions are enabled or disabled; The data bit width adjustment module is used to adjust the DIMM bit width information; The address mapping configuration module is used to adjust the address mapping parameters within the IP address. The performance tuning module is used to adjust the DDR bandwidth utilization.

2. The SoC chip-oriented efficient DDR4 memory debugging system according to claim 1, wherein, The training module includes a training parameter setting module, a training control module, and a training startup module, wherein: The training parameter setting module is used to set training parameters; The training control module is used to set the training control parameters; The training startup module is used to start the DDR4 IP to execute training tasks based on the settings of training parameters and training control.

3. The SoC chip-oriented efficient DDR4 memory debugging system according to claim 2, characterized in that, The testing module includes a training status monitoring module, a read / write testing module, and a system startup module, wherein: The training status monitoring module is used to check whether the adjusted register parameters are correct and to monitor whether the training results of the DDR4 IP are correct after starting the training task. The read / write test module is used to perform read / write tests on DRAM according to various preset test patterns and obtain test results. The system startup module is used to confirm that the operating system starts after training and testing have passed.

4. The SoC chip-oriented efficient DDR4 memory debugging system according to claim 3, characterized in that, The training status monitoring module is specifically used for: Verify that the adjusted register parameters are set correctly; Verify that the register parameters required to start the DDR4 IP to perform the training task are set correctly; Verify whether starting the DDR4 IP to execute the training task is successful; Determine if the DFI interrupt status bits are normal.

5. The high-efficiency DDR4 memory debugging system for SoC chips according to claim 4, characterized in that, The testing module is also used to: execute any one of the training status monitoring module, the read / write testing module, and the system startup module again after the training status monitoring module and the read / write testing module have been executed.

6. A high-efficiency DDR4 memory debugging method for SoC chips based on the system described in any one of claims 1-5, characterized in that, include: Obtain DIMM information, register configuration file and working mode information; adjust the parameters to be adjusted in the register configuration file according to the DIMM information, register configuration file and working mode information; and after completing the register parameter configuration, start the DDR4 IP to execute the training task according to the training parameter settings and training control settings. Check whether the adjusted register parameters are correct and monitor whether the training results of the training task performed on the DDR4 IP are correct. Perform read and write tests on the DRAM. If the check and training are confirmed to be successful and the read and write tests are successful, then select to start the operating system.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the efficient DDR4 memory debugging method for SoC chips as described in claim 6.

8. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the efficient DDR4 memory debugging method for SoC chips as described in claim 6.

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