Fan-out wiring structure and design method thereof, semiconductor package structure

By implementing a rotationally symmetric four-zone division and row-by-row fan-out routing design for the pad array, the fan-out problem of large-scale pad arrays within a limited metal routing layer is solved, achieving efficient utilization of routing resources and improved signal integrity.

CN121859827BActive Publication Date: 2026-07-21SHANGHAI QISHUAN GUANGQI INFORMATION TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI QISHUAN GUANGQI INFORMATION TECHNOLOGY CO LTD
Filing Date
2026-03-16
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

In existing technologies, large-scale pad arrays are difficult to fan out efficiently within a limited metal wiring layer, making it difficult to guarantee signal integrity. Traditional radial or simple stacked fan-out methods result in wiring congestion, parasitic effects, and severe signal crosstalk, making it difficult to meet the requirements of high-frequency applications.

Method used

The pad array is divided into four rotationally symmetrical regions, and a specific number of insertion points are inserted between each row of pads. The fan-out routing structure is designed using a row-by-row connection method, and the fan-out routing of other sub-regions is obtained by rotation and replication.

Benefits of technology

It achieves efficient fan-out of ultra-large-scale pad arrays within a limited metal wiring layer, reduces design complexity, improves wiring resource utilization efficiency, reduces interposer area and number of metal layers, and enhances signal transmission performance.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application provides a fan-out wiring structure and a design method thereof, and a semiconductor packaging structure, the fan-out wiring structure and the design method thereof are characterized in that a pad array is divided into four symmetrical regions, a specific number of insertion points are inserted between each row of pads, and a row-by-row connection mode is adopted, so that the high-efficiency fan-out of a super-large pad array in a limited metal wiring layer is realized. In addition, by adopting the design method of the fan-out wiring structure of the application in the interposer of the 2.5D packaging, the high-efficiency fan-out of the super-large pad array in the limited metal wiring layer is realized, the problems of fan-out difficulty, small wiring spacing, excessive metal wiring layers or excessive interposer area in the traditional method are effectively solved, the packaging cost is significantly reduced, and the signal transmission performance is improved.
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Citation Information

Patent Citations

  • Pad array, printed circuit board, manufacturing method of printed circuit board, board card, server and chip

    CN118250897A

  • Method of manufacturing a semiconductor device

    CN1607637A