A dynamic parameter testing method based on a fusion double-pulse model simulation test

Abstract

The application relates to the technical field of twin simulation, and particularly discloses a dynamic parameter testing method based on a fusion double-pulse model simulation test, which comprises the following steps: obtaining physical parameters and initial driving signals of a plurality of parallel chips, and calculating the transmission delay of the initial driving signals of each chip from a driver output end to a chip input end; determining a timing deviation according to the transmission delay, and generating a correction signal according to the timing deviation; simulating a switching process under a high-load working condition, and synchronously recording current waveforms and voltage waveforms of each chip in the switching process; calculating the turn-on loss, turn-off loss and conduction loss of each chip based on the current waveforms and the voltage waveforms, respectively; and summing the turn-on loss, the turn-off loss and the conduction loss to obtain the total loss of the chip. The transmission delay and the timing correction are introduced, so that the multi-chip parallel simulation is closer to actual operation, and the consistency between the simulation result and the actual performance is improved.

Description

Technical Field

[0001] This invention relates to the field of twin simulation technology, specifically to a dynamic parameter testing method based on fused dual-pulse model simulation testing. Background Technology

[0002] A SiCMOSFET module is a high-performance power switching device that integrates multiple silicon carbide metal oxide semiconductor field-effect transistor (MOSFET) chips and other necessary components (such as freewheeling diodes) into a compact package.

[0003] UPS power supplies commonly use SiCMOSFET modules with multiple chips connected in parallel. During simulation, the drive signals of all chips are set to be completely synchronized. However, in the actual drive circuit, the signals of different channels will have a micro-time deviation of 5ns-10ns.

[0004] Under high load conditions (such as 800A current), even a 5ns turn-on timing deviation will cause the chip that turns on first to bear a higher current in a short period of time (for example, the chip that turns on first will have an instantaneous current of 280A, while the chip that turns on later will only have 220A). Although the impact of a single deviation is short, the UPS switches thousands of times a day, and in the long run, this will lead to higher wear and tear on the chip that turns on first than in the simulation environment. Summary of the Invention

[0005] The purpose of this invention is to provide a dynamic parameter testing method based on fusion dual-pulse model simulation testing, thereby solving the above-mentioned technical problems.

[0006] The objective of this invention can be achieved through the following technical solutions: A dynamic parameter testing method based on fused dual-pulse model simulation includes the following steps: Obtain the physical parameters and initial drive signals of multiple parallel chips, calculate the transmission delay of the initial drive signal of each chip from the driver output to the chip input, and use the physical parameters to construct a behavioral model characterizing the electrical characteristics of the chips. Based on the transmission delay, the timing deviation of the chip's initial drive signal relative to the reference signal is determined. Based on the timing deviation, the chip's initial drive signal is offset on the time axis to generate a correction signal. In the dual-pulse test simulation environment, based on the behavior model, the correction signal is applied to the corresponding chip, and the preset load current and power supply voltage are applied to simulate the switching process under high load conditions. The current waveform and voltage waveform of each chip during the switching process are recorded simultaneously. Based on the current and voltage waveforms, the turn-on loss during the turn-on transient process, the turn-off loss during the turn-off transient process, and the conduction loss during the stable conduction state of each chip are calculated. The total loss of the chip is obtained by summing the turn-on loss, turn-off loss, and conduction loss.

[0007] As a further aspect of the present invention: calculating the transmission delay includes: Obtain the output resistance value of the driver; For each chip, obtain the trace length, inductance per unit length, and capacitance per unit length of its corresponding drive signal on the printed circuit board; Calculate the total distributed inductance of the drive signal trace based on the trace length and the distributed inductance per unit length; calculate the total distributed capacitance of the drive signal trace based on the trace length and the distributed capacitance per unit length. Based on the output resistance, total distributed inductance, and total distributed capacitance, an equivalent circuit model of the driving signal trace is constructed. By analyzing the response of the equivalent circuit model to the step signal, the transmission delay of the signal from the driver output to the chip input is determined.

[0008] As a further aspect of the present invention, calculating the transmission delay also includes: Build an equivalent circuit model in circuit simulation software; Apply a voltage step signal to the input of the equivalent circuit model; Monitor the voltage waveform at the output of the equivalent circuit model; The time elapsed from the start of the step signal until the output voltage reaches the first preset percentage of the voltage step signal amplitude is recorded; this time elapsed is the transmission delay.

[0009] As a further aspect of the present invention: determining the timing deviation includes: The initial drive signal corresponding to the maximum transmission delay is defined as the reference signal; Calculate the difference between the transmission delay of other chips and the maximum transmission delay. This difference is the timing deviation of the initial drive signal of the corresponding chip relative to the reference signal.

[0010] As a further aspect of the present invention: generating the correction signal includes: For chips with zero timing deviation, their initial drive signal is directly used as the correction signal; For a chip with a non-zero timing deviation, the overall waveform of its initial drive signal is delayed along the time axis by a duration equal to its timing deviation. The delayed drive signal is the correction signal for that chip.

[0011] As a further aspect of the present invention: calculating the turn-on loss includes: From the recorded current and voltage waveforms, the period from the rising edge of the correction signal to the chip current rising to the load current and the voltage dropping to zero is extracted as a waveform segment of the turn-on transient process. Within the time range of the waveform segment of the turn-on transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the first power; Integrating the first power over the entire time span of the waveform segment during the turn-on transient process yields the turn-on loss.

[0012] As a further aspect of the present invention: calculating the turn-off loss includes: From the recorded current and voltage waveforms, the period from the falling edge of the correction signal to the chip current dropping to zero and the voltage rising to the power supply voltage is extracted as a waveform segment of the turn-off transient process. Within the time range of the waveform segment of the turn-off transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the second power; Integrating the second power over the entire time span of the waveform segment during the turn-off transient process yields the turn-off loss.

[0013] As a further aspect of the present invention: calculating the conduction loss includes: Extract the periods when the chip is in the on state from the recorded current and voltage waveforms; During the conduction period, the time when the fluctuation amplitude of the instantaneous values ​​of the current waveform and voltage waveform relative to their respective average values ​​is less than the preset fluctuation threshold is selected as the stable conduction waveform segment. Within the time range of the waveform segment in the stable conduction state, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the third power; Integrating the waveform of the third power over the entire time range of the stable conduction state is the conduction loss of the chip.

[0014] The beneficial effects of this invention compared to the prior art are as follows: This invention introduces transmission delay calculation and timing deviation correction into simulation testing, enabling the drive signals of each chip to realistically reflect the timing differences in the actual circuit at the model level, thus making the dual-pulse simulation results closer to the real working state. By establishing a behavioral model based on physical parameters, the electrical response characteristics of the chips under high load conditions can be accurately characterized, providing a reliable basis for dynamic loss calculation. By constructing an equivalent circuit model to calculate the transmission delay of the drive signals and correcting the time axis of the drive signals of each chip, the errors caused by ignoring timing differences in ideal simulations can be effectively eliminated, ensuring the consistency and realism of the simulation drive under multi-chip parallel conditions. By performing piecewise integration calculations of turn-on loss, turn-off loss, and conduction loss, and using the corrected waveform as input data, the total loss distribution of each chip under real dynamic conditions can be obtained, thereby more accurately evaluating the loss differences between chips and the overall thermal load of the system.

[0015] In summary, this invention can significantly improve the dynamic parameter testing accuracy of multi-chip parallel power modules, making the simulation results more consistent with the actual operating characteristics, and providing a reliable simulation basis for chip selection, driver design and thermal management optimization. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings.

[0017] Figure 1 This is a flowchart illustrating a dynamic parameter testing method based on a fused dual-pulse model simulation test according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 As shown, this invention is a dynamic parameter testing method based on fused dual-pulse model simulation testing, comprising the following steps: Obtain the physical parameters and initial drive signals of multiple parallel chips, calculate the transmission delay of the initial drive signal of each chip from the driver output to the chip input, and use the physical parameters to construct a behavioral model characterizing the electrical characteristics of the chips. Specifically, before conducting simulation tests, based on the datasheets or experimental measurement results provided by the chip manufacturer, parameter information that can characterize the electrical performance of each chip, such as threshold voltage, on-resistance, transconductance, parasitic inductance, and parasitic capacitance, is extracted. This data is then input into the simulation environment as the chip's physical parameters.

[0020] The initial drive signal is obtained from the design documents of the drive circuit or the output waveform of the actual circuit. Its waveform shape is consistent with the signal output by the driver to the gate port of a single chip under standard conditions. It is usually a periodic pulse signal with specific amplitude, rising edge, and falling edge characteristics.

[0021] After obtaining the above information, the physical parameters of each chip are entered into the model parameter input interface using the power device behavior model module provided in the simulation software. This allows the model to parametrically reproduce the external electrical response characteristics of the chip without involving internal structural details. The behavior model constructed in this way can respond to the applied drive signal in the simulation environment and output the corresponding current and voltage waveforms to reflect the electrical behavior of the chip under different operating conditions.

[0022] In a preferred embodiment of the present invention, calculating the transmission delay includes: Obtain the output resistance value of the driver; For each chip, obtain the trace length, inductance per unit length, and capacitance per unit length of its corresponding drive signal on the printed circuit board; Calculate the total distributed inductance of the drive signal trace based on the trace length and the distributed inductance per unit length; calculate the total distributed capacitance of the drive signal trace based on the trace length and the distributed capacitance per unit length. Based on the output resistance, total distributed inductance, and total distributed capacitance, an equivalent circuit model of the driving signal trace is constructed. By analyzing the response of the equivalent circuit model to the step signal, the transmission delay of the signal from the driver output to the chip input is determined.

[0023] In a preferred embodiment, calculating the transmission delay further includes: Build an equivalent circuit model in circuit simulation software; Apply a voltage step signal to the input of the equivalent circuit model; Monitor the voltage waveform at the output of the equivalent circuit model; The time elapsed from the start of the step signal until the output voltage reaches the first preset percentage of the voltage step signal amplitude is recorded; this time elapsed is the transmission delay.

[0024] Specifically, calculating the propagation delay involves analyzing and simulating the electrical characteristics of the signal propagation path between the driver and the chip. In a real circuit, the drive signal is output by the driver and transmitted via wires on the printed circuit board to the input terminals of multiple parallel chips. Along this propagation path, the output resistance of the driver, as well as the distributed inductance and capacitance of the traces, jointly affect the signal propagation time. To accurately determine this propagation time delay, the resistance value at the driver output terminal must first be obtained. This resistance value can be provided in the driver's technical datasheet or measured through testing. For each chip, the corresponding drive signal path on the circuit board has a certain length, which determines the cumulative effect of the distributed inductance and capacitance of the wires. Each unit length of wire exhibits specific inductance and capacitance characteristics; these parameters can be determined based on the printed circuit board material, dielectric thickness, trace width, and wiring method. After understanding these unit length parameters and the actual trace length, the total distributed inductance and total distributed capacitance of the path can be calculated.

[0025] Based on this data, an equivalent circuit model describing the signal transmission path is established. In the model, the driver's output resistance, along with the total distributed inductance and capacitance of the traces, constitute the main electrical components of the signal transmission channel. This equivalent circuit allows for the analysis of the drive signal's transmission characteristics within the path in a simulation environment.

[0026] After building the equivalent circuit model in the circuit simulation software, a voltage step signal is applied to the input of the model to simulate the sudden change in the driver's output signal. Over time, the voltage propagates along the path and gradually builds up at the output. By monitoring the voltage waveform changes at the output of the equivalent circuit model, the process of the output voltage gradually rising from its initial value to close to the amplitude of the input signal is observed. The time elapsed from the start of the input voltage step until the output voltage reaches a predetermined percentage (preferably 60%) of the input voltage amplitude is recorded; this time elapsed is defined as the transmission delay of the signal from the driver output to the chip input.

[0027] Based on the transmission delay, the timing deviation of the chip's initial drive signal relative to the reference signal is determined. Based on the timing deviation, the chip's initial drive signal is offset on the time axis to generate a correction signal. In another preferred embodiment of the present invention, determining the timing deviation includes: The initial drive signal corresponding to the maximum transmission delay is defined as the reference signal; Calculate the difference between the transmission delay of other chips and the maximum transmission delay. This difference is the timing deviation of the initial drive signal of the corresponding chip relative to the reference signal.

[0028] In another preferred embodiment of the present invention, generating the correction signal includes: For chips with zero timing deviation, their initial drive signal is directly used as the correction signal; For a chip with a non-zero timing deviation, the overall waveform of its initial drive signal is delayed along the time axis by a duration equal to its timing deviation. The delayed drive signal is the correction signal for that chip.

[0029] In the dual-pulse test simulation environment, based on the behavior model, the correction signal is applied to the corresponding chip, and the preset load current and power supply voltage are applied to simulate the switching process under high load conditions. The current waveform and voltage waveform of each chip during the switching process are recorded simultaneously. It should be noted that, in order to accurately reproduce the dynamic switching behavior of multiple parallel chips under high load conditions during the simulation phase, a dual-pulse test simulation environment needs to be established. This simulation environment is based on the behavioral model constructed in the early stage. The behavioral model can respond to the input drive signal according to its external electrical parameters without involving the internal physical structure of the chip, and output the corresponding voltage and current changes, thereby reflecting the actual conduction and turn-off characteristics of the chip at the model level.

[0030] The timing-corrected drive signals are input to the corresponding chip behavior models, ensuring that each model receives signal timing consistent with the actual circuit drive path during simulation. This method allows for the reproduction of the relative time difference between multi-channel drive signals caused by transmission delays within the simulation environment. To make the simulation conditions more closely resemble the chip's operating state in a real power conversion device, preset load currents and power supply voltages are applied to each chip model. The load current is set based on expected operating conditions to simulate the chip's conduction state under high current output, while the power supply voltage represents the actual DC bus or power supply terminal voltage input.

[0031] Under this setup, the simulation scenario can reproduce the typical two-pulse operation process experienced by the chip during high-power conversion, including the transient changes during the turn-on, conduction, and turn-off phases. As the simulation runs, the rising and falling edges of the drive signal trigger the chip's turn-on and turn-off actions, respectively, and the voltage across the chip and the current flowing through the chip change dynamically over time. By synchronously monitoring these changes and recording the voltage and current waveforms in the simulation software, complete electrical response data for each chip during the switching process can be obtained.

[0032] The waveform recordings cover the entire process from the initial application of the drive signal to the chip returning to its static state, ensuring the inclusion of critical transient information during the turn-on, turn-off, and stable conduction phases. This waveform data provides a foundation for subsequent quantitative analysis of the turn-on, turn-off, and conduction losses of each chip, and also enables the simulation results to reflect the true power distribution characteristics of the multi-chip parallel structure during dynamic operation.

[0033] Based on the current and voltage waveforms, the turn-on loss during the turn-on transient process, the turn-off loss during the turn-off transient process, and the conduction loss during the stable conduction state of each chip are calculated. The total loss of the chip is obtained by summing the turn-on loss, turn-off loss, and conduction loss.

[0034] In a preferred embodiment of the present invention, calculating the turn-on loss includes: From the recorded current and voltage waveforms, the period from the rising edge of the correction signal to the chip current rising to the load current and the voltage dropping to zero is extracted as a waveform segment of the turn-on transient process. Within the time range of the waveform segment of the turn-on transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the first power; Integrating the first power over the entire time span of the waveform segment during the turn-on transient process yields the turn-on loss.

[0035] In another preferred embodiment of the present invention, calculating the turn-off loss includes: From the recorded current and voltage waveforms, the period from the falling edge of the correction signal to the chip current dropping to zero and the voltage rising to the power supply voltage is extracted as a waveform segment of the turn-off transient process. Within the time range of the waveform segment of the turn-off transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the second power; Integrating the second power over the entire time span of the waveform segment during the turn-off transient process yields the turn-off loss.

[0036] In another preferred embodiment of the present invention, the calculation of conduction loss includes: Extract the periods when the chip is in the on state from the recorded current and voltage waveforms; During the conduction period, the time when the fluctuation amplitude of the instantaneous values ​​of the current waveform and voltage waveform relative to their respective average values ​​is less than the preset fluctuation threshold is selected as the stable conduction waveform segment. Within the time range of the waveform segment in the stable conduction state, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the third power; Integrating the waveform of the third power over the entire time range of the stable conduction state is the conduction loss of the chip.

[0037] It should be noted that the method for obtaining the turn-on transient waveform segment is as follows: In the current and voltage waveforms recorded in simulations or tests, the rising edge of the correction signal is used as the time reference point to observe the dynamic process of the chip transitioning from the off state to the on state. During this stage, the voltage across the chip gradually decreases from the power supply voltage, while the current flowing through the chip gradually increases to a stable load current level. By marking the moment when the current begins to rise and the moment when the voltage drops to near zero in the waveform diagram, and extracting the time interval between these two points, the turn-on transient waveform segment is obtained.

[0038] The method for obtaining the waveform segment of the turn-off transient process is as follows: using the falling edge of the correction signal as the time reference point, observe the dynamic changes of the chip as it transitions from the on state to the off state. During this process, the current across the chip gradually decreases to near zero, while the voltage rises to the power supply voltage level within the same time period. In the recorded waveform, mark the moment when the current begins to decrease and the moment when the voltage rises and stabilizes, and extract the time interval between these two points; this is the waveform segment of the turn-off transient process.

[0039] The method for obtaining the waveform segment of the stable conduction state is as follows: During the continuous period when the chip is in the conduction state, select the portion where the current and voltage waveforms are relatively stable and do not fluctuate significantly. To determine the stability of the waveform, calculate the deviation of the instantaneous values ​​of current and voltage relative to their respective average values. When the deviation amplitude is less than a preset fluctuation threshold, the period can be considered a stable conduction state. On the waveform diagram, this segment is represented by a continuous time interval where the current remains near a constant value, the waveform is flat, and the voltage remains low and unchanged.

[0040] This solution addresses the discrepancy between simulation and actual operation of multi-chip parallel SiC MOSFET modules, resolving the technical problem of inaccurate loss assessment caused by the complete synchronization of drive signals in traditional simulations. In actual UPS power supplies, due to differences in signal transmission path length and impedance between driver channels, there is a minute time-series deviation in the arrival time of drive signals for each chip. This causes some chips to turn on prematurely under high load conditions and bear higher transient currents. Traditional simulations do not consider this deviation, resulting in simulated power losses that are lower than the actual operating values, failing to accurately reflect the thermal stress distribution of the chips under long-term operation.

[0041] This solution obtains the physical parameters of the drive path, calculates the transmission delay of the drive signal for each chip, and uses this to determine the timing deviation. The drive signals of each chip are then corrected on the time axis to ensure that the timing of the drive signals in the simulation matches the actual circuit. The corrected signals are applied to the corresponding behavioral model in a dual-pulse simulation environment. The model reproduces the dynamic electrical response of the chip based on its physical parameters, thus accurately reflecting the uneven current distribution and loss differences caused by timing deviations in the simulation. Through this method, the turn-on loss, turn-off loss, and conduction loss calculated by the simulation are closer to the actual operating results. This allows engineers to assess the impact of timing differences on chip thermal load and reliability during the design phase, achieving a realistic prediction of the dynamic characteristics of parallel chips. This avoids the underestimation of losses caused by ignoring timing errors in traditional simulations, fundamentally improving the accuracy of dynamic parameter testing and the reliability of engineering applications.

[0042] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A dynamic parameter testing method based on fused dual-pulse model simulation testing, characterized in that, Includes the following steps: Obtain the physical parameters and initial drive signals of multiple parallel chips, calculate the transmission delay of the initial drive signal of each chip from the driver output to the chip input, and use the physical parameters to construct a behavioral model characterizing the electrical characteristics of the chips. The initial drive signal corresponding to the maximum transmission delay is defined as the reference signal. Based on the transmission delay, the timing deviation of the chip's initial drive signal relative to the reference signal is determined. Based on the timing deviation, the chip's initial drive signal is offset on the time axis to generate a correction signal. In the dual-pulse test simulation environment, based on the behavior model, the correction signal is applied to the corresponding chip, and the preset load current and power supply voltage are applied to simulate the switching process under high load conditions. The current waveform and voltage waveform of each chip during the switching process are recorded simultaneously. Based on the current and voltage waveforms, the turn-on loss during the turn-on transient process, the turn-off loss during the turn-off transient process, and the conduction loss during the stable conduction state of each chip are calculated. The total loss of the chip is obtained by summing the turn-on loss, turn-off loss, and conduction loss.

2. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, Calculating transmission delay includes: Obtain the output resistance value of the driver; For each chip, obtain the trace length, inductance per unit length, and capacitance per unit length of its corresponding drive signal on the printed circuit board; Calculate the total distributed inductance of the drive signal trace based on the trace length and the distributed inductance per unit length; calculate the total distributed capacitance of the drive signal trace based on the trace length and the distributed capacitance per unit length. Based on the output resistance, total distributed inductance, and total distributed capacitance, an equivalent circuit model of the driving signal trace is constructed. By analyzing the response of the equivalent circuit model to the step signal, the transmission delay of the signal from the driver output to the chip input is determined.

3. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 2, characterized in that, Calculating transmission delay also includes: Build an equivalent circuit model in circuit simulation software; Apply a voltage step signal to the input of the equivalent circuit model; Monitor the voltage waveform at the output of the equivalent circuit model; The time elapsed from the start of the step signal until the output voltage reaches the first preset percentage of the voltage step signal amplitude is recorded; this time elapsed is the transmission delay.

4. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, Determining timing deviations includes: Calculate the difference between the transmission delay of other chips and the maximum transmission delay. This difference is the timing deviation of the initial drive signal of the corresponding chip relative to the reference signal.

5. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, The generation of the correction signal includes: For chips with zero timing deviation, their initial drive signal is directly used as the correction signal; For a chip with a non-zero timing deviation, the overall waveform of its initial drive signal is delayed along the time axis by a duration equal to its timing deviation. The delayed drive signal is the correction signal for that chip.

6. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, The calculation of turn-on losses includes: From the recorded current and voltage waveforms, the period from the rising edge of the correction signal to the chip current rising to the load current and the voltage dropping to zero is extracted as a waveform segment of the turn-on transient process. Within the time range of the waveform segment of the turn-on transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the first power; Integrating the first power over the entire time span of the waveform segment during the turn-on transient process yields the turn-on loss.

7. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, The calculation of turn-off losses includes: From the recorded current and voltage waveforms, the period from the falling edge of the correction signal to the chip current dropping to zero and the voltage rising to the power supply voltage is extracted as a waveform segment of the turn-off transient process. Within the time range of the waveform segment of the turn-off transient process, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the second power; Integrating the second power over the entire time span of the waveform segment during the turn-off transient process yields the turn-off loss.

8. The dynamic parameter testing method based on fused dual-pulse model simulation testing according to claim 1, characterized in that, The calculation of conduction loss includes: Extract the periods when the chip is in the on state from the recorded current and voltage waveforms; During the conduction period, the time when the fluctuation amplitude of the instantaneous values ​​of the current waveform and voltage waveform relative to their respective average values ​​is less than the preset fluctuation threshold is selected as the stable conduction waveform segment. Within the time range of the waveform segment in the stable conduction state, the current value and voltage value at the same moment are multiplied to obtain the instantaneous power at that moment, which is denoted as the third power; Integrating the waveform of the third power over the entire time range of the stable conduction state is the conduction loss of the chip.

Images