Memory control method and storage device

Abstract

This application belongs to the field of memory control, and provides a memory control method and a storage device. The method includes: receiving a maintenance policy setting command from a host system, the command being used to configure maintenance policy data for a specified logical region; updating a maintenance record in a critical data maintenance table according to the command, the maintenance record containing maintenance policy data and dynamic metadata of the logical region; dynamically selecting a target logical region among the logical regions associated with the critical data maintenance table, and performing a background health check on it; and triggering a graded repair action for the target logical region based on the health check results. This application achieves closed-loop management where the host flexibly defines reliability policies and the storage device autonomously performs health monitoring and graded repair, enabling proactive detection and handling of data degradation trends, effectively improving the reliability and maintainability of the storage device.

Description

Technical Field

[0001] This application relates to the field of memory control, and more particularly to a memory control method and a memory device. Background Technology

[0002] As the density of NAND (Not-AND) flash memory continues to increase, issues such as data retention and read / write interference are having an increasingly significant impact on storage reliability. In high-density storage environments, factors such as charge leakage and read operation interference can easily lead to bit flips in static data, and even cause metadata corruption. For boot data, critical system metadata, and important user-specified data, such corruption may directly result in device failure to boot or permanent data loss.

[0003] Existing technologies for ensuring data reliability mainly fall into two categories. One category is redundancy and error correction techniques, such as using multiple-copy storage or enhanced error-correcting codes like low-density parity-check codes. These techniques effectively address a certain degree of bit errors by adding redundancy information during data writing and detecting and correcting errors during data reading. However, these methods are essentially passive responses to errors that have already occurred, failing to proactively monitor and periodically assess the health of the data, and making it difficult to detect potential degradation trends in a timely manner.

[0004] Another type of technology involves metadata reconstruction and garbage collection mechanisms. For example, after an abnormal power outage, corrupted metadata can be reconstructed by scanning the flash memory media or using an auxiliary mapping table. This type of technology is typically initiated after an internal device event, such as when a power outage or an increased read error rate is detected, to perform a recovery operation.

[0005] In summary, existing solutions are insufficient to effectively intervene before irreversible data damage occurs, and there is an urgent need for a reliability management mechanism that allows upper-level definition of maintenance goals and autonomous health monitoring and maintenance by the equipment. Summary of the Invention

[0006] In view of this, this application provides a memory control method and a memory device to solve the technical problem of low reliability in health detection and maintenance of memory devices in the prior art.

[0007] Embodiments of this application provide a memory control method applied to a storage device including a memory module and a memory controller; The method includes: The system receives a maintenance policy setting command from the host system. The maintenance policy setting command is used to set maintenance policy data for a specified logical area. The maintenance policy setting command includes: type information, identity information, and maintenance policy data of the specified logical area. According to the maintenance strategy setting command, update the maintenance record in the critical data maintenance table. The maintenance record includes maintenance strategy data and dynamic metadata in a logical area. In each logical area associated with the critical data maintenance table, a target logical area to be checked is dynamically selected, and a background health check is performed on the target logical area. Based on the health check results, a graded repair action is triggered on the target logical region.

[0008] Embodiments of this application also provide a storage device including a connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; and The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method described above.

[0009] Based on the above, the memory control method and storage device proposed in the embodiments of this application introduce a mechanism in the memory controller where maintenance policies are issued by the host system. This allows the host to flexibly configure differentiated reliability maintenance policies for specified logical regions based on the importance of different data, including parameters such as inspection mode, inspection cycle, bit error rate threshold, verification algorithm, and priority. The memory controller updates the critical data maintenance table according to the received maintenance policy, dynamically selects the target logical region to be inspected, and performs background health checks. Then, based on the inspection results, it triggers tiered repair actions. This approach constructs a closed-loop management process from policy configuration and health monitoring to autonomous repair, achieving programmable and proactive prevention of storage reliability. On the one hand, the host system can define data protection levels according to application semantics, solving the problems of passive device response and lack of customized maintenance in existing technologies. On the other hand, the device firmware autonomously performs health checks and tiered repairs in the background, enabling timely detection and handling of data degradation trends, effectively reducing the risk of silent data corruption and irreversible data loss. Simultaneously, the dynamic selection mechanism and tiered repair strategy optimize resource scheduling and reduce the impact on front-end performance, thereby significantly improving the reliability, maintainability, and data security of the storage device.

[0010] To make the above-mentioned objectives, technical solutions and beneficial effects of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of this application.

[0012] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application; Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating the data structure and relationships of a three-level logic-to-entity mapping table according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating the division of a buffer memory into multiple cache units according to an embodiment of this application; Figure 6 This is a general flowchart of a memory control method according to an embodiment of this application; Figure 7 This is a schematic diagram of the health check process in the execution background provided in the embodiments of this application; Figure 8 This is a flowchart illustrating the process of adjusting the execution frequency of health checks according to an embodiment of this application; Figure 9 This is a schematic diagram of the process for detecting corrupted silent data provided in an embodiment of this application; Figure 10 This is a schematic diagram of the waste recycling process provided in an embodiment of this application; Figure 11 This is another schematic diagram of the process for performing background health checks provided in an embodiment of this application. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of this application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0014] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, automotive infotainment system, advanced driver assistance system (ADAS), game console, server, or computer system located in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. Furthermore, the storage device 12 can include a solid-state drive (SSD), universal flash storage (UFS), embedded multi-media card (eMMC), USB flash drive, memory card, or other types of non-volatile storage devices. It is particularly suitable for fields with stringent requirements for reliability, data integrity, environmental tolerance, and long-term stability, such as industrial control, edge computing, and automotive electronics.

[0015] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multimedia cards, general-purpose flash memory, Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0016] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quadruple-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics. For multi-level cell (MLC, TLC, QLC, and PLC) flash memory modules, specially selected and tested flash memory modules that meet the requirements of wide operating temperature (e.g., -40°C to 105°C or higher), high durability, and data retention can be used.

[0017] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller. In particular, for automotive functional safety requirements, the architecture of memory controller 123 may include safety islands, dual-core lockstep, or other redundancy and monitoring mechanisms to ensure the reliability of control logic.

[0018] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0019] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0020] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0021] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and controlled by the memory controller 123 to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. Specifically, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates. To ensure the reliability and consistency of the mapping table data (described in detail below) in the event of sudden events such as abnormal power failures, the buffer memory 24 may employ a storage medium with power loss protection (PLP) characteristics or incorporate a backup capacitor design to ensure that critical metadata has sufficient time to be written into the memory module 122.

[0022] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code.

[0023] In one embodiment, the memory controller 123 may also include other types of various circuit modules (e.g., power management circuits, etc.), which are not limited in this application.

[0024] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply of the storage device 12. The power management circuit 26 not only manages conventional power consumption, but also meets the complex power sequences and low static power consumption requirements of automotive electronics, and can handle voltage fluctuations during vehicle start-stop processes, ensuring that the storage device 12 operates stably in harsh power environments.

[0025] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0026] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0027] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0028] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0029] In one embodiment, an entity erasure unit may include multiple entity programmable units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0030] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0031] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with the free area 32. Furthermore, physical units in the free area 32 can be erased to clear the data within them. In one embodiment, physical units in the free area 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as the free pool.

[0033] In one embodiment, in response to the requirements of predictable storage lifetime for industrial and automotive applications, the memory control circuit 23 can implement wear leveling and bad block management strategies, and monitor the number of erase / write cycles, read counts, and data retention time of each physical unit in real time, so as to provide the host system 11 with a health status report and remaining lifetime prediction of the storage device 12, thereby meeting the diagnostic coverage requirements of relevant functional safety standards.

[0034] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0038] In one embodiment, the logical-to-physical mapping table includes a two-level, three-level, and four-level mapping table structure. Specifically, the two-level mapping table introduces a virtual address layer (also called a virtual cell address or virtual block address) between the logical address and the physical address. This allows the memory control circuit 23 to decouple the contiguous logical address space from the physical address space, which may become discontinuous due to bad blocks, wear leveling, or garbage collection. The core idea is that logical addresses are first mapped to virtual addresses, and then virtual addresses are mapped to physical addresses. When a physical block (such as a bad block) becomes unavailable, only the mapping from virtual address to physical address needs to be updated to point to a free and available physical block, while the mapping from logical address to virtual address remains unchanged. The workflow is as follows: when the host system 11 requests to write to a logical address (LBA), the memory control circuit 23 first finds the corresponding virtual address through the first-level mapping table (L1). Then, it actually writes the data to the currently mapped, free physical address (PBA), through the second-level mapping table (L2). If this physical block later becomes a bad block, the memory control circuit 23 only needs to remap the virtual address to a good, free physical block in the secondary mapping table and move the original valid data.

[0039] With the surge in storage capacity and increasingly sophisticated write amplification optimization requirements, a three-level mapping table data structure is proposed in one embodiment. This adds another layer of abstraction to the two-level mapping, primarily for finer-grained management of the space in the large-capacity storage device 12 and reducing unnecessary writes. The three-level mapping table typically includes mappings from logical addresses to virtual addresses, from virtual addresses to intermediate data packets, and from intermediate data packets to physical addresses. This structure allows the memory control circuitry 23 to manage data storage at a finer granularity (e.g., a single logical page corresponding to multiple physical pages or dynamic mapping units), thereby reducing write amplification during garbage collection and mapping item update operations. The workflow is as follows: when writing data, a mapping from logical addresses to virtual addresses is first generated; the data corresponding to the virtual addresses is organized into data packets, which are ultimately written to the specific physical pages of the memory module 122. Specifically, the memory control circuitry 23 does not immediately update the main mapping table (also called the complete mapping table) stored in the memory module 122 for each small write (e.g., 4KB in size), but instead accumulates these mapping changes in the buffer memory 24. When the amount of dirty mapping entries in the buffer memory 24 reaches a certain threshold (ratio = amount of written mapping entries / capacity of buffer memory 24), the memory control circuit 23 will write multiple dirty mapping entries in batches and in an orderly manner into the third-level mapping table (L3) of the main mapping table in the memory module 122. Preferably, during the mapping entry update operation, data packets with a large amount of mapping entry data or older age will be processed first to maximize the efficiency of the update operation.

[0040] When the storage device 12 is an enterprise-grade solid-state drive with extreme performance and ultra-high capacity, a four-level mapping table data structure is proposed in one embodiment. For example, it includes virtual channel mapping (L1), intra-channel die mapping (L2), die hybrid mapping (L3), and physical address mapping (L4). Specifically, virtual channel mapping breaks up consecutive LBAs and distributes them evenly across multiple virtual flash channels. Its main purpose is to utilize the parallelism of multiple channels within the memory module 122 to avoid a single channel becoming a performance bottleneck. Virtual channel mapping typically maintains a mapping table from LBA ranges to virtual channel IDs.

[0041] Once a virtual channel is defined, the intra-channel die mapping is responsible for scheduling multiple physical dies (chips) within that channel. This enables interleaving of operations between multiple dies within the channel. When one die is busy, operations can be routed to another idle die, thus hiding access latency. The intra-channel die mapping records the physical die ID corresponding to each virtual die address and typically integrates wear leveling operations to ensure that the same die is not frequently accessed.

[0042] Die hybrid mapping employs a hybrid mapping strategy within a single die. It divides the write operation into two parts: First, random write data is written to blocks using SLC mode, which employs page mapping, resulting in low latency and high speed. Once the SLC block is full, the memory control circuit 23 merges and organizes multiple SLC blocks, writing them into the final data block. This data block can use block mapping and page mapping, or 4K and sector mapping.

[0043] The lowest level physical address mapping records the final mapping relationship from each logical address to a physical address. When the host system 11 needs to read data, it locates the physical address of the data by querying this level of mapping table. Because there are many mapping relationships in L4, this level of mapping table is very large. It is usually not entirely resident in memory (DRAM or buffer memory 24), but uses a caching mechanism to cache only the active mapping tables in memory, while the majority of the rest is stored in the memory module 122. The memory control circuit 23 loads the corresponding mapping table into memory as needed.

[0044] In one embodiment, such as Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the data structure and relationships of a three-level logical-to-entity mapping table according to an embodiment of this application. This mapping structure is used to efficiently manage the mapping relationship between logical units and entity units, and is particularly suitable for industrial and automotive storage scenarios with stringent requirements for access speed, memory efficiency, and reliability.

[0045] Figure 4In this system, the first-level mapping table is relatively small, maintained by the memory control circuit 23, and resides in the buffer memory 24. Each entry records the base address or index number of a second-level mapping table in the buffer memory 24, with the index key being the high-order part of the logical address. Each second-level mapping table corresponds to a contiguous range of logical addresses (called a logical segment). Its entries store two types of information: one is a pointer directly to a physical unit (used for sequential large blocks of data or merged data); the other, more commonly, is a pointer to a third-level mapping table. The second-level mapping tables are loaded from the memory module 122 into the buffer memory 24 as needed. Each third-level mapping table manages a finer-grained mapping relationship within a logical block, storing the final physical address of each logical page to a physical programmable unit (e.g., a physical page). This is crucial for achieving random writes and efficient garbage collection.

[0046] When the host system 11 requests data access via a logical address, the memory control circuit 23 uses the most significant bit of the logical address to index the first-level mapping table and obtain the address of the template second-level mapping table. It loads (if not already in the buffer) and accesses the second-level mapping table, using the middle part of the logical address for indexing. If the entry directly points to a physical unit, the physical page offset is calculated using the low-order bits of the logical address. If the entry points to a third-level mapping table, it loads (if not already in the buffer) and accesses the third-level mapping table, using the least significant bit of the logical address for indexing to obtain the physical address of the final physical programmed unit. The memory control circuit 23 sends the corresponding read or write instruction sequence to the memory module 122 via the memory interface 22 to operate the physical programmed unit. Through hierarchical and on-demand loading, all mapping relationships are avoided from residing in the buffer memory 24, reducing the capacity requirement of the buffer memory 24 and saving hardware costs for the memory controller 123. Simultaneously, the resident first-level table ensures the initial speed of mapping lookups.

[0047] Figure 5 This is a schematic diagram of a buffer memory 24 shown in an embodiment of the present invention.

[0048] Please refer to Figure 5The buffer memory 24 has buffer units 510-51D, each with a capacity of, for example, 4KB, which is aligned with the typical small block I / O size of the host system 11. Specifically, the capacity of the four buffer units corresponds to the capacity of one physical programmable unit of the memory module 122 (i.e., a page size of 16KB). However, it must be understood that this embodiment does not limit the number of buffer units configured in the buffer memory 24, the capacity of the buffer units, or the size of the data transmitted by the host system 11. Furthermore, the host system 11 transmits or accesses data, for example, in units of 4KB. Alternatively, in another embodiment, the capacity of the data transmitted or accessed by the host system 11 each time may be greater than or less than 4KB.

[0049] Figure 6 This is a general flowchart of a memory control method according to an embodiment of the present invention. The method is applied to a storage device 12 including a memory module 122. A memory control circuit 23 is configured to execute this method. The method begins at step S601.

[0050] S601. Receive a maintenance policy setting command from the host system. The maintenance policy setting command is used to set the maintenance policy data of the specified logical area. The maintenance policy setting command includes: the type information, identity information and maintenance policy data of the specified logical area.

[0051] Specifically, the memory control circuit 23 receives a maintenance policy setting command from the host system 11 via the host interface 21. The maintenance policy setting command is used to specify a logical region and configure corresponding maintenance policy data for that logical region. The maintenance policy setting command contains at least three components: type information, identity information, and maintenance policy data.

[0052] Type information indicates the category attribute of the specified logical region. This category attribute can take various forms, such as a logical block address range, namespace, logical unit, or boot partition. Identity information uniquely identifies a specific logical region within the category defined by the type information. For example, when the type information indicates a logical block address range, the identity information includes the starting logical block address and the region length. When the type information indicates a namespace, the identity information includes the namespace identifier. When the type information indicates a logical unit, the identity information includes the logical unit number. When the type information indicates a boot partition, the identity information includes the boot partition identifier.

[0053] The maintenance strategy data contains a series of parameters used to guide the memory control circuit 23 in performing reliability maintenance on the logical region. The maintenance strategy data includes at least one of the following: Inspection mode, which determines the execution method of health checks, and can be a fixed-period or adaptive mode; Inspection cycle, which takes effect when the inspection mode is set to a fixed cycle and specifies the time interval between two health checks; First bit error rate threshold, used to trigger a refresh operation; when the bit error rate detected when reading data from this logical region reaches or exceeds this threshold, it indicates that the data in this region needs to be refreshed to prevent further error accumulation; Second bit error rate threshold, used to trigger an emergency alarm; when the bit error rate of the error checking and correction circuit 25 reaches or exceeds this threshold and exceeds the error correction capability, the memory control circuit 23 needs to immediately issue an emergency notification to the host system 11; Data integrity verification algorithm identifier, used to indicate which algorithm is used to verify data integrity during the health check process; Priority, used to determine the scheduling order among maintenance tasks of multiple logical regions when the memory control circuit 23 is under resource constraints.

[0054] After receiving the maintenance strategy setting command, the memory control circuit 23 parses the command, obtains the type information, identity information and maintenance strategy data carried in it, and temporarily stores this information through the memory interface 22 into the buffer memory 24 for subsequent processing.

[0055] For example, host system 11 sends a maintenance policy setting command to memory control circuit 23 via the UFS (Universal Flash Storage) protocol's device manager command. The command sets the type information to logical cell and the identity information to logical cell number zero. The maintenance policy data includes the following settings: Inspection mode is set to a fixed cycle; inspection cycle is set to 12 hours; first bit error rate threshold is set to 0.1%; second bit error rate threshold is set to 1%; data integrity verification algorithm identifier is set to CRC32 (Cyclic redundancy check); priority is set to highest. After receiving and parsing the command, memory control circuit 23 learns that host system 11 requests maintenance of the logical area with logical cell number 0 and obtains the aforementioned maintenance policy parameters configured for that area.

[0056] S602. According to the maintenance policy setting command, update the maintenance record in the critical data maintenance table. The maintenance record includes maintenance policy data and dynamic metadata of a logical area.

[0057] Specifically, the memory control circuit 23 creates or updates a maintenance record in the critical data maintenance table of its internal maintenance system based on the received maintenance policy setting command. The critical data maintenance table is a data structure used by the memory control circuit 23 to store maintenance information for all registered logical regions. This table can be stored in the random access memory (buffer memory 24) of the memory control circuit 23, or it can be periodically written to the memory module 122 to prevent data loss after power failure. Each maintenance record in the critical data maintenance table uniquely corresponds to a logical region that has been specified by the host system 11 through the maintenance policy setting command.

[0058] Each maintenance record consists of two parts. The first part is maintenance policy data, which comes from the maintenance policy setting commands issued by the host system 11 and includes various maintenance parameters configured by the host system 11 for this logical area. The second part is dynamic metadata, which is dynamically generated and maintained by the memory control circuit 23 during operation, reflecting the real-time status and historical inspection status of this logical area.

[0059] Dynamic metadata includes at least one or more of the following information: The last check timestamp records the most recent time a health check was performed on the logical region. The health score, calculated based on the most recent health check results, is a quantitative representation of the data health status within the logical region. The cumulative read count records the total number of times the logical region has been read by the host system since registration; this parameter can be used to assess the impact of read interference on data retention. The currently associated block information refers to the specific information of the flash storage blocks currently mapped to this logical address range, such as block number, block type, and number of erase / write operations. The risk coefficient benchmark is calculated based on the inherent attributes of each block currently associated with the logical region, including the average number of erase / write operations and the initial programming temperature of the block. The risk coefficient benchmark serves as a reference baseline for subsequent health checks and risk assessments.

[0060] When updating maintenance records, the memory control circuit 23 first determines the corresponding logical region based on the type and identity information in the maintenance policy setting command. Then, it checks the critical data maintenance table to see if a maintenance record already exists for that logical region. If it does, it updates the maintenance policy data field and recalculates or updates the dynamic metadata field. If it does not exist, it creates a new maintenance record, stores the maintenance policy data in the corresponding fields, and initializes the dynamic metadata field.

[0061] The health score is calculated based on the most recent health check results. The most recent health check results refer to various physical status and data integrity indicators collected from the logical region during the most recent health check, such as the actual bit error rate obtained when reading data, the number of erase / write operations on associated blocks in that region, data residence time, and cumulative read count. The memory control circuit 23 converts these indicators into a score according to preset rules. For example, in a health check, the average bit error rate of the logical region is 5.2e. -6 The current maximum number of erase / write cycles for the associated block is 3200, the data residency time is 45 days, and the cumulative number of reads is 12000. The memory control circuit 23 uses a weighted scoring formula to calculate the health score, which is 100 minus the sum of the products of each normalized indicator and its weight. Let the bit error rate normalization factor be the actual bit error rate divided by the reference bit error rate 1e-5 and then multiplied by 20; the erase / write cycle normalization factor be the actual erase / write cycle divided by the designed lifespan of 5000 cycles and then multiplied by 30; the data residency time normalization factor be the actual number of days divided by the reference number of 90 days and then multiplied by 25; and the read cycle normalization factor be the actual number of reads divided by the reference number of 100000 times and then multiplied by 15. The calculated normalized values ​​are: Bit Error Rate (BER) 10.4, Write Erasure Count 19.2, Data Dwell Time 12.5, and Read Count 15 multiplied by 0.12 equals 1.8. A total of 43.9 points are deducted, resulting in a health score of 56.1 points (100 minus 43.9). This score is stored in the health score field of the maintenance record to characterize the current health status of the region.

[0062] The risk coefficient benchmark is calculated based on the inherent attributes of the currently associated blocks in the logical region. Inherent attributes refer to the static characteristics of a block determined during manufacturing or initial use, such as the block's designed erase / write lifetime and initial programming temperature. The memory control circuit 23 acquires all blocks currently mapped to the logical region, extracts the erase / write cycles and initial programming temperature for each block, calculates the average as a representative value of the region's inherent attributes, and then obtains the risk coefficient benchmark through normalization. For example, if the logical region is currently mapped to three flash memory blocks, with block A having 800 erase / write cycles, block B having 1200, and block C having 1000, the average erase / write cycles is 1000. Dividing the average erase / write cycles by the designed lifetime of 5000 yields a normalized value of 0.2. The initial programming temperatures of the three blocks are 25°C, 30°C, and 29°C, respectively, with an average temperature of 28°C. Dividing this temperature by a reference temperature of 55°C yields a normalized value of 0.51. The risk coefficient benchmark can be calculated using a weighted average method. Assuming the write / erase frequency has a weight of 0.7 and temperature has a weight of 0.3, the risk coefficient benchmark would be 0.293. This value is stored as a benchmark in dynamic metadata and used during subsequent health checks to compare with current dynamic parameters to assess aging trends.

[0063] For example, continuing from the example in step S601, the memory control circuit 23 creates a new maintenance record for logic unit zero in the critical data maintenance table of the buffer memory 24. First, maintenance strategy data obtained from the maintenance strategy setting command is filled into the corresponding fields of the record. This data includes a fixed-cycle inspection mode, a 12-hour inspection cycle, a first bit error rate threshold of 0.1%, a second bit error rate threshold of 0.1%, a data integrity verification algorithm identifier of CRC32, and the highest priority. Then, dynamic metadata is initialized, setting the last inspection timestamp to the current time, initializing the health score to the default value of zero (indicating no evaluation yet), and initializing the cumulative read count to zero. The memory control circuit 23 further queries the flash memory blocks currently mapped to logic unit zero to obtain the block numbers and their respective erase / write counts. Assuming logic unit zero is currently associated with two blocks with erase / write counts of 1500 and 1700 respectively, the average erase / write count is 1600. The memory control circuit 23 calculates the risk coefficient benchmark based on the average number of erase / write cycles, divides 1600 by the design life of 5000 cycles to obtain a normalized value of 0.32, and stores this as the risk coefficient benchmark in the dynamic metadata. At this point, a complete maintenance record is added to the critical data maintenance table. This record contains both the maintenance strategy data defined by the host system 11 and the dynamic metadata maintained by the memory control circuit 23.

[0064] S603. In each logical area associated with the critical data maintenance table, dynamically select a target logical area to be checked, and perform a background health check on the target logical area.

[0065] Specifically, the memory control circuit 23 runs a low-priority background task. This task dynamically selects a target logical region to be checked from the various logical regions associated with the critical data maintenance table and performs a health check on that target logical region. The scheduling strategy of the background task considers multiple factors to determine the next target logical region to be checked. These factors include the difference between the last check timestamp and the set check cycle for each logical region, the current health score, and the input / output load of the memory control circuit 23 itself. For logical regions with high health scores (i.e., good data status), the check interval can be appropriately extended; for logical regions with low health scores or close to the threshold, checks are prioritized. At the same time, the background task senses the load of the memory control circuit 23. When input / output requests are busy, the check frequency is reduced or even the check is paused; when the storage device 12 is idle, the check intensity is increased. After selecting the target logical region, the memory control circuit 23 performs a health check operation on that region.

[0066] The health check comprises two aspects: data integrity verification and physical status acquisition. Data integrity verification involves reading some or all data pages within the target logical area according to the data integrity verification algorithm specified by the host system 11 in the maintenance policy data, recalculating the checksum, and comparing it with the original checksum previously stored in the out-of-band area or metadata area of ​​that data page to determine if there is any silent data corruption. Physical status acquisition involves obtaining the actual bit error rate when reading data through the error checking and correction circuit 25, and querying information about the flash memory blocks currently associated with that logical area, including the number of erase / write cycles, data residency time, cumulative read count, and possible historical temperature data. Based on this acquired information, the memory control circuit 23 can also calculate a comprehensive risk score according to preset rules. This score quantifies the current health status of the target logical area and updates the score to the health score field of the critical data maintenance table.

[0067] The granularity of health checks can be flexibly controlled, typically employing two modes. One is a local rapid scan, which randomly selects a subset of data pages within a region for quick updates to health indicators. This mode can be executed frequently to maintain timely awareness of the region's status. The other is a global deep scan, which performs a complete check of all data pages within the region. This mode is triggered only when a set check cycle is reached or when anomalies are detected by the local rapid scan, ensuring the accuracy of the assessment.

[0068] For example, the critical data maintenance table already records the maintenance record of logical unit zero, i.e., the startup partition. When the memory control circuit 23 detects that the storage device 12 is in an idle period, such as when a mobile phone is charging and the screen is off, the background task is awakened. The background task scans the critical data maintenance table and finds that the last check timestamp of the startup partition is more than 12 hours away from the current time, and this area has the highest priority. Therefore, the startup partition is selected as the target logical area for this health check. The memory control circuit 23 first performs a local fast scan, randomly selects several critical data pages in the startup partition, recalculates the check value of each data page according to the CRC32 algorithm specified by the host system 11, and compares it with the original CRC32 value stored in the out-of-band area of ​​each data page. All comparison results are consistent, indicating that the data integrity is good. At the same time, the error rate of each read page is obtained through the error checking and correction circuit 25, and the error rate is at a low level. The memory control circuit 23 also queries the erase and write count of the flash memory block currently associated with the startup partition. Since the startup partition is rarely written to, the erase and write count is very low. Based on the collected information, the memory control circuit 23 calculates a health score according to a preset weighted formula, for example, 95 points, indicating that the data in that area is very healthy. Subsequently, the memory control circuit 23 updates the last check timestamp of the starting partition to the current time, updates the health score to 95 points, and adds the number of pages involved in this read to the cumulative read count. After this health check is completed, the background task enters a waiting state, awaiting the next scheduling opportunity.

[0069] S604. Based on the health check results, trigger a graded repair action for the target logical area.

[0070] Specifically, after completing a health check of the target logic region, the memory control circuit 23 compares the obtained health check results with a preset threshold to determine whether a repair action needs to be performed and what level of repair should be taken. The graded repair action includes three levels, each corresponding to different triggering conditions and execution methods. Each level of repair action can be triggered individually or in combination as needed.

[0071] The triggering conditions for tiered repair actions are not limited to the bit error rate threshold; they can also be based on other indicators in the health check results. For example, the first level of repair is triggered when the health score is lower than the preset first repair trigger value, and the third level of repair is triggered directly when the health score is lower than the preset second repair trigger value.

[0072] In one possible embodiment, the health score is calculated by weighting at least two of the following factors: The current bit error rate of the logical region, the number of erase / write operations of the associated blocks, the data residence time and cumulative number of reads of the associated blocks, and the weights of each factor are either pre-configured or adaptively adjusted.

[0073] Specifically, after each health check of the logical region, the memory control circuit 23 calculates a health score for that logical region based on the collected parameters. The health score is a quantified value representing the health status of the data within the logical region, used for subsequent scheduling decisions and repair triggering. The health score is calculated based on a weighted sum of multiple factors, including at least two of the following four: The first factor is the current bit error rate, obtained from data read by the error checking and correction circuit 25 during the most recent health check. The second factor is the number of erase / write operations on the associated block, reflecting the wear level of the flash memory block currently mapped to the logical region. The third factor is the data residency time of the associated block, i.e., the time elapsed since the data was written, reflecting the degree to which data retention is affected by time. The fourth factor is the cumulative number of reads, recording the total number of reads of the logical region by the host system 11 since registration, used to assess the impact of read interference effects.

[0074] When calculating the health score, the memory control circuit 23 first needs to normalize the original values ​​of each factor, converting them into dimensionless values ​​so that factors with different dimensions can be weighted and combined. Normalization can be based on pre-set reference values. For example, for the current bit error rate, a reference bit error rate can be used as the denominator for normalization. For the number of erase / write cycles, the design life of the flash memory block can be used as the denominator. For data residence time, a reference residence time can be used as the denominator. For the cumulative number of reads, a reference number of reads can be used as the denominator. The normalized factor values ​​are typically distributed between 0 and 1.

[0075] After normalization, the memory control circuit 23 assigns a weight to each factor involved in the calculation. There are two ways to determine the weights. One way is pre-configuration, where a fixed set of weights is preset in the firmware of the memory control circuit 23, or the host system 11 specifies the weights of each factor when issuing a maintenance strategy setting command. The other way is adaptive adjustment, where the memory control circuit 23 dynamically adjusts the weights of each factor based on the overall operating status of the storage device 12 or historical statistical information. For example, when the storage device 12 is in the later stages of its lifespan, the weight of the erase / write count factor is appropriately increased; when significant read interference is detected, the weight of the cumulative read count factor is appropriately increased.

[0076] The memory control circuit 23 multiplies the normalized values ​​of each factor with their corresponding weights, and then sums the products to obtain the base value of the health score. In some embodiments, the base value can be further modified, for example, by subtracting it from a perfect score, so that the health score falls within an intuitive numerical range, such as between zero and one percent, where a higher score indicates healthier data and a lower score indicates that the data requires more attention.

[0077] This embodiment integrates multiple physical factors affecting data reliability into a comprehensive health score through weighted calculation, providing an intuitive quantitative decision-making basis for the memory control circuit 23. Simultaneously, through a configurable or adaptive adjustment mechanism for the weights, the health score can flexibly adapt to the needs of different application scenarios and different stages of device lifespan.

[0078] In one possible embodiment, see Figure 7 , Figure 7 This is a flowchart illustrating the health check process performed in the execution background according to an embodiment of this application, including the following steps: S701. Based on the dynamic metadata or load status of each logical region in the key data maintenance table, dynamically select a target logical region to be inspected.

[0079] Specifically, the memory control circuit 23 runs a low-priority background task that dynamically selects a target logical region to be inspected from multiple logical regions recorded in the critical data maintenance table. The information used in the selection process mainly includes two types: dynamic metadata of each logical region and the current load status of the storage device 12.

[0080] The dynamic metadata contains real-time status information for each logical region, which can provide a basis for selection decisions. For example, the last inspection timestamp can be combined with the inspection cycle set in the maintenance strategy data to calculate the degree of overdueness of each logical region before its next inspection. The health score directly reflects the data health status of the logical region; regions with lower scores need to receive inspection opportunities earlier. The cumulative number of reads reflects the degree to which the logical region is affected by read interference. The memory control circuit 23 can calculate a scheduling priority value for each logical region based on preset rules, integrating multiple fields in this dynamic metadata. The higher the value, the higher the priority of inspection for that logical region.

[0081] The load state of storage device 12 refers to the level of activity of the memory control circuit 23 in processing input / output requests from the host system 11. When the load state is high, the memory control circuit 23 can suspend background tasks or only allow checks on a few high-priority logical regions. When the load state is low, the selection criteria can be relaxed, allowing more logical regions to enter the check queue. The memory control circuit 23 can quantify the current load state by monitoring the command queue depth or idle time ratio, and use the load state as a threshold condition in the selection process of the target logical region. For example, only when the load state is below a certain threshold is a background task allowed to wake up and perform the selection of logical regions.

[0082] Considering the above two factors, each time a background task is woken up, the memory control circuit 23 first obtains the current load status and determines whether the selection of execution region is allowed. If allowed, it traverses all maintenance records in the critical data maintenance table, calculates the scheduling priority value based on the dynamic metadata in each record, and then selects one or more logical regions from high priority to low priority as the target logical regions to be checked this time.

[0083] For example, the critical data maintenance table currently records three logical regions: logical unit zero, logical unit one, and a user-specified document region. The dynamic metadata for logical unit zero shows that the last check timestamp is 13 hours past the last check, while its set check cycle is 12 hours, the overdue level is 1 hour, and the health score is 95. The dynamic metadata for logical unit one shows that the overdue level is 2 hours, and the health score is 80. The dynamic metadata for the document region shows that the overdue level is not yet significant, and the health score is 60. The memory control circuit 23 sets the calculation rule for the scheduling priority value to be the sum of the overdue minutes and the health score deduction value, where the health score deduction value is 100 points minus the current health score. The calculated scheduling priority value for logical unit zero is 60 minutes plus 5 points equals 65, the scheduling priority value for logical unit one is 120 minutes plus 20 points equals 140, and the scheduling priority value for the document region is 0 minutes plus 40 points equals 40. At this time, the memory control circuit 23 detects that the load status is low and the command queue is empty, therefore allowing the selection of two logical regions for checking. The background task selects logical unit one and logical unit zero as the target logical region for this task according to the scheduling priority value from high to low.

[0084] S702. Perform a background health check on the target logical region and update the dynamic metadata of the target logical region based on the health check results.

[0085] Specifically, after selecting a target logical region, the memory control circuit 23 performs a background health check on that region. The health check includes two aspects: data integrity verification and physical status acquisition. The health check results for the target logical region are obtained through these two aspects of the check.

[0086] Data integrity verification involves reading some or all data pages within the target logical area according to the data integrity verification algorithm identifier stored in the maintenance record of the target logical area, recalculating the check value for each data page, and comparing it with the original check value stored in the out-of-band area of ​​that data page. If the comparison matches, it indicates that no silent corruption has occurred during data storage. If the comparison does not match, it indicates that the data has been corrupted, and this corruption will be recorded in the health check results.

[0087] Physical status acquisition involves obtaining the actual bit error rate detected during data reading through the error checking and correction circuit 25. Simultaneously, the memory control circuit 23 queries information about the flash memory blocks currently mapped to the target logical region, including the erase / write count for each block and the timestamp of data writing, to calculate the current data residency time. For cumulative read counts, the memory control circuit 23 increments the number of reads added to the target logical region since the last health check.

[0088] After data acquisition is complete, the memory control circuit 23 recalculates the health score of the target logical region based on the parameters obtained from this health check, i.e., the health check results, according to the preset health scoring rules. The health score can be calculated by weighted summation of multiple factors, such as the current bit error rate, the number of erase / write operations of associated blocks, data residence time, and cumulative read counts. After calculating the new health score, this value is updated to the health score field in the dynamic metadata of the maintenance record. At the same time, the time of this health check is updated to the last check timestamp field in the dynamic metadata. The accumulated read count is updated to the cumulative read count field in the dynamic metadata. If inconsistencies in data integrity verification are found during the health check, an anomaly marker needs to be added to the dynamic metadata, or the anomaly event needs to be recorded in a dedicated log area for use in subsequent graded repair steps.

[0089] The granularity of the health check can be flexibly adjusted as needed. Typically, the memory control circuit 23 employs a local fast scan mode, randomly selecting a subset of data pages within the target logical region for inspection to quickly obtain representative indicators. When the set global inspection cycle is reached, or when an abnormal indicator is detected by the local fast scan, a global deep scan mode is triggered to perform a comprehensive inspection of all data pages within that region, ensuring the accuracy of the assessment.

[0090] For example, continuing from the example in step S701, the memory control circuit 23 selects logic unit one as one of the target logic regions. The data integrity verification algorithm identifier stored in the maintenance record of this target logic region is CRC32. The memory control circuit 23 randomly selects 16 data pages from logic unit one as samples and performs a health check on each data page. The error checking and correction circuit 25 reads the data of each data page and recalculates the CRC32 value, comparing it with the original CRC32 value stored in the out-of-band area of ​​each data page. The comparison results of all 16 pages are consistent, and this result is used as part of the health check result. The error rate of each read page is obtained through the error checking and correction circuit 25, and the average error rate is calculated to be 3.2e. -6 This is also part of the health check results. The flash memory block information currently mapped to the target logical region is queried, revealing an average write / erase count of 2100 times for the associated blocks. The average data residency time, calculated based on the data write timestamps, is 30 days. This information is also included in the health check results. Simultaneously, the number of reads of the target logical region by the host system 11 since the last health check is accumulated, assuming an additional 800 reads. The memory control circuit 23 recalculates the health score based on these health check results, setting the bit error rate reference value to 1e. -5 The design lifespan for erase / write cycles is 5000 times, the reference value for data residence time is 90 days, and the reference value for cumulative read counts is 100,000 times, with weights of 20, 30, 25, and 15 respectively. Normalized calculations yield a bit error rate of 0.32, an erase / write cycle normalization of 0.42, a data residence time normalization of 0.33, and a cumulative read count normalization of 0.108. The weighted sum equals 28.87, and the health score is 100 minus 28.87, which equals 71.13. The memory control circuit 23 updates the dynamic metadata of target logic unit one, updates the timestamp to the current time, updates the health score to 71.13, and updates the cumulative read count to 10800. This health check is complete, and the background task continues processing the next target logic area.

[0091] This embodiment employs a dynamic selection mechanism to ensure that the memory control circuit 23 can rationally allocate inspection resources based on the health urgency of each logic region and the load of the storage device 12. Simultaneously, through background health checks and real-time updates of dynamic metadata, it provides timely and accurate data status information for tiered repair.

[0092] In one possible embodiment, see Figure 8 As shown, Figure 8 The flowchart illustrating the adjustment of the execution frequency of health checks provided in this application embodiment includes the following steps: S801. When the storage device 12 is detected to be under high load, reduce the execution frequency of health checks or suspend health checks.

[0093] Specifically, during the background health check task, the memory control circuit 23 continuously monitors the current load status of the storage device. The load status reflects the busyness of the memory control circuit 23 in processing input / output requests from the host system 11, and can be quantified in various ways, such as monitoring the number of commands waiting to be processed in the command queue, calculating the data read / write throughput per unit time, or calculating the percentage of idle time for the memory control circuit 23. The memory control circuit 23 presets one or more load thresholds to determine whether it is currently in a high-load state. When the load status is detected to exceed a preset high-load threshold, for example, if the command queue depth continuously exceeds a certain value, or if the idle time of the storage device 12 is lower than a certain percentage, then the storage device 12 is determined to be in a high-load state.

[0094] Under high load, the memory control circuit 23 needs to reduce the impact of health checks on front-end input / output performance, and therefore takes corresponding measures to adjust the execution mode of background health checks. Specific ways to reduce the execution frequency of health checks include extending the time interval between two health check task initiations, or reducing the number of logical regions checked after each wake-up. Suspending health checks is a more thorough measure, temporarily suspending the background health check task until the load returns to normal before restarting the health check. When deciding whether to reduce the execution frequency or suspend health checks, the memory control circuit 23 can implement tiered processing based on the degree of load exceeding limits; for example, reducing the execution frequency of health checks when the load is slightly exceeding limits, and suspending health checks when the load is severely exceeding limits. These adjustments are all automatically completed internally by the memory control circuit 23 without intervention from the host system 11.

[0095] For example, the memory control circuit 23 sets a command queue depth threshold as the basis for judging the load state, stipulating that when the command queue depth exceeds 32, the storage device 12 is considered to be in a high-load state. During a certain period, the host system 11 continuously initiates a large number of data write requests. The memory control circuit 23 detects that the command queue depth remains above 40, thus determining that the storage device 12 is in a high-load state. According to a preset adjustment strategy, the memory control circuit 23 adjusts the execution frequency of the background health check from once every 100 milliseconds to once every 500 milliseconds, thereby reducing the execution frequency of the health check. If the command queue depth further rises to above 64, the memory control circuit 23 directly suspends the background health check until the queue depth falls back below 32 before restarting the health check.

[0096] S802. When the detection storage device 12 is in a low load state, increase the execution frequency of health checks.

[0097] Specifically, corresponding to the high-load state, the memory control circuit 23 also detects whether the storage device 12 is in a low-load state. A low-load state means that the host system 11 has fewer input / output requests, and the memory control circuit 23 has sufficient idle resources for background maintenance operations. The determination of a low-load state is also based on a preset load threshold, such as a command queue depth consistently below a certain value, or the memory control circuit 23 having an idle time higher than a certain percentage. When the load is detected to be below the low-load threshold, the memory control circuit 23 determines that the storage device 12 is in a low-load state.

[0098] Under low load conditions, the memory control circuit 23 can fully utilize idle resources to enhance data reliability maintenance, thus increasing the execution frequency of health checks. Specific ways to increase the execution frequency of health checks include shortening the time interval between two health check task initiations, increasing the number of logical regions checked after each wake-up, or switching the check granularity from local fast scanning to global deep scanning. These measures help to discover potential data reliability issues more quickly and trigger timely repair actions. The memory control circuit 23 can also dynamically adjust the increase based on the degree of low load; for example, moderately increasing the execution frequency of health checks during light idle periods and performing the most intensive health checks during deep idle periods.

[0099] For example, continuing the above scenario, after a period of time, the input / output requests of the host system 11 decrease. The memory control circuit 23 detects that the command queue depth drops below 8 and remains low, thus determining that the storage device 12 is in a low-load state. According to a preset adjustment strategy, the memory control circuit 23 increases the execution frequency of the background health check from once every 500 milliseconds to once every 50 milliseconds. At the same time, the number of logical regions checked after each health check increases from 1 to 3, and the check granularity is switched from local fast scan to global deep scan, performing a comprehensive check on all data pages within the selected region. This high-intensity health check continues until the load state recovers to above the low-load threshold.

[0100] This embodiment uses load-aware dynamic scheduling to match the intensity of health checks with the real-time load of storage device 12. It yields to high loads to ensure front-end performance and strengthens maintenance to improve data reliability under low loads. This adaptive mechanism maximizes the use of idle resources for proactive data health management while ensuring a good user experience.

[0101] In one possible embodiment, see Figure 9 , Figure 9 This is a schematic diagram of the process for detecting corrupted silent data provided in an embodiment of this application, including the following steps: S901. Read the data of the target logical region and calculate the first verification value using the verification algorithm specified in the maintenance strategy data of the target logical region. S902. Compare the first check value with the pre-stored second check value, and detect whether there is silent data corruption in the target logical area based on the comparison result.

[0102] In step S901, during the background health check of the target logical region, the memory control circuit 23 first needs to verify the integrity of the data stored in the target logical region. The first step of the integrity verification is to read the data from the target logical region and recalculate the first verification value according to the verification algorithm specified in the maintenance strategy data of the target logical region.

[0103] The memory control circuit 23 retrieves the data integrity verification algorithm identifier contained in the maintenance strategy data of the target logical region based on the maintenance record of the target logical region in the critical data maintenance table. This identifier indicates the verification algorithm type specified by the host system 11 for the target logical region, such as Cyclic Redundancy Check (CRC32) or Secure Hash Algorithm (SHA-256). Different verification algorithms correspond to different calculation methods and check value lengths. The error checking and correction circuit 25 pre-implements the calculation modules for these verification algorithms and can call the corresponding calculation functions according to the algorithm identifier.

[0104] When reading data, the memory control circuit 23 determines the reading range based on the granularity of the health check. If a local fast scan is being performed, a certain number of data pages are randomly selected from the target logical region as samples for reading. If a global deep scan is being performed, all data pages within the target logical region are read. For each read data page, the memory control circuit 23 inputs the data of that page into a specified verification algorithm, and the algorithm calculates a fixed-length checksum, which is the first checksum. The first checksum reflects the data characteristics of that data page at the current moment; any change in any bit in the data will cause the recalculated first checksum to differ from the original value.

[0105] For example, the target logical region is logical unit one, and the verification algorithm specified in its maintenance strategy data is CRC32. When performing a health check on the target logical region, the memory control circuit 23 uses a local fast scan mode to randomly select 16 data pages as samples. For the first selected data page, the memory control circuit 23 reads 4096 bytes of data from the flash memory, and then inputs this 4096 bytes of data into the CRC32 algorithm module for calculation to obtain a new 32-bit check value. Assuming this value is 0xA5B6C7D8, this value is the first check value of the data page. The memory control circuit 23 continues to repeat the same operation for the remaining 15 sample pages to obtain the first check value for each sample page.

[0106] In step S902, after calculating the first check value of each read data page in the target logic area, the memory control circuit 23 needs to compare these first check values ​​with the pre-stored second check values, and determine whether there is silent data corruption in the target logic area based on the comparison result.

[0107] The second checksum is the original checksum calculated and stored by the memory control circuit 23 based on the data at that time when the data is initially written to the buffer memory 24. During the data writing process, the memory control circuit 23 calculates the checksum of the data according to the same checksum algorithm and stores the checksum along with the data. Typically, the second checksum is stored in the out-of-band area of ​​the data page, which belongs to the same flash memory physical page as the data page itself, but can be accessed separately during reading.

[0108] The memory control circuit 23 compares the first check value of each data page bit by bit with the second check value read from the out-of-band area of ​​that data page to obtain the comparison result. If the comparison result shows that the first check value and the second check value are completely consistent, it is determined that the data page has no silent data corruption. If the comparison result shows that the two are inconsistent, it is determined that the data page has silent data corruption. This corruption may be caused by factors such as charge leakage, read interference, or programming interference, and may exceed the detection capability of the error correction code. The memory control circuit 23 records the comparison result in the health check result. For data pages found to have silent data corruption, it records their logical address and error type for subsequent graded repair steps.

[0109] For example, continuing from the scenario in step S901, after calculating the first checksum of the first sample page (0xA5B6C7D8), the memory control circuit 23 reads the stored second checksum from the out-of-band region of that data page. Assuming the read second checksum is 0xA5B6C7D8, the comparison result shows they are completely consistent, and the memory control circuit 23 determines that the data page has no quiescent data corruption. For the second sample page, the memory control circuit 23 calculates the first checksum to be 0x11223344, but the second checksum read from the out-of-band region is 0x11223355. The comparison result shows they are inconsistent, and the memory control circuit 23 determines that the data page has quiescent data corruption and records the logical address and error type of the data page in the health check result. The memory control circuit 23 continues to compare the remaining 14 sample pages, finally obtaining the data integrity verification result of this health check.

[0110] This embodiment, by introducing data integrity verification specified by the host system 11 into the background health check, can effectively detect silent data corruption that traditional error correction codes cannot detect. This proactive verification mechanism, combined with physical condition monitoring, provides a more comprehensive view of data health for tiered repair, thereby further improving the data reliability of the storage device 12.

[0111] In one possible embodiment, the graded repair action is the first-level repair action; The triggering condition for the first-level repair action is: the current bit error rate obtained based on the health check results exceeds the first bit error rate threshold defined in the maintenance strategy data, and the data in the target logical area is within the error-correctable range; The first level of repair action is to mark the block containing the target logical region as having a high refresh priority.

[0112] Specifically, after completing a health check of the target logic region, the memory control circuit 23 determines whether a first-level repair action needs to be triggered based on the obtained health check results. The first-level repair action is a preventative measure taken when data has deteriorated to a certain extent but has not yet exceeded the error-correctable range.

[0113] The triggering conditions for a Level 1 repair action include two conditions that must be met simultaneously. The first triggering condition is a comparison between the current bit error rate (BER) in the health check results and the first BER threshold defined in the maintenance strategy data. The current BER refers to the ratio of the number of erroneous bits detected by the error checking and correction circuit 25 to the total number of bits read when data is read from the target logical area. The first BER threshold is a value pre-set by the host system 11 in the maintenance strategy data, used to indicate the critical point at which data needs to be refreshed. When the current BER exceeds the first BER threshold, it indicates that the data quality of the target logical area has deteriorated to a level requiring attention. The second triggering condition is that the data in the target logical area is still within the error-correctable range. The error-correctable range means that although the current BER is high, the error correction codes can still successfully correct all erroneous bits, thereby restoring the original correct data. If the data has exceeded the error-correctable range, it falls under a higher level of repair.

[0114] When both of the above triggering conditions are met simultaneously, the memory control circuit 23 determines that a first-level repair action needs to be performed. This first-level repair action specifically involves marking the block containing the target logical region as having a high refresh priority. The block containing the target logical region refers to the flash memory block currently mapped to that target logical region. In its internally maintained block management data structure, the memory control circuit 23 sets a status flag bit for each block, indicating whether the block has a high refresh priority. When a block is marked as having a high refresh priority, its information is added to the garbage collection candidate source block list, where it enjoys a higher priority. During subsequent garbage collection, the garbage collection process prioritizes moving these blocks marked as having a high refresh priority, thereby completing data reading, error correction, and rewriting during the moving process, thus achieving a data refresh operation. This marking mechanism itself does not immediately trigger a write operation; instead, it coordinates the first-level repair action with the garbage collection process, minimizing additional write overhead.

[0115] For example, during a health check of the target logic region, i.e., logic cell one, the memory control circuit 23 obtains, through the error checking and correction circuit 25, the current bit error rate of a data page in the target logic region as 1.2e. -3 The first bit error rate threshold defined in the maintenance strategy data for this target logical region is 1.0e. -3 Due to the current bit error rate of 1.2e -3 It has exceeded the first bit error rate threshold of 1.0e. -3The first trigger condition is met. Simultaneously, the error checking and correction circuit 25 successfully corrected all erroneous bits in the data page, restoring the correct data, indicating that the data is still within the error-correctable range, thus meeting the second trigger condition. Therefore, both trigger conditions for the first-level repair action have been met. The memory control circuit 23 then queries the block containing the data page, assuming it is block number 1024, and sets the block's status flag to high refresh priority in the block management data structure. Simultaneously, it adds the block number to the garbage collection candidate source block list and adjusts its priority order in the list so that it will be prioritized during subsequent garbage collection. Later, when the memory control circuit 23 detects a low load on the storage device 12, it initiates the garbage collection process. This process prioritizes block 1024 from the candidate source block list for relocation, reads all data pages within the block, corrects errors using error correction codes, and writes them into a new free block, thereby completing the data refresh.

[0116] This embodiment of the technical solution achieves a preventative first-level repair action for data that is about to deteriorate by coordinating data refresh requirements with the garbage collection mechanism by marking data refresh requirements as high refresh priority, while effectively controlling write amplification. This lightweight marking action itself does not consume additional write bandwidth, and the data refresh is completed naturally only during the subsequent garbage collection process, with minimal impact on the performance of the storage device 12.

[0117] In one possible embodiment, see Figure 10 As shown, Figure 10 The schematic diagram of the waste recycling process provided in the embodiments of this application includes the following steps: S1001. Add blocks marked as high refresh priority to the priority source block candidate list for the garbage collection process.

[0118] Specifically, after marking a block as having a high refresh priority, the memory control circuit 23 needs to ensure that the block can be processed with priority in subsequent garbage collection. To this end, the memory control circuit 23 adds the information of the block to the priority source block candidate list maintained by the garbage collection process.

[0119] Garbage collection is a background operation in storage device 12 used to reclaim space occupied by invalid data. Memory control circuitry 23 maintains one or more source block candidate lists to record information about blocks to be reclaimed. In this scheme, memory control circuitry 23 additionally maintains a priority source block candidate list, specifically for storing blocks marked with high refresh priority. When a block is marked with high refresh priority, memory control circuitry 23 adds the block's identifier, such as its block number, to the priority source block candidate list. This list has a higher priority than the ordinary source block candidate list. When the garbage collection process starts, it first checks the priority source block candidate list; only when this list is empty will it select a block to be reclaimed from the ordinary list.

[0120] The priority source block candidate list can be implemented using data structures such as queues or linked lists. When adding a block, the memory control circuit 23 can append the block information to the end of the list or insert it into an appropriate position in the list according to the urgency of the block being marked. To ensure the timeliness of the refresh operation, the priority source block candidate list is usually processed in a first-in, first-out (FIFO) order, so that blocks marked earlier can get the opportunity to be reclaimed earlier.

[0121] For example, after block number 1024 is marked as high refresh priority, the memory control circuit 23 immediately adds block number 1024 to the priority source block candidate list. At this time, block numbers 512 and 768 are already waiting to be processed in the priority source block candidate list, and the memory control circuit 23 appends 1024 to the end of the list. This list currently records the information of blocks 512, 768, and 1024 in sequence for priority processing in subsequent garbage collection processes.

[0122] S1002. During the garbage collection process, when a block from the priority source block candidate list is collected, the process of moving the valid data in the block is used to complete the reading, error correction and writing of the valid data to a new location.

[0123] Specifically, when initiating the garbage collection process, the memory control circuit 23 first checks the priority source block candidate list. If the list is not empty, it selects one or more blocks from it as the objects to be collected in this garbage collection process. For the blocks selected from the priority source block candidate list, the garbage collection process performs a relocation operation, which also serves as a data refresh function.

[0124] During garbage collection, when moving a selected block, all data pages in that block are first read. For each read data page, the memory control circuit 23 corrects detected errors in the data page using the error checking and correction circuit 25, restoring the correct data. After reading and correction, the memory control circuit 23 determines whether the data page is valid. Valid data refers to data whose logical address is still being used by the host system 11 and has not been updated or deleted. For valid data, the memory control circuit 23 writes the corrected data to a new free block, i.e., writes it to a new location. After writing, the mapping relationship between the logical address and the new physical block is updated. Invalid data pages do not need to be moved. Once all valid data pages in the block have been moved, the memory control circuit 23 marks the original block as recyclable and erases it at an appropriate time, making it a new free block for subsequent use.

[0125] Through this process, data originally stored in blocks marked as high refresh priority undergoes a series of operations—reading, error correction, and writing to a new location—during the garbage collection process's relocation, thus achieving a refresh operation. This refresh operation is completely integrated with the regular garbage collection relocation operation, without introducing additional read, write, or erase actions, therefore having minimal impact on write amplification. Simultaneously, due to the existence of the priority source block candidate list, this data requiring refresh receives a higher processing priority than ordinary garbage collection, ensuring that data degradation issues are addressed promptly.

[0126] For example, the memory control circuit 23 initiates a garbage collection process when the storage device 12 is idle. This process first checks the priority source block candidate list and finds blocks 512, 768, and 1024. The memory control circuit 23 selects block 1024 as the target for this garbage collection. Then, it reads all 128 data pages in block 1024. The error checking and correction circuit 25 processes the read data and finds that three data pages contain erroneous bits, but all errors are successfully corrected. The memory control circuit 23 checks the logical address mapping status of each data page, confirming that 96 data pages are valid and 32 are invalid. For the 96 valid data pages, the memory control circuit 23 sequentially writes the corrected data into a free block, such as block 2048, i.e., writes it to a new location. Each time a data page is written, the mapping relationship between the page's logical address and block 2048 is updated. Once all 96 valid data pages have been moved, the memory control circuit 23 marks block 1024 as awaiting reclamation and reclaims it as a free block during the subsequent erase operation. At this point, the data originally stored in block 1024 has been refreshed during the move, migrated to the new block 2048, and all correctable errors have been fixed during the move.

[0127] This embodiment achieves deep integration of refresh operations and garbage collection by including high refresh priority blocks in the priority source block candidate list of the garbage collection process. This collaborative mechanism completes preventive data refresh without adding extra write operations, effectively controls write amplification, and ensures that data that needs to be refreshed can be processed in a timely manner.

[0128] In one possible embodiment, the graded repair action is a second-level repair action; The trigger condition for the second-level repair action is: the logical-to-physical address mapping table is detected to be corrupted based on the health check results; The second-level repair action is to rebuild the logical-to-physical address mapping table using the metadata backup information stored in the memory module 122.

[0129] Specifically, the memory control circuit 23 continuously monitors the integrity of the logical-to-physical address mapping table during operation. The logical-to-physical address mapping table is the core data structure of the flash memory translation layer, used to record the correspondence between the logical addresses accessed by the host system 11 and the physical addresses where the data is actually stored. When this logical-to-physical address mapping table is damaged, the host system 11 will be unable to find the correct data through the logical address, resulting in inaccessible or even unrecognizable data.

[0130] The second-level repair action is triggered based on the detection of damage to the logical-to-physical address mapping table (Logic-to-Physical Address Mapping) by the health check results. Health check results can indicate Logic-to-Physical Address Mapping damage through several means. One means is that during normal data access, when querying the physical address according to the Logic-to-Physical Address Mapping table, if the address points to an invalid area or the error correction code verification of the read data frequently fails, the memory control circuit 23 can infer that the Logic-to-Physical Address Mapping table may be damaged. Another means is that during the power-on initialization of the storage device 12, when loading the Logic-to-Physical Address Mapping table from the memory module 122, if an inconsistency in the checksum or partial unreadable data is detected, it directly indicates that the Logic-to-Physical Address Mapping table is damaged. Yet another means is that during a background health check, when performing integrity verification on the dedicated storage area where the Logic-to-Physical Address Mapping table resides, if silent data corruption or an abnormally high error rate is found, it can be determined that the Logic-to-Physical Address Mapping table is at risk of damage or has already been damaged.

[0131] When the aforementioned triggering conditions are met, the memory control circuit 23 initiates the second-level repair action, namely, reconstructing the logical-to-physical address mapping table using the metadata backup information stored in the memory module 122. Metadata backup information refers to redundant data pre-saved to address potential damage to the logical-to-physical address mapping table, typically stored in a specific area of ​​the memory module 122. This metadata backup information can include the following types: Checkpoint information refers to snapshots formed by periodically saving the complete logical-to-physical address mapping table or incremental changes to the logical-to-physical address mapping table to the memory module 122, recording the complete state of the logical-to-physical address mapping table at a certain moment. Physical-to-logical address pointers are reverse mapping information stored in the out-of-band area of ​​each data page, recording the logical address corresponding to the data stored in that physical page. Write logs record address mapping changes that have occurred within a recent period, which can serve as the basis for incremental updates during the reconstruction process.

[0132] When the memory control circuit 23 performs the reconstruction process, it first reads the most recently saved checkpoint information from the memory module 122 and loads it into memory as the base version of the logical-to-physical address mapping table. Then, it scans all physical blocks, reads the physical-to-logical address pointers stored in the out-of-band area of ​​each valid data page, compares and supplements these pointers with the base version, and corrects any missing or incorrect mapping entries found in the base version. Simultaneously, it reads the most recent change operations recorded in the write log and applies mapping updates not yet reflected in the checkpoint to the reconstructed logical-to-physical address mapping table. Through the combined use of these three types of metadata backup information, the memory control circuit 23 can gradually restore the complete logical-to-physical address mapping relationship. After reconstruction is complete, the new logical-to-physical address mapping table is written to the memory module 122 for persistent storage, and normal address translation services are restored.

[0133] For example, if a storage device 12 suddenly loses power during normal operation, and upon power-up, the memory control circuit 23 loads the logical-to-physical address mapping table from the memory module 122. During loading, the memory control circuit 23 detects that the cyclic redundancy check value in the data area of ​​the logical-to-physical address mapping table is inconsistent with the stored check value, indicating that the logical-to-physical address mapping table is corrupted, thus meeting the triggering conditions for the second-level repair action. The memory control circuit 23 then initiates the reconstruction process. First, it reads the checkpoint information most recently saved when the storage device 12 was idle from the dedicated area of ​​the memory module 122. This checkpoint records the complete logical-to-physical address mapping table state three days ago. Then, the checkpoint is loaded into memory as the basis for reconstruction. Next, the memory control circuit 23 scans all physical blocks. For each valid data page, it reads the physical-to-logical address pointer stored in its out-of-band area. For example, reading the pointer information from the data page with block number 512 indicates that the logical address corresponding to this page is 0x12345. By comparing these pointer information with the mapping relationships in the checkpoints, it was found that logical address 0x12345 in the checkpoint was mapped to block 256, while the pointer information showed that it was actually stored in block 512. The memory control circuit 23 corrected this mapping entry accordingly. Simultaneously, the memory control circuit 23 read the mapping change operations recorded in the write log for the past three days and applied the updates not yet reflected in the checkpoints to the reconstructed logical-to-physical address mapping table one by one. After scanning all physical blocks and applying the log, the memory control circuit 23 reconstructed the complete logical-to-physical address mapping table. Finally, the reconstructed logical-to-physical address mapping table was written to a new location in the memory module 122, and the normal operation of the storage device 12 was restored.

[0134] This embodiment achieves reliable reconstruction of a damaged logical-to-physical address mapping table by comprehensively utilizing multiple metadata backup information such as checkpoints, physical-to-logical address pointers, and write logs. This second-level repair action can automatically restore data accessibility when the logical-to-physical address mapping table is damaged, significantly improving the fault tolerance and data reliability of the storage system under abnormal conditions.

[0135] In one possible embodiment, graded repair is a third-level repair action; The triggering condition for the third-level repair action is: the current bit error rate obtained based on the health check results exceeds the second bit error rate threshold defined in the maintenance strategy data, and the data in the target logical area has exceeded the device's internal error correction redundancy recovery capability. The third level of repair action is to send an asynchronous event notification to the host system. The asynchronous event notification is used to notify the host system that unrecoverable data corruption has occurred.

[0136] Specifically, after completing the health check of the target logic area, the memory control circuit 23 determines whether to trigger the third-level repair action based on the obtained health check results. The third-level repair action is the highest-level alarm measure taken in the case of irrecoverable data corruption. Its purpose is to promptly notify the host system that the data has been corrupted so that the recovery process of the upper-layer application can be initiated.

[0137] The triggering conditions for the third-level repair action include two conditions that must be met simultaneously. The first triggering condition is a comparison between the current bit error rate (BER) in the health check results and the second BER threshold defined in the maintenance strategy data. The current BER refers to the ratio of the number of erroneous bits detected by the error checking and correction circuit 25 to the total number of bits read when reading data from the target logical area. The second BER threshold is a value preset by the host system 11 in the maintenance strategy data, which is usually higher than the first BER threshold and is used to indicate that the data has deteriorated to an unacceptable level. When the current BER exceeds the second BER threshold, it indicates that the data quality of the target logical area has deteriorated to a very serious level. The second triggering condition is that the data in the target logical area has exceeded the error correction redundancy recovery capability of the device (storage device 12). Error correction redundancy recovery capability refers to the maximum BER range that the error correction code algorithm used by the memory control circuit 23 can correct, and the maximum tolerance for data recovery by possible redundant copies. When the data exceeds this capacity, it means that even with the best efforts of error correction codes or by trying all available redundant copies, it is still impossible to restore the original correct data. The data has been irreversibly damaged, that is, the data is irrecoverable.

[0138] When both of the above triggering conditions are met simultaneously, the memory control circuit 23 determines that a third-level repair action needs to be performed. This third-level repair action is specifically implemented by sending an asynchronous event notification to the host system 11. The asynchronous event notification is a message proactively sent by the memory control circuit 23 to the host system 11 through an asynchronous event mechanism defined by the protocol, without requiring the host system 11 to poll. This asynchronous event notification contains at least the following information: the logical address or logical address range where the corruption occurred, indicating which specific data is inaccessible; the error type, indicating that the data corruption is irrecoverable; and the severity level, indicating the urgency of the event. Upon receiving the asynchronous event notification, the host system 11 can take corresponding recovery measures according to the application layer strategy, such as restoring data from a backup copy, terminating ongoing related operations, recording error logs for subsequent analysis, or issuing an alarm message to the user indicating that the data is corrupted.

[0139] For example, during a health check of the target logic region, i.e., logic unit one, the memory control circuit 23 obtains, through the error checking and correction circuit 25, the current bit error rate of a critical data page in the target logic region as 1.5e. -2 The second bit error rate threshold defined in the maintenance strategy data for this target logical region is 1.0e. -2 Due to the current bit error rate of 1.5e -2 It has exceeded the second bit error rate threshold of 1.0e. -2 The first trigger condition is met. Simultaneously, the error checking and correction circuit 25 attempts to correct the data page, but finds that the number of error bits exceeds the maximum correctable range, making it impossible to recover the correct data. This indicates that the data has exceeded the device's internal error correction redundancy recovery capability, thus meeting the second trigger condition. Therefore, both trigger conditions for the third-level repair action are met. The memory control circuit 23 immediately sends a high-priority asynchronous event notification to the host system 11 through the protocol-defined asynchronous event mechanism. This asynchronous event notification carries the logical address of the corrupted data as 0x12345, the error type as unrecoverable data corruption, and the severity level as urgent. Upon receiving this asynchronous event notification, the host system 11 triggers the application's data recovery process according to the file system configuration, such as reading the file data from a backup and prompting the user that some data is corrupted.

[0140] This embodiment sends asynchronous event notifications to the host system 11 to promptly inform the upper layer of the most severe and unrecoverable data corruption, thus buying valuable time for data recovery. This third-level repair action, in close cooperation with the host system 11, constructs a complete data reliability closed loop from the device layer to the application layer, ensuring that even if data cannot be recovered within the storage device 12, the upper layer still has the opportunity to take measures to reduce data loss.

[0141] In one possible embodiment, the method further includes: The health check results and the triggered graded repair actions are recorded in the dedicated log area of ​​the memory module 122; In response to a log query command from the host system, return relevant information from a dedicated log area.

[0142] Specifically, after completing each health check of the target logic region and any triggered hierarchical repair actions, the memory control circuit 23 needs to persistently store the relevant information of these events in the memory module 122 for subsequent traceability and analysis. To this end, the memory control circuit 23 records the health check results and triggered hierarchical repair actions in a dedicated log area of ​​the memory module 122.

[0143] The dedicated log area is a contiguous storage space pre-allocated within the memory module 122, specifically for storing log information. This area is created during the initialization of the storage device 12, and its size can be determined according to product design requirements. The memory control circuit 23 internally maintains a log write pointer, pointing to the currently writable position. When the log is full, a circular buffer can be used to overwrite the oldest log entry.

[0144] Each time a log entry is recorded, the memory control circuit 23 generates a log entry. This entry contains at least some of the following information: a timestamp of the event, indicating when the event occurred; an identifier for the target logical region, such as the logical cell number or logical block address range; a summary of the health check results, such as the current bit error rate, health score, and whether silent data corruption was detected; and a description of the hierarchical repair action, such as which level of repair action was triggered, whether the repair was successful or failed, and the specific physical blocks involved. For first-level repair actions, the block number marked with high refresh priority can also be recorded. For second-level repair actions, the status of the reconstruction process can be recorded. For third-level repair actions, the time when the asynchronous event notification was sent and the corrupted logical address can be recorded.

[0145] When writing log entries to the dedicated log area, the memory control circuit 23 uses an append-only method, that is, it writes a new log entry to the position pointed to by the current write pointer each time, and then updates the write pointer. To ensure the reliability of the log data, a cyclic redundancy check value can be appended to each log entry to verify the integrity of the data during reading.

[0146] For example, during a health check of logic cell one, the memory control circuit 23 detects that the current bit error rate exceeds the first bit error rate threshold, triggering a first-level repair action and marking block 1024 as a high refresh priority. After the health check is completed, the memory control circuit 23 generates a log entry containing the following: The timestamp is March 15, 2025, 14:30:25. The target logic area is logic cell one. The health check result is an average bit error rate of 1.2e. -3 The health score is 56.1, indicating no silent data corruption. The tiered repair action is Level 1, involving block number 1024, which is marked as added to the priority source block candidate list. The memory control circuit 23 writes this log entry to the position currently pointed to by the write pointer in the dedicated log area and updates the write pointer.

[0147] In this system, the memory control circuit 23 responds to a log query command from the host system 11, reads relevant information from a dedicated log area, and returns it to the host system 11. The log query command is an extended command sent by the host system 11 via a storage protocol to retrieve maintenance logs recorded internally by the storage device 12. This command may include query parameters, such as specifying the time range, logical region range, or repair level type to filter the returned relevant information.

[0148] After receiving a log query command, the memory control circuit 23 first parses the query conditions carried in the command. Then, based on the query conditions, it searches for matching log entries in the dedicated log area. For each matching log entry found, the memory control circuit 23 assembles its contents into response data according to the format defined by the protocol. The response data can contain multiple log entries, each arranged in a predefined field order. After assembly, the memory control circuit 23 returns the response data to the host system 11 through the protocol's data transmission mechanism. The log entry contents returned to the host system 11 are the relevant information requested by the command.

[0149] If no filter criteria are specified in the query conditions, or if storage device 12 supports reading the entire log, memory control circuit 23 can return a certain number of log entries back from the current write pointer. Considering that the dedicated log area may be large and a single response may not be able to transmit all data, a paging method can be used, with the host system 11 sending log query commands multiple times and specifying offsets.

[0150] For example, the debugging tool from the storage device 12 vendor sends a log query command through the host system 11, requesting all log entries that triggered tiered repair actions within the past 24 hours. This command includes a time range parameter of 24 hours prior to the current time. Upon receiving the command, the memory control circuit 23 parses the query conditions and then searches backward from the current write pointer in a dedicated log area to find all log entries with timestamps within the past 24 hours. Assume three entries that meet the conditions are found, recording two Level 1 repairs and one Level 2 repair event, respectively. The memory control circuit 23 assembles the contents of these entries into response data according to a prescribed format, including the timestamp, logical area, health check results, tiered repair action type, and relevant key information for each entry. After assembly, the response data is returned to the host system's debugging tool via protocol data transmission. Upon receiving the data, the debugging tool can display this relevant information for analysis by maintenance personnel.

[0151] This embodiment achieves full-cycle traceability of data health status by persistently recording health check results and tiered repair actions in a dedicated log area. Simultaneously, by responding to log query commands from the host system and returning relevant information, it provides data support for upper-level operations and maintenance for fault analysis and strategy optimization, further enhancing the observability and maintainability of the storage device 12.

[0152] In one possible embodiment, the inspection mode includes an adaptive mode; In adaptive mode, the check cycle and / or the first bit error rate threshold are dynamically adjusted based on the cumulative write amount of the memory control circuit 23 or the average number of erase / write cycles of the associated blocks of the target logic region.

[0153] Specifically, the memory control circuit 23 supports two inspection modes: fixed-cycle mode and adaptive mode. When the host system sets the inspection mode to adaptive mode in the maintenance strategy data, the memory control circuit 23 no longer performs health checks according to a fixed inspection cycle, but dynamically adjusts the inspection cycle and the first bit error rate threshold according to the operating status of the storage device 12.

[0154] In adaptive mode, the memory control circuit 23 dynamically adjusts based on two key parameters. The first parameter is the cumulative write volume of the memory control circuit 23, which is the total amount of data written by the host system since the storage device 12 was put into use. This parameter reflects the overall wear and tear of the storage device 12. The second parameter is the average number of erase / write cycles of the blocks associated with the target logical region, which is the average number of erase / write cycles of the blocks currently mapped to the target logical region. This parameter reflects the local wear and tear of the target logical region. The memory control circuit 23 can use one of these parameters alone or a combination of both parameters for judgment.

[0155] The specific objects of dynamic adjustment include at least one of the inspection cycle and the first bit error rate threshold. The inspection cycle refers to the time interval between two health checks; in adaptive mode, this interval is no longer fixed but changes dynamically according to the degree of wear. The first bit error rate threshold is the bit error rate threshold that triggers the first level of repair action; in adaptive mode, this threshold can also be dynamically adjusted according to the degree of wear.

[0156] The basic logic of the adjustment is that as wear and tear increases, data retention decreases, thus requiring more frequent health checks and more sensitive repair triggers. Specifically, when the cumulative write volume increases or the average number of erase / write cycles rises, the memory control circuit 23 shortens the check cycle accordingly, making health checks more frequent. Simultaneously, the first bit error rate threshold is appropriately lowered, allowing repair actions to be triggered when the bit error rate is relatively low, intervening early to prevent further data degradation. Conversely, when the storage device 12 is in its early lifespan, with low cumulative write volume or low average number of erase / write cycles, the memory control circuit 23 can extend the check cycle and appropriately increase the first bit error rate threshold to reduce unnecessary health checks and repair operations, thus minimizing the impact on the performance of the storage device 12.

[0157] The memory control circuit 23 internally maintains an adjustment mapping table or calculation formula to convert the cumulative write volume or average erase / write cycles into corresponding check cycle values ​​and a first bit error rate threshold. For example, the cumulative write volume can be divided into multiple intervals, each corresponding to a check cycle value, with higher intervals having shorter cycles. Alternatively, a continuous function can be used, where the check cycle decreases linearly or non-linearly as the average erase / write cycles increase. Similarly, the first bit error rate threshold can be adjusted in a segmented or continuous manner, causing the threshold to decrease with increasing wear.

[0158] For example, when the storage device 12 leaves the factory, the host system 11 configures an adaptive inspection mode for the target logical area, i.e., logical unit one, with an initial inspection cycle of seven days and an initial first bit error rate threshold of 1.0e. -3 After one year of operation, storage device 12 has accumulated 100TB of writes, and the average write / erase cycles of the associated block of logic unit 1 have reached 3000. Based on internally preset adjustment rules, memory control circuit 23 adjusts the check cycle corresponding to the accumulated 100TB of writes to five days, and adjusts the first bit error rate threshold corresponding to the average write / erase cycles of 3000 to 0.8e. -3 The memory control circuit 23, considering both parameters and taking the more stringent adjustment result, ultimately sets the inspection cycle to five days and the first bit error rate threshold to 0.8e. -3 Subsequently, health checks on logic unit 1 will be performed according to the new check cycle and the first bit error rate threshold. As storage device 12 continues to age, when the cumulative write volume reaches 200TB and the average write / erase cycles reach 4000, the memory control circuit 23 further shortens the check cycle to three days and reduces the first bit error rate threshold to 0.6e. -3 .

[0159] This embodiment employs an adaptive adjustment mechanism to match the intensity of health checks with the actual wear and tear on the storage device 12, reducing unnecessary overhead in the early stages of its lifespan and strengthening protection in the later stages. This dynamic adjustment strategy effectively balances performance overhead and data reliability, extending the overall service quality of the storage device 12 throughout its lifespan.

[0160] In one possible embodiment, the method further includes: Acquire temperature data from memory control circuit 23; Based on temperature data, the frequency of performing health checks on logical regions is dynamically adjusted.

[0161] Specifically, the memory control circuit 23 continuously acquires its own temperature data during operation and dynamically adjusts the frequency of health checks on the logic area based on the temperature data. Temperature is a crucial factor affecting the data retention capacity of flash memory; higher temperatures accelerate charge leakage, leading to a shorter data retention time and an increased risk of higher error rates. Therefore, incorporating temperature data into the health check scheduling decision can more effectively address the impact of temperature changes on data reliability.

[0162] The memory control circuit 23 acquires temperature data in real time via an internally integrated temperature sensor. The memory control circuit 23 typically contains one or more temperature sensors that can collect the chip's current temperature at a fixed frequency and store the temperature data in a register for firmware retrieval. The accuracy and sampling frequency of the temperature data can be determined according to the product design, for example, sampling once per second with an accuracy of ±1 degree Celsius. Alternatively, the memory control circuit 23 can acquire temperature data periodically sent by the host system, as a supplement or replacement for the internal sensor data.

[0163] The frequency of health checks is dynamically adjusted based on temperature data. The basic logic is that when temperature rises, data retention decreases more rapidly, thus requiring a higher frequency of health checks to promptly detect and correct potential data degradation. Conversely, when temperature falls, data retention remains relatively stable, allowing for a reduction in the frequency of health checks to minimize the impact of unnecessary background operations on performance.

[0164] There are several ways to implement dynamic adjustment. One approach is to set multiple temperature thresholds, with each threshold range corresponding to a frequency adjustment coefficient for health checks. For example, when the temperature is below 40 degrees Celsius, the base frequency is used; when the temperature is between 40 and 60 degrees Celsius, the frequency is increased to twice the base frequency; and when the temperature exceeds 60 degrees Celsius, the frequency is increased to four times the base frequency. Another approach is to use a continuous function to calculate the frequency adjustment coefficient linearly or non-linearly based on the difference between the current temperature and the reference temperature, and then multiply it by the base frequency to obtain the adjusted actual execution frequency.

[0165] When adjusting the frequency of health checks, the memory control circuit 23 can make uniform adjustments for all logic regions or differentiate adjustments based on the characteristics of different logic regions. For example, for logic regions of higher importance, a more aggressive frequency increase can be used when temperature data rises. The adjusted frequency will be applied to subsequent background health check task scheduling, directly affecting the time interval between two health checks.

[0166] For example, a memory control circuit 23 integrates a temperature sensor that samples temperature data every five seconds. Under basic settings, health checks on the logic area are performed every twelve hours. The memory control circuit 23 dynamically adjusts to three temperature ranges. When the temperature is below 40 degrees Celsius, the health check frequency remains at the base frequency of once every twelve hours. When the temperature is between 40 and 55 degrees Celsius, the health check frequency increases to once every six hours. When the temperature exceeds 55 degrees Celsius, the health check frequency further increases to once every three hours. During a certain operation, the memory control circuit 23 reads the current temperature as 48 degrees Celsius, which is in the second range, and therefore adjusts the health check frequency to once every six hours. The background task performs the health check according to the adjusted frequency. Several hours later, the load on the storage device 12 decreases, and the temperature drops to 35 degrees Celsius. The memory control circuit 23 detects the temperature change and restores the health check frequency to once every twelve hours.

[0167] This embodiment introduces temperature data as a basis for dynamically adjusting the frequency of health checks, enabling the memory control circuit 23 to sense the impact of environmental changes on data retention and respond promptly. This temperature-sensing adaptive adjustment mechanism further enhances the proactiveness of data reliability maintenance and provides stronger protection under harsh conditions such as high temperatures.

[0168] In one possible embodiment, performing a background health check on the target logical region includes: A single health check task targeting a target logical region is broken down into multiple check subtasks; each subtask corresponds to a sub-region within the target logical region. Execute multiple check sub-tasks in batches during idle periods.

[0169] Specifically, when performing a background health check on the target logic region, the memory control circuit 23, in order to avoid excessive system resource consumption by a single health check task leading to fluctuations in front-end input / output performance, splits the single health check task for the target logic region into multiple check sub-tasks. Each check sub-task corresponds to a sub-region within the target logic region.

[0170] There are several ways to divide subregions. One method is to divide them according to logical address ranges, that is, to evenly divide the continuous interval from the start logical block address to the end logical block address of the target logical region into several segments, each segment being a subregion. Another method is to divide them according to physical storage structure, such as grouping multiple flash memory blocks mapped to a target logical region according to the number of blocks, with each group being a subregion. The size of the subregions can be determined according to the design requirements of the storage device 12, for example, each subregion may contain a certain number of logical block addresses or a certain number of physical blocks. Dividing the subregions too finely will increase task management overhead, while dividing them too coarsely will fail to effectively distribute the load; a balance needs to be struck between the two.

[0171] When splitting a single health check task, the memory control circuit 23 needs to record the status information of each check subtask, including the sub-region identifier, check progress, and whether it has been completed. This information can be stored in the random access memory of the memory control circuit 23 to form a check task status table. Only when all check subtasks are completed is the single health check task for the target logical region considered fully completed. In the event of a power outage or other abnormality, the memory control circuit 23 can restore unfinished check subtasks based on the recorded status information after a restart, ensuring the integrity of the check.

[0172] For example, the target logical region is logical unit one, which contains one million logical blocks with addresses from 0 to 1,000,000. The memory control circuit 23 plans to perform a single health check task involving a global deep scan of this target logical region. However, to avoid prolonged occupation of system resources, it decides to split this single health check task into ten sub-tasks. Dividing the logical address range evenly, each sub-task corresponds to one hundred thousand consecutive logical block addresses; that is, the first sub-task corresponds to logical block addresses 0 to 99,999, the second sub-task corresponds to addresses 100,000 to 199,999, and so on. The memory control circuit 23 creates a task status table in memory, recording the identifiers and initial states of these ten sub-tasks as pending inspection.

[0173] Specifically, the memory control circuit 23 schedules the split, multiple check subtasks to be executed in batches during idle periods. An idle period refers to a time when the memory control circuit 23 processes fewer input / output requests from the host system 11 and has sufficient idle resources available for background operations. The memory control circuit 23 determines whether it is currently in an idle period by monitoring factors such as command queue depth, data throughput, or the proportion of processor idle time.

[0174] When the storage device 12 is detected to be in an idle period, the memory control circuit 23 selects one or more inspection subtasks from the inspection task status table for execution. The selection strategy can be a round-robin approach, i.e., executing sequentially; or a priority approach, such as prioritizing the inspection subtasks corresponding to higher-risk sub-regions. When executing each inspection subtask, the memory control circuit 23 performs a health check on all data pages within that sub-region, including data integrity verification and physical status acquisition, and records the check results.

[0175] If the storage device 12 suddenly becomes busy during the execution of a certain check subtask, i.e., exits the idle period, the memory control circuit 23 can pause the current check subtask, save the check progress, and resume execution from the breakpoint when the idle period returns. This method can minimize the impact of background health checks on front-end performance. After all check subtasks have been completed, the memory control circuit 23 summarizes the check results of each check subtask to obtain the complete health check result of the target logical region, and updates the dynamic metadata of the target logical region accordingly, including the last check timestamp and health score.

[0176] For example, the memory control circuit 23 records ten check subtasks to be checked in memory. During a certain period, the host system 11 has no input / output requests, and the memory control circuit 23 detects that the command queue is empty, determining that the storage device 12 is currently in an idle period. Therefore, it selects the first check subtask from the check task status table to begin execution. The memory control circuit 23 performs health checks on all data pages within the logical block address range of 0 to 99999, including reading data, calculating checksums, and obtaining the bit error rate. After completing the first check subtask, the memory control circuit 23 updates the check task status table, marking the check subtask as completed. At this time, the storage device 12 is still in an idle period, and the memory control circuit 23 continues to execute the second check subtask. When the third check subtask is executed, the host system 11 initiates a batch of read requests, the command queue begins to accumulate, the memory control circuit 23 detects an increase in the load on the storage device 12, determines that it is exiting the idle period, immediately pauses the current check subtask, and saves the check progress of the third check subtask, such as which logical block address has been checked. When storage device 12 enters an idle period again, memory control circuit 23 resumes execution of the remaining part of the third check subtask from the saved breakpoint. After multiple idle periods of batch execution, all ten check subtasks are completed. Memory control circuit 23 summarizes the check results of each check subtask, generates a complete health check result for logic unit one, updates the last check timestamp to the current time, recalculates the health score based on the summarized results, and updates it to the dynamic metadata.

[0177] This embodiment effectively mitigates the impact of background checks on front-end performance by breaking down a single health check task into multiple sub-tasks and executing them in batches during idle periods. This segmentation and recovery mechanism ensures the integrity of the health check while minimizing the impact on the host system's input / output performance, achieving a good balance between reliability and performance.

[0178] In one possible embodiment, see Figure 11 , Figure 11 This is another flowchart illustrating the background health check process provided in this application embodiment, including the following steps: S1101. Randomly select a physical page from multiple physical pages corresponding to the target logical region, and perform a background local quick health check on the selected physical page. S1102. When a local rapid health check detects an abnormality or the set check cycle is reached, a background global deep health check is performed on all physical pages of the target logical region. S1103. When no abnormalities are found in the local rapid health check, the results of the local rapid health check shall be taken as the health check results.

[0179] In step S1101, when the memory control circuit 23 performs a background health check on the target logic region, in order to balance the check efficiency and the load on the storage device 12, it first adopts a local fast health check mode. The core of this mode is to randomly select a portion of physical pages from multiple physical pages corresponding to the target logic region as samples, and perform a background local fast health check only on these selected physical pages.

[0180] The process of randomly selecting physical pages needs to ensure the representativeness of the samples. The memory control circuit 23 can generate physical page indices using a pseudo-random number algorithm and uniformly sample from all physical pages currently mapped to the target logical region. The number of samples can be preset, for example, 16 or 32 physical pages can be sampled for each local rapid health check, or it can be dynamically adjusted according to the size of the target logical region, for example, by determining the sample size as one-thousandth of the total number of physical pages in the region. The purpose of random selection is to quickly perceive the health status of the entire target logical region with fewer check operations and to promptly detect potential problems.

[0181] A background partial rapid health check is performed on the selected physical pages. Its content is the same as a regular health check, including data integrity verification and physical status acquisition. Data integrity verification involves reading the physical page data and recalculating the checksum according to the verification algorithm specified in the target logical area maintenance strategy data. This recalculated checksum is compared with the original stored checksum to determine if there is any silent data corruption. Physical status acquisition involves obtaining the current bit error rate of the physical page through the error checking and correction circuit 25 and recording relevant physical parameters. Because the number of physical pages checked is small, the execution time of the background partial rapid health check is short, and its impact on the performance of the storage device 12 is minimal; therefore, it can be performed relatively frequently.

[0182] For example, the target logical region is logical unit one, which is currently mapped to 1024 physical pages. The memory control circuit 23 adopts a local fast health check mode, randomly sampling 16 physical pages each time. During a certain idle period, the memory control circuit 23 generates 16 random numbers as physical page indices, such as physical pages 45, 127, 203, etc., and then reads these 16 physical pages one by one, calculates the CRC32 check value and compares it with the original value stored in the out-of-band area. At the same time, the error checking and correction circuit 25 obtains the bit error rate of each physical page. The check values ​​of all 16 physical pages are consistent, and the average bit error rate is 2.1e. -6 No abnormalities were found.

[0183] In step S1102, although the local rapid health check is efficient, it can only reflect the condition of the sample physical pages and cannot guarantee full coverage of the entire target logical region. Therefore, when certain conditions are met, the memory control circuit 23 needs to trigger a background global deep health check to perform a complete health check on all physical pages of the target logical region.

[0184] There are two conditions that trigger a global deep health check in the backend; either one will suffice. The first condition is that a local rapid health check in the backend detects an anomaly. Anomalies can manifest in various ways, such as inconsistencies in data integrity verification on a checked physical page (indicating silent data corruption); a physical page's current error rate exceeding a preset warning threshold; or a significant drop in the average health score calculated based on sample physical pages. These anomaly signals indicate potential problems in the entire target logical area, requiring a comprehensive investigation. The second condition is the arrival of the set check cycle. Even if the local rapid health check does not detect any anomalies, a comprehensive check is required when the time since the last global deep health check exceeds the check cycle defined in the maintenance strategy data, ensuring long-term data reliability.

[0185] The background global deep health check is performed by verifying data integrity and collecting physical status data for each physical page currently mapped to the target logical region. This is equivalent to performing the same operation as a local quick health check on every physical page within the target logical region, ultimately obtaining complete health data for the entire target logical region. Due to the large amount of data to be checked, the background global deep health check is usually scheduled during the storage device's 12-second idle period, or executed in blocks and batches to minimize the impact on frontend performance.

[0186] For example, continuing from the scenario in step H1, during a background local rapid health check, the memory control circuit 23 randomly selected 16 physical pages, and the CRC32 check value of one physical page was inconsistent with the original value, indicating that there was silent data corruption, thus meeting the first trigger condition. The memory control circuit 23 immediately decided to trigger a background global deep health check on the target logical region, i.e., logical unit one. During the subsequent idle period of the storage device 12, the memory control circuit 23 read, calculated the check value, and collected the bit error rate of all 1024 physical pages mapped to logical unit one. Ultimately, it was found that in addition to the damaged physical page found in the local rapid health check, there were two other physical pages with high bit error rates but not exceeding the error correction capability, and the data of one physical page was no longer correctable. The background global deep health check obtained the complete health status of the target logical region.

[0187] In step S1103, when the background local quick health check does not find any abnormalities, the memory control circuit 23 does not need to immediately perform a background global deep health check. Instead, it directly uses the result of the current background local quick health check as the current health check result of the target logical region. This means that in most cases, the health status update of the target logical region can be completed by a lightweight background local quick health check, and the more expensive background global deep health check is only initiated when necessary.

[0188] The health check results of the background partial rapid health check include various information obtained during the check, such as the average bit error rate of the sample physical pages, the amount of silent data corruption found in the sample physical pages, and the health score of the sample physical pages. Based on this sample information, the memory control circuit 23 can estimate the health status of the entire target logical region and update the health score in the dynamic metadata. For example, the average bit error rate of the sample physical pages can be used as a representative value of the current bit error rate of the target logical region, and the number of anomalies found in the sample physical pages can be used as a reference indicator of the health status of the target logical region. Although the health check results of the background partial rapid health check are not as accurate as those of the background global deep health check, they are sufficient for daily health monitoring and trend analysis.

[0189] The advantage of this approach is that it significantly reduces the overall cost of health checks. In most cases, data storage is stable, and a quick local health check in the background is sufficient to confirm the health of the target logical area. A deep global health check in the background is only performed when a real problem occurs or when a full check is performed according to the prescribed check cycle, thus achieving a good balance between reliability and performance.

[0190] For example, in a background partial rapid health check, the memory control circuit 23 checks 16 random physical pages of logic unit one. The data integrity checks of all physical pages are consistent, and the average bit error rate is 2.0e. -6 The status is within the normal range, and no abnormalities were found. Since the set seven-day check cycle has not yet been reached since the last global deep health check, no global deep health check will be triggered. The memory control circuit 23 directly uses the health check result of this local rapid health check as the health check result, calculates a new health score (e.g., 98 points) based on the average bit error rate of the 16 sample physical pages, and updates it to the dynamic metadata. Subsequent health checks and scheduling will continue based on this updated status.

[0191] This technical solution achieves a balance between efficiency and accuracy in health checks through a two-level inspection mechanism that combines rapid local health checks in the background with deep global health checks. In most cases, it quickly detects the health status of the target logical region with extremely low overhead, performing a comprehensive check only when necessary, effectively reducing the overall impact of background health checks on the performance of the storage device 12.

[0192] However, Figures 6 to 11 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 6 to 11 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 6 to 11 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0193] In summary, the memory control method and storage device proposed in the embodiments of this application introduce a mechanism in the memory control circuit 23 where the host system 11 issues maintenance strategies. This allows the host system 11 to flexibly configure differentiated reliability maintenance strategies for specified logical regions based on the importance of different data, including parameters such as inspection mode, inspection cycle, bit error rate threshold, verification algorithm, and priority. The memory control circuit 23 updates the critical data maintenance table according to the received maintenance strategy, dynamically selects the target logical region to be inspected, performs background health checks, and then triggers graded repair actions based on the inspection results. This approach constructs a closed-loop management process from strategy configuration and health monitoring to autonomous repair, realizing programmable and proactive prevention of storage reliability. On the one hand, the host system 11 can define data protection levels according to application semantics, solving the problem of passive response and lack of customized maintenance in the prior art for the storage device 12; on the other hand, autonomously performing health checks and graded repairs in the background can promptly detect and handle data degradation trends, effectively reducing the risk of silent data corruption and irreversible data loss. Meanwhile, the dynamic selection mechanism and hierarchical repair strategy optimize resource scheduling and reduce the impact on front-end performance, thereby significantly improving the reliability, maintainability and data security of storage device 12.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A memory control method, characterized by, Applied to storage devices including memory modules and memory controllers; The method includes: The system receives a maintenance policy setting command from the host system. The maintenance policy setting command is used to set maintenance policy data for a specified logical area. The maintenance policy setting command includes: type information, identity information, and maintenance policy data of the specified logical area. The maintenance policy data includes: inspection mode, inspection cycle, first bit error rate threshold, second bit error rate threshold, data integrity verification algorithm identifier, and priority. According to the maintenance strategy setting command, update the maintenance record in the critical data maintenance table. The maintenance record includes maintenance strategy data and dynamic metadata for a logical region. The dynamic metadata includes: last check timestamp, cumulative number of reads, block information currently associated with the logical region, and risk coefficient benchmark. Based on the dynamic metadata of each logical region in the key data maintenance table, a target logical region to be checked is dynamically selected; a background health check is performed on the target logical region, and the dynamic metadata of the target logical region is updated based on the health check results; and a background health check is performed on the target logical region. Based on the health check results, a tiered repair action is triggered for the target logical region. The background health check of the target logical region includes: uniformly selecting physical pages from all currently mapped physical pages of the target logical region using a pseudo-random number algorithm, with the number of selected pages dynamically adjusted according to the size of the target logical region; performing a local rapid health check on the selected physical pages; when the local rapid health check detects an anomaly or a set check cycle is reached, performing a global deep health check on all physical pages of the target logical region; when the local rapid health check does not detect an anomaly, the check results are shared. As a result of the health check; the graded repair action is the first-level repair action; the triggering condition for the first-level repair action is: the current bit error rate obtained based on the health check result exceeds the first bit error rate threshold defined in the maintenance strategy data, and the data of the target logical region is within the error-correctable range; the first-level repair action is: marking the block where the target logical region is located as a high refresh priority; the inspection mode of the health check includes an adaptive mode; in the adaptive mode, the inspection cycle of the health check and / or the first bit error rate threshold are dynamically adjusted according to the cumulative write volume of the memory controller or the average number of erase and write cycles of the block associated with the target logical region; Blocks marked as high refresh priority are added to the priority source block candidate list for the garbage collection process; During the garbage collection process, when collecting blocks from the priority source block candidate list, the process of moving the valid data in the block completes the reading, error correction, and writing of the valid data to a new location.

2. The memory control method according to claim 1, wherein, The health score of the logical region is calculated by weighting at least two of the following factors: The current bit error rate of the logical region, the number of erase / write operations of the associated blocks, the data residence time of the associated blocks, and the cumulative number of reads are all factors whose weights are either pre-configured or adaptively adjusted.

3. The memory control method of claim 1, wherein, Also includes: When a storage device is detected to be under high load, reduce the frequency of health checks or pause health checks. Increase the frequency of health checks when the storage device is under low load.

4. The memory control method of claim 1, wherein, The background health check performed on the target logical region includes: Read the data of the target logical region and calculate the first verification value using the verification algorithm specified in the maintenance strategy data of the target logical region; The first check value is compared with the pre-stored second check value, and the target logical area is checked for silent data corruption based on the comparison result.

5. The memory control method of claim 1, wherein, The graded repair action is the second-level repair action; The trigger condition for the second-level repair action is: the health check results indicate that the logical-to-physical address mapping table has been damaged; The second-level repair action is to rebuild the logical-to-physical address mapping table using the metadata backup information stored in the memory module.

6. The memory control method of claim 1, wherein, The graded repair is the third-level repair action; The triggering condition for the third-level repair action is: the current bit error rate obtained based on the health check results exceeds the second bit error rate threshold defined in the maintenance strategy data, and the data in the target logical area has exceeded the error correction redundancy recovery capability of the device. The third-level repair action is to send an asynchronous event notification to the host system, which is used to notify the host system that unrecoverable data corruption has occurred.

7. The memory control method of claim 1, wherein, The method further includes: The health check results and the triggered graded repair actions are recorded in the dedicated log area of ​​the memory module; In response to a log query command from the host system, relevant information in the dedicated log area is returned.

8. The memory control method of claim 1, wherein, The method further includes: Obtain the temperature data of the memory controller; Based on the temperature data, the frequency of performing health checks on the logical region is dynamically adjusted.

9. The memory control method of claim 1, wherein, The background health check performed on the target logical region includes: A single health check task targeting the target logical region is broken down into multiple check subtasks; each subtask corresponds to a sub-region within the target logical region. The multiple check subtasks are executed in batches during the idle periods of the storage device.

10. A storage device, characterized in that, The storage device includes: A connection interface for electrically connecting to a host computer; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple physical pages; and The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 9.

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