Resolution enhanced time domain two-step analog-to-digital conversion system

Abstract

A resolution-enhanced time-domain two-step analog-to-digital converter system includes: a voltage-to-time converter, a time-to-voltage converter, a time-to-digital converter, a capacitor-to-digital converter array, a comparator, a latch, and a SAR logic module. This invention multiplexes the time-to-digital converter within a voltage-time mixed-domain successive approximation register analog-to-digital converter. After coarse quantization in the time domain, the time-to-digital converter is multiplexed to quantize the comparator decision time. An additional bit of precision is obtained through the relationship between the decision time and the input voltage, thereby improving resolution without significantly increasing power consumption and hardware area, and significantly reducing the probability of flickering codes or conversion failures caused by metastability.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically a resolution-enhanced time-domain two-step analog-to-digital conversion system. Background Technology

[0002] Existing mixed-domain analog-to-digital converters (ADCs) perform coarse quantization in the time domain using voltage-to-time converters (VTCs) and time-to-digital converters (TDCs), followed by fine quantization using a successive approximation register-type ADC (SAR ADC) in the voltage domain. However, in this architecture, the time-domain ADC remains idle for a considerable period after completing its quantization task, resulting in low hardware utilization. SAR ADC comparators are prone to metastability when the input voltage difference is extremely small, leading to prolonged decision time; exceeding the preset clock cycle can cause serious conversion errors. Increasing the regenerative current or extending the comparison time will further reduce power consumption or speed. Existing multiplexing techniques, which process the time interval and voltage intensity signals in a time-division manner, cannot solve the performance bottleneck caused by the dynamic behavior of the comparator. Summary of the Invention

[0003] This invention addresses the shortcomings of existing hybrid-domain SAR ADC technology, such as low TDC hardware utilization, conversion errors and speed limitations caused by comparator metastability, and the inability to perform phased task switching and functional expansion of the same module within the same conversion cycle. It proposes a resolution-enhanced time-domain two-step analog-to-digital converter system. This system multiplexes the time-to-digital converter within the voltage-time hybrid-domain successive approximation register analog-to-digital converter. After coarse quantization in the time domain, the TDC is multiplexed to quantize the comparator decision time. An additional bit of precision is obtained by analyzing the relationship between the decision time and the input voltage. This improves resolution without significantly increasing power consumption and hardware area, and significantly reduces the probability of flicker codes or conversion failures caused by metastability.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a resolution-enhanced time-domain two-step analog-to-digital converter system, comprising: a voltage-to-time converter, a time-to-voltage converter, a time-to-digital converter, a capacitor-to-analog converter array, a comparator, a latch, and a SAR logic module. The voltage-to-time converter, the time-to-voltage converter, and the multiplexed time-to-digital converter constitute a 4-bit coarse-quantized time-domain ADC, while the capacitor-to-analog converter array, the comparator, and the SAR logic module constitute a 5-bit fine-quantized SAR with one bit of redundancy. The ADC (Digital-to-Time Converter) converts the input differential signal into a time difference signal through a pair of pseudo-differential VTC pairs. The time-to-voltage converter converts the time difference signal back into a voltage signal and outputs it to the capacitor digital-to-analog converter array. Based on the time difference information output by the voltage-to-time converter, the time-to-digital converter applies an integer multiple unit delay to the earlier signal, causing the rising edges of the two input signals to gradually approach each other in time, resulting in a coarse quantization digital code result of the high 4 bits. The capacitor digital-to-analog converter array generates a successive approximation feedback voltage by switching the voltage of the split capacitor bottom plate, based on the voltage acquired from the time-to-voltage converter and the control code information provided by the TDC module and the SAR logic module. The comparator compares this feedback voltage with the sampled voltage information from the time-to-voltage converter to obtain the quantization result of the current bit. The SAR logic module updates its internal registers based on the comparator output and generates the capacitor digital-to-analog converter array control code for the next cycle and generates the TDC operating mode selection signal SL. The latch is used to temporarily latch the 4-bit coarse quantization output result generated by the TDC coarse quantization. After the time-to-voltage converter completes charging of the capacitor digital-to-analog converter array, the voltage is applied to the high 4 bits of the capacitor bottom plate.

[0006] Technical effect

[0007] This invention addresses the metastability issue in the comparator quantization process by multiplexing the time-to-digital converter (TDC) and utilizing the TDC's idle time to quantize the comparison time of the SAR comparator. This improves hardware utilization while simultaneously monitoring the comparison time and enhancing the ADC's resolution. It avoids the increased power consumption caused by adding comparator regeneration current in traditional solutions and overcomes the speed loss resulting from extending the clock cycle, achieving a balance between improved accuracy and hardware efficiency. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of the present invention;

[0009] Figure 2 This is a schematic diagram of the ADC timing.

[0010] Figure 3 A schematic diagram of the TDC architecture for reuse;

[0011] Figure 4 To quantify the flowchart;

[0012] Figure 5 The circuit that generates the SL signal for selecting the TDC operating mode;

[0013] Figure 6 The result of the Fast Fourier Transform of the ADC output with Nyquist input. Detailed Implementation

[0014] like Figure 1 As shown in this embodiment, a resolution-enhanced time-domain two-step analog-to-digital converter system includes: a voltage-to-time converter, a time-to-voltage converter, a time-to-digital converter, a capacitor-to-digital converter array, a comparator, a latch, and a SAR logic module. The voltage-to-time converter, the time-to-voltage converter, and the multiplexed time-to-digital converter constitute a 4-bit coarse-quantized time-domain ADC. The capacitor-to-digital converter array, the comparator, and the SAR logic module constitute a 5-bit fine-quantized SAR with 1-bit redundancy. The ADC (Digital-to-Time Converter) converts the input differential signal into a time difference signal through a pair of pseudo-differential VTC pairs. The time-to-voltage converter converts the time difference signal back into a voltage signal and outputs it to the capacitor digital-to-analog converter array. Based on the time difference information output by the voltage-to-time converter, the time-to-digital converter applies an integer multiple unit delay to the earlier signal, causing the rising edges of the two input signals to gradually approach each other in time, resulting in a coarse quantization digital code result of the high 4 bits. The capacitor digital-to-analog converter array generates a successive approximation feedback voltage by switching the voltage of the split capacitor bottom plate, based on the voltage acquired from the time-to-voltage converter and the control code information provided by the TDC module and the SAR logic module. The comparator compares this feedback voltage with the sampled voltage information from the time-to-voltage converter to obtain the quantization result of the current bit. The SAR logic module updates its internal registers based on the comparator output and generates the capacitor digital-to-analog converter array control code for the next cycle and generates the TDC operating mode selection signal SL. The latch is used to temporarily latch the 4-bit coarse quantization output result generated by the TDC coarse quantization. After the time-to-voltage converter completes charging of the capacitor digital-to-analog converter array, the voltage is applied to the high 4 bits of the capacitor bottom plate.

[0015] like Figure 2 The diagram shows the quantization timing of the two-step time-domain analog-to-digital converter system described in this embodiment. VT, TD, and TV represent the processes of converting the input signal from a voltage signal to a time signal, from a time signal to a digital signal, and from a time signal to a voltage signal, respectively. The coarse quantization process of the time-domain ADC consists of these three processes. When time-domain quantization ends, the SARStart indicator signal goes high, and SAR ADC quantization begins.

[0016] Compared to existing hybrid-domain ADCs where the time-to-digital converter (TDC) is idle during SAR quantization, this embodiment reactivates the idle TDC during SAR quantization, achieving higher utilization of the hardware circuitry.

[0017] like Figure 1 As shown, the voltage-time converter is a constant current source type VTC structure composed of a pair of pseudo-differential structures. The voltage-time converter charges the sampling capacitor through the input voltage signal. After sampling, the sampling switch is opened and the constant current source begins to discharge. Since the sampled input voltages are different, the voltage on the upper plate of the capacitor flips at different times through the inverter at the back end, thereby converting the input voltage difference signal into a time difference signal.

[0018] The time-to-voltage converter employs a current integrator structure composed of PMOS transistors. Upon reset, the topmost PMOS transistor in the time-to-voltage converter charges the capacitor-to-digital converter array to a high level. During operation, the converter receives a time difference signal from the voltage-to-time converter and controls a switch to discharge the integrating capacitors with a constant current, linearly converting the time interval back into a differential voltage signal. Its conversion gain is calibrated by adjusting the discharge current to ensure it matches the quantization step size of the time-to-digital converter in both operating modes.

[0019] The capacitor-to-digital converter array employs a split capacitor switching strategy to ensure the comparator comparison time is stable, so that the common-mode voltage remains basically constant during the switching process of the capacitor-to-digital converter, thereby eliminating the impact of common-mode voltage fluctuations on the comparator decision time and ensuring the accuracy of subsequent quantization based on decision time.

[0020] The comparator employs a strong-arm latch structure, where the decision time from triggering to the valid output is negatively correlated with the input differential voltage. This is used to detect subthresholds and extract additional resolution information from metastable regions.

[0021] like Figure 3As shown, the multiplexed time-to-digital converter adopts a SAR TDC structure, specifically including: OR gates and AND gates, delay time units, four comparators, and multiplexers. The OR and AND gates are connected to the input signals of the current stage to distinguish between earlier and later input signals. The delay time units are connected after the AND and OR gates of each stage with weights of 4, 2, and 1, respectively, to apply a delay to the distinguished signals, completing the successive approximation logic. The four comparators are connected to the external input port of the TDC and the signals distinguished by the AND and OR gates and then delayed, to determine whether the time order of the signals changes after the delay is applied. The two multiplexers are respectively connected to the two quantization signals of the TDC, controlled by the TDC operating mode selection signal SL. When SL is high, the multiplexer receives the external determination signal Valid and clock signal CLKc as the decision time for the TDC input signal quantization comparator; when SL is low, the main path of the multiplexer is turned on, used to quantize the leftmost VTC input T. IP and T IN Signal.

[0022] like Figure 5 As shown, the SAR logic module includes a D flip-flop for generating the TDC operating mode selection signal SL. This D flip-flop is controlled by the SARStart signal: at the start of periodic quantization, the reset signal RST resets the SL port of the D flip-flop to 0; when the SARStart signal goes high, the SL port of the D flip-flop is set to 1, indicating whether the TDC is operating in coarse quantization mode or comparator time monitoring mode. This SL port is connected to the time-to-digital converter (TD-SCDMA) to control the multiplexer inside the TDC: when the TDC operating mode selection signal SL is low, the TDC operates in coarse quantization mode, receiving the time difference signal from the VTC output; when SL is high, the multiplexer switches to receiving the comparator decision time signal; when the TDC operating mode selection signal SL is pulled high, the TDC enters the comparator decision time monitoring mode, and the input becomes... Figure 3 The clock signal CLKc and the determination signal Valid are used in the comparison. When the clock signal CLKc goes high, it indicates that the comparator has started comparing. When the determination signal Valid goes high, it indicates that the comparison is complete. The TDC quantizes the time difference between the rising edges of the two signals and compares it with the quantization time corresponding to the set threshold voltage to determine whether it has entered the metastable state. At the same time, this voltage is also used to measure the amount of additional resolution weight extracted from the metastable state.

[0023] like Figure 4 As shown, this embodiment relates to a two-step time-domain analog-to-digital conversion method based on the above system, including:

[0024] Step 1: At the beginning of the quantization cycle, the TDC working mode selection signal SL is at a low level, and the TDC switches back to coarse quantization mode by default.

[0025] Step 2, Time-domain ADC coarse quantization, specifically includes:

[0026] 2.1 The VTC receives the ADC input signal and quantizes it into a time-domain signal T. IP and T IN。

[0027] 2.2 Time-domain signal T IP and T IN The signal is passed to a time-to-voltage converter, which converts the time-domain signal back to the voltage domain and stores it in a capacitor-to-digital converter array for subsequent quantization.

[0028] 2.3 Simultaneous Time Domain Signal T IP and T IN The signal is passed to a time-to-digital converter, which differentially quantizes the time signal into the high 4 bits of the output.

[0029] 2.4 Once the time-domain quantization is complete, the SARstart signal goes high, signifying the start of SAR quantization. Simultaneously, the TDC operating mode selection signal SL goes high, and the TDC enters the comparison time monitoring mode.

[0030] Step 3, SAR ADC fine quantization, specifically including:

[0031] 3.1 The strong arm comparator is used for comparison, and TDC quantizes the comparison time of the comparator.

[0032] 3.2 Observe the quantification results of the comparison time using the reused TDC.

[0033] 3.3 If the comparison time exceeds the threshold time, it proves that the input signal is close enough, and the SAR partial quantization ends, and the SAR partial quantization result is directly output.

[0034] 3.4 If the comparison time is less than the threshold time and the number of comparisons is less than 5, the SAR logic section changes the capacitor-to-digital converter array according to the output result of the strong arm comparator and starts the next comparison.

[0035] 3.5 When the comparison time exceeds the threshold or the number of comparisons reaches 5, the SAR partial quantization is completed.

[0036] Step 4: The ADC outputs a complete 9-bit quantization result, and all modules are reset. The quantization cycle is now complete.

[0037] When the quantization result indicates that the threshold is exceeded, it means that the comparator input voltage is sufficiently close. At this point, quantization in the SAR section stops, and the remaining output bits are directly filled based on the current comparison result. Simultaneously, an additional resolution based on metastability is obtained from the quantization result. If the threshold is not exceeded in this quantization, the SAR section performs normal 5-bit fine quantization, and the additional output remains in its default state.

[0038] Through practical application experiments, in the Cadence Virtuoso software environment, the resolution-enhanced time-domain two-step analog-to-digital converter (ADC) system of this invention was instantaneously simulated. The ADC system worked normally and correctly completed quantization. The TDC multiplexing technology functioned as expected. The overall performance of the ADC was verified under 40nm CMOS process, and the ADC simulation results are as follows: Figure 6 As shown, at the Nyquist input frequency, the ADC's signal-to-noise ratio (SNDR) is 51.97 dB, its spurious-free dynamic range (SFDR) is 63.58 dB, and its total power consumption is 0.94 mW. Table 1 shows a comparison of this invention with other research results.

[0039] Table 1 Performance Summary and Comparison with Existing Work

[0040] The JSSC2023 in the table uses the technology described in "A 6-bit 0.81-mW 700-MS / s SAR ADC With Sparkle-CodeCorrection, Resolution Enhancement, and Background Window Width Calibration"; the CICC2024 uses the technology described in "An 8b 1GS / s SAR ADC with Metastability-BasedResolution / Speed ​​Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input".

[0041] Compared with existing technologies, this invention solves the metastability problem and achieves an additional 1 bit of resolution while maintaining low power consumption and requiring almost no additional hardware, thus improving the quality factor.

[0042] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A resolution-enhanced time-domain two-step analog-to-digital conversion system, characterized in that, include: The system comprises a voltage-to-time converter, a time-to-voltage converter, a time-to-digital converter, a capacitor-to-digital converter array, a comparator, a latch, and a SAR logic module. Specifically, the voltage-to-time converter, the time-to-voltage converter, and the multiplexed time-to-digital converter constitute a 4-bit coarse-quantized time-domain ADC. The capacitor-to-digital converter array, the comparator, and the SAR logic module constitute a 5-bit fine-quantized SAR ADC with one bit of redundancy. The voltage-to-time converter converts the input differential signal into a time difference signal using a pair of pseudo-differential VTC pairs. The time-to-voltage converter converts the time difference signal back into a voltage signal and outputs it to the capacitor-to-digital converter array. The time-to-digital converter applies an integer multiple unit delay to the earlier signal based on the time difference information output by the voltage-to-time converter, causing the rising edges of the two input signals to gradually approach each other in time. After obtaining the high 4 bits of coarse quantization digital code, the capacitor-to-analog converter array generates a successive approximation feedback voltage by switching the voltage of the split capacitor bottom plate, based on the voltage acquired from the time-to-voltage converter and the control code information provided by the TDC module and the SAR logic module. The comparator compares this feedback voltage with the sampled voltage information from the time-to-voltage converter to obtain the quantization result of the current bit. The SAR logic module updates its internal registers based on the comparator output and generates the capacitor-to-analog converter array control code for the next cycle and generates the TDC operating mode selection signal SL. The latch is used to temporarily latch the 4-bit coarse quantization output result generated by the TDC coarse quantization. After the time-to-voltage converter completes charging of the capacitor-to-analog converter array, the voltage is applied to the high 4 bits of the capacitor bottom plate.

2. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The voltage-time converter is a constant current source type VTC structure composed of a pair of pseudo-differential structures. The voltage-time converter charges the sampling capacitor through the input voltage signal. After sampling is completed, the sampling switch is opened and the constant current source begins to discharge. Since the sampled input voltages are different, the voltage on the upper plate of the capacitor flips at different times through the inverter at the back end, thereby converting the input voltage difference signal into a time difference signal.

3. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The time-voltage converter uses a current integrator structure composed of PMOS transistors. During reset, the topmost PMOS transistor of the time-voltage converter charges the array of capacitor digital-to-analog converters to a high level. During operation, the converter receives the time difference signal from the voltage-time converter and controls the switch to discharge the integrating capacitor with a constant current, linearly converting the time interval back into a differential voltage signal. Its conversion gain is calibrated by adjusting the discharge current to ensure that it matches the quantization step size of the time-to-digital converter in both operating modes.

4. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The capacitor-to-digital converter array employs a split capacitor switching strategy to ensure the comparator comparison time is stable, so that the common-mode voltage remains basically constant during the switching process of the capacitor-to-digital converter, thereby eliminating the impact of common-mode voltage fluctuations on the comparator decision time and ensuring the accuracy of subsequent quantization based on decision time.

5. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The comparator employs a strong-arm latch structure, where the decision time from triggering to the valid output is negatively correlated with the input differential voltage. This is used to detect subthresholds and extract additional resolution information from metastable regions.

6. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The multiplexed time-to-digital converter (TDC) adopts a SARTDC structure, specifically including: OR gates and AND gates, delay time units, four comparators, and multiplexers. Specifically, the OR and AND gates are connected to the input signals of the current stage to distinguish between earlier and later input signals. The delay time units are connected after the AND and OR gates of each stage with weights of 4, 2, and 1, respectively, to apply a delay to the distinguished signals, completing the successive approximation logic. The four comparators are connected to the external input port of the TDC and the signals distinguished by the AND and OR gates and then delayed, to determine whether the time order of the signals changes after the delay is applied. The two multiplexers are connected to the two quantization signals of the TDC, controlled by the TDC operating mode selection signal SL: when the TDC operating mode selection signal SL is high, the multiplexer receives the Valid signal and the clock signal CLKc, which serve as the decision time for the TDC input signal quantization comparator; when the TDC operating mode selection signal SL is low, the main path of the multiplexer is turned on, used to quantize the leftmost VTC input T... IP and T IN Signal.

7. The resolution-enhanced time-domain two-step analog-to-digital conversion system according to claim 1, characterized in that, The SAR logic module includes a D flip-flop for generating the TDC operating mode selection signal SL. This D flip-flop is controlled by the SARStart signal: at the start of periodic quantization, the reset signal RST resets the SL port of the D flip-flop to 0; when the SARStart signal goes high, the SL port of the D flip-flop is set to 1, indicating whether the TDC is operating in coarse quantization mode or comparison time monitoring mode. This SL port is connected to the time-to-digital converter to control the multiplexer inside the TDC: when the TDC operating mode selection signal SL is low, the TDC operates in coarse quantization mode, receiving the time difference signal output from the VTC; when SL is high, the multiplexer switches to receiving the comparator decision time signal.

8. A two-step time-domain analog-to-digital conversion method based on the system described in any one of claims 1-7, characterized in that, include: Step 1: At the beginning of the quantization cycle, the TDC working mode selection signal SL is low, and the TDC switches back to coarse quantization mode by default. Step 2, Time-domain ADC coarse quantization, specifically includes: 2.1 The VTC receives the ADC input signal and quantizes it into a time-domain signal T. IP and T IN； 2.2 Time-domain signal T IP and T IN The signal is passed to a time-to-voltage converter, which converts the time-domain signal back to the voltage domain and stores it in a capacitor-to-digital converter array for subsequent quantization. 2.3 Simultaneous Time Domain Signal T IP and T IN The signal is passed to the time-to-digital converter, which quantizes the time signal differentially into the high 4 bits of the output. 2.4 Once the time-domain quantization is complete, the SARstart signal goes high, signifying the start of SAR quantization. Simultaneously, the TDC operating mode selection signal SL goes high, and the TDC enters the comparison time monitoring mode. Step 3, SARADC fine quantization, specifically including: 3.1 The strong arm comparator is used for comparison, and TDC quantizes the comparison time of the comparator; 3.2 Observe the quantification results of the comparison time using the multiplexed TDC; 3.3 If the comparison time exceeds the threshold time, it proves that the input signals are close enough, and the SAR partial quantization ends, directly outputting the SAR partial quantization result; 3.4 If the comparison time is less than the threshold time and the number of comparisons is less than 5, the SAR logic part changes the capacitor-to-digital converter array according to the output result of the strong arm comparator and starts the next comparison. 3.5 When the comparison time exceeds the threshold or the number of comparisons reaches 5, the SAR partial quantization is completed; Step 4: The ADC outputs a complete 9-bit quantization result, and all modules are reset. The quantization cycle is now complete.

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