Semiconductor device and manufacturing method thereof, integrated circuit and electronic equipment

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, an integrated circuit and electronic equipment. The semiconductor device includes a first vertical transistor and a second vertical transistor. The first vertical transistor comprises a first vertical nanosheet and a first grid electrode, the first vertical nanosheet comprises a first connecting part, and the first grid electrode is connected with the peripheral side face of the first connecting part. The second vertical transistor comprises a second vertical nanosheet and a second grid electrode, the second vertical nanosheet comprises a second connecting part, and the second grid electrode is connected with the peripheral side face of the second connecting part. The size of the second connecting part in the first direction is smaller than that of the first connecting part in the first direction, so that the threshold voltage value of the second vertical transistor is higher than that of the first vertical transistor. According to the semiconductor device provided by the invention, a high threshold voltage transistor and a conventional threshold voltage transistor are provided at the same time.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing a semiconductor device, an integrated circuit, and an electronic device. Background Technology

[0002] With the development of advanced processes, the miniaturization of horizontally mounted transistors, such as FinFETs and Gate-all-around Field-Effect Transistors (GAAFETs), faces significant challenges. Due to physical limitations, the contacted gate pitch (CGP) of horizontally mounted transistors cannot be scaled below 40nm. Vertically mounted transistors (VFETs), with their source, gate, and drain stacked in space, can break through the 40nm gate pitch limitation, thus extending Moore's Law.

[0003] In the current technology, vertical transistors still face many technical challenges from the laboratory to mass production. Among them, how to provide both high threshold voltage devices (Wimpy Devices) and conventional threshold voltage devices (Nominal Devices) is one of the technical challenges. Summary of the Invention

[0004] This application provides a semiconductor device, a method for manufacturing a semiconductor device, an integrated circuit, and an electronic device, with the aim of providing a high threshold voltage device for a vertical transistor.

[0005] In a first aspect, embodiments of this application provide a semiconductor device including a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first vertical nanosheet, a first gate, a first bottom electrode, and a first top electrode, spaced apart from each other. The first vertical nanosheet includes a first connecting portion, with the first gate connected to at least a portion of the peripheral side of the first connecting portion. The first bottom electrode and the first top electrode are connected to the first vertical nanosheet. The second vertical transistor includes a second vertical nanosheet, a second gate, a second bottom electrode, and a second top electrode, spaced apart from each other. The second vertical nanosheet includes a second connecting portion, with the second gate connected to at least a portion of the peripheral side of the second connecting portion. The second bottom electrode and the second top electrode are connected to the second vertical nanosheet. The dimension of the second connecting portion in a first direction is smaller than the dimension of the first connecting portion in the first direction, where the first direction is the width direction of both the first and second vertical transistors.

[0006] In summary, the dimensions of the second connection portion of the second vertical nanosheet in the first direction of the semiconductor device provided in this application are smaller than the dimensions of the first connection portion of the first vertical nanosheet in the first direction, so that the width of the vertical nanosheet of the second vertical transistor is smaller than that of the first vertical transistor, thereby achieving a threshold voltage value of the second vertical transistor that is higher than that of the first vertical transistor. The semiconductor device provided in this application realizes the simultaneous provision of a high threshold voltage transistor and a conventional threshold voltage transistor.

[0007] Furthermore, existing technologies adjust the length of vertical nanosheets in vertical transistors by changing their height, thereby achieving high threshold voltage transistors and conventional threshold voltage transistors. However, controlling the fabrication process for nanosheets with different heights is more difficult. In other words, existing technologies for high threshold voltage transistors and conventional threshold voltage transistors are technically challenging to implement and have poor manufacturability. Processes involving etching or grinding the transistor height can introduce a loading effect on the vertical nanosheets, increasing the error in the vertical nanosheet height and consequently increasing device error and performance degradation.

[0008] In an exemplary embodiment, the dimension of the second connection portion in the first direction is 1 nm to 4 nm smaller than the dimension of the first connection portion in the first direction, that is, the width difference between the first connection portion and the second connection portion is 1 nm to 4 nm. The width of the second connection portion being 1 nm to 4 nm smaller than the width of the first connection portion can meet the requirements for adjusting the threshold voltage of the second vertical transistor, and can also avoid a reduction in the structural strength of the second connection portion due to the width being too much smaller than the width of the first connection portion.

[0009] In an exemplary embodiment, the first vertical nanosheet further includes a first bottom and a first top. The first bottom, the first connecting portion, and the first top are stacked sequentially, and the peripheral side surface of the first connecting portion is connected to and flush with the peripheral side surface of the first bottom and the peripheral side surface of the first top, respectively. The first bottom electrode is connected to the first bottom, and the first top electrode is connected to the first top. The width of the first connecting portion, the width of the first bottom, and the width of the first top are equal, meaning the width of the entire first vertical nanosheet is consistent. This allows the first vertical nanosheet to be formed in a single process, which helps save costs.

[0010] In an exemplary embodiment, the second vertical nanosheet further includes a second bottom and a second top, wherein the second bottom, the second connecting portion, and the second top are sequentially stacked. The second bottom electrode is connected to the second bottom, and the second top electrode is connected to the second top. The second bottom electrode is electrically connected to the second bottom, and the second top electrode is electrically connected to the second top.

[0011] In one possible implementation, the width of the second connecting portion is equal to the width of the second bottom, the width of the second connecting portion is equal to the width of the second top, and the peripheral side surfaces of the second bottom, the second connecting portion, and the second top are flush with each other. That is, the entire second vertical nanosheet has a consistent size in the first direction, and only one process is needed to form the second vertical nanosheet, which helps to save costs.

[0012] In one possible implementation, the dimension of the second connecting portion in the first direction is smaller than the dimension of the second bottom in the first direction, and the dimension of the second connecting portion in the first direction is smaller than the dimension of the second top in the first direction. Reducing only the dimension of the second connecting portion of the second vertical nanosheet in the first direction can avoid the increase in contact resistance between the second bottom and the second bottom electrode caused by the reduction in the dimension of the second bottom in the first direction, and also avoid the increase in contact resistance between the second top and the second top electrode caused by the reduction in the dimension of the second top in the first direction.

[0013] In one possible implementation, the size of the second connection portion in the first direction is 1 nm to 4 nm smaller than the size of the second bottom in the first direction, and the size of the second connection portion in the first direction is 1 nm to 4 nm smaller than the size of the second top in the first direction. This can meet the requirements for adjusting the threshold voltage of the second vertical transistor, and can also avoid the structural strength of the second connection portion being reduced due to the size of the second connection portion in the first direction being too much smaller than the size of the second bottom and the size of the second top in the first direction.

[0014] In an exemplary embodiment, the semiconductor device further includes a substrate disposed on the surface of the first bottom facing away from the first connection portion and the surface of the second bottom facing away from the second connection portion. The first vertical transistor and the second vertical transistor share a single substrate, simplifying the structure of the semiconductor device and facilitating the simultaneous formation of the first and second vertical transistors on a single substrate, thereby simplifying the fabrication process of the semiconductor device and saving costs.

[0015] In an exemplary embodiment, the first apex is symmetrical along the plane containing its own central axis, which improves the dimensional and positional accuracy of the first apex and helps to reduce transistor performance errors.

[0016] In an exemplary embodiment, the second apex is symmetrical along the plane containing its own central axis, which improves the dimensional and positional accuracy of the second apex and helps to reduce transistor performance errors.

[0017] In an exemplary embodiment, the first gate is symmetrical along the plane containing the central axis of the first vertical nanosheet, which improves the dimensional and positional accuracy of the first gate and helps to reduce transistor performance errors.

[0018] In an exemplary embodiment, the second gate is symmetrical along the plane containing the central axis of the second vertical nanosheet, which improves the dimensional and positional accuracy of the second gate and helps to reduce transistor performance errors.

[0019] In an exemplary embodiment, the first vertical transistor further includes a first bottom isolation portion and a first top isolation portion. The first bottom isolation portion is disposed between the first bottom electrode and the first gate electrode, and the first top isolation portion is disposed between the first top electrode and the first gate electrode. The first bottom isolation portion is used to insulate the first gate electrode from the first bottom electrode, and the first bottom isolation portion is used to insulate the first gate electrode from the first top electrode.

[0020] In an exemplary embodiment, the second vertical transistor further includes a second bottom isolation portion and a second top isolation portion. The second bottom isolation portion is disposed between the second bottom electrode and the second gate, and the second top isolation portion is disposed between the second top electrode and the second gate. The second bottom isolation portion is used to insulate the second gate electrode from the second bottom electrode, and the second bottom isolation portion is used to insulate the second gate electrode from the second top electrode.

[0021] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, the method comprising:

[0022] A substrate is formed comprising a substrate, a first vertical nanosheet, a second vertical nanosheet, and a bottom electrode layer. The first vertical nanosheet, the second vertical nanosheet, and the bottom electrode layer are all located on one surface of the substrate, with the first vertical nanosheet and the second vertical nanosheet spaced apart. The bottom electrode layer connects the peripheral surfaces of the first vertical nanosheet and the second vertical nanosheet. The first vertical nanosheet includes a first connecting portion, and the second vertical nanosheet includes a second connecting portion.

[0023] A bottom isolation layer, a protective layer, a gate replacement layer, and a top isolation layer are sequentially formed on the bottom electrode layer. The bottom isolation layer is located on the surface of the bottom electrode layer facing away from the substrate, and the bottom electrode layer connects the peripheral surfaces of the first vertical nanosheet and the second vertical nanosheet. The protective layer is located on the surface of the bottom isolation layer facing away from the bottom electrode layer, as well as on the peripheral surfaces of the first and second vertical nanosheets. The gate replacement layer is located on the surface of the protective layer facing away from the bottom isolation layer, and the top isolation layer is located on the surface of the gate replacement layer facing away from the bottom isolation layer.

[0024] A first apex is formed on the surface of the first vertical nanosheet facing away from the substrate, and a second apex is formed on the surface of the second vertical nanosheet facing away from the substrate. A first insulating structure is formed on the first apex, and a second insulating structure is formed on the second apex.

[0025] Using the first insulating structure and the second insulating structure as a mask, remove the portion of the top insulating layer that is offset from the first insulating structure and the second insulating structure.

[0026] After removing the gate replacement layer and the protective layer, the first connecting portion of the first vertical nanosheet and the second connecting portion of the second vertical nanosheet are exposed.

[0027] A first gate is formed on the peripheral side surface of the first connecting portion and a second gate is formed on the peripheral side surface of the second connecting portion.

[0028] Using the first insulating structure and the second insulating structure as masks, the portion of the bottom isolation layer that is offset from the first insulating structure and the second insulating structure is removed, and the portion of the bottom electrode layer that is offset from the first insulating structure and the second insulating structure is removed to form a first bottom electrode and a second bottom electrode. The first bottom electrode is connected to the first vertical nanosheet, and the second bottom electrode is connected to the second vertical nanosheet. The dimension of the second connection portion in the first direction is smaller than the dimension of the first connection portion in the first direction. The first vertical nanosheet, the first gate, the first bottom electrode, and the first top electrode constitute a first vertical transistor, and the second vertical nanosheet, the second gate, the second bottom electrode, and the second top electrode constitute a second vertical transistor.

[0029] In summary, the second connection portion of the second vertical nanosheet formed by the semiconductor device fabrication method provided in this application has a smaller size in the first direction than the first connection portion of the first vertical nanosheet in the first direction, which makes the threshold voltage of the second vertical transistor higher than the threshold voltage of the first vertical transistor. The semiconductor device provided in this application realizes the simultaneous provision of a high threshold voltage transistor and a conventional threshold voltage transistor.

[0030] In an exemplary embodiment, the dimension of the second connection portion in the first direction is 1 nm to 4 nm smaller than the dimension of the first connection portion in the first direction. This smaller dimension allows for adjustment of the threshold voltage of the second vertical transistor while avoiding a reduction in the structural strength of the second connection portion due to the second connection portion being significantly smaller in the first direction.

[0031] In one possible implementation, the step of forming a substrate, a first vertical nanosheet, a second vertical nanosheet, and a bottom layer includes:

[0032] A barrier layer, a passivation layer, a first pad, and a second pad are sequentially formed on the substrate. The barrier layer is located on one surface of the substrate, the passivation layer is located on the surface of the barrier layer opposite to the substrate, and both the first pad and the second pad are located on the surface of the passivation layer opposite to the barrier layer, with the first pad and the second pad spaced apart. The dimension of the second pad in the first direction is smaller than the dimension of the first pad in the first direction.

[0033] Using the first and second pads as masks, the portions of the passivation layer that are offset from the first and second pads are removed, as are the portions of the barrier layer that are offset from the first and second pads. The substrate is then etched to form a substrate transition layer, the first vertical nanosheet, and the second vertical nanosheet. The peripheral side surface of the first vertical nanosheet is aligned with the peripheral side surface of the first pad, and the peripheral side surface of the second vertical nanosheet is aligned with the peripheral side surface of the second pad. The dimension of the second vertical nanosheet in the first direction is smaller than the dimension of the first vertical nanosheet in the first direction.

[0034] Ions are implanted into the substrate transition layer to form the substrate and the bottom electrode layer.

[0035] By making the size of the second spacer in the first direction smaller than that of the first spacer in the first direction, the size of the formed second vertical nanosheet in the first direction is also smaller than that of the first vertical nanosheet in the first direction. The second vertical nanosheet and the first vertical nanosheet can be formed in a single process, simplifying the semiconductor device fabrication process and saving costs. Furthermore, using the first spacer to limit the size of the first vertical nanosheet in the first direction and the second spacer to limit the size of the second vertical nanosheet in the first direction helps improve the accuracy of both the size of the first and second vertical nanosheets in the first direction.

[0036] In an exemplary embodiment, the size of the second pad in the first direction is 1 nm to 4 nm smaller than the size of the first pad in the first direction, and the size of the second vertical nanosheet in the first direction is 1 nm to 4 nm smaller than the size of the first vertical nanosheet in the first direction.

[0037] In one possible implementation, before forming the first gate and the second gate after removing the gate replacement layer and the protective layer, the method for fabricating the semiconductor device includes:

[0038] The second connecting portion of the second vertical nanosheet is modified such that the dimension of the second connecting portion in the first direction is smaller than the dimension of the first connecting portion in the first direction.

[0039] By reducing only the size of the second connection portion of the second vertical nanosheet in the first direction, the overall structural strength of the second vertical nanosheet can be prevented from decreasing.

[0040] In an exemplary embodiment, the step of modifying the second connecting portion of the second vertical nanosheet includes:

[0041] A protective structure is formed on the peripheral side of the first connecting part.

[0042] The second connecting portion is modified to reduce its size in the first direction. The second vertical nanosheet also includes a second bottom and a second top, which are respectively connected to opposite ends of the second connecting portion. Specifically, the size of the second connecting portion in the first direction is smaller than the size of the second bottom in the first direction, and the size of the second connecting portion in the first direction is smaller than the size of the second top in the first direction.

[0043] Remove the protective structure, and the first connecting portion is exposed.

[0044] By forming a protective structure on the peripheral side of the first connecting portion, modification of the first connecting portion can be avoided. Furthermore, since the dimensions of the second bottom and the second top in the first direction are not reduced, an increase in contact resistance between the second bottom and the second bottom electrode, and an increase in contact resistance between the second top and the second top electrode, can be avoided.

[0045] In an exemplary embodiment, the size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second bottom in the first direction, and the size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second top in the first direction.

[0046] Thirdly, embodiments of this application also provide an integrated circuit, the integrated circuit including an electronic device and the aforementioned semiconductor device, the semiconductor device being electrically connected to the electronic device.

[0047] In summary, the integrated circuit provided in this application includes a semiconductor device. The size of the second connection portion of the second vertical nanosheet in the first direction is smaller than the size of the first connection portion of the first vertical nanosheet in the first direction, so that the threshold voltage of the second vertical transistor is higher than that of the first vertical transistor. The semiconductor device provided in this application realizes the simultaneous provision of a high threshold voltage transistor and a conventional threshold voltage transistor.

[0048] Fourthly, embodiments of this application also provide an electronic device, the electronic device including a circuit board and the aforementioned integrated circuit, the integrated circuit being electrically connected to the circuit board.

[0049] In summary, the electronic device provided in this application includes an integrated circuit, which includes a semiconductor device. The size of the second connection portion of the second vertical nanosheet of the semiconductor device in the first direction is smaller than the size of the first connection portion of the first vertical nanosheet in the first direction. The threshold voltage of the second vertical transistor is higher than that of the first vertical transistor. The semiconductor device provided in this application realizes the simultaneous provision of a high threshold voltage transistor and a conventional threshold voltage transistor. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0051] Figure 1 This is a schematic diagram of the structure of the first electronic device disclosed in the embodiments of this application;

[0052] Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the embodiments of this application;

[0053] Figure 3 This is a schematic diagram of the first layer structure of the semiconductor device disclosed in the embodiments of this application;

[0054] Figure 4 This is a flowchart illustrating a method for fabricating a first layer structure of a semiconductor device disclosed in an embodiment of this application.

[0055] Figure 5 for Figure 4 A schematic flowchart of step S100 of the method for fabricating the semiconductor device shown.

[0056] Figure 6 for Figure 5 A schematic flowchart of step S110 of the method for fabricating the semiconductor device shown.

[0057] Figure 7 for Figure 6 The schematic diagram of the structure formed corresponding to step S111 shown;

[0058] Figure 8 for Figure 6 The schematic diagram of the structure formed corresponding to step S112 shown;

[0059] Figure 9 for Figure 6 The schematic diagram of the structure formed corresponding to step S113 shown;

[0060] Figure 10 for Figure 6 The schematic diagram of the structure formed corresponding to step S114 shown;

[0061] Figure 11 for Figure 6 The schematic diagram of the structure formed corresponding to step S115 is shown below;

[0062] Figure 12 for Figure 6 The schematic diagram of the structure formed corresponding to step S116 is shown below;

[0063] Figure 13 for Figure 5 The schematic diagram of the structure formed corresponding to step S120 is shown below;

[0064] Figure 14 for Figure 5 The schematic diagram of the structure formed corresponding to step S130 is shown below;

[0065] Figure 15 for Figure 4 A schematic flowchart of step S200 of the method for fabricating the semiconductor device shown;

[0066] Figure 16 for Figure 15 The schematic diagram of the structure formed corresponding to step S210 shown;

[0067] Figure 17 for Figure 15 The schematic diagram of the structure formed corresponding to step S220 is shown below;

[0068] Figure 18 for Figure 15 The schematic diagram of the structure formed corresponding to step S230 is shown below;

[0069] Figure 19 for Figure 15 The schematic diagram of the structure formed corresponding to step S240 shown;

[0070] Figure 20 for Figure 4 A schematic flowchart of step S300 of the method for fabricating the semiconductor device shown.

[0071] Figure 21 for Figure 20 The schematic diagram of the structure formed corresponding to step S310 is shown below;

[0072] Figure 22 for Figure 20 The schematic diagram of the structure formed corresponding to step S320 is shown below;

[0073] Figure 23 for Figure 20 The schematic diagram of the structure formed corresponding to step S330 is shown below;

[0074] Figure 24 for Figure 20The schematic diagram of the structure formed corresponding to step S340 is shown below;

[0075] Figure 25 for Figure 20 The schematic diagram of the structure formed corresponding to step S350 is shown below;

[0076] Figure 26 for Figure 20 The schematic diagram of the structure formed corresponding to step S360 is shown below;

[0077] Figure 27 for Figure 20 The schematic diagram of the structure formed corresponding to step S370 is shown below;

[0078] Figure 28 for Figure 4 The schematic diagram of the structure formed corresponding to step S400 is shown below;

[0079] Figure 29 for Figure 4 The schematic diagram of the structure formed corresponding to step S500 is shown below;

[0080] Figure 30 for Figure 4 A schematic flowchart of step S600 of the method for fabricating a semiconductor device is shown.

[0081] Figure 31 for Figure 30 The schematic diagram of the structure formed corresponding to step S610 is shown below;

[0082] Figure 32 for Figure 30 The schematic diagram of the structure formed corresponding to step S620 is shown below;

[0083] Figure 33 for Figure 4 The schematic diagram of the structure formed corresponding to step S700 is shown below;

[0084] Figure 34 for Figure 4 The schematic diagram of the structure formed corresponding to step S800 is shown below;

[0085] Figure 35 for Figure 4 The schematic diagram of the structure formed corresponding to step S900 shown;

[0086] Figure 36 for Figure 4 The schematic diagram of the structure formed corresponding to step S1000 shown;

[0087] Figure 37 for Figure 4 The schematic diagram of the structure formed corresponding to step S1100 is shown below;

[0088] Figure 38 This is a schematic diagram of a second layer structure of a semiconductor device disclosed in an embodiment of this application;

[0089] Figure 39 A flowchart illustrating step S600' of the method for fabricating the second layer structure of a semiconductor device;

[0090] Figure 40 for Figure 39 The schematic diagram of the structure formed corresponding to step S610' is shown below;

[0091] Figure 41 for Figure 39 The schematic diagram of the structure formed corresponding to step S620' is shown. Detailed Implementation

[0092] In the description of the embodiments of this application, it is understood that, unless otherwise expressly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after the connection.

[0093] The directional terms mentioned in the embodiments of this application, such as "upper", "lower", "top", "bottom", "inner", "outer", "side", etc., are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0094] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature. The term "multiple" refers to at least two.

[0095] In the embodiments of this application, the terms "parallel," "perpendicular," and "aligned" are used in relation to the current technological level, rather than being absolutely strict mathematical definitions. Slight deviations are permissible; approximations of parallelism, perpendicularity, and alignment are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, with the angle between A and B ranging from 0° to 10°. Similarly, "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, with the angle between A and B ranging from 80° to 100°. Finally, "A and B are aligned" means that A and B are aligned or approximately aligned, with the alignment difference between A and B within 1 nm.

[0096] References to "some embodiments" and the like in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "some embodiments," "in other embodiments," and "in still other embodiments" appearing in different parts of this specification do not necessarily refer to the same embodiments, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically emphasized.

[0097] It is understood that the specific embodiments described herein are merely illustrative of related embodiments and not intended to limit the scope of those embodiments. It is also understood that, for ease of description, the accompanying drawings show only the parts relevant to the embodiments.

[0098] It is understood that, without conflict, the embodiments and features described in this application can be combined with each other.

[0099] The embodiments of this application are described below with reference to the accompanying drawings.

[0100] This application provides an electronic device, which can be a mobile phone, laptop computer, tablet computer, smart TV, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet, smart glasses), in-vehicle device, smart home device, smart city device, terminal device, and other electronic products. This application does not impose any special limitations on the specific type of this electronic device. Please refer to... Figure 1 and Figure 2 , Figure 1This is a schematic diagram of the structure of the first electronic device disclosed in the embodiments of this application. Figure 2 This is a schematic diagram of the structure of the second electronic device disclosed in the embodiments of this application. Figure 1 The electronic device shown is a mobile phone. Figure 2 The electronic device shown is a laptop computer. For ease of explanation, a mobile phone will be used as an example below.

[0101] The aforementioned electronic devices include components such as integrated circuits and circuit boards. Integrated circuits are electrically connected to circuit boards via pins, and integrated circuits can be electrically connected to external circuits through circuit boards to achieve signal exchange. Integrated circuits can be used to perform logical operations, process digital signals, or store data and instructions.

[0102] The aforementioned integrated circuit includes electronic devices and semiconductor devices, which are electrically connected to transmit electrical signals. The electronic devices include resistors, capacitors, and controllers, etc., which are not specifically limited in this application.

[0103] Based on this, embodiments of this application provide a semiconductor device, which may be a CoreLogic chip, Static Random Access Memory (SRAM), Memory Selector, Image Signal Processor (ISP), Digital Signal Processor (DSP), or Graphics Processing Unit (GPU), etc. Embodiments of this application do not impose any special limitations on the specific type of this semiconductor device.

[0104] In the embodiments of this application, please refer to Figure 3 , Figure 3 This is a schematic diagram of a first layer structure of a semiconductor device disclosed in an embodiment of this application. The semiconductor device 1 includes a first vertical transistor 10, a second vertical transistor 20, a substrate 30, an interlayer isolation layer 60, a first contact 70, a second contact 80, and a conductive network layer 90. Figure 3The rectangular dashed box in the figure shows the positions of the first vertical transistor 10 and the second vertical transistor 20. The first vertical transistor 10 and the second vertical transistor 20 are disposed on one surface of the substrate 30, and are spaced apart from each other. An interlayer isolation layer 60 is disposed on the surface of the first vertical transistor 10 facing away from the substrate 30 and on its peripheral side, and on the surface of the second vertical transistor 20 facing away from the substrate 30 and on its peripheral side. A conductive network layer 90 is disposed on the surface of the interlayer isolation layer 60 facing away from the substrate 30. A first contact 70 electrically connects the conductive network layer 90 to the first vertical transistor 10, and a second contact 80 electrically connects the conductive network layer 90 to the second vertical transistor 20. The conductive network layer 90 is used to transmit electrical signals to the first vertical transistor 10 and the second vertical transistor 20.

[0105] For ease of description, define Figure 3 The width direction of the first vertical transistor 10 and the second vertical transistor 20 shown is the X-axis direction, the length direction of the first vertical transistor 10 and the second vertical transistor 20 is the Y-axis direction, and the height direction of the first vertical transistor 10 and the second vertical transistor 20 is the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are mutually perpendicular. The X-axis direction can also be defined as a first direction, the Y-axis direction can also be defined as a second direction, and the Z-axis direction can also be defined as a third direction. The directional terms such as "upper" and "lower" mentioned in the embodiments of this application are based on the appendix to the specification. Figure 3 The description of the orientation shown uses "up" and "top" to refer to the positive direction of the Z-axis and "down" and "bottom" to refer to the negative direction of the Z-axis. This does not constitute a limitation on the actual application scenario of the semiconductor device 1.

[0106] In this embodiment, the first vertical transistor 10 is a conventional threshold voltage (Nominal) transistor, and the second vertical transistor 20 is a high threshold voltage (Wimpy) transistor. The on-state current of the second vertical transistor 20 is less than the on-state current of the first vertical transistor 10, and the off-state current of the second vertical transistor 20 is less than the off-state current of the first vertical transistor 10.

[0107] The semiconductor device 1 provided in this application includes both a first vertical transistor 10 and a second vertical transistor 20, enabling the semiconductor device 1 to meet different electrical requirements. For example, a first module of the semiconductor device 1 includes the first vertical transistor 10, and a second module of the semiconductor device 1 includes the second vertical transistor 20. The first module requires a larger on-state current, and the first vertical transistor 10 has a larger on-state current, which meets the electrical requirements of the first module. The second module requires lower power consumption, and the second vertical transistor 20 has a smaller off-state current, which meets the electrical requirements of the second module.

[0108] In other embodiments, the semiconductor device 1 may also include only the second vertical transistor 20, and this application does not impose specific limitations on this.

[0109] It should be noted that there are multiple first vertical transistors 10 and multiple second vertical transistors 20 in semiconductor device 1. Each first vertical transistor 10 has the same structure, and each second vertical transistor 20 has the same structure. For ease of demonstration, Figure 3 Only one first vertical transistor 10 and one second vertical transistor 20 are shown in the image.

[0110] In this embodiment of the application, the substrate 30 includes a base 31 and a protrusion 32. The protrusion 32 is disposed on the surface of the base 31 facing the Z-axis direction, and the protrusion 32 is used to provide the surface for the formation of the first vertical transistor 10 and the second vertical transistor 20.

[0111] In one possible embodiment, the number of protrusions 32 is multiple, equal to the total number of the first vertical transistor 10 and the second vertical transistor 20, such that each vertical transistor is formed on a protrusion 32. For ease of illustration, Figure 3 Only two protrusions 32 are shown. The two protrusions 32 are spaced apart from each other and are flush with the surface of the base 31 with their backs to each other.

[0112] Understandably, the first vertical transistor 10 and the second vertical transistor 20 share a substrate 30, which simplifies the structure of the semiconductor device 1 and facilitates the simultaneous formation of the first vertical transistor 10 and the second vertical transistor 20 on a substrate 30, thus simplifying the manufacturing process of the semiconductor device 1 and saving costs.

[0113] In this embodiment of the application, the first vertical transistor 10 includes a first vertical nanosheet 11, a first gate 12, a first bottom electrode 13, a first top electrode 14, a first bottom isolation portion 15, a first top isolation portion 16, a first insulating structure 17, and a first oxide layer pad 18.

[0114] Specifically, the first vertical nanosheet 11 is disposed on the surface of the protrusion 32 facing away from the substrate 31, and the first vertical nanosheet 11 extends along the direction of the protrusion 32 facing away from the substrate 31, that is, the first vertical nanosheet 11 extends along the Z-axis direction. The first vertical nanosheet 11 includes a first bottom 111, a first connecting portion 112, and a first top 113. Figure 3The dashed lines in the first vertical nanosheet 11 indicate the positions of the first bottom 111, the first connecting portion 112, and the first top 113. The first bottom 111 is disposed on the surface of the protrusion 32 facing away from the substrate 31, the first connecting portion 112 is disposed on the surface of the first bottom 111 facing away from the protrusion 32, and the first top 113 is disposed on the surface of the first connecting portion 112 facing away from the first bottom 111. That is, the first bottom 111, the first connecting portion 112, and the first top 113 are arranged sequentially along the direction in which the protrusion 32 faces away from the substrate 31.

[0115] For example, the peripheral side surface of the first bottom 111 is connected to and flush with the peripheral side surface of the first connecting portion 112, and the peripheral side surface of the first connecting portion 112 is connected to and flush with the peripheral side surface of the first top 113.

[0116] It should be noted that the first vertical nanosheet 11 and the substrate 30 are formed by an etching process, and the first vertical nanosheet 11 and the substrate 30 are made of the same material.

[0117] The first bottom electrode 13 is disposed on the surface of the protrusion 32 facing away from the substrate 31. The first bottom electrode 13 is connected to the peripheral side surface of the first bottom 111 of the first vertical nanosheet 11, wherein the first bottom 111 has four peripheral side surfaces, and the first bottom electrode 13 can be connected to at least two of the four peripheral side surfaces of the first bottom 111. The peripheral side surface of the first bottom electrode 13 is connected to and flush with the peripheral side surface of the protrusion 32.

[0118] A first bottom isolation portion 15 is disposed on the surface of the first bottom 111 facing away from the first bottom electrode 13. The first bottom isolation portion 15 is connected to the peripheral side surface of the first bottom 111 of the first vertical nanosheet 11, wherein the first bottom isolation portion 15 may be connected to at least two of the four peripheral side surfaces of the first bottom 111. The peripheral side surface of the first bottom isolation portion 15 is connected to and flush with the peripheral side surface of the first bottom electrode 13. The surface of the first bottom isolation portion 15 facing away from the first bottom electrode 13 is connected to and flush with the surface of the first bottom 111 facing away from the substrate 30.

[0119] A first gate 12 is disposed on the surface of the first bottom isolation portion 15 facing away from the first bottom electrode 13. The first gate 12 is connected to the peripheral side surface of the first connecting portion 112 of the first vertical nanosheet 11, wherein the first bottom 111 has four peripheral side surfaces, and the first gate 12 can be connected to at least two of the four peripheral side surfaces of the first connecting portion 112. The peripheral side surface of the first gate 12 is connected to and flush with the peripheral side surface of the first bottom isolation portion 15. The surface of the first gate 12 facing away from the first bottom isolation portion 15 is connected to and flush with the surface of the first connecting portion 112 facing away from the first bottom 111.

[0120] In an exemplary embodiment, the first gate 12 is symmetrical about the plane containing the central axis of the first vertical nanosheet 11. The central axis of the first vertical nanosheet 11 is parallel to the Z-axis direction, and the central axis of the first vertical nanosheet 11 passes through the geometric center point of the first vertical nanosheet 11.

[0121] Understandably, by making the first gate 12 symmetrical along the plane containing the central axis of the first vertical nanosheet 11, the dimensional and positional accuracy of the first gate 12 is improved, which helps to reduce transistor performance errors. The first gate 12 is formed by a self-aligned process, which can reduce the error of the first gate 12.

[0122] A first oxide layer pad 18 is disposed on the surface of the first gate 12 facing away from the first bottom isolation portion 15. The first oxide layer pad 18 is connected to the peripheral side surface of the first top 113 of the first vertical nanosheet 11, wherein the first top 113 has four peripheral side surfaces, and the first oxide layer pad 18 can be connected to at least two of the four peripheral side surfaces of the first top 113. The surface of the first oxide layer pad 18 facing away from the first gate 12 is connected to and flush with the surface of the first top 113 facing away from the first connection portion 112.

[0123] The first top isolation portion 16 is disposed on the surface of the first gate 12 opposite to the first bottom isolation portion 15. The first top isolation portion 16 is connected to the outer side surface of the first oxide layer pad 18, that is, the first top isolation portion 16 is connected to the surface of the first oxide layer pad 18 opposite to the first top 113. The peripheral side surface of the first top isolation portion 16 is connected to and flush with the peripheral side surface of the first gate 12. The surface of the first top isolation portion 16 opposite to the first gate 12 is connected to and flush with the surface of the first oxide layer pad 18 opposite to the first gate 12.

[0124] The first top electrode 14 is disposed on the surface of the first vertical nanosheet 11 opposite to the protrusion 32, and the first top electrode 14 is connected to the surface of the first oxide layer pad 18 opposite to the first gate 12 and the surface of the first top isolation portion 16 opposite to the first gate 12.

[0125] In an exemplary embodiment, the first apex 14 is symmetrical about the plane containing its own central axis. The central axis of the first apex 14 is parallel to the Z-axis direction, and the central axis of the first apex 14 passes through the geometric center point of the first apex 14.

[0126] Understandably, by making the first apex 14 symmetrical along the plane containing its own central axis, the dimensional and positional accuracy of the first apex 14 is improved, which helps to reduce errors in transistor performance. The first apex 14 is formed by a self-aligned process, which can reduce errors in the first apex 14.

[0127] A first insulating structure 17 is disposed on the surface of the first top electrode 14 facing away from the first vertical nanosheet 11 and on the peripheral side surface surrounding the first top electrode 14. The first insulating structure 17 is also connected to the surface of the first top isolation portion 16 facing away from the first gate 12. The peripheral side surface of the first insulating structure 17 is connected to and flush with the peripheral side surface of the first top isolation portion 16.

[0128] It should be noted that the first bottom electrode 13 is the source of the first vertical transistor 10, and the first top electrode 14 is the drain of the first vertical transistor 10; or, the first bottom electrode 13 is the drain of the first vertical transistor 10, and the first top electrode 14 is the source of the first vertical transistor 10. The first bottom electrode 13 is electrically connected to the first bottom electrode 111, and the first top electrode 14 is electrically connected to the first top electrode 113. The first bottom isolation portion 15 is used to insulate the first gate electrode 12 from the first bottom electrode 13, and the first bottom isolation portion 15 is used to insulate the first gate electrode 12 from the first top electrode 14. The first oxide layer pad 18 is used to protect the first top electrode 113 of the first vertical nanosheet 11, and the first insulating structure 17 is used to insulate the surface of the first top electrode 14 and protect the first top electrode 14.

[0129] In this embodiment, the second vertical transistor 20 includes a second vertical nanosheet 21, a second gate 22, a second bottom electrode 23, a second top electrode 24, a second bottom isolation portion 25, a second top isolation portion 26, a second insulating structure 27, and a second oxide layer pad 28.

[0130] Specifically, the second vertical nanosheet 21 is disposed on the surface of the protrusion 32 facing away from the substrate 31, and the second vertical nanosheet 21 extends along the direction of the protrusion 32 facing away from the substrate 31, that is, the second vertical nanosheet 21 extends along the Z-axis direction. The second vertical nanosheet 21 includes a second bottom 211, a second connecting portion 212, and a second top 213. Figure 3 The dashed lines in the second vertical nanosheet 21 indicate the positions of the second bottom 211, the second connecting portion 212, and the second top 213. The second bottom 211 is disposed on the surface of the protrusion 32 facing away from the substrate 31, the second connecting portion 212 is disposed on the surface of the second bottom 211 facing away from the protrusion 32, and the second top 213 is disposed on the surface of the second connecting portion 212 facing away from the second bottom 211. That is, the second bottom 211, the second connecting portion 212, and the second top 213 are arranged sequentially along the direction in which the protrusion 32 faces away from the substrate 31.

[0131] For example, the peripheral side surface of the second bottom 211 is connected to and flush with the peripheral side surface of the second connecting portion 212, and the peripheral side surface of the second connecting portion 212 is connected to and flush with the peripheral side surface of the second top 213.

[0132] It should be noted that the second vertical nanosheet 21 and the substrate 30 are formed by an etching process, and the second vertical nanosheet 21 and the substrate 30 are made of the same material.

[0133] The second bottom electrode 23 is disposed on the surface of the protrusion 32 facing away from the substrate 31. The second bottom electrode 23 is connected to the peripheral side surface of the second bottom 211 of the second vertical nanosheet 21, wherein the second bottom 211 has four peripheral side surfaces, and the second bottom electrode 23 can be connected to at least two of the four peripheral side surfaces of the second bottom 211. The peripheral side surface of the second bottom electrode 23 is connected to and flush with the peripheral side surface of the protrusion 32.

[0134] The second bottom isolation portion 25 is disposed on the surface of the second bottom 211 facing away from the second bottom electrode 23. The second bottom isolation portion 25 is connected to the peripheral side surface of the second bottom 211 of the second vertical nanosheet 21, wherein the second bottom isolation portion 25 can connect to at least two of the four peripheral side surfaces of the second bottom 211. The peripheral side surface of the second bottom isolation portion 25 is connected to and flush with the peripheral side surface of the second bottom electrode 23. The surface of the second bottom isolation portion 25 facing away from the second bottom electrode 23 is connected to and flush with the surface of the second bottom 211 facing away from the substrate 30.

[0135] The second gate 22 is disposed on the surface of the second bottom isolation portion 25 opposite to the second bottom electrode 23. The second gate 22 is connected to the peripheral side surface of the second connecting portion 212 of the second vertical nanosheet 21, wherein the second bottom 211 has four peripheral side surfaces, and the second gate 22 can be connected to at least two of the four peripheral side surfaces of the second connecting portion 212. The peripheral side surface of the second gate 22 is connected to and flush with the peripheral side surface of the second bottom isolation portion 25. The surface of the second gate 22 opposite to the second bottom isolation portion 25 is connected to and flush with the surface of the second connecting portion 212 opposite to the second bottom 211.

[0136] In an exemplary embodiment, the second gate 22 is symmetrical about the plane containing the central axis of the second vertical nanosheet 21. The central axis of the second vertical nanosheet 21 is parallel to the Z-axis direction, and the central axis of the second vertical nanosheet 21 passes through the geometric center point of the second vertical nanosheet 21.

[0137] Understandably, by making the second gate 22 symmetrical along the plane containing the central axis of the second vertical nanosheet 21, the dimensional and positional accuracy of the second gate 22 is improved, which helps to reduce transistor performance errors. The second gate 22 is formed by a self-aligned process, which can reduce the error of the second gate 22.

[0138] The second oxide layer pad 28 is disposed on the surface of the second gate 22 facing away from the second bottom isolation portion 25. The second oxide layer pad 28 is connected to the peripheral side surface of the second top 213 of the second vertical nanosheet 21, wherein the second top 213 has four peripheral side surfaces, and the second oxide layer pad 28 can be connected to at least two of the four peripheral side surfaces of the second top 213. The surface of the second oxide layer pad 28 facing away from the second gate 22 is connected to and flush with the surface of the second top 213 facing away from the second connection portion 212.

[0139] The second top isolation portion 26 is disposed on the surface of the second gate 22 opposite to the second bottom isolation portion 25. The second top isolation portion 26 is connected to the peripheral side surface of the second oxide layer pad 28, that is, the second top isolation portion 26 is connected to the surface of the second oxide layer pad 28 opposite to the second top 213. The peripheral side surface of the second top isolation portion 26 is connected to and flush with the peripheral side surface of the second gate 22. The surface of the second top isolation portion 26 opposite to the second gate 22 is connected to and flush with the surface of the second oxide layer pad 28 opposite to the second gate 22.

[0140] The second top electrode 24 is disposed on the surface of the second vertical nanosheet 21 opposite to the protrusion 32, and the second top electrode 24 is connected to the surface of the second oxide layer pad 28 opposite to the second gate 22 and the surface of the second top isolation portion 26 opposite to the second gate 22.

[0141] In an exemplary embodiment, the second apex 24 is symmetrical about the plane containing its own central axis. The central axis of the second apex 24 is parallel to the Z-axis direction, and the central axis of the second apex 24 passes through the geometric center point of the second apex 24.

[0142] Understandably, by making the second apex 24 symmetrical along the plane containing its own central axis, the dimensional and positional accuracy of the second apex 24 is improved, which helps to reduce errors in transistor performance. The second apex 24 is formed through a self-aligned process, which can reduce errors in the second apex 24.

[0143] The second insulating structure 27 is disposed on the surface of the second top electrode 24 facing away from the second vertical nanosheet 21 and surrounding the peripheral side surface of the second top electrode 24. The second insulating structure 27 is also connected to the surface of the second top isolation portion 26 facing away from the second gate 22. The peripheral side surface of the second insulating structure 27 is connected to and flush with the peripheral side surface of the second top isolation portion 26.

[0144] It should be noted that the second bottom electrode 23 is the source of the second vertical transistor 20, and the second top electrode 24 is the drain of the second vertical transistor 20; or, the second bottom electrode 23 is the drain of the second vertical transistor 20, and the second top electrode 24 is the source of the second vertical transistor 20. The second bottom electrode 23 is electrically connected to the second bottom electrode 211, and the second top electrode 24 is electrically connected to the second top electrode 213. The second bottom isolation portion 25 is used to insulate the second gate electrode 22 from the second bottom electrode 23, and the second bottom isolation portion 25 is used to insulate the second gate electrode 22 from the second top electrode 24. The second oxide layer pad 28 is used to protect the second top electrode 213 of the second vertical nanosheet 21, and the second insulating structure 27 is used to insulate the surface of the second top electrode 24 and protect the second top electrode 24.

[0145] The height of the second vertical nanosheet 21 is the same as the height of the first vertical nanosheet 11, that is, the surface of the second vertical nanosheet 21 facing away from the protrusion 32 is flush with the surface of the first vertical nanosheet 11 facing away from the protrusion 32. The surface of the second bottom 211 facing away from the protrusion 32 is flush with the surface of the first bottom 111 facing away from the protrusion 32. The surface of the second connecting portion 212 facing away from the second bottom 211 is flush with the surface of the first connecting portion 112 facing away from the first bottom 111. The surface of the second top 213 facing away from the second connecting portion 212 is flush with the surface of the first top 113 facing away from the first connecting portion 112.

[0146] The surface of the second bottom electrode 23 facing away from the protrusion 32 is flush with the surface of the first bottom electrode 13 facing away from the protrusion 32. The surface of the second bottom isolation portion 25 facing away from the second bottom electrode 23 is flush with the surface of the first bottom isolation portion 15 facing away from the first bottom electrode 13. The surface of the second gate electrode 22 facing away from the second bottom isolation portion 25 is flush with the surface of the first gate electrode 12 facing away from the first bottom isolation portion 15. The surface of the second oxide layer pad 28 facing away from the second gate electrode 22 is flush with the surface of the first oxide layer pad 18 facing away from the first gate electrode 12. The surface of the second top isolation portion 26 facing away from the second gate electrode 22 is flush with the surface of the first top isolation portion 16 facing away from the first gate electrode 12. The surface of the second top electrode 24 facing away from the second vertical nanosheet 21 is flush with the surface of the first top electrode 14 facing away from the first vertical nanosheet 11. The surface of the second insulating structure 27 facing away from the second top isolation portion 26 is flush with the surface of the first insulating structure 17 facing away from the first top isolation portion 16.

[0147] In this embodiment, the width of the second vertical nanosheet 21 is smaller than the width of the first vertical nanosheet 11. The width of the vertical nanosheet is its dimension along the X-axis. Specifically, the width of the first bottom 111, the width of the first connecting portion 112, and the width of the first top 113 of the first vertical nanosheet 11 are equal. The width of the second bottom 211, the width of the second connecting portion 212, and the width of the second top 213 of the second vertical nanosheet 21 are equal. That is, the width of the second bottom 211 is smaller than the width of the first bottom 111, the width of the second connecting portion 212 is smaller than the width of the first connecting portion 112, and the width of the second top 213 is smaller than the width of the first top 113. In this application, the width of the first vertical nanosheet 11 is also its critical dimension (CD), and the width of the second vertical nanosheet 21 is also its critical dimension.

[0148] Understandably, because the width of the second connection portion 212 is smaller than the width of the first connection portion 112, the threshold voltage of the second vertical transistor 20 is higher than that of the first vertical transistor 10, thereby making the on-state current of the second vertical transistor 20 smaller than that of the first vertical transistor 10, and the off-state current of the second vertical transistor 20 smaller than that of the first vertical transistor 10. By making the width of the second top portion 213 smaller than the width of the first top portion 113, the semiconductor device 1 provided in this application simultaneously provides a high threshold voltage (Wimpy) transistor and a conventional threshold voltage (Nominal) transistor.

[0149] It is also understandable that the width of the first bottom 111, the width of the first connecting portion 112, and the width of the first top 113 are equal, meaning the width of the entire first vertical nanosheet 11 is consistent. This allows the first vertical nanosheet 11 to be formed in a single process, which helps save costs. Similarly, the width of the second bottom 211, the width of the second connecting portion 212, and the width of the second top 213 are equal, meaning the width of the entire second vertical nanosheet 21 is consistent. This allows the second vertical nanosheet 21 to be formed in a single process, which also helps save costs.

[0150] In an exemplary embodiment, the width of the second connection portion 212 is 1 nm to 4 nm smaller than the width of the first connection portion 112, for example, 1 nm, 1.5 nm, 2 nm, 2.3 nm, 2.5 nm, 2.8 nm, 3 nm, 3.1 nm, 3.4 nm, 3.7 nm, 4 nm, or other values. This application does not impose specific limitations on this. That is, the width difference between the first connection portion 112 and the second connection portion 212 is 1 nm to 4 nm. The fact that the width of the second connection portion 212 is 1 nm to 4 nm smaller than the width of the first connection portion 112 can meet the requirements for adjusting the threshold voltage of the second vertical transistor 20, and can also avoid a reduction in the structural strength of the second connection portion 212 due to the width of the second connection portion 212 being too much smaller than the width of the first connection portion 112. Among them, the threshold voltage adjustment of the second vertical transistor 20 is generally 30 mV.

[0151] In an exemplary embodiment, the width of the second bottom electrode 23 is 1 nm to 4 nm smaller than the width of the first bottom electrode 13, and the width of the second bottom isolation portion 25 is 1 nm to 4 nm smaller than the width of the first bottom isolation portion 15. The width of the second gate 22 is 1 nm to 4 nm smaller than the width of the first gate 12. The width of the second top isolation portion 26 is 1 nm to 4 nm smaller than the width of the first top isolation portion 16. The width of the second top electrode 24 is 1 nm to 4 nm smaller than the width of the first top electrode 14. The width of the second insulating structure 27 is 1 nm to 4 nm smaller than the width of the first insulating structure 17. All widths mentioned in this application refer to the dimension along the X-axis direction.

[0152] In an exemplary embodiment, the width of the first vertical nanosheet 11 is 5 nm to 10 nm, for example, 5 nm, 5.3 nm, 6 nm, 6.8 nm, 7.5 nm, 7.9 nm, 8.1 nm, 8.5 nm, 9 nm, 9.4 nm, 10 nm, or other values, and this application does not impose a specific limitation thereon. The length (dimension in the Y-axis direction) of the first vertical nanosheet 11 can be 15 nm to 30 nm, for example, 15 nm, 17 nm, 20 nm, 22 nm, 26 nm, 27 nm, 30 nm, or other values, and this application does not impose a specific limitation thereon. The height (dimension in the Z-axis direction) of the first vertical nanosheet 11 can be 5 nm to 50 nm, for example, 5 nm, 9 nm, 17 nm, 24 nm, 30 nm, 31 nm, 35 nm, 40 nm, 44 nm, 50 nm, or other values, and this application does not impose a specific limitation thereon.

[0153] It should be noted that the second vertical nanosheet 21 and the first vertical nanosheet 11 may differ only in width in size. The length of the second vertical nanosheet 21 is equal to the length of the first vertical nanosheet 11, and the height of the second vertical nanosheet 21 is equal to the height of the first vertical nanosheet 11.

[0154] It should also be noted that the height of the first vertical nanosheet 11 of the first vertical transistor 10 is equal to the height of the second vertical nanosheet 21 of the second vertical transistor 20. The structure of the first vertical transistor 10 is basically the same as that of the second vertical transistor 20, which maximizes the elimination of the loading effect. The transistor forming process, such as etching process, chemical mechanical polishing process, etc., has little impact on the first vertical transistor 10 and the second vertical transistor 20, thus improving the reliability of the device.

[0155] An interlayer isolation layer 60 covers the first vertical transistor 10 and the second vertical transistor 20 onto the substrate 31. That is, the interlayer isolation layer 60 is disposed on the surface of the substrate 31 facing the Z-axis, the peripheral side of the first vertical transistor 10, the surface of the first vertical transistor 10 facing away from the substrate 31, the peripheral side of the second vertical transistor 20, and the surface of the second vertical transistor 20 facing away from the substrate 31. Specifically, the interlayer isolation layer 60 is disposed on the peripheral side of the protrusion 32, the peripheral side of the first bottom electrode 13, the peripheral side of the first bottom isolation portion 15, the peripheral side of the first gate 12, the peripheral side of the first top isolation portion 16, the peripheral side of the first insulating structure 17, and the surface of the first insulating structure 17 facing away from the first top isolation portion 16. The interlayer isolation layer 60 is also disposed on the peripheral side of the second bottom electrode 23, the peripheral side of the second bottom isolation portion 25, the peripheral side of the second gate 22, the peripheral side of the second top isolation portion 26, the peripheral side of the second insulating structure 27, and the surface of the second insulating structure 27 facing away from the second top isolation portion 26. The interlayer isolation layer 60 is used to insulate the first vertical transistor 10 from the second vertical transistor 20.

[0156] The interlayer separator 60 has a first through hole and a second through hole extending through the interlayer separator 60 along the Z-axis direction, with the first through hole and the second through hole spaced apart. The first insulating structure 17 has a first connecting hole extending through the first insulating structure 17 along the Z-axis direction, with the first top electrode 14 exposed in the first connecting hole, and the first connecting hole communicating with the first through hole. The second insulating structure 27 has a second connecting hole extending through the second insulating structure 27 along the Z-axis direction, with the second top electrode 24 exposed in the second connecting hole, and the second connecting hole communicating with the second through hole.

[0157] The first contact 70 is disposed within the first through hole and the first connecting hole, and the first contact 70 is connected to the first top electrode 14, thereby electrically connecting the first contact 70 to the first top electrode 14. The second contact 80 is disposed within the second through hole and the second connecting hole, and the second contact 80 is connected to the second top electrode 24, thereby electrically connecting the second contact 80 to the second top electrode 24.

[0158] It should be noted that the interlayer separator 60 may also have a third and a fourth through hole extending through the interlayer separator 60 along the Z-axis. The first bottom electrode 13 exposes the third through hole, and the second bottom electrode 23 exposes the fourth through hole. The third through hole accommodates the third contact, and the fourth through hole accommodates the fourth contact. The third contact is connected to and electrically connected to the first bottom electrode 13. The fourth contact is connected to and electrically connected to the second bottom electrode 23.

[0159] A conductive network layer 90 is disposed on the surface of the interlayer isolation layer 60 facing away from the substrate 31, and the conductive network layer 90 is connected to the first contact 70 and the second contact 80 respectively, so that the conductive network layer 90 is electrically connected to the first contact 70 and the second contact 80 respectively. The conductive network layer 90 provides an electrical signal to the first top electrode 14 through the first contact 70 and to the second top electrode 24 through the second contact 80.

[0160] The conductive network layer 90 can also be connected to the third contact and the fourth contact respectively, so that the conductive network layer 90 is electrically connected to the third contact and the fourth contact respectively.

[0161] In summary, the semiconductor device provided in this application includes a first vertical transistor 10 and a second vertical transistor 20. The first vertical transistor 10 includes a first vertical nanosheet 11 and a first gate 12. The first vertical nanosheet 11 includes a first connection portion 112, and the first gate 12 is connected to at least a portion of the peripheral side surface of the first connection portion 112. The second vertical transistor 20 includes a second vertical nanosheet 21 and a second gate 22. The second vertical nanosheet 21 includes a second connection portion 212, and the second gate 22 is connected to at least a portion of the peripheral side surface of the second connection portion 212. The width of the second connection portion 212 is smaller than the width of the first connection portion 112. Therefore, the width of the second connection portion 212 of the second vertical nanosheet 21 is smaller than the width of the first connection portion 112 of the first vertical nanosheet 11, so that the threshold voltage of the second vertical transistor 20 is higher than the threshold voltage of the first vertical transistor 10, thereby making the on-state current of the second vertical transistor 20 less than the on-state current of the first vertical transistor 10, and the off-state current of the second vertical transistor 20 less than the off-state current of the first vertical transistor 10. The semiconductor device 1 provided in this application realizes the simultaneous provision of a high threshold voltage transistor and a conventional threshold voltage transistor.

[0162] This application also provides a method for fabricating a semiconductor device. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a flowchart illustrating a method for fabricating a first layer structure of a semiconductor device disclosed in an embodiment of this application. Figure 4 The method for fabricating the semiconductor device shown is used to form Figure 3 For a description of the similarities between the structure of the semiconductor device 1 and the structure of semiconductor device 1 used in its fabrication method, please refer to the relevant description of semiconductor device 1 above; it will not be repeated here. Please refer to... Figure 3 and Figure 4 The specific steps involved in fabricating semiconductor devices are as follows.

[0163] Step S100: The substrate 210 is formed into a substrate 30, a first vertical nanosheet 11, a second vertical nanosheet 21, and a bottom electrode layer 260. The first vertical nanosheet 11, the second vertical nanosheet 21, and the bottom electrode layer 260 are all located on one surface of the substrate 30. The first vertical nanosheet 11 and the second vertical nanosheet 21 are spaced apart. The bottom electrode layer 260 connects the peripheral surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. The first vertical nanosheet 11 includes a first connecting portion 112, and the second vertical nanosheet 21 includes a second connecting portion 212.

[0164] In step S200, a bottom isolation layer 270, a protective layer 280, a gate replacement layer 290, and a top isolation layer 300 are sequentially formed on the bottom electrode layer 260. The bottom isolation layer 270 is located on the surface of the bottom electrode layer 260 facing away from the substrate 30. The bottom electrode layer 260 connects the peripheral side surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. The protective layer 280 is located on the surface of the bottom isolation layer 270 facing away from the bottom electrode layer 260, as well as the peripheral side surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. The gate replacement layer 290 is located on the surface of the protective layer 280 facing away from the bottom isolation layer 270. The top isolation layer 300 is located on the surface of the gate replacement layer 290 facing away from the bottom isolation layer 270.

[0165] Step S300: A first apex 14 is formed on the surface of the first vertical nanosheet 11 facing away from the substrate 30, and a second apex 24 is formed on the surface of the second vertical nanosheet 21 facing away from the substrate 30. A first insulating structure 17 is formed on the first apex 14, and a second insulating structure 27 is formed on the second apex 24.

[0166] Step S400: Using the first insulating structure 17 and the second insulating structure 27 as masks, remove the portion of the top insulating layer 300 that is offset from the first insulating structure 17 and the second insulating structure 27.

[0167] Step S500: Remove the gate replacement layer 290 and the protective layer 280, exposing the first connecting portion 112 of the first vertical nanosheet 11 and the second connecting portion 212 of the second vertical nanosheet 21.

[0168] In step S600, a first gate 12 is formed on the peripheral side surface of the first connecting portion 112 and a second gate 22 is formed on the peripheral side surface of the second connecting portion 212.

[0169] Step S700: Using the first insulating structure 17 and the second insulating structure 27 as masks, remove the portion of the bottom isolation layer 270 that is offset from the first insulating structure 17 and the second insulating structure 27, and remove the portion of the bottom electrode layer 260 that is offset from the first insulating structure 17 and the second insulating structure 27 to form the first bottom electrode 13 and the second bottom electrode 23. The first bottom electrode 13 is connected to the first vertical nanosheet 11, and the second bottom electrode 23 is connected to the second vertical nanosheet 21. The width of the second connection portion 212 is smaller than the width of the first connection portion 112. The first vertical nanosheet 11, the first gate 12, the first bottom electrode 13 and the first top electrode 14 constitute the first vertical transistor 10, and the second vertical nanosheet 21, the second gate 22, the second bottom electrode 23 and the second top electrode 24 constitute the second vertical transistor 20.

[0170] In step S800, an interlayer isolation layer 60 is formed on the peripheral side surface of the first vertical transistor 10 and the peripheral side surface of the second vertical transistor 20, and the interlayer isolation layer 60 covers the first insulating structure 17 and the second insulating structure 27.

[0171] Step S900: A first through hole and a second through hole are made in the interlayer isolation layer 60, a first connecting hole is made in the first insulating structure 17 and a second connecting hole is made in the second insulating structure 27. The first connecting hole is connected to the first through hole, and the second connecting hole is connected to the second through hole. The first top electrode 14 is exposed through the first connecting hole, and the second top electrode 24 is exposed.

[0172] Step S1000: A first contact 70 is formed in the first through hole and the first connecting hole, and a second contact 80 is formed in the second through hole and the second connecting hole. The first contact 70 is connected to the first top electrode 14, and the second contact 80 is connected to the second top electrode 24.

[0173] Step S1100: A conductive network layer 90 is formed on the surface of the interlayer isolation layer 60 facing away from the substrate 30. The conductive network layer 90 is connected to the first contact 70 and the second contact 80 respectively.

[0174] Understandably, because the width of the second connection portion 212 is smaller than the width of the first connection portion 112, the threshold voltage of the second vertical transistor 20 is higher than that of the first vertical transistor 10, thereby making the on-state current of the second vertical transistor 20 smaller than that of the first vertical transistor 10, and the off-state current of the second vertical transistor 20 smaller than that of the first vertical transistor 10. By making the width of the second top portion 213 smaller than the width of the first top portion 113, the semiconductor device 1 provided in this application simultaneously provides a high threshold voltage (Wimpy) transistor and a conventional threshold voltage (Nominal) transistor.

[0175] In an exemplary embodiment, the width of the second connection portion 212 is 1 nm to 4 nm smaller than the width of the first connection portion 112. The fact that the width of the second connection portion 212 is 1 nm to 4 nm smaller than the width of the first connection portion 112 can meet the threshold voltage adjustment requirements of the second vertical transistor 20, and also avoids a reduction in the structural strength of the second connection portion 212 due to the width being too much smaller than the width of the first connection portion 112.

[0176] Please see Figure 5 , Figure 5 for Figure 4 The diagram shows a flowchart of step S100 of the method for fabricating a semiconductor device.

[0177] Step S110: A barrier layer 220, a passivation layer 230, a first pad 251, and a second pad 252 are sequentially formed on a substrate 210. The barrier layer 220 is located on one surface of the substrate 210, the passivation layer 230 is located on the surface of the barrier layer 220 facing away from the substrate 210, and the first pad 251 and the second pad 252 are both located on the surface of the passivation layer 230 facing away from the barrier layer 220. The first pad 251 and the second pad 252 are spaced apart, wherein the width of the second pad 252 is smaller than the width of the first pad 251.

[0178] Please see Figure 6 , Figure 6 for Figure 5 The diagram shows a flowchart of step S110 of the method for fabricating a semiconductor device.

[0179] Step S111: A barrier layer 220, a passivation layer 230 and a crystal layer 240 are sequentially formed on a substrate 210. The barrier layer 220 is located on one surface of the substrate 210, the passivation layer 230 is located on the surface of the barrier layer 220 opposite to the substrate 210, and the crystal layer 240 is located on the surface of the passivation layer 230 opposite to the barrier layer 220.

[0180] Specifically, please refer to Figure 7 , Figure 7 for Figure 6 The schematic diagram of the structure formed corresponding to step S111 is shown. A barrier layer 220 is formed on one surface of the substrate 210 by a deposition process. A passivation layer 230 is formed on the surface of the barrier layer 220 opposite to the substrate 210 by a deposition process. A crystalline layer 240 is formed on the surface of the passivation layer 230 opposite to the barrier layer 220. The barrier layer 220 is made of silicon nitride (SiN), the passivation layer 230 is made of silicon dioxide (SiO2), and the crystalline layer 240 is made of amorphous silicon (a-Si).

[0181] Step S112: Remove part of the crystal layer 240 to form a crystal structure 241, and expose the crystal structure 241 on part of the passivation layer 230 facing away from the barrier layer 220.

[0182] Specifically, please refer to Figure 8 , Figure 8 for Figure 6 The schematic diagram of the structure formed corresponding to step S112 is shown. A photolithography layer is formed on the surface of the crystal layer 240 opposite to the passivation layer 230. The crystal layer 240 is etched to form a crystal structure 241 by photolithography. The part of the passivation layer 230 opposite to the barrier layer 220 is not blocked by the crystal structure 241.

[0183] Step S113: Form a pad layer 250 on the surface of the passivation layer 230 opposite to the barrier layer 220.

[0184] Specifically, please refer to Figure 9 , Figure 9 for Figure 6 The schematic diagram shows the structure formed in step S113. A spacer layer 250 is formed on the surface of the passivation layer 230 opposite to the barrier layer 220 using atomic layer deposition (ALD). The spacer layer 250 is connected to and covers the peripheral side surface of the crystal structure 241. The material of the spacer layer 250 includes silicon nitride.

[0185] Step S114: Form a first gasket 251 and a second gasket 252 from the gasket layer 250. Both the first gasket 251 and the second gasket 252 are connected to the peripheral side of the crystal structure 241, and the first gasket 251 and the second gasket 252 are spaced apart.

[0186] Specifically, please refer to Figure 10 , Figure 10 for Figure 6 The schematic diagram shows the structure formed in step S114. A portion of the pad layer 250 is removed by etching to form a first pad 251 and a second pad 252, located on the surface of the passivation layer 230 opposite to the barrier layer 220. The first pad 251 and the second pad 252 have equal widths. The width of the first pad 251 can be from 10 nm to 20 nm, and the width of the second pad 252 can also be from 10 nm to 20 nm, for example, 10 nm, 11 nm, 14 nm, 15 nm, 18 nm, 20 nm, or other values; this application does not impose specific limitations on these values.

[0187] Step S115, Remove crystal structure 241.

[0188] Specifically, please refer to Figure 11 , Figure 11 for Figure 6 The schematic diagram of the structure formed corresponding to step S115 is shown. The crystal structure 241 is removed by etching with a high selectivity.

[0189] Step S116: Modify the second gasket 252, the width of the second gasket 252 is smaller than the width of the first gasket 251.

[0190] Specifically, please refer to Figure 12 , Figure 12 for Figure 6 The schematic diagram of the structure formed corresponding to step S116 is shown. Photoresist covers the first pad 251. The second pad 252 is modified by an etching process, reducing its width by 1 nm to 4 nm. The width of the second pad 252 is 1 nm to 4 nm smaller than the width of the first pad 251, for example, 1 nm, 1.5 nm, 2 nm, 2.2 nm, 2.5 nm, 2.9 nm, 3 nm, 3.3 nm, 3.7 nm, 4 nm, or other values. This application does not impose specific limitations on this.

[0191] Understandably, by making the width of the second spacer 252 smaller than the width of the first spacer 251, the width of the formed second vertical nanosheet 21 is smaller than the width of the first vertical nanosheet 11. The second vertical nanosheet 21 and the first vertical nanosheet 11 can be formed in a single process, simplifying the semiconductor device fabrication process and saving costs. Furthermore, limiting the width of the first vertical nanosheet 11 with the first spacer 251 and the width of the second vertical nanosheet 21 with the second spacer 252 helps improve the accuracy of the width of both the first and second vertical nanosheets.

[0192] Step S120: Using the first pad 251 and the second pad 252 as masks, remove the portion of the passivation layer 230 that is misaligned with the first pad 251 and the second pad 252, remove the portion of the barrier layer 220 that is misaligned with the first pad 251 and the second pad 252, and etch the substrate 210 to form the substrate transition layer 30a, the first vertical nanosheet 11 and the second vertical nanosheet 21.

[0193] It should be noted that "offset" refers to not coinciding in the Z-axis direction. For example, the offset part between A and B means that this part of A does not coincide with B in the Z-axis direction.

[0194] Specifically, please refer to Figure 13 , Figure 13 for Figure 5The schematic diagram of the structure formed corresponding to step S120 is shown. Using the first pad 251 and the second pad 252 as masks, the portion of the passivation layer 230 that is offset from the first pad 251 and the second pad 252 is removed by etching process to form the first passivation structure 231 and the second passivation structure 232. The portion of the barrier layer 220 that is offset from the first pad 251 and the second pad 252 is removed by etching process to form the first barrier structure 221 and the second barrier structure 222. The substrate 210 is etched downward by etching process to form the substrate transition layer 30a, the first vertical nanosheet 11 and the second vertical nanosheet 21.

[0195] In this design, a first vertical nanosheet 11 and a second vertical nanosheet 21 are located on one surface of the substrate transition layer 30a. A first barrier structure 221, a first passivation structure 231, and a first spacer 251 are sequentially stacked on the surface of the first vertical nanosheet 11 facing away from the substrate transition layer 30a. A second barrier structure 222, a second passivation structure 232, and a second spacer 252 are sequentially stacked on the surface of the second vertical nanosheet 21 facing away from the substrate transition layer 30a. The peripheral side surface of the first vertical nanosheet 11 is aligned with the peripheral side surface of the first spacer 251, and the peripheral side surface of the second vertical nanosheet 21 is aligned with the peripheral side surface of the second spacer 252. The width of the first vertical nanosheet 11 is equal to the width of the first spacer 251, and the width of the second vertical nanosheet 21 is equal to the width of the second spacer 252. That is, the width of the second vertical nanosheet 21 is 1 nm to 4 nm smaller than the width of the first vertical nanosheet 11.

[0196] Step S130: Ions are implanted into the substrate transition layer 30a to form the substrate 30 and the bottom layer 260.

[0197] Specifically, please refer to Figure 14 , Figure 14 for Figure 5 The schematic diagram of the structure formed corresponding to step S130 is shown. Ions are implanted into the substrate transition layer 30a to form a substrate 30 and a bottom layer 260. The first vertical nanosheet 11 and the second vertical nanosheet 21 are located on one surface of the substrate 30. The bottom layer 260 connects the peripheral surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. After the bottom layer 260 is formed, the first pad 251, the second pad 252, the first passivation structure 231, and the second passivation structure 232 are removed.

[0198] In other embodiments, the bottom layer 260 can also be formed by selecting an epitaxial process, and this application does not impose specific limitations on this.

[0199] Please see Figure 15 , Figure 15 for Figure 4 The diagram shows a flowchart of step S200 of the method for fabricating a semiconductor device.

[0200] Step S210: A bottom isolation layer 270 is formed on the surface of the bottom layer 260 facing away from the substrate 30.

[0201] Specifically, please refer to Figure 16 , Figure 16 for Figure 15 The schematic diagram shows the structure formed in step S210. A bottom isolation layer 270 is formed on the surface of the bottom electrode layer 260 facing away from the substrate 30 using a dielectric filling process. The bottom isolation layer 270 surrounds the peripheral surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. After forming the bottom isolation layer 270, the surface of the bottom isolation layer 270 facing away from the bottom electrode layer 260 is smoothed using a chemical mechanical planarization (CMP) process, a recess process, or an oxidation process.

[0202] Understandably, smoothing the surface of the bottom insulating layer 270 opposite to the bottom electrode layer 260 can improve the quality of the layer structure formed on the surface of the bottom insulating layer 270.

[0203] Step S220: A protective layer 280 is formed on the surface of the bottom isolation layer 270 opposite to the bottom electrode layer 260.

[0204] Specifically, please refer to Figure 17 , Figure 17 for Figure 15 The schematic diagram of the structure formed corresponding to step S220 is shown. A protective layer 280 is formed on the surface of the bottom isolation layer 270 opposite to the bottom electrode layer 260 by a thermal oxidation process or an atomic deposition process. The protective layer 280 connects the peripheral side surface of the first vertical nanosheet 11, the peripheral side surface of the second vertical nanosheet 21, the peripheral side surface of the first barrier structure 221, the peripheral side surface of the second barrier structure 222, the surface of the first barrier structure 221 opposite to the first vertical nanosheet 11, and the surface of the second barrier structure 222 opposite to the second vertical nanosheet 21.

[0205] Understandably, the protective layer 280 is used to protect the first vertical nanosheet 11 and the second vertical nanosheet 21, to avoid loss of the first vertical nanosheet 11 and the second vertical nanosheet 21 due to subsequent processes, and to improve the quality of the first vertical nanosheet 11 and the second vertical nanosheet 21.

[0206] Step S230: A gate replacement layer 290 is formed on the surface of the protective layer 280 opposite to the bottom isolation layer 270.

[0207] Specifically, please refer to Figure 18 , Figure 18 for Figure 15The schematic diagram shows the structure formed in step S230. A gate replacement layer 290 is formed on the surface of the protective layer 280 opposite to the bottom isolation layer 270 using a filling process. The gate replacement layer 290 surrounds the peripheral side of the protective layer 280 opposite to the first vertical nanosheet 11 and the peripheral side of the protective layer 280 opposite to the second vertical nanosheet 21. The material of the gate replacement layer 290 includes amorphous silicon. After forming the gate replacement layer 290, the surface of the gate replacement layer 290 opposite to the bottom isolation layer 270 is planarized using a chemical mechanical polishing process, a re-etching process, or an oxidation process.

[0208] Understandably, smoothing the surface of the gate replacement layer 290 facing away from the bottom isolation layer 270 can improve the quality of the layer structure formed on the surface of the gate replacement layer 290.

[0209] Step S240: A top isolation layer 300 is formed on the surface of the gate replacement layer 290 opposite to the bottom isolation layer 270.

[0210] Specifically, please refer to Figure 19 , Figure 19 for Figure 15 The schematic diagram corresponding to step S240 is shown. A top isolation layer 300 is formed on the surface of the gate replacement layer 290 opposite to the bottom isolation layer 270 through a filling process. The top isolation layer 300 surrounds the peripheral side of the protective layer 280 opposite to the first vertical nanosheet 11 and the peripheral side of the protective layer 280 opposite to the second vertical nanosheet 21. The material of the top isolation layer 300 includes silicon oxide (SiO2) and silicon carbide (SiOC). After the top isolation layer 300 is formed, the surface of the top isolation layer 300 opposite to the gate replacement layer 290 is flattened by a chemical mechanical polishing process, a re-etching process, or an oxidation process. The surface of the top isolation layer 300 opposite to the gate replacement layer 290 is flush with the surface of the first vertical nanosheet 11 opposite to the substrate 30 and the surface of the second vertical nanosheet 21 opposite to the substrate 30.

[0211] Please see Figure 20 , Figure 20 for Figure 4 The diagram shows a flowchart of step S300 of the method for fabricating a semiconductor device.

[0212] Step S310: A first sidewall structure 310 is formed on the peripheral side of the protective layer 280 facing away from the first blocking structure 221, and a second sidewall structure 320 is formed on the peripheral side of the protective layer 280 facing away from the second blocking structure 222.

[0213] Specifically, please refer to Figure 21 , Figure 21 for Figure 20The schematic diagram of the structure formed in step S310 is shown. A first sidewall structure 310 is formed on the peripheral side of the protective layer 280 facing away from the first barrier structure 221 by atomic layer deposition (ALD) conformal deposition process, and a second sidewall structure 320 is formed on the peripheral side of the protective layer 280 facing away from the second barrier structure 222.

[0214] In an exemplary embodiment, the wall thickness of the first sidewall structure 310 is the same as the wall thickness of the second sidewall structure 320. Since the width of the second blocking structure 222 is 1 nm to 4 nm smaller than the width of the first blocking structure 221, the width of the second sidewall structure 320 is 1 nm to 4 nm smaller than the width of the first sidewall structure 310.

[0215] Step S320: A dielectric layer 330 is formed on the surface of the top isolation layer 300 opposite to the gate replacement layer 290.

[0216] Specifically, please refer to Figure 22 , Figure 22 for Figure 20 The schematic diagram corresponding to step S320 is shown. A dielectric layer 330 is formed on the surface of the top isolation layer 300 opposite to the gate replacement layer 290 through a filling process. The dielectric layer 330 connects the peripheral side surface of the first sidewall structure 310 and the peripheral side surface of the second sidewall structure 320. The material of the dielectric layer 330 includes silicon dioxide. After the dielectric layer 330 is formed, the surface of the dielectric layer 330 opposite to the top isolation layer 300 is planarized by a chemical mechanical polishing process, so that the surface of the dielectric layer 330 opposite to the top isolation layer 300 is flush with the surfaces of the first sidewall structure 310 and the second sidewall structure 320 opposite to the top isolation layer 300.

[0217] Step S330: Remove the first blocking structure 221, the protective layer 280 on the periphery of the first blocking structure 221, the first sidewall structure 310, the second blocking structure 222, and the protective layer 280 and the second sidewall structure 320 on the periphery of the second blocking structure 222.

[0218] Specifically, please refer to Figure 23 , Figure 23 for Figure 20 The schematic diagram shows the structure formed corresponding to step S330. The first barrier structure 221, the protective layer 280 on the periphery of the first barrier structure 221, the first sidewall structure 310, the second barrier structure 222, and the protective layer 280 and second sidewall structure 320 on the periphery of the second barrier structure 222 are removed by dry etching or wet etching. The surface of the first vertical nanosheet 11 facing away from the substrate 30 is exposed, and the surface of the second vertical nanosheet 21 facing away from the substrate 30 is also exposed.

[0219] Step S340: A first apex 14 is formed on the surface of the first vertical nanosheet 11 facing away from the substrate 30, and a second apex 24 is formed on the surface of the second vertical nanosheet 21 facing away from the substrate 30.

[0220] Specifically, please refer to Figure 24 , Figure 24 for Figure 20 The schematic diagram shows the structure formed corresponding to step S340. A first apex 14 is formed on the surface of the first vertical nanosheet 11 facing away from the substrate 30 using either vapor phase epitaxy or solid phase epitaxy. A second apex 24 is formed on the surface of the second vertical nanosheet 21 facing away from the substrate 30. The first apex 14 is connected to the dielectric layer 330, and the second apex 24 is also connected to the dielectric layer 330. The material of the first apex 14 includes boron-doped germanium-silicon or phosphorus-doped silicon, and the material of the second apex 24 includes boron-doped germanium-silicon or phosphorus-doped silicon.

[0221] Step S350: A first insulating portion 171 is formed on the surface of the first top electrode 14 opposite to the first vertical nanosheet 11, and a second insulating portion 271 is formed on the surface of the second top electrode 24 opposite to the second vertical nanosheet 21.

[0222] Specifically, please refer to Figure 25 , Figure 25 for Figure 20 The diagram shows the structure formed corresponding to step S350. A first insulating portion 171 is formed on the surface of the first top electrode 14 opposite to the first vertical nanosheet 11 through a filling process. A second insulating portion 271 is formed on the surface of the second top electrode 24 opposite to the second vertical nanosheet 21. The first insulating portion 171 is connected to the dielectric layer 330, and the second insulating portion 271 is also connected to the dielectric layer 330. The surface of the first insulating portion 171 opposite to the first top electrode 14 is connected to and flush with the surface of the dielectric layer 330 opposite to the top isolation layer 300. The surface of the second insulating portion 271 opposite to the second top electrode 24 is connected to and flush with the surface of the dielectric layer 330 opposite to the top isolation layer 300. The peripheral side surface of the first insulating portion 171 is connected to and flush with the peripheral side surface of the first top electrode 14, and the peripheral side surface of the second insulating portion 271 is connected to and flush with the peripheral side surface of the second top electrode 24. The material of both the first insulating portion 171 and the second insulating portion 271 is silicon nitride.

[0223] Step S360: Remove the dielectric layer 330, exposing the peripheral side surface of the first top electrode 14 and the peripheral side surface of the second top electrode 24.

[0224] Specifically, please refer to Figure 26 , Figure 26 for Figure 20The schematic diagram of the structure formed corresponding to step S360 is shown. The dielectric layer 330 is removed, exposing the peripheral side surfaces of the first top electrode 14 and the second top electrode 24, the peripheral side surfaces of the first insulating portion 171 and the second insulating portion 271, and a portion of the surface of the top insulating layer 300 facing away from the gate replacement layer 290.

[0225] In step S370, a third insulating portion 172 is formed on the peripheral side of the first top electrode 14, and a fourth insulating portion 272 is formed on the peripheral side of the second top electrode 24.

[0226] Specifically, please refer to Figure 27 , Figure 27 for Figure 20 The schematic diagram of the structure formed corresponding to step S370 is shown. A third insulating portion 172 is formed on the peripheral side of the first apex 14 and a fourth insulating portion 272 is formed on the peripheral side of the second apex 24 by atomic deposition conformal growth process. The third insulating portion 172 is also connected to the peripheral side of the first insulating portion 171, and the fourth insulating portion 272 is also connected to the peripheral side of the second insulating portion 271.

[0227] In an exemplary embodiment, the first insulating portion 171 and the third insulating portion 172 constitute a first insulating structure 17, and the third insulating portion 172 and the fourth insulating portion 272 constitute a second insulating structure 27. The first insulating structure 17 protects the first top electrode 14 from being etched in subsequent processes. The second insulating structure 27 protects the second top electrode 24 from being etched in subsequent processes.

[0228] Please see Figure 28 , Figure 28 for Figure 4 The schematic diagram shows the structure formed corresponding to step S400. Specifically, using the first insulating structure 17 and the second insulating structure 27 as masks, the portion of the top insulating layer 300 that is offset from the first insulating structure 17 and the second insulating structure 27 is removed to form the first top insulating portion 16 and the second top insulating portion 26. The first top insulating portion 16 and the second top insulating portion 26 are spaced apart. The first top insulating portion 16 is connected to the first top electrode 14, and the second top insulating portion 26 is connected to the second top electrode 24.

[0229] Please see Figure 29 , Figure 29 for Figure 4The schematic diagram of the structure formed corresponding to step S500 is shown. Specifically, the gate replacement layer 290 is removed by a wet etching process, and the protective layer 280 on the peripheral side of the first connection portion 112, the protective layer 280 on the peripheral side of the second connection portion 212, and the protective layer of the bottom isolation layer 270 facing away from the surface of the bottom electrode layer 260 are removed to form the first oxide layer pad 18 and the second oxide layer pad 28. The first connection portion 112 of the first vertical nanosheet 11 and the first connection portion 112 of the second vertical nanosheet 21 are exposed.

[0230] In an exemplary embodiment, a first oxide layer liner 18 surrounds the peripheral side surface of a first top 113, and a second oxide layer liner 28 surrounds the peripheral side surface of a second top 213. A first top insulating portion 16 surrounds the peripheral side surface of the first oxide layer liner 18, and a second top insulating portion 26 surrounds the peripheral side surface of the second oxide layer liner 28.

[0231] Please see Figure 30 , Figure 30 for Figure 4 The schematic diagram of step S600 of the method for fabricating a semiconductor device shown includes the following steps.

[0232] Step S610: A gate layer 350 is formed on the exposed peripheral side surface of the first vertical nanosheet 11 and the exposed peripheral side surface of the second vertical nanosheet 21.

[0233] Specifically, please refer to Figure 31 , Figure 31 for Figure 30 The schematic diagram shows the structure formed in step S610. An interface layer (IL), a high-k dielectric layer, and a metal layer are sequentially formed on the exposed peripheral surfaces of the first vertical nanosheet 11 and the second vertical nanosheet 21. The interface layer, the high-k dielectric layer, and the metal layer constitute the gate layer 350. After forming the gate layer 350, the surface of the gate layer 350 facing away from the bottom isolation layer 270 is smoothed by a chemical mechanical polishing process, so that the surface of the gate layer 350 facing away from the bottom isolation layer 270, the surface of the first insulating structure 17 facing away from the first top isolation portion 16, and the surface of the second insulating structure 27 facing away from the second top isolation portion 26 are flush.

[0234] Step S620: Using the first insulating structure 17 and the second insulating structure 27 as masks, remove the portion of the gate layer 350 that is offset from the first insulating structure 17 and the second insulating structure 27 to form the first gate 12 and the second gate 22. The first gate 12 is connected to the peripheral side of the first connection portion 112 of the first vertical nanosheet 11, and the second gate 22 is connected to the peripheral side of the second connection portion 212 of the second vertical nanosheet 21.

[0235] Specifically, please refer to Figure 32 , Figure 32 for Figure 30 The schematic diagram of the structure formed corresponding to step S620 is shown. Using the first insulating structure 17 and the second insulating structure 27 as masks, the gate layer 350 is formed into the first gate 12 and the second gate 22 through a self-aligned process. The first gate 12 is connected to the surface of the first top isolation portion 16 facing away from the first top electrode 14, and the second gate 22 is connected to the surface of the second top isolation portion 26 facing away from the second top electrode 24.

[0236] Please see Figure 33 , Figure 33 for Figure 4 The schematic diagram of the structure formed corresponding to step S700 is shown. Specifically, using the first insulating structure 17 and the second insulating structure 27 as masks, the portion of the bottom insulating layer 270 that is offset from the first insulating structure 17 and the second insulating structure 27 is removed to form the first bottom insulating portion 15 and the second bottom insulating portion 25, and the portion of the bottom electrode layer 260 that is offset from the first insulating structure 17 and the second insulating structure 27 is removed to form the first bottom electrode 13 and the second bottom electrode 23.

[0237] In an exemplary embodiment, the first bottom isolation portion 15 connects the peripheral side surface of the first vertical nanosheet 11 and the surface of the first gate 12 opposite to the first top isolation portion 16, and the second bottom isolation portion 25 connects the peripheral side surface of the second vertical nanosheet 21 and the surface of the second gate 22 opposite to the second top isolation portion 26. The first bottom electrode 13 connects the peripheral side surface of the first vertical nanosheet 11 and the surface of the first bottom isolation portion 15 opposite to the first gate 12, and the second bottom electrode 23 connects the peripheral side surface of the second vertical nanosheet 21 and the surface of the second bottom isolation portion 25 opposite to the second gate 22.

[0238] The first vertical nanosheet 11, the first gate 12, the first bottom electrode 13, the first top electrode 14, the first bottom isolation portion 15, the first top isolation portion 16, the first insulating structure 17, and the first oxide layer pad 18 constitute the first vertical transistor 10. The second vertical nanosheet 21, the second gate 22, the second bottom electrode 23, the second top electrode 24, the second bottom isolation portion 25, the second top isolation portion 26, the second insulating structure 27, and the second oxide layer pad 28 constitute the second vertical transistor 20.

[0239] Understandably, in order to completely remove the portion of the bottom layer 260 that is offset from the first insulating structure 17 and the second insulating structure 27, the substrate 30 is etched downwards to form the substrate 31 and the protrusion 32. This application does not impose a specific limitation on the depth of the downward etching.

[0240] Please see Figure 34 , Figure 34 for Figure 4The schematic diagram corresponding to step S800 is shown. Specifically, an interlayer isolation layer 60 is formed on the peripheral side surface of the first vertical transistor 10 and the peripheral side surface of the second vertical transistor 20. The interlayer isolation layer 60 connects the peripheral side surface of the protrusion 32, the peripheral side surface of the first bottom electrode 13, the peripheral side surface of the first bottom isolation portion 15, the peripheral side surface of the first gate 12, the peripheral side surface of the first top isolation portion 16, the peripheral side surface of the first insulating structure 17, and the surface of the first insulating structure 17 facing away from the first top isolation portion 16. The interlayer isolation layer 60 also connects the peripheral side surface of the second bottom electrode 23, the peripheral side surface of the second bottom isolation portion 25, the peripheral side surface of the second gate 22, the peripheral side surface of the second top isolation portion 26, the peripheral side surface of the second insulating structure 27, and the surface of the second insulating structure 27 facing away from the second top isolation portion 26.

[0241] Please see Figure 35 , Figure 35 for Figure 4 The schematic diagram shows the structure formed corresponding to step S900. Specifically, a first through-hole and a second through-hole are formed in the interlayer isolation layer 60, a first connecting hole is formed in the first insulating structure 17, and a second connecting hole is formed in the second insulating structure 27. The centerline of the first connecting hole is parallel to the centerline of the first through-hole, and the first connecting hole is connected to the first through-hole. The centerline of the second connecting hole is parallel to the centerline of the second through-hole, and the second connecting hole is connected to the second through-hole. The first connecting hole is exposed on the surface of the first top electrode 14 facing away from the first vertical nanosheet 11, and the second connecting hole is exposed on the surface of the second top electrode 24 facing away from the second vertical nanosheet 21.

[0242] Please see Figure 36 , Figure 36 for Figure 4 The schematic diagram of the structure formed corresponding to step S1000 is shown. Specifically, a first contact 70 is formed in the first through hole and the first connecting hole, and a second contact 80 is formed in the second through hole and the second connecting hole. The first contact 70 is connected to the first top electrode 14, and the second contact 80 is connected to the second top electrode 24.

[0243] It should be noted that when making the first and second through holes, the third and fourth through holes can also be made simultaneously, with the first bottom electrode 13 exposed through the third through hole and the second bottom electrode 23 exposed through the fourth through hole. When forming the first contact 70 and the second contact 80, the third contact can also be formed in the third through hole and the fourth contact can also be formed in the fourth through hole simultaneously, with the third contact connected to the first bottom electrode 13 and the fourth contact connected to the second bottom electrode 23.

[0244] Please see Figure 37 , Figure 37 for Figure 4The schematic diagram shows the structure formed corresponding to step S1100. A conductive network layer 90 is formed on the surface of the interlayer isolation layer 60 facing away from the substrate 30. The conductive network layer 90 is connected to the first contact 70 and the second contact 80, respectively.

[0245] It should be noted that the conductive network layer 90 can also be connected to the third contact and the fourth contact respectively, and the conductive network layer 90 is electrically connected to the third contact and the fourth contact respectively.

[0246] Please see Figure 38 , Figure 38 This is a schematic diagram of a second layer structure of the semiconductor device disclosed in the embodiments of this application. The difference between the semiconductor device with the second layer structure and the semiconductor device with the first layer structure is that the second vertical nanosheet 21 of the semiconductor device with the second layer structure is different from the second vertical nanosheet 21 of the semiconductor device with the first layer structure. For a description of the structural similarities between the semiconductor device with the second layer structure and the semiconductor device with the first layer structure, please refer to the relevant description of the semiconductor device with the first layer structure, which will not be repeated here.

[0247] In this embodiment, the peripheral side surface of the second connecting portion 212 is not flush with the peripheral side surface of the second bottom portion 211, and the peripheral side surface of the second connecting portion 212 is not flush with the peripheral side surface of the second top portion 213. The peripheral side surface of the second bottom portion 211 is flush with the peripheral side surface of the second top portion 213. The peripheral side surface of the second bottom portion 211 extends beyond the peripheral side surface of the second connecting portion 212, and the peripheral side surface of the second top portion 213 extends beyond the peripheral side surface of the second connecting portion 212.

[0248] The width of the second connection portion 212 is 1nm to 4nm smaller than the width of the second bottom portion 211, and the width of the second connection portion 212 is 1nm to 4nm smaller than the width of the second top portion 213. This can meet the threshold voltage adjustment requirements of the second vertical transistor 20, and can also avoid the structural strength of the second connection portion 212 being reduced due to the width of the second connection portion 212 being too much smaller than the width of the second bottom portion 211 and the width of the second top portion 213.

[0249] In an exemplary embodiment, the width of the second connection portion 212 is 1 nm to 4 nm smaller than the width of the first connection portion 112. The width of the second bottom electrode 23 is equal to the width of the first bottom electrode 13, and the width of the second bottom isolation portion 25 is equal to the width of the first bottom isolation portion 15. The width of the second gate electrode 22 is equal to the width of the first gate electrode 12. The width of the second top isolation portion 26 is equal to the width of the first top isolation portion 16. The width of the second top electrode 24 is equal to the width of the first top electrode 14. The width of the second insulating structure 27 is equal to the width of the first insulating structure 17. All widths mentioned in this application refer to the dimension along the X-axis direction.

[0250] Understandably, by simply reducing the width of the second connection portion 212 of the second vertical nanosheet 21, it is possible to avoid the increase in contact resistance between the second bottom 211 and the second bottom electrode 23 caused by the reduction in the width of the second bottom 211, and to avoid the increase in contact resistance between the second top 213 and the second top electrode 24 caused by the reduction in the width of the second top 213.

[0251] This application also provides a second method for fabricating a semiconductor device, used to form... Figure 38 The semiconductor device 1 shown. The second semiconductor device manufacturing method includes steps S100', S200', S300', S400', S500', S600', S700', S800', S900', S1000', S1100' and S1200'.

[0252] In this embodiment of the application, please refer to the description of step S100 for the specific scheme of step S100. Step S100' includes steps S110', S120' and S130'.

[0253] In step S110', a barrier layer 220, a passivation layer 230, a first pad 251, and a second pad 252 are sequentially formed on the substrate 210. The barrier layer 220 is located on one surface of the substrate 210, the passivation layer 230 is located on the surface of the barrier layer 220 opposite to the substrate 210, and both the first pad 251 and the second pad 252 are located on the surface of the passivation layer 230 opposite to the barrier layer 220, with the first pad 251 and the second pad 252 spaced apart. The width of the second pad 252 is equal to the width of the first pad 251.

[0254] Step S110' includes steps S111', S112', S113', S114', and S115'. For details on step S111', please refer to the description of step S111; for details on step S112', please refer to the description of step S112; for details on step S113', please refer to the description of step S113; for details on step S114', please refer to the description of step S114; and for details on step S115', please refer to the description of step S115.

[0255] It should be noted that the process of modifying the second gasket 252 is not performed in step S110'. Therefore, the width of the second gasket 252 is equal to the width of the first gasket 251.

[0256] For details on step S120', please refer to the description of step S120; for details on step S130', please refer to the description of step S130.

[0257] It should be noted that since the width of the second pad 252 is equal to the width of the first pad 251, the first vertical nanosheet 11 and the second vertical nanosheet 21 formed by etching the substrate 210 using the first pad 251 and the second pad 252 as masks in step S120' have a width equal to the width of the second vertical nanosheet 21. That is, the widths of the first bottom 111, the first connecting portion 112, and the first top 113 of the first vertical nanosheet 11 are all equal to the widths of the second bottom 211, the second connecting portion 212, and the second top 213 of the second vertical nanosheet 21.

[0258] In this embodiment of the application, please refer to the description of step S200 for the specific scheme of step S200. Step S200' includes steps S210', S220', S230', S230' and S240'. Please refer to the description of step S210' for the specific scheme of step S210', S220' for the specific scheme of step S220', S230' for the specific scheme of step S230', and S240' for the specific scheme of step S240'.

[0259] In this embodiment of the application, the specific scheme of step S300' is described in the description of step S300. Step S300' includes steps S310', S320', S330', S340', S350', S360', and S370'. The specific scheme of step S310' is described in the description of step S310, the specific scheme of step S320' is described in the description of step S320, the specific scheme of step S330' is described in the description of step S330, the specific scheme of step S340' is described in the description of step S340, the specific scheme of step S350' is described in the description of step S350, the specific scheme of step S360' is described in the description of step S360, and the specific scheme of step S370' is described in the description of step S370.

[0260] In this application embodiment, please refer to the description of step S400 for the specific scheme of step S400', and please refer to the description of step S500 for the specific scheme of step S500'.

[0261] Step S600': Modify the second connecting portion 212 of the second vertical nanosheet 21 so that the width of the second connecting portion 212 is smaller than the width of the first connecting portion 112.

[0262] Please see Figure 39 , Figure 39 This is a flowchart illustrating step S600' of a method for fabricating a second layer structure of a semiconductor device.

[0263] Step S610': A protective structure 360 ​​is formed on the peripheral side of the first connecting portion 112 of the first vertical nanosheet 11.

[0264] Specifically, please refer to Figure 40 , Figure 40 for Figure 39 The schematic diagram of the structure formed corresponding to step S610' is shown. A protective structure 360 ​​is formed on the peripheral side of the first connecting portion 112 of the first vertical nanosheet 11. The protective structure 360 ​​surrounds the peripheral side of the first connecting portion 112, the peripheral side of the first top isolation portion 16, the peripheral side of the first insulating structure 17, and the surface of the first insulating structure 17 facing away from the first top isolation portion 16.

[0265] Step S620': Modify the second connecting portion 212 to reduce the width of the second connecting portion 212.

[0266] Specifically, please refer to Figure 41 , Figure 41 for Figure 39 The schematic diagram of the structure formed corresponding to step S620' is shown. The width of the second connection portion 212 is reduced by etching. The second vertical nanosheet 21 also includes a second bottom 211 and a second top 213. The second bottom 211 and the second top 213 are respectively connected to the opposite ends of the second connection portion 212. The second bottom 211 is connected to the bottom electrode layer 260, and the second top electrode 24 is connected to the second top 213. The width of the second connection portion 212 is smaller than the width of the second bottom 211, and the width of the second connection portion 212 is smaller than the width of the second top 213.

[0267] In an exemplary embodiment, the width of the second connecting portion 212 is 1 nm to 4 nm less than the width of the second bottom portion 211, and the width of the second connecting portion 212 is 1 nm to 4 nm less than the width of the second top portion 213.

[0268] Step S630': Remove the protective structure 360, exposing the first connecting portion 112 of the first vertical nanosheet 11.

[0269] In this embodiment of the application, the specific scheme of step S700' is described in the description of step S600. Step S700' includes steps S710' and S720'. The specific scheme of step S710' is described in the description of step S610, and the specific scheme of step S720' is described in the description of step S620. The specific scheme of step S800' is described in the description of step S700, the specific scheme of step S900' is described in the description of step S800, the specific scheme of step S1000' is described in the description of step S900, the specific scheme of step S1100' is described in the description of step S1000, and the specific scheme of step S1200' is described in the description of step S1100.

[0270] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A semiconductor device, characterized in that, Includes a first vertical transistor and a second vertical transistor; The first vertical transistor includes a first vertical nanosheet, a first gate, a first bottom electrode, and a first top electrode. The first gate, the first bottom electrode, and the first top electrode are spaced apart from each other. The first vertical nanosheet includes a first connecting portion. The first gate is connected to at least a portion of the peripheral side of the first connecting portion. The first bottom electrode is connected to the first vertical nanosheet. The first top electrode is connected to the first vertical nanosheet. The second vertical transistor includes a second vertical nanosheet, a second gate, a second bottom electrode, and a second top electrode. The second gate, the second bottom electrode, and the second top electrode are spaced apart from each other. The second vertical nanosheet includes a second connecting portion. The second gate is connected to at least a portion of the peripheral side of the second connecting portion. The second bottom electrode is connected to the second vertical nanosheet. The second top electrode is connected to the second vertical nanosheet. Wherein, the dimension of the second connection portion in the first direction is smaller than the dimension of the first connection portion in the first direction, and the first direction is the width direction of the first vertical transistor and the second vertical transistor.

2. The semiconductor device as claimed in claim 1, characterized in that, The size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the first connecting portion in the first direction.

3. The semiconductor device as described in claim 1, characterized in that, The first vertical nanosheet also includes a first bottom and a first top, the first bottom, the first connecting portion and the first top are stacked in sequence, and the peripheral side of the first connecting portion is connected to and flush with the peripheral side of the first bottom and the peripheral side of the first top respectively. The first bottom electrode is connected to the first bottom, and the first top electrode is connected to the first top.

4. The semiconductor device as described in claim 3, characterized in that, The second vertical nanosheet also includes a second bottom and a second top, wherein the second bottom, the second connecting portion and the second top are stacked sequentially; The second bottom electrode is connected to the second bottom, and the second top electrode is connected to the second top.

5. The semiconductor device as claimed in claim 4, characterized in that, The dimension of the second connecting portion in the first direction is equal to the dimension of the second bottom in the first direction, the dimension of the second connecting portion in the first direction is equal to the dimension of the second top in the first direction, and the peripheral side surface of the second connecting portion is connected to and flush with the peripheral side surface of the second bottom and the peripheral side surface of the second top, respectively.

6. The semiconductor device as claimed in claim 4, characterized in that, The dimension of the second connecting portion in the first direction is smaller than the dimension of the second bottom in the first direction, and the dimension of the second connecting portion in the first direction is smaller than the dimension of the second top in the first direction.

7. The semiconductor device as claimed in claim 6, characterized in that, The size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second bottom portion in the first direction, and the size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second top portion in the first direction.

8. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device further includes a substrate disposed on the first bottom surface opposite to the first connection portion and the second bottom surface opposite to the second connection portion.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The first apex is symmetrical along the plane containing its own central axis, and the second apex is symmetrical along the plane containing its own central axis.

10. The semiconductor device according to any one of claims 1-8, characterized in that, The first gate is symmetrical along the plane containing the central axis of the first vertical nanosheet, and the second gate is symmetrical along the plane containing the central axis of the second vertical nanosheet.

11. The semiconductor device according to any one of claims 1-8, characterized in that, The first vertical transistor further includes a first bottom isolation portion and a first top isolation portion, wherein the first bottom isolation portion is disposed between the first bottom electrode and the first gate electrode, and the first top isolation portion is disposed between the first top electrode and the first gate electrode; The second vertical transistor further includes a second bottom isolation portion and a second top isolation portion, the second bottom isolation portion being disposed between the second bottom electrode and the second gate, and the second top isolation portion being disposed between the second top electrode and the second gate.

12. A method for fabricating a semiconductor device, characterized in that, include: A substrate is formed by forming a substrate, a first vertical nanosheet, a second vertical nanosheet, and a bottom electrode layer. The first vertical nanosheet, the second vertical nanosheet, and the bottom electrode layer are all located on one surface of the substrate. The first vertical nanosheet and the second vertical nanosheet are spaced apart. The bottom electrode layer connects the peripheral surfaces of the first vertical nanosheet and the second vertical nanosheet. The first vertical nanosheet includes a first connecting portion, and the second vertical nanosheet includes a second connecting portion. A bottom isolation layer, a protective layer, a gate replacement layer, and a top isolation layer are sequentially formed on the bottom electrode layer. The bottom isolation layer is located on the surface of the bottom electrode layer facing away from the substrate. The bottom electrode layer connects the peripheral surfaces of the first vertical nanosheet and the second vertical nanosheet. The protective layer is located on the surface of the bottom isolation layer facing away from the bottom electrode layer and on the peripheral surfaces of the first vertical nanosheet and the second vertical nanosheet. The gate replacement layer is located on the surface of the protective layer facing away from the bottom isolation layer. The top isolation layer is located on the surface of the gate replacement layer facing away from the bottom isolation layer. A first apex is formed on the surface of the first vertical nanosheet facing away from the substrate, and a second apex is formed on the surface of the second vertical nanosheet facing away from the substrate. A first insulating structure is formed on the first apex, and a second insulating structure is formed on the second apex. Using the first insulating structure and the second insulating structure as a mask, remove the portion of the top insulating layer that is offset from the first insulating structure and the second insulating structure; Remove the gate replacement layer and the protective layer, exposing the first connecting portion of the first vertical nanosheet and the second connecting portion of the second vertical nanosheet; A first gate is formed on the peripheral side surface of the first connecting portion and a second gate is formed on the peripheral side surface of the second connecting portion; Using the first insulating structure and the second insulating structure as masks, the portion of the bottom isolation layer that is offset from the first insulating structure and the second insulating structure is removed, and the portion of the bottom electrode layer that is offset from the first insulating structure and the second insulating structure is removed to form a first bottom electrode and a second bottom electrode. The first bottom electrode is connected to the first vertical nanosheet, and the second bottom electrode is connected to the second vertical nanosheet. The dimension of the second connection portion in the first direction is smaller than the dimension of the first connection portion in the first direction. The first vertical nanosheet, the first gate, the first bottom electrode, and the first top electrode constitute a first vertical transistor, and the second vertical nanosheet, the second gate, the second bottom electrode, and the second top electrode constitute a second vertical transistor.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the first connecting portion in the first direction.

14. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The steps of forming a substrate, a first vertical nanosheet, a second vertical nanosheet, and a bottom electrode layer include: A barrier layer, a passivation layer, a first pad, and a second pad are sequentially formed on the substrate. The barrier layer is located on one surface of the substrate, and the passivation layer is located on the surface of the barrier layer opposite to the substrate. The first pad and the second pad are both located on the surface of the passivation layer opposite to the barrier layer. The first pad and the second pad are spaced apart. The dimension of the second pad in the first direction is smaller than the dimension of the first pad in the first direction. Using the first and second pads as masks, the portion of the passivation layer that is offset from the first and second pads is removed, the portion of the barrier layer that is offset from the first and second pads is removed, and the substrate is etched to form a substrate transition layer, the first vertical nanosheet and the second vertical nanosheet. The peripheral side surface of the first vertical nanosheet is aligned with the peripheral side surface of the first pad, the peripheral side surface of the second vertical nanosheet is aligned with the peripheral side surface of the second pad, and the size of the second vertical nanosheet in the first direction is smaller than the size of the first vertical nanosheet in the first direction. Ions are implanted into the substrate transition layer to form the substrate and the bottom electrode layer.

15. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The second gasket is 1 nm to 4 nm smaller in size in the first direction than the first gasket, and the second vertical nanosheet is 1 nm to 4 nm smaller in size in the first direction than the first vertical nanosheet.

16. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The method for fabricating the semiconductor device, after removing the gate replacement layer and the protective layer and before forming the first gate and the second gate, includes: The second connecting portion of the second vertical nanosheet is modified such that the dimension of the second connecting portion in the first direction is smaller than the dimension of the first connecting portion in the first direction.

17. The method for fabricating a semiconductor device as described in claim 16, characterized in that, The step of modifying the second connecting portion of the second vertical nanosheet includes: A protective structure is formed on the peripheral side of the first connecting portion; The second connecting portion is modified to reduce the size of the second connecting portion in the first direction. The second vertical nanosheet also includes a second bottom and a second top, which are respectively connected to opposite ends of the second connecting portion. The size of the second connecting portion in the first direction is smaller than the size of the second bottom in the first direction, and the size of the second connecting portion in the first direction is smaller than the size of the second top in the first direction. Remove the protective structure, and the first connecting portion is exposed.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second bottom portion in the first direction, and the size of the second connecting portion in the first direction is 1 nm to 4 nm smaller than the size of the second top portion in the first direction.

19. An integrated circuit, characterized in that, It includes electronic devices and semiconductor devices as described in any one of claims 1-11, wherein the semiconductor device is electrically connected to the electronic devices.

20. An electronic device, characterized in that, It includes a circuit board and an integrated circuit as described in claim 19, wherein the integrated circuit is electrically connected to the circuit board.

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