Isolation between filters using inductive coupling cancellation

Abstract

Techniques for isolation between filters using inductive coupling cancellation are disclosed. An apparatus includes a first filter comprising a first plurality of inductors and a second filter comprising a second plurality of inductors. The first filter and the second filter are physically implemented adjacent to each other. A first inductor and a second inductor of the first plurality of inductors and a first inductor of the second plurality of inductors are polarized in a first direction, while a second inductor of the second plurality of inductors is polarized in a second direction opposite the first direction. The second inductor of the second plurality of inductors is physically adjacent to one of the first inductor and the second inductor of the first plurality of inductors such that magnetically coupled currents induced into each other are cancelled.

Description

Background of the Invention Technical Field

[0002] This disclosure relates to electronic circuits, and more specifically to passive electronic filters.

[0003] Related technical descriptions Passive filters utilizing inductors and capacitors are widely used in electronic circuits to modify the frequency response of signals. These filters (often referred to as LC filters) can be more complex than simple first-order designs. By combining multiple inductors and capacitors, higher-order filter configurations can be produced, allowing for greater control over the filter characteristics. Higher-order LC filters offer improved performance in terms of steeper roll-off rates and more abrupt attenuation outside the desired frequency range. These higher-order LC filters can be designed for specific frequency bands, such as low-pass filters, high-pass filters, band-pass filters, or band-stop filters, depending on the arrangement of the inductors and capacitors.

[0004] In summary, passive LC filters of different orders offer flexibility and customization options for modifying signal characteristics, enabling engineers to tailor the frequency response to specific application requirements. Summary of the Invention

[0005] A technique for isolating filters using inductive coupling cancellation is disclosed. In one embodiment, an apparatus includes: a first filter including a first plurality of inductors; and a second filter including a second plurality of inductors. The first and second filters are implemented physically adjacent to each other. The first and second inductors of the first plurality of inductors, and the first inductor of the second plurality of inductors, are polarized in a first direction, while the second inductor of the second plurality of inductors is polarized in a second direction opposite to the first direction. The second inductor of the second plurality of inductors is physically adjacent to one of the first and second inductors of the first plurality of inductors, such that the magnetic coupling currents induced in each other are canceled.

[0006] In various implementations, multiple filters using inductors can be implemented close to each other in physically adjacent channels. In alternating filters, one inductor can be polarized in the opposite direction to its corresponding inductor in a physically adjacent filter in another channel. This allows for the cancellation of currents induced by magnetic coupling, resulting in better filter performance and less noise in the filtered signal. Filters can be of any type utilizing inductors, including low-pass, high-pass, band-pass, and band-stop filters. Attached Figure Description

[0007] The following detailed embodiments are described with reference to the accompanying drawings, which will now be briefly described.

[0008] Figure 1 This is a schematic diagram illustrating a device with two channels, which have physically adjacent filters arranged such that magnetic coupling currents are canceled out.

[0009] Figure 2 This is a diagram illustrating a specific implementation of an inductor arranged on an integrated circuit (IC) die or a printed circuit board (PCB) to counteract coupling current.

[0010] Figure 3 This is a schematic diagram illustrating an alternating arrangement of multiple filters configured to cancel coupling current.

[0011] Figures 4A to 4E This is a schematic diagram of different types of filters that can be implemented according to this disclosure.

[0012] Figures 5A to 5B This is a block diagram of an example receiver in which the filter arrangement of this disclosure can be implemented.

[0013] Figure 6 This is a flowchart of one embodiment of a method for operating multiple filters according to the present disclosure.

[0014] Figure 7 This is a block diagram of one embodiment of a device that can utilize the filter arrangement of this disclosure.

[0015] Figure 8 These are diagrams illustrating different systems that can utilize the filter arrangements of this disclosure.

[0016] Figure 9 This is a diagram illustrating one embodiment of a non-transitory computer-readable medium storing circuit design information, including circuitry, according to the present disclosure. Detailed Implementation

[0017] Many passive filters use inductors. Inductive coupling can occur when two filters with inductors are placed close together. Inductive coupling can have negative effects, such as mutual interference affecting filter characteristics, resonant shift (changing the resonant frequencies of the two filters), and undesirable attenuation or amplification at certain frequencies. The coupling effect is typically mitigated by increasing the physical distance between the filters or by using shielding / isolation techniques.

[0018] This disclosure utilizes the insight that when inductors that are adjacent to each other have the same polarity, the currents generated by magnetic coupling can enhance each other. If the polarity can be changed, the currents from magnetic coupling will cancel each other out.

[0019] Therefore, this disclosure relates to the arrangement of multiple adjacent filters. The filters are arranged such that at least one inductor of a particular filter has the opposite polarity to that of another adjacent filter. When adjacent filters are implemented on an integrated circuit, an inductor can have the opposite polarity to another inductor in an adjacent filter by changing the orientation of its windings relative to each other. For example, one inductor can be wound clockwise on the IC, while the corresponding inductor of an adjacent filter can be wound counterclockwise. When two inductors of physically adjacent filters are arranged in this way, cancellation of coupling currents induced by the magnetic field can occur. Therefore, using the techniques of this disclosure, coupling currents can be cancelled, and the need for, for example, shielding between filters can be avoided.

[0020] Various implementations of the filter circuit arranged according to the above will now be discussed in further detail below. First, a schematic diagram of a basic dual-filter implementation with inductors arranged to cancel coupling currents is discussed, followed by examples of specific implementations of physical inductors that can be executed on an integrated circuit (IC) or printed circuit board (PCB). Examples of alternating arrangements of filters (more than two) are then presented. Subsequently, different filter types (e.g., low-pass, high-pass) and different orders (e.g., second-order, fourth-order) that can be implemented using the arrangements disclosed herein are discussed. Examples of receivers (both wired and wireless) utilizing the filter arrangements of this disclosure are then described. Methods for operating the filters of this disclosure are then discussed, followed by a description of example devices and systems in which the arrangement can be implemented, and a description of a computer-readable medium storing instructions that can be used to manufacture such devices and systems.

[0021] Filter arrangement for coupling current cancellation : Figure 1 This is a schematic diagram illustrating a device with two channels having physically adjacent filters arranged such that magnetically coupled currents are canceled out. In the illustrated embodiment, filter 101 is arranged adjacent to filter 102. In practice, the two filters are arranged so that the electromagnetic fields induced in the inductor interact with each other. It should also be noted that while the inductor is the only component shown herein, other components (such as resistors and / or capacitors) may also be present. It should also be noted that while the discussion in this disclosure relates to passive components, the components shown herein can be implemented in filters that also include active components (such as transistors). Generally, the filters discussed herein can be completely passive filters or filters that include a combination of passive and active components.

[0022] In the illustrated embodiment, filter 101 includes inductors L1 and L2, while filter 102 includes inductors L3 and L4. In the physical arrangement of these filters, L1 of filter 101 is adjacent to and closest to L3 of filter 102, and L2 of filter 101 is adjacent to and closest to inductor L4 of filter 102. Figure 1 As shown, the magnetizing current flowing through inductors L1 and L2 can induce currents in inductors L3 and L4. Conversely, the magnetizing current flowing through inductors L3 and L4 (from...) Figure 1 The excitation current from the external source shown will induce current in inductors L1 and L2.

[0023] Filters 101 and 102 can be part of a multichannel communication system in which signals pass concurrently with each other. In some embodiments, the filters can be configured to filter out different frequency bands. During such operation, an induced current in the other filter generated by the excitation current in one filter can cause undesirable operation and degrade the effectiveness of both filters. However, as Figure 1 As shown, inductor L4 is implemented such that it is polarized in the opposite direction relative to the adjacent inductor L2. Due to this arrangement, the magnetizing current through L2 causes the induced current in L4 to flow in the opposite direction to the induced current in L3. Therefore, the induced coupling currents in both L3 and L4 essentially (if not completely) cancel each other out. This operation also occurs in the other direction, i.e., the magnetizing currents through L3 and L4 (due to the opposite polarities of L2 and L4) cause the induced coupling currents through L1 and L2 to flow in opposite directions, thus achieving cancellation.

[0024] Figure 1 The arrangement shown can be repeated for any number of filters. For a larger number of filters, this arrangement allows alternating instances of filters to have inductors polarized in opposite directions for any physically adjacent inductors in different filters. Therefore, coupling currents can be canceled from each filter in this arrangement, resulting in better overall performance of the system in which the filter arrangement is implemented.

[0025] Physical inductor arrangement for coupling current cancellation : Figure 2This is a diagram illustrating a specific implementation of inductors arranged on an integrated circuit (IC) die or a printed circuit board (PCB) to cancel coupling currents. In the illustrated embodiment, portions of filters 201, 202, and 203 are shown arranged adjacent to each other. Although only the inductors of these filters are shown, it should be understood that other components such as resistors and capacitors may also be included as part of each filter. It should also be understood that while this disclosure illustrates filters that are substantially identical to each other, the technique for canceling coupling currents can be applied to filters that are not identical to each other but are otherwise physically adjacent to each other. Furthermore, this technique can be applied to other circuits that utilize inductors arranged physically close to each other.

[0026] In the illustrated embodiments, filters 201, 202, and 203 are implemented on dielectric 200. In one embodiment, dielectric 200 may be an integrated circuit die, while in another embodiment, dielectric 200 may be a printed circuit board. More generally, dielectric 200 may be any suitable dielectric on which inductors can be implemented (including the dielectrics discussed herein), as well as some type of substrate. This disclosure also contemplates inductors implemented as discrete components but with windings in a specific orientation, wherein the polarization techniques discussed herein are achieved by mounting discrete inductors in alternating orientations to achieve this effect.

[0027] In the illustrated embodiment, filter 201 includes inductors L1 and L2, filter 202 includes inductors L3 and L4, and filter 203 includes inductors L5 and L6. Inductor L4 of filter 202 is physically adjacent to inductors L2 of filter 201 and L6 of filter 203. Inductors L1, L3, and L5 have the same polarity.

[0028] Compared to the same-direction polarization of inductors L1, L3, and L5, inductor L4 of filter 202 is polarized in the opposite direction to inductors L2 and L6. Therefore, inductor L4 is polarized in the opposite direction to inductors L2 and L6. Due to this arrangement, the coupling current induced in filter 202 by the inductors of filters 201 and 203 flows in opposite directions. Furthermore, due to this arrangement, the coupling current induced, for example, in L4 flows in the opposite direction to the coupling current induced in L2 and L6. Therefore, the current induced in the inductors of one filter due to the magnetizing current in adjacent filters is substantially (if not completely) canceled out. This also occurs in both directions, thereby reducing the coupling current between the inductors of adjacent filters. If L4 were instead arranged in the opposite orientation to that shown here, these coupling currents would be amplified, thus degrading the performance of all filters in this embodiment. Conversely, due to the cancellation of coupling currents, filter performance can be significantly improved, and thus the performance of the system in which these filters are implemented is improved.

[0029] It should be noted that Figure 2 The inductor shown has diagonal corners. However, the illustrated shape is not intended to be limiting. On the contrary, many different inductor shapes are possible and envisioned, including inductor shapes with square / rectangular corners.

[0030] Alternating filter arrangement for coupling current cancellation : Figure 3 This is a schematic diagram illustrating an alternating arrangement of multiple filters configured for coupling current cancellation. In the example shown, the inductor portions of four different filters 301, 302, 303, and 304 are illustrated. As noted above, each filter may include other components not shown here, and the filter may include a combination of passive and active components as needed.

[0031] Filters 301-304 can be implemented in a manner in which they are physically adjacent to each other. Filter 301 includes inductors L1 and L2, filter 302 includes inductors L3 and L4, filter 303 includes inductors L5 and L6, and filter 304 includes inductors L7 and L8. Inductor L3 is physically adjacent to inductors L1 and L5, and inductor L5 is also physically adjacent to inductor L7. Similarly, inductor L4 is physically adjacent to inductors L2 and L6, and inductor L6 is also adjacent to inductor L8.

[0032] Inductors L1, L3, L5, and L7 are all polarized in the same direction. For example, if the inductors are polarized in a similar direction... Figure 3In this configuration, inductors L1, L3, L5, and L7 can all be arranged in the same direction (e.g., counterclockwise). In contrast, the polarities of inductors L2, L4, L6, and L8 are arranged in an alternating pattern, with inductors L4 and L8 having the opposite polarity to inductors L2 and L6. This arrangement can be further extended to include any desired number of additional filters. With inductors L4 and L8 polarized in the opposite direction to inductors L2 and L6, coupling currents can be canceled in each of filters 301-304, as described above.

[0033] Example filter types with coupling current cancellation arrangement : The various implementation schemes of the arrangement discussed above can be used in a wide variety of filters with different inductor arrangements. Figures 4A to 4E Some of these arrangements are illustrated.

[0034] Figure 4A This is a schematic diagram of a pair of low-pass filters that can be physically arranged to cancel coupling currents according to various techniques discussed in this disclosure. In the illustrated embodiment, filter 401 is dedicated to use by a first channel (channel 1), while filter 402 is dedicated to use by a second channel (channel 2). Both low-pass filters 401 and 402 are third-order filters. Filter 401 includes capacitor C1, while filter 402 includes capacitor C2.

[0035] Filters 401 and 402, along with their inductors, are arranged according to the polarization technique disclosed herein. Thus, while L1 and L3 are polarized in the same direction, inductors L2 and L4 are polarized in opposite directions relative to each other. In specific implementations of filters 401 and 402, these inductors may be physically adjacent to each other. Therefore, coupling currents induced in the inductors of the filters are substantially or completely canceled.

[0036] Figure 4B This is a schematic diagram of two fourth-order low-pass filters. Filters 411 and 412 in the illustrated embodiments are fourth-order filters, each including two inductors and two capacitors. Filter 411 includes inductors L5 and L6 and capacitors C3 and C5. Filter 412 includes inductors L7 and L8 and capacitors C4 and C6. In a physical embodiment of these filters, filters 411 and 412 may be placed adjacent to each other, with inductors L6 and L8 being immediately adjacent. These two inductors are polarized in opposite directions, and therefore, substantially or completely eliminating coupling currents can be achieved in a manner similar to other embodiments of this disclosure.

[0037] Figure 4CThis is a schematic diagram of two high-pass filters (filter 422 and filter 423). Filter 422 includes inductors L1 and L2 and capacitor C1, which provides AC coupling between the two inductors. Similarly, filter 423 includes inductors L3 and L4 and capacitor C2, and is configured for operation similar to that of filter 422 (but the cutoff point may differ). The physical arrangement of filters 422 and 423 is such that inductors L1 and L4 are adjacent to each other, as are inductors L2 and L3. However, the corresponding polarizations of inductors L2 and L3 are opposite to each other in order to achieve cancellation of coupling currents according to this disclosure.

[0038] Figure 4D This is a schematic diagram of two bandpass filters that are physically adjacent to each other in their implementation. Filters 432 and 433 can operate in a similar manner, but the corresponding frequency bands across each filter can be different. Filter 432 includes inductors L1, L2, and L5, and capacitors C1, C2, and C5. Filter 433 includes inductors L3, L4, and L6, and capacitors C3, C4, and C6. Filters 432 and 433 are arranged such that inductors L1 and L3 are physically adjacent to each other, as are inductors L2 and L4. L1 and L3 are polarized in the same direction, while inductors L2 and L4 are polarized in opposite directions. Due to the opposite polarization of L2 and L4, the coupling currents induced in the two filters can be canceled out, resulting in better filter performance.

[0039] Figure 4E This is a schematic diagram of a pair of band-stop filters that can be physically arranged adjacent to each other. In the illustrated embodiment, filter 442 includes inductors L1, L2, and L5, and capacitors C1, C2, and C5. Filter 443 includes inductors L3, L4, and L6, and capacitors C3, C4, and C6. Filters 442 and 443 are arranged such that inductors L1 and L3 are physically adjacent to each other, as are inductors L2 and L4. Inductors L1 and L3 are polarized in the same direction, while inductors L2 and L4 are polarized in opposite directions. Therefore, due to the opposite polarization of L2 and L4, the coupling currents through the two filters are canceled out.

[0040] Receiver Implementation Plan : Figure 5A and Figure 5B This is a block diagram of a multichannel communication system in which the filter arrangement discussed above can be utilized. Figure 5AThe invention relates to a wireless receiver with multiple channels, wherein filters 502, 503, 504, and 505 are coupled to antenna 501 and configured to output filtered signals A, B, C, and D, respectively, to processing circuitry 510. Processing circuitry 510 can provide various processing functions for the received filtered signals, such as down-conversion (e.g., to baseband frequency), conversion of analog signals to digital format, decoding, etc.

[0041] Receiver 500 can be one of many different types of wireless receivers. In one example implementation, receiver 500 can be a receiver in a communication system utilizing frequency hopping, and each of the filters 502 can be a bandpass filter configured to allow frequencies of a specific frequency band to pass through. Other types of wireless communication systems are possible and envisioned.

[0042] Each of the filters 502-505 in the illustrated embodiment may include an inductor and other passive components, and may be arranged physically close to each other. Furthermore, the filters may be arranged such that some inductors of adjacent filters are polarized in opposite directions relative to each other, similar to the above description regarding... Figures 1 to 4E The filter arrangement discussed.

[0043] Figure 5B Receiver 511 is part of a wired communication system and is configured to receive signals via a transmitting medium 517, which may be, for example, a coaxial cable or some other type of transmitting medium. Filters 512-515 in the illustrated embodiment are configured to filter the signals received via the transmitting medium 517 and output a filtered signal EH. Processing circuitry 520 can receive the filtered signal and perform additional processing functions, such as conversion to digital and decoding. In one example embodiment, receiver 511 may be part of an analog communication system utilizing frequency division multiplexing, but other types are possible and contemplated.

[0044] and Figure 5A Similar to the implementation scheme, filters 512-515 can be arranged physically adjacent to each other, and each filter may include an inductor and other passive components. According to the above regarding... Figures 1 to 4E In other arrangements discussed, the inductors may be arranged such that in an alternating filter, at least one inductor is polarized relative to an adjacent inductor in another filter, such that coupling currents are canceled out.

[0045] Operating method : Figure 6This is a flowchart of one embodiment of a method for operating multiple filters according to the present disclosure. Method 600 can be performed using any of the filter arrangements discussed above, and using various types of filters. Filter arrangements not explicitly disclosed herein but otherwise capable of performing method 600 are also considered to fall within the scope of this disclosure.

[0046] Method 600 begins by filtering a first signal in a first channel using a first filter having a first plurality of inductors (block 605), and filtering a second signal in a second channel using a second filter having a second plurality of inductors, wherein the first and second filters are physically adjacent to each other (block 610). Method 600 further includes cancelling magnetically coupled currents induced in the first and second filters, wherein the first and second inductors of the first plurality of inductors and the first inductor of the second plurality of inductors are polarized in a first direction, and wherein the second inductor of the second plurality of inductors is polarized in a second direction opposite to the first direction, and wherein the cancellation includes induced current flowing in the second inductor of the second plurality of inductors flowing in a direction opposite to the induced current in the first inductor of the second plurality of inductors (block 615).

[0047] In various embodiments, the method includes filtering a third signal in a third channel using a third filter having a third plurality of inductors, wherein a second filter is adjacent to the third filter and arranged between the first filter and the third filter. Such embodiments may also include filtering a fourth signal in a fourth channel using a fourth filter having a fourth plurality of inductors, wherein the third filter is adjacent to the fourth filter and arranged between the second filter and the fourth filter, wherein the first and second inductors of the third plurality of inductors and the first inductor of the fourth plurality of inductors are polarized in a first direction, and wherein the second inductor of the fourth plurality of inductors is polarized in a second direction. In these various embodiments, the method includes canceling magnetic coupling currents induced in the third and fourth filters.

[0048] Some embodiments, including low-pass filtering of the signals in the first channel and the second channel using a first filter and a second filter respectively, are also possible and envisioned. Other embodiments may include high-pass filtering of the signals in the first channel and the second channel using a first filter and a second filter respectively. Still other embodiments may include band-pass filtering of the signals in the first channel and the second channel using a first filter and a second filter respectively.

[0049] Example device : Now for reference Figure 7A block diagram illustrating an example embodiment of device 700 is shown. In some embodiments, the components of device 700 may be included within a system-on-a-chip. In some embodiments, device 700 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 700 may be an important design consideration. In the illustrated embodiment, device 700 includes a structure 710, a computing complex 720, an input / output (I / O) bridge 750, a cache / memory controller 745, a graphics unit 775, and a display unit 765. In some embodiments, as supplements to or alternatives to the illustrated components, device 700 may also include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0050] Structure 710 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 700. In some embodiments, portions of structure 710 may be configured to implement various different communication protocols. In other embodiments, structure 710 may implement a single communication protocol, and components coupled to structure 710 may internally switch from a single communication protocol to other communication protocols.

[0051] In the illustrated embodiments, computing complex 720 includes a bus interface unit (BIU) 725, a cache 730, and cores 735 and 740. In various embodiments, computing complex 720 may include a variety of numbers of processors, processor cores, and caches. For example, computing complex 720 may include one, two, four, or any other suitable number of processor cores. In one embodiment, cache 730 is a set-associative L2 cache. In some embodiments, cores 735 and 740 may include internal instruction and data caches. In some embodiments, coherence units (not shown) in architecture 710, cache 730, or elsewhere in device 700 may be configured to maintain coherence between the various caches of device 700. BIU 725 may be configured to manage communication between computing complex 720 and other elements of device 700. Processor cores (such as cores 735 and 740) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions. These instructions can be stored in a computer-readable medium, such as memory coupled to the memory controller 745 discussed below.

[0052] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling may include intermediate elements. For example, in Figure 7In this context, the graphics unit 775 can be described as being "coupled" to memory via structure 710 and cache / memory controller 745. In contrast, in... Figure 7 In the exemplary implementation, the graphics unit 775 is "directly coupled" to the structure 710 because there are no intermediate elements.

[0053] The cache / memory controller 745 can be configured to manage data transfer between the structure 710 and one or more caches and memories. For example, the cache / memory controller 745 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 745 may be directly coupled to memory. In some embodiments, the cache / memory controller 745 may include one or more internal caches. The memory coupled to the controller 745 can be any type of volatile memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), dual data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR4, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled onto a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, these devices can be mounted with integrated circuits in a chip-stacked configuration, a package-stacked configuration, or a multi-chip module configuration. The memory coupled to the controller 745 can be any type of non-volatile memory, such as NAND flash memory, NOR flash memory, nanometer RAM (NRAM), magnetoresistive RAM (MRAM), phase-change RAM (PRAM), raceway memory, memristor memory, etc. As noted above, the memory can store program instructions executable by the computing complex 720 to cause the computing device to perform the functionality described herein.

[0054] The graphics unit 775 may include one or more processors, such as one or more graphics processing units (GPUs). For example, the graphics unit 775 may receive graphics-oriented instructions, such as OpenGL. ® Metal ® Or DIRECT3D ®Instructions. The graphics unit 775 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 775 is typically configured to process large blocks of data in parallel and can construct an image in a frame buffer for output to a display, which may be included in a device or may be a separate device. The graphics unit 775 may include a transformation engine, a lighting engine, a triangle engine, and a rendering engine in one or more graphics processing pipelines. The graphics unit 775 can output pixel information for displaying the image. In various embodiments, the graphics unit 775 may include programmable shader circuitry, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may or may not be graphics-dependent).

[0055] Display unit 765 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 765 can be configured as a display pipeline. Additionally, display unit 765 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 765 may include one or more interfaces (e.g., MIPI) for coupling to a user display (e.g., a touchscreen or an external display). ® Or embedded display port (eDP)).

[0056] I / O bridge 750 may include various components configured to implement functionalities such as Universal Serial Bus (USB) communication, security, audio, and low-power always-on connectivity. I / O bridge 750 may also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 700 via I / O bridge 750.

[0057] In some embodiments, device 700 includes network interface circuitry (not explicitly shown) that can be connected to structure 710 or I / O bridge 750. This network interface circuitry can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuitry can be configured to communicate via a wired local area network (LAN), a wireless LAN (e.g., via Wi-Fi), or Wi-Fi. ™ The network interface circuitry can communicate via one or more cellular networks using one or more radio access technologies, or wide area networks (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuitry is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuitry is configured to use device-to-device communication (e.g., Bluetooth). ® or Wi-Fi ™Communication can be achieved through direct connection, etc. In various implementations, this network interface circuitry can provide device 700 with connectivity to various types of other devices and networks.

[0058] The various communication circuits discussed in the preceding paragraphs can implement one or more instances of the filter arrangements of this disclosure. Filters can be implemented using passive components, including inductors, and the filters can be physically adjacent to each other. For the purpose of canceling coupling currents that would otherwise be induced, alternating filters in the filter array can have inductors polarized in the opposite direction to another adjacent inductor in the adjacent filter. This allows for better filter performance and better overall performance of the communication links using these filters.

[0059] Example Application : Now go to Figure 8 Systems can include any of the circuits, devices, or systems discussed above. Systems or devices 800 that may utilize one or more of the techniques described herein, in combination with or otherwise, can be used in a wide range of fields. For example, system or device 800 can be used as part of the hardware of a system such as a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television).

[0060] Similarly, the disclosed components can be used in wearable devices 860, such as smartwatches or health monitoring devices. In many embodiments, a smartwatch can perform a variety of different functions—for example, access to email, cellular services, calendars, health monitoring, etc. Wearable devices can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also envisioned, including devices worn around the neck, implantable devices, and glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality.

[0061] System or device 800 can also be used in a variety of other contexts. For example, system or device 800 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware implementing cloud-based services 870. Furthermore, system or device 800 can be implemented in a wide range of dedicated everyday devices, including common household devices 880 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the “Internet of Things” (IoT). Components can also be implemented in various modes of transportation. For example, system or device 800 can be used in control systems, guidance systems, entertainment systems, etc., of various types of vehicles 890.

[0062] In various embodiments, the system or device 800 shown herein may implement circuitry including examples of filters of the present disclosure. Multiple filters may be implemented in an arrangement in which they are physically adjacent to each other, and passive components including inductors may be utilized, wherein at least some inductors are polarized in opposite directions relative to their corresponding inductors in adjacent filters for the purpose of counteracting coupling currents.

[0063] Figure 8 The applications illustrated are merely exemplary and are not intended to limit the potential future applications of the disclosed systems or devices. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, and unmanned aerial vehicles.

[0064] Example computer-readable media : This disclosure has described various example circuits in detail above. It is intended that this disclosure covers not only embodiments including such circuits, but also computer-readable storage media that include design information specifying such circuits. This includes various embodiments of the circuits discussed above (and specifically, filters implemented using passive components), and instances of these filters are arranged physically adjacent to each other. Therefore, this disclosure is intended to support claims that cover not only means including the disclosed circuits, but also storage media specifying such circuits in formats for programming a computing system to generate a simulation model of hardware circuitry, programming a manufacturing system configured to generate hardware (e.g., integrated circuits) including the disclosed circuits. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves perform complete operations (such as design simulation, design synthesis, circuit fabrication, etc.).

[0065] Figure 9 This is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a computing system 940 is configured to process the design information. This may include executing instructions included in the design information, interpreting instructions included in the design information, compiling, transforming, or otherwise updating the design information. Thus, in some embodiments, the design information (e.g., by programming the computing system 940) controls the computing system 940 to perform various operations discussed below.

[0066] In the illustrated example, computing system 940 processes the design information to generate both a computer simulation model 960 of the hardware circuit and lower-level design information 950. In other embodiments, computing system 940 may generate only one of these outputs, may generate other outputs based on the design information, or both. Regarding the computational simulation, computing system 940 may execute instructions in a hardware description language, which includes register-transfer-level (RTL) code, behavioral code, structural code, or some combination thereof. The simulation model may perform the functionality specified by the design information, facilitate verification of the functional correctness of the hardware design, generate power consumption estimates, generate timing estimates, etc.

[0067] In the illustrated example, computing system 940 further processes the design information to generate lower-level design information 950 (e.g., gate-level design information, netlists, etc.). As shown, this may include synthesis operations such as constructing multi-level networks, optimizing the network using technology-independent techniques, technology-dependent techniques, or both, and outputting a gate network (with potential constraints based on a library of available gate pairs, size adjustments, delays, power, etc.). Based on the lower-level design information 950 (and potentially other inputs), semiconductor manufacturing system 920 is configured to manufacture integrated circuit 930 (which may correspond to the functionality of analog model 960). Note that computing system 940 may generate different analog models based on design information at various descriptive levels (including information 950, 915, etc.). Data representing design information 950 and model 960 may be stored on medium 910 or one or more other media.

[0068] In some embodiments, lower-level design information 950 controls (e.g., programs) the semiconductor manufacturing system 920 to manufacture integrated circuit 930. Therefore, when processed by the manufacturing system, the design information can program the manufacturing system to manufacture circuits including the various circuits disclosed herein.

[0069] The non-transitory computer-readable storage medium 910 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 910 may be: mounting media, such as CD-ROM, floppy disk, or magnetic tape devices; computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory, such as flash memory, magnetic media, such as hard disk drives or optical storage devices; registers or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 910 may also include other types of non-transitory memory or combinations thereof. Therefore, the non-transitory computer-readable storage medium 910 may include two or more memory media; such media may reside in different locations—for example, in different computer systems connected via a network.

[0070] Design information 915 may be specified using any suitable computer language, including hardware description languages, such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The formats of various design information can be recognized by one or more applications executed by computing system 940, semiconductor manufacturing system 920, or both. In some embodiments, design information may also include one or more cell libraries specifying the composition, layout, or both of integrated circuit 930. In some embodiments, design information is specified, wholly or partially, in the form of a netlist specifying cell library elements and their connectivity. Individually, the design information discussed herein may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information may specify circuit elements to be manufactured but not their physical layout. In this case, design information may need to be combined with layout information to actually manufacture the specified circuit.

[0071] In various implementations, integrated circuit 930 may include one or more custom macrocells, such as memory and analog or mixed-signal circuitry. In this case, design information may include information associated with the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. Mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0072] The semiconductor manufacturing system 920 may include any of the various suitable elements configured to manufacture integrated circuits. This may include elements for, for example, depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or by using ultraviolet treatment to modify the dielectric constant), etc. The semiconductor manufacturing system 920 may also be configured to perform various tests on the manufactured circuits to ensure proper operation.

[0073] In various embodiments, integrated circuit 930 and model 960 are configured to operate according to a circuit design specified by design information 915, which may include performing any of the functionalities described herein. For example, integrated circuit 930 may include Figures 1 to 5B Any of the various components shown. Additionally, integrated circuit 930 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0074] As used herein, a phrase in the form of “design information specifying a circuit configured to…” does not imply that the circuit in question must be manufactured to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components. Similarly, stating that “instructions of a hardware description programming language” are “executable” to program a computing system to generate a computer simulation model does not mean that the instructions must be executed to satisfy the element, but rather specifies the characteristics of those instructions. In this case, additional features associated with the model (or the circuit represented by the model) may similarly relate to the characteristics of those instructions. Therefore, an entity selling a computer-readable medium having instructions that satisfy the stated characteristics may provide an infringing product even if another entity actually executes those instructions on the medium.

[0075] It is important to note that a given design, at least within a digital logic context, can be implemented using multiple different gate arrangements, circuit techniques, etc. As an example, different designs may choose or connect gates based on design trade-offs (e.g., focusing on power consumption, performance, circuit area, etc.). Furthermore, different manufacturers may have proprietary libraries, gate designs, physical gate implementations, etc. Different entities may also use different tools to process design information at various layers (e.g., from behavioral specifications to the physical layout of gates).

[0076] However, once a digital logic design is specified, those skilled in the art do not need to perform extensive experiments or studies to determine these specific implementations. Instead, they understand the process for reliably and predictably producing one or more circuit implementations that provide the functionality described by the design information. Different circuit implementations may affect the performance, area, power consumption, etc., of a given design (potentially trade-offs between different design goals), but the logic function remains unchanged between different circuit implementations of the same circuit design.

[0077] In some implementations, instructions included in the design information instructions provide RTL information (or other higher-level design information) and can be executed by a computing system to synthesize a gate-level netlist representing the hardware circuitry based on the RTL information as input. Similarly, these instructions provide behavioral information and can be executed by the computing system to synthesize netlists or other lower-level design information. This lower-level design information can be used to program the manufacturing system 920 to manufacture the integrated circuit 930.

[0078] It should be noted that although the circuits discussed above have been implemented using NMOS and PMOS transistors, this disclosure is not intended to limit the implementations within its scope to these types of devices. Therefore, in addition to the various MOSFET types discussed above, this disclosure also contemplates implementations using non-planar devices, such as FinFETs, GAAFETs (Gate All-Around FETs), and other types. Implementations using bipolar devices are also possible and contemplated. This disclosure also contemplates devices that can be implemented using speculative techniques at the time of writing to implement the various implementations of the circuits discussed herein. These techniques include (but are not limited to) graphene transistors, carbon nanotube transistors, gallium arsenide transistors, etc. The use of memristors in some circuit structures is also contemplated.

[0079] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0080] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0081] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the benefits of this disclosure.

[0082] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0083] Therefore, while the appended dependent claims are drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of features of the dependent claims consistent with the present disclosure is contemplated, and such combinations may be claimed in this patent application or another patent application. In short, combinations are not limited to those specifically recited in the appended claims.

[0084] Where appropriate, claims drafted in one format or statutory type (e.g., apparatus) are also contemplated to support corresponding claims in another format or statutory type (e.g., method).

[0085] Because the present disclosure is a legal document, various terms and phrases are subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, and the definitions provided throughout this disclosure, are used to determine how to interpret claims drafted based on the present disclosure.

[0086] Unless the context clearly requires otherwise, references to items in the singular (i.e., nouns or noun phrases preceded by "a", "an" or "the") are intended to mean "one or more". Therefore, a reference to "an element" in a claim, without an accompanying context that requires otherwise, does not exclude additional instances of that element. A "plurality" of items refers to a set of two or more of the items.

[0087] The word "may" is used herein in the permissive sense (i.e., having potential, capable of) rather than the mandatory sense (i.e., must).

[0088] The terms "comprise" and "include", and their forms, are open-ended and mean "including but not limited to".

[0089] When the term "or" is used in the present disclosure in relation to a list of options, it will generally be understood to be used in the inclusive sense unless the context indicates otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both", and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is being used in the exclusive sense.

[0090] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0091] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0092] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0093] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0094] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions, etc. This phrase is not used herein to refer to intangible things.

[0095] In some cases, various units / circuits / components may be described herein as a collection of entities that perform tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated otherwise.

[0096] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0097] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. No Referencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0098] Different “circuits” may be described in this disclosure. These circuits, or “circuits,” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits.

[0099] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0100] In various implementations, as discussed in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill, by decoding the description of the circuit / cell / component in a hardware description language (HDL) (such as Verilog or VHDL). The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, this HDL description is a way of transforming the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0101] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0102] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

[0103] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be construed as encompassing all such variations and modifications.

Claims

1. An apparatus comprising: A first filter, the first filter comprising a first plurality of inductors; and A second filter, comprising a second plurality of inductors, wherein the first filter and the second filter are implemented physically adjacent to each other; in: The first inductor and the second inductor in the first plurality of inductors, and the first inductor in the second plurality of inductors, are polarized in a first direction; The second inductor in the second plurality of inductors is polarized in a second direction opposite to the first direction; The first inductor and the second inductor in the first plurality of inductors are coupled in series; The first inductor and the second inductor in the second plurality of inductors are coupled in series; and The second inductor in the second plurality of inductors is physically adjacent to one of the first inductors and the second inductor in the first plurality of inductors, such that the magnetic coupling current induced in each other is canceled out.

2. The apparatus according to claim 1, further comprising: A third filter, comprising a third plurality of inductors, wherein a second filter is arranged between and physically adjacent to both the first and third filters, and wherein the inductors of the third plurality of inductors are polarized in the first direction, wherein the first and second inductors of the third plurality of inductors are coupled in series.

3. The apparatus according to claim 2, further comprising: A fourth filter, wherein the third filter is arranged between and physically adjacent to the second filter and the fourth filter, wherein the fourth filter includes a fourth plurality of inductors, the fourth plurality of inductors including an inductor polarized in the first direction and another inductor polarized in the second direction, wherein the first inductor and the second inductor of the fourth plurality of inductors are coupled in series.

4. The apparatus of claim 1, wherein the first filter and the second filter are implemented on an integrated circuit die.

5. The apparatus of claim 1, wherein the first filter and the second filter are implemented on a printed circuit board.

6. The apparatus of claim 1, wherein the first filter includes at least one capacitor coupled to at least one inductor of the first plurality of inductors, and wherein the second filter includes at least one capacitor coupled to at least one inductor of the second plurality of inductors.

7. The apparatus of claim 1, wherein the first filter and the second filter are low-pass filters.

8. The apparatus of claim 1, wherein the first filter and the second filter are high-pass filters.

9. The apparatus of claim 1, wherein the first filter and the second filter are bandpass filters.

10. The apparatus of claim 1, wherein the first filter and the second filter are band-stop filters.

11. A method, the method comprising: A first signal in a first channel is filtered using a first filter, the first filter having a first plurality of inductors; The second signal in the second channel is filtered using a second filter having a second plurality of inductors, wherein the first filter and the second filter are physically adjacent to each other; as well as To cancel the magnetic coupling current induced in the first filter and the second filter, wherein: The first inductor and the second inductor in the first plurality of inductors, and the first inductor in the second plurality of inductors, are polarized in a first direction; The second inductor in the second plurality of inductors is polarized in a second direction opposite to the first direction; The first inductor and the second inductor in the first plurality of inductors are coupled in series; The first inductor and the second inductor in the second plurality of inductors are coupled in series; and The cancellation includes the induced current flowing in the second inductor of the second plurality of inductors flowing in the opposite direction to the induced current in the first inductor of the second plurality of inductors.

12. The method according to claim 11, further comprising: The third signal in the third channel is filtered by a third filter having a third plurality of inductors, wherein the second filter is adjacent to the third filter and is arranged between the first filter and the third filter; A fourth filter with a fourth plurality of inductors is used to filter the fourth signal in the fourth channel, wherein a third filter is adjacent to the fourth filter and is arranged between the second filter and the fourth filter, wherein: The first and second inductors in the third plurality of inductors and the first inductor in the fourth plurality of inductors are polarized in the first direction; The second inductor of the fourth plurality of inductors is polarized in the second direction; The first inductor and the second inductor in the third plurality of inductors are coupled in series; The first inductor and the second inductor in the fourth plurality of inductors are coupled in series; and To counteract the magnetic coupling current induced in the third and fourth filters.

13. The method according to claim 11, further comprising: The signals in the first channel and the second channel are low-pass filtered using the first filter and the second filter, respectively.

14. The method according to claim 11, further comprising: The signals in the first channel and the second channel are high-pass filtered using the first filter and the second filter, respectively.

15. The method according to claim 11, further comprising: The signals in the first channel and the second channel are bandpass filtered using the first filter and the second filter, respectively.

16. A system comprising: Receiver circuit, wherein the receiver circuit includes a plurality of filter circuits corresponding to channels among a plurality of channels, wherein the plurality of filter circuits include: A first passive filter circuit, the first passive filter circuit having a first plurality of inductors including a first inductor and a second inductor coupled in series; and A second passive filter circuit, the second passive filter circuit having a second plurality of inductors including a third inductor and a fourth inductor coupled in series, wherein the first passive filter circuit is physically adjacent to the first passive filter circuit; and The first inductor, the second inductor, and the third inductor are polarized in a first direction, and the fourth inductor is polarized in a second direction opposite to the first direction and is configured to cancel the magnetic coupling current induced in the first plurality of inductors and the second plurality of inductors.

17. The system of claim 16, further comprising: A third passive filter circuit, comprising a third plurality of inductors, including a first inductor and a second inductor series-coupled among the third plurality of inductors, wherein the third passive filter circuit is physically adjacent to the second passive filter circuit, and wherein the second passive filter circuit is arranged between the first passive filter circuit and the third passive filter circuit; and A fourth passive filter circuit includes a fourth plurality of inductors, comprising a first inductor and a second inductor coupled in series among the fourth plurality of inductors. The fourth passive filter circuit is physically adjacent to a third passive filter circuit, and the third passive filter circuit is arranged between the second passive filter circuit and the fourth passive filter circuit. The inductors in the third plurality of inductors are polarized in the first direction, and at least one of the fourth plurality of inductors includes an inductor polarized in the second direction.

18. The system of claim 16, wherein the first passive filter circuit and the second passive filter circuit are low-pass filter circuits.

19. The system of claim 16, wherein the first passive filter circuit and the second passive filter circuit are high-pass filter circuits.

20. The system of claim 16, wherein the first passive filter circuit and the second passive filter circuit are bandpass filter circuits.

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