Servo drive control method and system with multi-platform architecture

Abstract

This invention provides a servo drive control method and system with a multi-platform architecture, relating to the field of industrial automation control technology. First, it receives and parses a set of instructions from a multi-axis motion control system to obtain the instruction type identifier, priority parameters, and target execution axis number. Then, it uses a field-programmable gate array (FPGA) platform to classify and reorganize the instructions, generating an axis instruction queue set. This queue is then transmitted to a digital signal processor (DSP) platform for preemptive task scheduling, generating an axis control instruction block set. This block is then fed back to the FPGA platform to generate a multi-phase pulse width modulation (PWM) drive signal set, which is sent to the power drive module to trigger the servo motor's action. Simultaneously, it captures the original feedback signal set of the servo motor in real time, achieving efficient, accurate, and stable servo drive control.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and more specifically, to a servo drive control method and system with a multi-platform architecture. Background Technology

[0002] In the field of modern industrial automation, multi-axis motion control systems are widely used in various precision machining equipment, robots, and other applications, placing extremely high demands on the accuracy, response speed, and stability of servo drive control. Traditional servo drive control methods typically employ a single processing platform architecture, which faces numerous challenges when processing complex multi-axis motion control commands.

[0003] On the one hand, a single platform has limitations in instruction processing capabilities. When receiving a set of instructions containing multiple types such as position, speed, and torque instructions, the lack of an efficient instruction classification and reorganization mechanism makes it difficult to determine the processing order and priority of the instructions, which can easily lead to chaotic instruction execution and affect the system's response speed and control accuracy.

[0004] On the other hand, in terms of task scheduling, traditional methods often employ simple sequential scheduling, failing to perform flexible preemptive task scheduling based on instruction priority and servo drive control cycle parameters. This prevents high-priority instructions from being processed in a timely manner, thereby reducing the system's real-time and dynamic performance and making it difficult to meet the requirements of high-precision motion control.

[0005] Furthermore, in the signal generation and feedback processing stages, traditional methods may suffer from insufficient accuracy and stability in generating pulse width modulation drive signals due to performance limitations of the processing platform, thus affecting the driving effect of the servo motor. Simultaneously, the lack of an efficient acquisition and processing mechanism for the raw feedback signals returned by the servo motor makes it impossible to obtain the motor's operating status in a timely and accurate manner, further impacting the system's control accuracy and stability. Summary of the Invention

[0006] In view of the aforementioned problems, and in conjunction with the first aspect of the present invention, embodiments of the present invention provide a servo drive control method for a multi-platform architecture, the method comprising:

[0007] The system receives a set of instructions sent by a multi-axis motion control system, performs instruction type parsing on the instruction set, and obtains the instruction type identifier, instruction priority parameter, and instruction target execution axis number corresponding to each instruction unit in the instruction set. The instruction set includes position instructions, speed instructions, and torque instructions.

[0008] The instruction preprocessing logic unit of the field-programmable gate array platform is invoked to perform instruction stream classification and reorganization processing on the instruction type identifier, the instruction priority parameter, and the instruction target execution axis number to generate an axis instruction queue set. Each axis instruction queue in the axis instruction queue set is bound to a unique instruction target execution axis number.

[0009] The set of axis command queues is transmitted to the core control algorithm execution unit of the digital signal processor platform. Based on the command priority parameters and servo drive control cycle parameters in the set of axis command queues, task preemptive scheduling is performed to generate a set of axis control command blocks.

[0010] The set of axis control command blocks is fed back to the high-speed signal generation unit of the field programmable gate array platform, and the set of axis control command blocks is processed to generate pulse width modulation waveforms to obtain a set of multiphase pulse width modulation drive signals.

[0011] The multiphase pulse width modulation drive signal set is sent to the power drive module to trigger the servo motor to perform position adjustment, speed adjustment or torque adjustment actions. At the same time, the encoder signal acquisition unit of the field programmable gate array platform captures the original feedback signal set returned by the servo motor in real time.

[0012] Furthermore, embodiments of the present invention also provide a multi-platform architecture servo drive control system, including:

[0013] A processor; a machine-readable storage medium for storing machine-executable instructions of the processor; wherein the processor is configured to execute the aforementioned multi-platform architecture servo drive control method by executing the machine-executable instructions.

[0014] In another aspect, embodiments of the present invention also provide a computer program product, the computer program product including machine-executable instructions, the machine-executable instructions being stored in a computer-readable storage medium, the processor of a multi-platform architecture servo drive control system reading the machine-executable instructions from the computer-readable storage medium, the processor executing the machine-executable instructions, causing the multi-platform architecture servo drive control system to execute the aforementioned multi-platform architecture servo drive control method.

[0015] Based on the above, after receiving the instruction set from the multi-axis motion control system, the instructions are parsed to accurately obtain the instruction type identifier, instruction priority parameter, and target execution axis number for each instruction unit. The instruction preprocessing logic unit of the field-programmable gate array (FPGA) platform is then used to classify and reorganize the parsed instructions, generating an axis instruction queue set bound to a unique target execution axis number. This effectively solves the problem of chaotic instruction processing, allowing instructions to be arranged in an orderly manner according to the target execution axis, improving the efficiency and accuracy of instruction processing. The axis instruction queue set is transmitted to the core control algorithm execution unit of the digital signal processor (DSP) platform. Based on the instruction priority parameter and servo drive control cycle parameter, preemptive task scheduling is performed to generate an axis control instruction block set. This ensures that high-priority instructions are processed promptly, improving the system's real-time performance and dynamic capabilities, enabling the system to quickly respond to various complex motion control requirements. The axis control instruction block set is fed back to the high-speed signal generation unit of the FPGA platform for pulse width modulation (PWM) waveform generation, resulting in a multi-phase PWM drive signal set. Utilizing the high-speed processing capability of the FPGA platform, high-precision and stable drive signals can be generated, effectively improving the driving effect of the servo motor. Finally, the drive signal is sent to the power drive module to trigger the servo motor to perform the corresponding action. At the same time, the encoder signal acquisition unit of the field programmable gate array platform captures the original feedback signal set returned by the servo motor in real time, which further improves the control accuracy and stability of the system and realizes high-performance servo drive control of the multi-axis motion control system. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the execution flow of the servo drive control method with a multi-platform architecture provided in the embodiments of the present invention.

[0017] Figure 2 This is a schematic diagram of exemplary hardware and software components of a multi-platform architecture servo drive control system provided in an embodiment of the present invention. Detailed Implementation

[0018] Figure 1 This is a flowchart illustrating a multi-platform architecture servo drive control method according to an embodiment of the present invention, which will be described in detail below.

[0019] Step S110: Receive the instruction set sent by the multi-axis motion control system, perform instruction type parsing processing on the instruction set, and obtain the instruction type identifier, instruction priority parameter and instruction target execution axis number corresponding to each instruction unit in the instruction set.

[0020] In this embodiment, for example, on a production line used for precision electronic assembly, a multi-axis motion control system (e.g., a robotic arm controller responsible for picking and placing actions) needs to issue a series of motion commands to a servo drive control system. First, within the servo drive control system, logic units deployed on a field-programmable gate array platform perform command reception and parsing.

[0021] Step S111: Construct a physical interface for communication with the multi-axis motion control system in the field programmable gate array platform, and receive the original instruction data frame sent by the multi-axis motion control system in broadcast form through the physical interface. The original instruction data frame includes a frame header identifier field, a frame length field, multiple consecutively arranged instruction units, and a frame check field.

[0022] Specifically, the physical interface is configured to support industrial Ethernet protocols, such as the EtherCAT slave interface. In this electronic assembly scenario, the multi-axis motion control system (master station) periodically broadcasts data frames. The structure of the raw command data frame is strictly defined: the frame header identifier field is a specific 16-bit hexadecimal value used to indicate the start of the data frame; the frame length field is a 16-bit binary number recording the total number of bytes from the end of the frame header to the beginning of the frame check field; followed by multiple consecutive command units, each command unit being a fixed 64-bit length, containing all the raw information of the command; the frame check field uses a 32-bit cyclic redundancy check code to verify the integrity of the transmission process.

[0023] Step S112: Call the hardware parser of the field-programmable gate array platform to perform frame boundary recognition processing on the original instruction data frame, locate the start position of the original instruction data frame according to the frame header identifier field, and determine the end position of the original instruction data frame according to the frame length field, and generate a complete instruction data frame unit.

[0024] The hardware parser is a finite state machine instantiated using a hardware description language. In the idle state, the state machine continuously monitors the input data stream. Once it detects 16 bits of data matching the preset frame header identifier field, it immediately jumps to the "frame receive" state. In the "frame receive" state, the parser begins counting the number of bytes received and compares it with the frame length field value parsed from the frame header. When the count reaches the number of bytes indicated by the frame length field, the state machine jumps to the "frame end" state, completing the capture of a complete instruction data frame unit and storing it in a first-in-first-out buffer.

[0025] Step S113: Perform serial-to-parallel conversion processing on the complete instruction data frame unit to convert the serially transmitted bit stream data into a set of instruction words in parallel data bus format, wherein each instruction word in the instruction word set corresponds to an instruction unit.

[0026] The data frame units output by the hardware parser are still in serial bitstream form. The field-programmable gate array (FPGA) platform internally instantiates a serial-to-parallel conversion module. This module uses a specific bit clock as a reference to shift the input serial bitstream one bit at a time into a 64-bit shift register. Whenever the shift register is full with 64 bits of data (i.e., the length of one instruction unit), the module latches this 64-bit parallel data as an instruction word onto the output bus, forming a parallel instruction word set consisting of multiple 64-bit instruction words. Each instruction word corresponds one-to-one with an instruction unit in the original instruction frame.

[0027] Step S114: Input the instruction word set into the instruction type decoder of the field programmable gate array platform. The instruction type decoder extracts the bit segment information at a predefined position in each instruction word and compares and matches the bit segment information with a preset instruction type encoding table to obtain the instruction type identifier corresponding to each instruction unit.

[0028] An instruction type decoder is essentially a combinational logic circuit. For each 64-bit input instruction word, it extracts the 0th to 3rd bits (the least significant bit) according to a pre-designed bit-segment mapping rule. These 4 bits represent the raw instruction type code. The decoder internally stores an instruction type code table, which is a read-only memory (ROM) containing mappings such as "0001" for "position instruction," "0010" for "speed instruction," and "0011" for "torque instruction." The decoder uses these 4 raw bits as an address to query the ROM, and the retrieved data is the instruction type identifier corresponding to that instruction unit. For example, an 8-bit normalized value might have a position instruction identifier of 0x01, a speed instruction identifier of 0x02, and a torque instruction identifier of 0x03.

[0029] Step S115: Synchronously extract the bit segment information of another predefined position in each instruction word as the original code of the instruction priority of the instruction unit, perform numerical mapping processing on the original code of the instruction priority, and convert it into instruction priority parameters for subsequent scheduling comparison.

[0030] Meanwhile, another parallel combinational logic circuit extracts bits 4 through 7 from the same 64-bit instruction word as the raw instruction priority code. This raw code is a 4-bit binary number ranging from 0 to 15. To accommodate the comparison logic of the real-time task scheduler in the subsequent digital signal processor platform, it needs to be mapped to a unified instruction priority parameter. The mapping process is implemented through a simple arithmetic logic unit; for example, the 4-bit raw code is treated as an unsigned integer and directly used as the core value of the instruction priority parameter. Considering that the system reserves the highest priority for safe tasks, the mapping logic maps the instruction priority parameter with a raw code of 15 to a specific high value, while the raw code of 0 is mapped to the lowest value, ensuring that the larger the value, the higher the priority.

[0031] Step S116: Extract the instruction target execution axis number field from each instruction word. The instruction target execution axis number field contains a binary code value that identifies the target servo drive axis. The binary code value is directly used as the instruction target execution axis number of the instruction unit.

[0032] Another set of combinational logic circuits extracts bits 8 through 15 from the instruction word as the target axis number field. This 8-bit binary code directly corresponds to the unique identifier of each axis in the servo drive system. For example, the binary code "00000001" corresponds to axis 1 (e.g., the shoulder joint of a robotic arm), and "00000010" corresponds to axis 2 (e.g., the elbow joint of a robotic arm). This encoded value is directly latched as the target axis number for this instruction unit, without any conversion.

[0033] Step S117: Perform an integrity check on each instruction unit that has been parsed, and associate and combine the instruction type identifier, the instruction priority parameter, and the instruction target execution axis number to form a structured instruction entry containing the three elements of information.

[0034] An integrity check logic verifies whether the three extraction operations are completed synchronously within the same clock cycle and checks for any out-of-bounds bit extractions. After confirmation, a data combiner concatenates the instruction type identifier (8 bits) output from step S114, the instruction priority parameter (8 bits, mapped from 4 bits) output from step S115, and the instruction target execution axis number (8 bits) output from step S116 to form a 24-bit structured instruction entry. The high 8 bits of this structured instruction entry are the instruction type identifier, the middle 8 bits are the instruction priority parameter, and the low 8 bits are the instruction target execution axis number.

[0035] Step S118: Write the structured instruction entries into the input buffer queue of the field programmable gate array platform in the order of their reception time, and each structured instruction entry in the input buffer queue maintains its original arrival order.

[0036] These 24-bit structured instruction entries are sequentially written to a first-in-first-out (FIFO) input buffer queue consisting of block random access memory. The write clock of this FIFO input buffer queue is synchronized with the clock of the instruction parsing logic, ensuring that the entries are arranged in the arrival order of the instruction units in the original instruction frame. The queue depth is set to be sufficient to buffer instructions over multiple communication cycles, for example, a depth of 512, to prevent data overflow.

[0037] Step S119: Read the structured instruction entries one by one from the input buffer queue, and attach an arrival timestamp obtained from the global clock tree of the field programmable gate array platform to each structured instruction entry to generate instruction entries to be classified with timestamps.

[0038] A read control logic pops structured instruction entries one by one from the read port of the first-in-first-out (FIFO) input buffer queue at a fixed rate. Simultaneously with each entry read, a timestamp appending module captures the current clock count value from the FPGA platform's global clock tree. This global clock tree operates at a very high base frequency (e.g., 100 MHz), providing a high-precision time reference. The timestamp appending module appends the captured 64-bit clock count value to the 24-bit structured instruction entry, forming an 88-bit timestamped instruction entry to be categorized.

[0039] Step S1110: Transmit the instruction entries to be classified with time tags to the instruction preprocessing logic unit as the input data source for subsequent instruction stream classification and reorganization processing.

[0040] Finally, each generated 88-bit instruction entry to be classified is directly transmitted via the internal data bus to the input register group of the instruction preprocessing logic unit instantiated in the field-programmable gate array platform, waiting for the logic unit to perform the next step of processing.

[0041] Step S120: Call the instruction preprocessing logic unit of the field-programmable gate array platform to perform instruction stream classification and reorganization processing on the instruction type identifier, the instruction priority parameter and the instruction target execution axis number to generate an axis instruction queue set. Each axis instruction queue in the axis instruction queue set is bound to a unique instruction target execution axis number.

[0042] In this embodiment, the instruction preprocessing logic unit of the field-programmable gate array platform is responsible for classifying the mixed instruction streams according to the physical axes they control.

[0043] Step S121: The instruction preprocessing logic unit parses each input instruction entry to be classified and extracts its instruction target execution axis number field.

[0044] The logic unit parses the lower 8 bits (i.e., bits 0 to 7) from the 88-bit instruction entry to be classified input in step S1110 above, and uses them as the instruction target execution axis number corresponding to the instruction entry.

[0045] Step S122: Based on the extracted instruction target execution axis number, the instruction preprocessing logic unit routes the instruction entry to the write data port of the private first-in-first-out queue corresponding to the axis number through a multiplexer network.

[0046] The field-programmable gate array (FPGA) platform internally instantiates multiple independent first-in-first-out (FIFO) queues, the number of which is equal to the total number of servo drive axes supported by the system, for example, eight. Each queue is assigned a unique identifier, corresponding one-to-one with the axis number (e.g., 1 to 8) targeted by the instruction. The instruction preprocessing logic unit contains a decoder that decodes the 8-bit axis number extracted in step S121 to generate a corresponding strobe signal. This strobe signal controls the multiplexer network so that the 88-bit data containing the instruction entry is written only to the input of the FIFO queue that matches the axis number.

[0047] Step S123: Each private first-in-first-out queue stores the input instruction entries to be classified sequentially in the queue's memory according to the write enable signal it receives. The queue's memory is composed of block random access memory resources.

[0048] When the write enable signal in step S122 is valid, the corresponding FIFO queue writes the 88-bit instruction entries to be classified on the data bus into its internal block random access memory array. The write address is automatically managed by the read / write pointers inside the queue. In this way, each FIFO queue stores all instructions sent to a specific axis, strictly maintaining the original time order of instruction arrival.

[0049] Step S124: The instruction preprocessing logic unit periodically checks the status of each private first-in-first-out queue, reads its non-empty flag, and extracts the axis number of the non-empty queue and the instruction priority parameter in the head instruction entry of the queue.

[0050] During the preparation phase before the start of each servo drive control cycle (e.g., a 125-microsecond cycle signal synchronously generated by the digital signal processor platform), the instruction preprocessing logic unit initiates a polling round, sequentially accessing the status register of each private first-in-first-out queue. If the non-empty flag of a queue is logic high, it indicates that there are instructions to be processed in that queue. The logic unit then prefetches the first 88 bits of the instruction entry from the queue's read data port and parses the instruction priority parameter (bits 8 to 15) from it. This instruction priority parameter will be used for subsequent scheduling decisions.

[0051] Step S125: Pack the extracted axis number, the corresponding instruction priority parameter, and other relevant information (such as the storage pointer of the head instruction) to generate a queue descriptor, and gather all the queue descriptors of non-empty queues to form a description table of the axis instruction queue set.

[0052] For each non-empty queue, the instruction preprocessing logic unit generates a queue descriptor. This queue descriptor is a fixed-length data structure, for example, 64 bits, containing: an axis number field (8 bits), a highest priority parameter field parsed from the head instruction (8 bits), a pointer field (32 bits) pointing to the current read pointer position of the queue in block random access memory, and a count field (16 bits) of the currently accumulated instruction entries in the queue. All these descriptors are organized into a descriptor table, stored in another dedicated block random access memory. This descriptor table, together with the actual instruction data in each queue's memory, constitutes the axis instruction queue set.

[0053] Step S126: Through the high-speed data communication link between the field-programmable gate array platform and the digital signal processor platform, the description table of the axis instruction queue set and the memory access interface information of each queue are transmitted to the digital signal processor platform.

[0054] This high-speed data communication link is, for example, a parallel data bus with handshake signal lines. The Field-Programmable Gate Array (FPGA) platform acts as the slave device, and the Digital Signal Processor (DSP) platform acts as the master device. The FPGA platform maps the block random access memory (BRAM) of the instruction queue set description table (ISDS) of the memory axis into the address space of the DSP platform. The DSP platform can directly read this description table via direct memory access (DMI) without intervention from the FPGA core, and then, based on the pointer information in the description table, directly access the memory of each private first-in-first-out (FIFO) queue through the same address mapping mechanism to read the specific instruction entries.

[0055] Step S130: The axis instruction queue set is transmitted to the core control algorithm execution unit of the digital signal processor platform. Task preemptive scheduling is performed according to the instruction priority parameters and servo drive control cycle parameters in the axis instruction queue set to generate an axis control instruction block set.

[0056] In this embodiment, the digital signal processor platform is responsible for the core servo control algorithm calculation and performs task scheduling within a strict time period according to the instruction priority.

[0057] Step S131: In the core control algorithm execution unit of the digital signal processor platform, a priority-based real-time task scheduling kernel is maintained. The real-time task scheduling kernel manages multiple software task control blocks that correspond one-to-one with the instruction target execution axis number.

[0058] The real-time operating system running on the digital signal processor platform (e.g., a lightweight real-time kernel conforming to the POSIX standard) maintains a list of task control blocks. Each servo drive axis (axis 1 to axis 8) corresponds to an independent software task control block. Each task control block is a complex data structure containing the task's current state (ready, running, suspended), task priority, task function entry pointer, task stack pointer, and a pointer to the instruction queue of that axis mapped from the field-programmable gate array platform.

[0059] Step S132: Receive the axis instruction queue set through the high-speed data communication link, parse the axis instruction queue set and classify it according to the axis number to be executed by the instruction target, and store them into the task private data buffer associated with each software task control block.

[0060] The digital signal processor (DSP) platform, through its direct memory access controller (DMI), automatically moves the actual instruction data from the FPGA's block random access memory (BRAM) to the DSP's internal local static random access memory (SRAM) based on address mapping information obtained from the FPGA platform. The moving process is categorized by axis number, with each axis's data stored in a circular buffer associated with its corresponding software task control block, serving as its task-private data buffer.

[0061] Step S133: Each software task control block maintains a local task ready flag and a task priority attribute. The local task ready flag is set according to whether its corresponding task private data buffer is empty. The task priority attribute is obtained directly from the instruction priority parameter of the received instruction entry.

[0062] The real-time task scheduling kernel periodically checks the read / write pointers of each task's private data buffer (circular buffer). If the read and write pointers are not equal, indicating the buffer is not empty, the kernel sets the local task ready flag in the corresponding task control block to 1 (valid). Simultaneously, when a new instruction entry is stored in the buffer, the kernel parses the instruction priority parameter field (8 bits) of that entry and updates the dynamic priority attribute in the corresponding task control block with this value. This priority changes with the arrival of new instructions.

[0063] Step S134: At the beginning of each servo drive control cycle, the real-time task scheduling kernel scans the local task ready flags of all software task control blocks and adds all software task control blocks with valid local task ready flags to the competitive task set of the current cycle.

[0064] Each servo drive control cycle is initiated by an interrupt generated by a high-precision timer on the digital signal processor platform. In the interrupt service routine, the scheduler is awakened and iterates through all software task control blocks, checking their task ready flags. For task control blocks with a flag of 1, the scheduler adds their pointers to a temporary ready task list, which represents the set of competing tasks for the current cycle.

[0065] Step S135: Extract the task priority attribute of each software task control block from the set of competing tasks, and simultaneously extract the instruction timeout deadline of the instruction queue corresponding to each software task control block; sort all tasks in the set of competing tasks in descending order according to the task priority attribute; for tasks with the same task priority attribute, calculate the urgency factor based on their instruction timeout deadline, and sort the corresponding part of the tasks in secondary order according to the urgency factor, and finally generate the set of competing tasks in descending order.

[0066] The scheduler traverses the ready task list. First, it extracts the current dynamic priority attribute from each task control block. Simultaneously, it extracts the previously attached arrival timestamp from the head entry of the corresponding axis instruction queue and, combined with the instruction type (e.g., position instructions typically have strict completion deadlines), calculates an instruction timeout deadline. The scheduler first performs a descending quicksort of the list using the priority attribute as the key. After the primary sort, the scheduler divides the list into several sub-lists, each containing tasks with the same priority. Next, for each task in the sub-list, the scheduler calculates a urgency factor based on its instruction timeout deadline. This urgency factor is inversely proportional to the deadline; the closer the deadline, the higher the urgency factor. Then, within each sub-list, it performs a descending insertion sort based on the urgency factor. Finally, the entire list presents an ordered state with the highest priority and most urgent tasks at the front.

[0067] Step S136: The real-time task scheduling kernel selects the task with the highest ranking from the set of competing tasks arranged in descending order as the first task to be executed in the current cycle, saves the context of the current task, and jumps to the entry point of the core control algorithm program corresponding to the first task to be executed in the current cycle.

[0068] The scheduler retrieves the task control block pointed to by the head node of the ordered linked list. A context switch is triggered, saving the current CPU register state (if any tasks were previously running) to their task stack. Then, the task stack pointer and program counter are loaded from the selected task control block, causing the CPU to jump to the entry address of the task's core control algorithm program to begin execution.

[0069] Step S137: Execute the core control algorithm program, read the instruction type identifier and related parameters of the first instruction entry from the task private data buffer corresponding to the task, perform position loop, speed loop and current loop control algorithm calculations, and generate a preliminary axis control instruction block.

[0070] The scheduled task begins execution, first reading the instruction entry at the head of the queue from its private data buffer (circular buffer). Based on the instruction type identifier (0x01 for position, 0x02 for velocity, 0x03 for torque), the program enters different branches.

[0071] For example, if the instruction is a position instruction, the algorithm flow is as follows: First, the position loop controller reads the target position parameter (a 32-bit value) given in the instruction and the current actual position fed back from the field-programmable gate array platform (obtained via shared memory). The position loop controller uses a proportional-integral (PI) control algorithm, and its output (i.e., the setpoint of the velocity loop) consists of a proportional term and an integral term. The proportional term is the position deviation multiplied by the position loop proportional gain coefficient Kp_pos, and the integral term is the accumulated sum of position deviations multiplied by the position loop integral gain coefficient Ki_pos. This accumulated sum is stored in the task's data segment and updated every cycle. The output of the position loop is then limited and used as the setpoint of the velocity loop.

[0072] Next, the speed loop controller uses the output of the position loop as the setpoint and the actual speed feedback value as the feedback value, and performs calculations using the proportional-integral control algorithm. Its output is the setpoint of the current loop (torque current component Iq_ref). The calculation process is similar, using the speed loop proportional gain coefficient Kp_spd and the speed loop integral gain coefficient Ki_spd. Simultaneously, based on the motor model, an excitation current component Id_ref (usually 0) is typically provided.

[0073] Finally, the calculation results of these three loops, along with some auxiliary information (such as command priority, axis number, etc.), are packaged into a data structure, namely the preliminary axis control command block. This preliminary axis control command block contains the direct axis current command value Id_ref (16 bits), the quadrature axis current command value Iq_ref (16 bits), and some control words (such as enable signals, mode selection, etc.).

[0074] Step S138: Store the initial axis control instruction block into the task private data output buffer, and check whether the current servo drive control cycle deadline has been reached. If it has not been reached and there are still unexecuted tasks in the competing task set, save the current task state, resume the execution of the real-time task scheduling kernel, and select the next ranked task to execute.

[0075] After the task is completed, the generated preliminary axis control instruction block is written to another output circular buffer associated with the task. Then, the task actively calls a scheduling point function to return control to the kernel. The kernel saves the context of the current task, then retrieves the task corresponding to the next node from the task list sorted in step S136, restores its context, and executes it.

[0076] Step S139: Repeat the task selection and task execution process until the current servo drive control cycle deadline is reached. The real-time task scheduling kernel stops starting new tasks and collects and packages the preliminary axis control instruction blocks generated in the private data output buffers of all tasks to generate the axis control instruction block set for the current cycle.

[0077] A timer in the kernel generates an interrupt at the end of the servo drive control cycle. In the interrupt service routine, the kernel sets a global flag to prevent any new tasks from starting. For currently executing tasks, they are allowed to run until the next scheduling point and are not rescheduled. At the end of the cycle, the kernel iterates through all tasks, collecting the initial axis control instruction blocks to be sent from their output buffers into a main send buffer via a high-speed data communication link (such as a parallel bus). These instruction blocks are packaged into a single set according to the order in which they were generated—the axis control instruction block set for the current cycle. This set is then sent as a whole to the field-programmable gate array (FPGA) platform.

[0078] Step S140: Feed back the set of axis control command blocks to the high-speed signal generation unit of the field programmable gate array platform, and perform pulse width modulation waveform generation processing on the set of axis control command blocks to obtain a set of multiphase pulse width modulation drive signals.

[0079] In this embodiment, the axis control instruction block calculated by the digital signal processor platform is sent back to the field programmable gate array platform, where the pulse width modulation waveform required to drive the motor is generated at high speed by hardware.

[0080] Step S141: The set of axis control command blocks is sent to the high-speed input port of the field programmable gate array platform in parallel data burst transmission mode through a high-speed data communication link between the pre-established digital signal processor platform and the field programmable gate array platform.

[0081] The digital signal processor platform, through its external memory interface, writes a packaged set of axis control instructions as a data burst to a specific address range mapped on the field-programmable gate array (FPGA) platform. This write operation triggers a high-speed parallel data transmission. With a 32-bit data bus width, and in conjunction with the address bus and write control signals, multiple 32-bit data bits can be written consecutively in a single burst, transmitting the entire set of axis control instructions completely.

[0082] Step S142: The direct memory access controller instantiated inside the field programmable gate array platform automatically transfers the set of axis control command blocks received by the high-speed input port to a dedicated dual-port block random access memory to complete zero-overhead data transmission.

[0083] An internal direct memory access controller (DMI) is instantiated within the field-programmable gate array (FPGA) platform. This DMI monitors write transactions on the high-speed input ports. Once a data write is detected, it takes over bus control and directly transfers the written data from the input port register to a pre-designated dual-port block random access memory (BRAM). This process requires no intervention from the soft-core processor within the FPGA logic, achieving data transfer with zero CPU overhead. One port of the BRAM is dedicated to writing by the DMI, while the other port is used for reading by subsequent high-speed signal generation units.

[0084] Step S143: Continuously read the set of axis control instruction blocks from one read port of the dual-port block random access memory, parse the current loop setpoint sequence in each axis control instruction block, and load the current loop setpoint sequence into the reference value register group of the waveform generator inside the high-speed signal generation unit.

[0085] At the start of the next pulse width modulation (PWM) carrier cycle, the state machine inside the high-speed signal generation unit initiates a read operation on the dual-port block random access memory (DRAM). Starting from the memory's starting address, it sequentially reads each axis control instruction block. For each instruction block, it parses out the direct-axis current instruction value Id_ref and the quadrature-axis current instruction value Iq_ref. These two values ​​constitute the current loop setpoint for that axis. However, PWM requires the instantaneous values ​​of the three-phase sine waves, thus necessitating an inverse coordinate transformation. The high-speed signal generation unit integrates a hardware coordinate transformation module. Based on the current electrical angle (from encoder feedback), it uses the inverse Parker and inverse Clarke transforms to calculate the three-phase voltage instruction values ​​Va, Vb, and Vc in the stationary coordinate system in real time from Id_ref and Iq_ref in the rotating coordinate system. These three values ​​are then loaded into three reference value register groups of the waveform generator, each register group corresponding to a half-bridge.

[0086] Step S144: Invoke the digital triangular wave generator instantiated inside the high-speed signal generation unit. The digital triangular wave generator generates a digital triangular carrier signal with stable periodicity and amplitude in real time based on the carrier frequency setting value and carrier amplitude setting value read from the parameter storage module.

[0087] A digital triangular wave generator is instantiated within the high-speed signal generation unit. This digital triangular wave generator is essentially a reversible counter that reads two key parameters from a parameter storage module: a carrier frequency setting (e.g., a value determining the counting step size) and a carrier amplitude setting (determining the counter's maximum value). The counter starts at 0, increments by one step each clock cycle until it reaches the maximum amplitude, then decrements, returns to 0, and increments again, repeating this process. The output count forms a triangular wave in time. This digital value represents the instantaneous value of the carrier signal.

[0088] Step S145: The current loop setpoint sequence (actually the three-phase voltage command value) stored in the reference value register group of the waveform generator is synchronously input to multiple parallel hardware comparators along with the digital triangular carrier signal. Each hardware comparator compares one current loop setpoint with the instantaneous value of the digital triangular carrier signal point by point.

[0089] The three-phase voltage command values ​​Va, Vb, and Vc are each sent to one input of three parallel hardware comparators. Simultaneously, the current instantaneous count value of the digital triangular carrier signal is sent to the other input of these three comparators.

[0090] Step S146: Each hardware comparator outputs a pulse signal in real time according to the comparison result. When the current loop setpoint is greater than the instantaneous value of the digital triangular carrier signal, it outputs a high level; otherwise, it outputs a low level, thereby generating the original pulse width modulation waveform sequence corresponding to the current loop setpoint sequence.

[0091] In each clock cycle, the comparators perform a comparison. If the value of Va is greater than the instantaneous value of the triangular carrier wave, the comparator outputs a logic high level; otherwise, it outputs a low level. Thus, the magnitude of Va determines the duration of the high-level output (i.e., the pulse width), thereby converting the analog voltage command into the width information of a digital pulse. The outputs of the three comparators, PWM_A, PWM_B, and PWM_C, constitute the original pulse width modulation waveform sequence of the three phases.

[0092] Step S147: Input the original pulse width modulation waveform sequence into the dead time insertion unit. The dead time insertion unit delays the output by a preset dead time parameter at each rising edge of the original pulse width modulation waveform sequence before allowing the output to rise, and terminates the output at each falling edge by a preset dead time parameter in advance, thereby generating a complementary pulse width modulation waveform pair with a dead time interval.

[0093] The original pulse width modulation waveform sequences PWM_A, PWM_B, and PWM_C correspond to the upper transistor drive signals for each half-bridge. To prevent shoot-through short circuits between the upper and lower transistors, a dead time must be inserted. The dead time insertion unit receives the original signals and generates a complementary pair of signals (upper and lower transistors) for each phase. The implementation is as follows: for the upper transistor signal, when a rising edge of the original signal is detected, the upper transistor output rises only after a delay of one clock cycle set by the dead time parameter register; when a falling edge of the original signal is detected, the upper transistor output falls immediately. For the lower transistor signal, the logic is reversed: when a rising edge of the original signal is detected, the lower transistor output falls immediately; when a falling edge of the original signal is detected, the lower transistor output rises only after a delay of one dead time parameter. This ensures that during the switching of the upper and lower transistors, there is a dead time during which both transistors are simultaneously turned off.

[0094] Step S148: Assign the complementary pulse width modulation waveform to the input pulse matrix. The pulse allocation matrix routes the complementary pulse width modulation waveform to the specific output channel group corresponding to the instruction target execution axis number carried in each axis control instruction block.

[0095] The pulse distribution matrix is ​​a multiplexer network. When processing each axis control command block, the high-speed signal generation unit simultaneously resolves the target axis number (8 bits) corresponding to that command block. This axis number is used as the matrix's routing signal. For example, if the currently processed axis command block corresponds to axis number "00000001", then the matrix connects the currently calculated three complementary pulse width modulation waveform pairs (a total of 6 signals) to the set of output channels physically connected to the power drive module of axis 1.

[0096] Step S149: Instantiate an output driver buffer at the end of each output channel group. The output driver buffer converts the level standard of the complementary pulse width modulation waveform pair from the core logic level to a level standard that can directly drive the external power module, and performs current amplification.

[0097] Before a signal is sent out of the field-programmable gate array (FPGA) chip pins, it needs to pass through an output driver buffer. This buffer has a level conversion function, which can convert the logic level of the FPGA's internal core voltage (e.g., 1.2V) to the level standard required by the external interface, such as 3.3V or 5V transistor-to-transistor logic levels. At the same time, the buffer has a large drive current capability, which can drive the LEDs of the subsequent optocoupler or directly drive the input stage of the power module.

[0098] Step S1410: Collect the complementary pulse width modulation waveforms of all output channel groups after level conversion and current amplification to form a complete set of drive signals containing multiphase pulse width modulation drive signals, and send them to the power drive module through the parallel output pin of the field programmable gate array platform.

[0099] All processed signals are ultimately sent out simultaneously through multiple dedicated parallel output pins of the field-programmable gate array (FPGA) chip. These signal lines are connected to the interface of the power drive module via ribbon cables or differential cables, thereby transmitting the calculated drive instructions to the execution layer in the form of hardware pulses.

[0100] Step S150: The multiphase pulse width modulation drive signal set is sent to the power drive module to trigger the servo motor to perform position adjustment, speed adjustment or torque adjustment actions. At the same time, the encoder signal acquisition unit of the field programmable gate array platform captures the original feedback signal set returned by the servo motor in real time.

[0101] In this embodiment, the signal ultimately acts on the motor in the physical world, while the system's "eyes"—the encoder feedback—start working and collects the actual motion state.

[0102] Step S151: The set of multiphase pulse width modulation drive signals output from the parallel output pin of the field programmable gate array platform is transmitted to the power drive module at the remote end through optical fiber or differential cable. The power drive module includes a smart power module and a drive optocoupler.

[0103] To enhance anti-interference capabilities, especially in industrial settings, these pulse-width modulated signals are first converted into optical or differential signals for remote transmission. For example, the signal is fed into an electro-optical conversion module and transmitted via optical fiber to a power drive module near the motor. The optocoupler receiver in the power drive module converts the optical signal back into an electrical signal. The drive optocoupler not only provides electrical isolation but also incorporates an amplifier circuit, amplifying the received weak electrical signal into a strong electrical signal (typically +15V for turn-on and -5V for turn-off) capable of driving the gate of the insulated-gate bipolar transistor inside the intelligent power module.

[0104] Step S152: The drive optocoupler in the power drive module receives the set of multiphase pulse width modulation drive signals, isolates and amplifies the received optical or electrical signals, and generates a high-voltage drive signal that can drive the gate of the insulated gate bipolar transistor inside the intelligent power module.

[0105] The driver optocoupler integrates high-speed isolation and drive circuitry. It receives weak pulse-width modulation signals from a field-programmable gate array (FPGA). After isolation by an internal LED-photodetector, the output stage uses its internally integrated totem-pole circuit to connect an externally supplied drive power supply (e.g., +15V) or a shutdown power supply (e.g., -5V) to the gate of an insulated-gate bipolar transistor, depending on the state of the input signal. This generates a gate drive signal with sufficient drive capability and appropriate voltage swing.

[0106] Step S153: The three-phase inverter bridge arm inside the intelligent power module controls the conduction and cutoff of the upper bridge arm insulated gate bipolar transistor and the lower bridge arm insulated gate bipolar transistor according to the logic level of the high voltage drive signal, so as to convert the external DC bus power supply into a three-phase AC power supply with controlled frequency and amplitude.

[0107] The intelligent power module integrates six insulated-gate bipolar transistors (IGBTs) to form a three-phase full-bridge circuit. When the IGBT in the upper bridge arm receives a high-level (+15V) drive signal from the drive optocoupler, it turns on, connecting the positive DC bus voltage to one phase winding of the motor. When the IGBT in the lower bridge arm receives a high-level drive signal, it turns on, connecting that phase winding to the negative DC bus (ground). By controlling the on / off combinations of these six transistors, voltage vectors of arbitrary direction and magnitude can be synthesized on the three-phase windings of the motor. Continuous switching operations generate a three-phase sinusoidal alternating current at the motor terminals, with frequency and amplitude determined by the fundamental component of the pulse width modulation signal.

[0108] Step S154: Apply the three-phase AC power supply to the three-phase stator windings of the servo motor. A rotating magnetic field is generated inside the servo motor according to the principle of electromagnetic induction. The rotation direction of the rotating magnetic field is determined by the phase sequence of the multi-phase pulse width modulation drive signal set, and the rotation speed is determined by the fundamental frequency of the multi-phase pulse width modulation drive signal set.

[0109] A three-phase sinusoidal alternating current flowing through stator windings spaced 120 degrees apart will generate a rotating magnetic field. The direction of the rotating magnetic field depends on the phase sequence of the three-phase alternating current (U, V, W), while the rotational speed of the magnetic field is proportional to the frequency of the alternating current and is determined by the fundamental frequency of the pulse width modulation signal.

[0110] Step S155: The rotor of the servo motor is subjected to electromagnetic torque under the action of the rotating magnetic field and begins to rotate along the direction of the rotating magnetic field to realize position adjustment or speed adjustment. The rotation angle is determined by the pulse width and number of the multiphase pulse width modulation drive signal set.

[0111] The magnetic field generated by the permanent magnets on the rotor interacts with the rotating magnetic field of the stator, producing electromagnetic torque that drives the rotor to rotate synchronously with the rotating magnetic field (for permanent magnet synchronous motors). The angle through which the motor rotates is macroscopically determined by the cumulative effect of the applied voltage pulses. For example, in a speed control mode, if a pulse width modulation signal of a certain frequency is continuously applied, the motor will rotate continuously at a constant speed, and the angle through which it rotates will increase linearly with time.

[0112] Step S156: When the instruction type identifier in the set of axis control instruction blocks is a torque instruction, the axis control instruction block output by the core control algorithm execution unit contains a torque current instruction value. By controlling the amplitude and phase of the stator current, the magnitude of the electromagnetic torque is directly controlled to achieve torque adjustment.

[0113] If the instruction type identifier is a torque instruction, then in the control instruction blocks Id_ref and Iq_ref generated in step S137, Iq_ref directly corresponds to the given value of the torque. In this case, the position loop and speed loop are bypassed or do not participate in the calculation. The system directly controls the magnitude of the q-axis current (torque current) flowing into the motor, thereby directly and quickly controlling the magnitude of the motor's output torque, for example, in applications such as tension control.

[0114] Step S157: During the servo motor's operation, the encoder signal acquisition unit continuously captures changes in rotor position and speed, forming feedback for closed-loop control.

[0115] Meanwhile, physical changes at the site are captured by sensors. This capture process is described in detail below.

[0116] Step S1571: Configure multiple input pins of the field programmable gate array platform to differential signal receiving mode, and make a one-to-one physical connection between each input pin and the differential signal lines A positive, A negative, B positive, B negative, Z positive, and Z negative of the incremental encoder of the servo motor.

[0117] The first step in the encoder signal acquisition unit is physical connection. The input / output pins of the field-programmable gate array (FPGA) platform are configured for low-voltage differential signal reception mode to suppress common-mode noise. The six differential signal lines (A+, A-, B+, B-, Z+, Z-) output by the incremental encoder of each axis are connected to the six pre-assigned differential input pin pairs corresponding to that axis on the FPGA platform.

[0118] Step S1572: Instantiate a differential signal decoder in the subsequent stage of each differential input pin pair. The differential signal decoder performs subtraction and shaping operations on the received positive and negative A signals to restore the standard single-ended A-phase signal. At the same time, the same processing is performed on the B-phase signal and the Z-phase signal.

[0119] Each differential input pin pair (e.g., A+ and A-) is followed by a hardware differential decoder. This hardware differential decoder internally contains a high-speed comparator that compares the difference between the A+ and A- signals (V_A+ minus V_A-) with a zero-level threshold. If the difference is positive, it outputs a high level; if negative, it outputs a low level. In this way, it restores the tiny differential voltage signals to standard single-ended digital signals A, B, and Z with amplitudes equal to the core logic level (e.g., 3.3V).

[0120] Step S1573: Input the restored single-ended A-phase signal and single-ended B-phase signal into the quadrature decoding module. The quadrature decoding module performs phase detection processing on the phase relationship between the A-phase signal and the B-phase signal. When the A-phase leads the B-phase signal, it determines that the motor is rotating in the forward direction and generates a forward direction indicator. When the B-phase leads the A-phase signal, it determines that the motor is rotating in the reverse direction and generates a reverse direction indicator.

[0121] Single-ended signals A and B are fed into a quadrature decoding module. The core of this module is a finite state machine that detects the edges and levels of signals A and B. Within one clock cycle, it compares the state changes of signals A and B. If, at one edge, signal A changes from 0 to 1 while signal B is 0, and at the next edge, signal A changes from 1 to 0 while signal B is 1, this pattern corresponds to phase A leading phase B by 90 degrees. The state machine determines this as forward rotation and outputs a direction flag indicating "forward rotation." The opposite pattern is determined as reverse rotation, and the direction flag is set to "reverse rotation."

[0122] Step S1574: The quadrature decoding module simultaneously performs quadruple frequency counting on the rising and falling edges of the A-phase signal and the B-phase signal, and accumulates the change in the count value in each servo drive control cycle to generate a high-resolution position increment count value.

[0123] To achieve higher position resolution, the quadrature decoding module includes an edge detection and counter that detects every rising and falling edge of the A and B signals. For each detected edge, regardless of direction, the internal quadruple frequency counter increments or decrements by 1 based on the direction indicator. Thus, instead of the encoder generating N pulses per revolution, the quadruple frequency generates 4N count values ​​per revolution, improving the resolution by a factor of four. At the end of each servo drive control cycle, the change in the count value during that cycle (i.e., the current count value minus the count value of the previous cycle) is latched and used as the position increment count value for that cycle.

[0124] Step S1575: Input the position increment count value into the increment accumulator. The increment accumulator sums the position increment count values ​​obtained in each control cycle based on the motor power-on time to generate a relative position accumulation value starting from the starting position.

[0125] Each axis has a dedicated incremental accumulator, which is a 32-bit hardware register. At the beginning of each control cycle, the incremental accumulator automatically adds the position increment count calculated in step S1574 to its current value. This accumulation process is purely hardware-based and is completed within one clock cycle. The initial value of the accumulator is cleared to zero upon system reset; therefore, its value represents the cumulative number of pulses the motor has rotated since power-on, i.e., the relative position accumulation value.

[0126] Step S1576: Input the restored single-ended Z-phase signal into the zero-position capture module. The zero-position capture module detects the rising edge of the Z-phase signal. When the rising edge is detected, a zero-position pulse flag is generated, and the current accumulated value of the incremental accumulator is locked as the zero-position offset of the servo motor.

[0127] The zero-position capture module continuously monitors the Z signal. The Z signal is the encoder's zero-position signal, outputting only one pulse per revolution. When the module detects the rising edge of the Z signal, it immediately generates a zero-position capture event. Simultaneously, it enables a hardware latch, which instantly captures and saves the value of the incremental accumulator at that moment. This latched value represents the offset of the encoder's zero position relative to the power-on starting point, i.e., the zero-position offset.

[0128] Step S1577: Correct the relative position accumulation value according to the zero position offset, subtract the zero position offset from the relative position accumulation value, and generate an absolute position count value with the encoder zero position as the reference point.

[0129] During normal operation, a subtractor module performs real-time calculations: subtracting the zero-position offset latched and stored in step S1576 from the current incremental accumulator's relative position accumulation value. This calculation result is the absolute position count value based on the encoder's physical zero position, eliminating the influence of random power-on position. Each time the motor completes one revolution and the Z signal arrives again, this absolute position count value is reset to zero, thus ensuring its periodicity.

[0130] Step S1578: Input the absolute position count value and the cycle duration in the servo drive control cycle parameters into the speed calculation unit. The speed calculation unit calculates the difference between the absolute position count values ​​of two adjacent control cycles and divides the difference by the cycle duration to obtain the actual speed feedback value of the servo motor.

[0131] The speed calculation unit performs a calculation once per control cycle. It reads the absolute position count value P_current for the current cycle from the register and the absolute position count value P_previous saved from the previous cycle. Then, it calculates the difference delta_P = P_current - P_previous. This difference represents the number of pulses the motor has rotated in the current cycle. Since the mechanical angle corresponding to each pulse is known (depending on the number of encoder lines and the fourth harmonic), multiplying delta_P by the angle of each pulse gives the angle change. However, it is more convenient to measure the speed in pulses per second. The speed calculation unit uses delta_P as the numerator and the duration of the servo drive control cycle T_cycle (in seconds) as the denominator, and calculates the speed N_fb = delta_P / T_cycle using a hardware divider. This value is the actual speed feedback value for the current cycle, in pulses per second.

[0132] Step S1579: Bind the actual rotational speed feedback value and the absolute position count value with the current time information obtained from the global clock tree to generate a rotational speed feedback data unit and a position feedback data unit with a precise timestamp.

[0133] Before sending the feedback data to the digital signal processor platform, a data packaging module obtains a 64-bit high-precision clock count value from the global clock tree as the current time information. This time information is then combined with the 32-bit absolute position count value calculated in step S1577, the 32-bit actual rotational speed feedback value calculated in step S1578, and the corresponding instruction target execution axis number (8 bits) to form a timestamped feedback data unit. Position and rotational speed are packaged separately for easier subsequent processing.

[0134] Step S1580: The speed feedback data units and position feedback data units with precise timestamps are classified and stored according to the corresponding instruction target axis number, and the original feedback signal set of each servo drive axis is constructed.

[0135] These timestamped feedback data units are written to another set of dual-port block random access memory on the field-programmable gate array platform via an internal bus. This set of memory is also partitioned according to axis number. The digital signal processor platform can read these memories in each control cycle through a direct memory access method similar to that in step S132 to obtain the actual motion state feedback with precise timestamps corresponding to the currently issued command, thereby forming the raw feedback signal set for each axis for closed-loop control calculation in the next cycle.

[0136] At this point, a complete control cycle, from command reception, parsing, scheduling, calculation, waveform generation to drive execution and feedback acquisition, has been completed.

[0137] Step S210: Communication management and peripheral device control steps performed in the ARM processor platform.

[0138] In this embodiment, in addition to the core real-time control tasks, the system also includes an ARM processor platform responsible for handling non-real-time tasks such as communication, monitoring, and human-computer interaction.

[0139] Step S211: Run an embedded real-time operating system on the ARM processor platform, establish an Ethernet communication connection with the upper-level factory information system through the network protocol stack of the embedded real-time operating system, and receive the production task configuration file issued by the upper-level factory information system.

[0140] After the ARM processor platform powers on, it starts an embedded real-time operating system, such as Linux. This operating system runs a TCP / IP network protocol stack. The ARM processor, acting as a network node, connects to the factory's local area network via an Ethernet interface, establishing a TCP-based communication connection with the upper-level Manufacturing Execution System (MES). The MES then distributes a production task configuration file, which may be in JSON or XML format and contains all the settings for the current production task.

[0141] Step S212: Parse the production task configuration file and extract the multi-axis motion trajectory planning parameters, the operating mode setting parameters of each axis servo drive, and the fault protection threshold parameters contained in the production task configuration file.

[0142] An application running on an ARM processor parses the received configuration file and extracts key parameters based on predefined tags. For example, it extracts the content under the "Track Planning" tag to obtain motion trajectory parameters for each axis, such as movement speed, acceleration, and target position sequence. It extracts the content under the "Operating Mode" tag to determine whether each axis is operating in position mode, speed mode, or torque mode. It extracts the content under the "Fault Protection" tag to obtain fault protection threshold parameters such as overcurrent threshold, overspeed threshold, and position following error limit.

[0143] Step S213: The multi-axis motion trajectory planning parameters are transmitted to the trajectory planning algorithm module running on the ARM processor platform through the internal process communication mechanism of the embedded real-time operating system. The trajectory planning algorithm module performs motion trajectory interpolation calculations based on the multi-axis motion trajectory planning parameters to generate a continuous instruction sequence containing position instructions, speed instructions, and torque instructions.

[0144] The trajectory planning algorithm module (a separate software process) inside the ARM processor receives trajectory planning parameters via shared memory or a message queue. This module executes an interpolation algorithm. For example, for point-to-point motion, it can use an S-curve velocity planning algorithm to discretize the entire motion path into a series of small path segments. Each servo drive control cycle (e.g., 125 microseconds) calculates an intermediate point containing information such as the target position and target velocity of each axis at that moment. This information is formatted into standard instruction units and combined into a continuous instruction sequence.

[0145] Step S214: The generated instruction sequence is sent to the digital signal processor platform in the form of data packets through the high-speed bus interface between the ARM processor platform and the digital signal processor platform, so that the core control algorithm execution unit can perform preemptive scheduling processing of tasks.

[0146] The ARM processor writes the generated instruction sequence data packet to a memory area shared with the digital signal processor platform via a high-speed bus interface (such as PCIe or RapidIO), and triggers an interrupt to notify the digital signal processor platform that a new instruction task has arrived. After receiving the notification, the interrupt service routine of the digital signal processor platform processes these instructions according to step S130 and subsequent steps.

[0147] Step S215: Read the set of raw feedback signals captured in real time from the field programmable gate array platform through a high-speed data communication link, perform data parsing and format conversion processing on the set of raw feedback signals, and generate unified format feedback data suitable for processing in the ARM processor platform.

[0148] The ARM processor periodically reads the raw feedback signal set from the FPGA platform memory via a high-speed data communication link (e.g., via a PCIe-mapped address space). Since the raw feedback data is in timestamped binary two's complement form, a driver on the ARM processor is responsible for parsing this raw data, converting it into floating-point numbers or standard integers, and organizing it into a uniform format of feedback data that includes physical units (such as revolutions per minute, degrees).

[0149] Step S216: Compare and monitor the unified format feedback data with the operating mode setting parameters set in the production task configuration file. When the deviation between the actual speed feedback value or position feedback value in the unified format feedback data and the set value exceeds the preset monitoring threshold, an abnormal operating status event is generated.

[0150] The monitoring thread on the ARM processor continuously compares the converted feedback data with the set values ​​parsed from the configuration file. For example, it compares the current actual rotational speed feedback value N_fb with the planned target speed value N_ref, calculating the deviation e = |N_fb - N_ref|. If this deviation e exceeds the speed tracking error threshold set in the configuration file, or the position tracking error exceeds the position deviation threshold, the monitoring thread generates an abnormal running status event and encapsulates the relevant data (such as axis number, deviation value, and occurrence timestamp) into an event structure.

[0151] Step S217: Invoke the fault handling thread in the ARM processor platform. The fault handling thread queries the corresponding fault response action code from the fault handling strategy table stored in non-volatile memory according to the type of the abnormal running state event.

[0152] The fault handling thread is awakened and receives the exception event. It then queries a database table stored in non-volatile memory using the event type (e.g., "speed tracking error") as the key. This database table defines the handling strategies for different fault types. For example, for "excessive speed tracking error," the query result might be "shutdown and alarm" (action code 0x01); for "loss of sensor communication," it might be "emergency shutdown" (action code 0x02).

[0153] Step S218: Based on the fault response action code, send an alarm trigger signal to an external audible and visual alarm device through a general input / output interface, and simultaneously report fault alarm information, including the fault type and the time of fault occurrence, to the upper-level factory information system through an Ethernet communication connection.

[0154] Based on the retrieved fault response action code, the ARM processor outputs a specific level signal through the general-purpose input / output interface. For example, for action code 0x01, it sets one pin connected to the alarm light to a high level, triggering the alarm light to flash; and outputs a square wave to another pin connected to the buzzer, triggering an audible alarm. Simultaneously, the network protocol stack is invoked to report the encapsulated fault alarm information (including fault type, axis number, and timestamp) to the manufacturing execution system via Ethernet connection, so that production management personnel are aware of it.

[0155] Step S219: Read data from multiple peripheral sensors connected to the ARM processor platform via the integrated circuit bus interface or serial peripheral interface bus. The peripheral sensors include an ambient temperature sensor, a power module temperature sensor, and a bus voltage sensor.

[0156] The ARM processor also periodically reads data from other peripheral sensors via the onboard integrated circuit bus or serial peripheral interface bus. For example, it addresses a temperature sensor mounted on a heatsink via the integrated circuit bus to read the temperature value of the power module. It also communicates with an analog-to-digital converter chip via the serial peripheral interface to read the DC bus voltage value after voltage division and sampling.

[0157] Step S2110: The data from multiple peripheral sensors read are correlated and analyzed with the set of raw feedback signals obtained from the field programmable gate array platform to generate a comprehensive status monitoring report containing all-round operating status information of the system, and the comprehensive status monitoring report is periodically reported through the Ethernet communication connection.

[0158] A data aggregation service on the ARM processor aligns and correlates motor operation feedback (speed, position), power module status (temperature, voltage, current), and environmental data (such as chassis temperature) in terms of time. For example, it creates a data structure containing the current timestamp, the operating status of each axis, power module temperature values, bus voltage values, etc. Then, it packages this data in a format recognizable by the manufacturing execution system (such as the OPCUA protocol), generates a comprehensive condition monitoring report, and periodically reports it via Ethernet (e.g., every 100 milliseconds), enabling predictive maintenance and remote condition monitoring of the equipment.

[0159] Step S310: Hardware-level fault protection and fast current loop processing steps implemented in the field programmable gate array platform.

[0160] To further improve the system's response speed and security, the field-programmable gate array platform also undertakes hardware-level fast current loop and fault protection functions.

[0161] Step S311: Instantiate a parallel hardware current loop operation unit in the field programmable gate array platform. The parallel hardware current loop operation unit runs in parallel with the high-speed signal generation unit and is independent of the core control algorithm execution unit of the digital signal processor platform.

[0162] In addition to the high-speed signal generation unit, the field-programmable gate array (FPGA) platform also instantiates a dedicated hardware current loop operation unit. This hardware current loop operation unit consists of a series of parallel hardware multipliers, adders, and coordinate transformation modules. Its operations are entirely performed by hardware logic and do not depend on any software program. Therefore, its response time is only a few clock cycles, which is much faster than the software current loop on the digital signal processor (DSP) platform.

[0163] Step S312: The absolute position count value contained in the set of original feedback signals captured in real time by the encoder signal acquisition unit is combined with the initial angle of the motor magnetic pole position read from the parameter storage module, and Clark transformation and Park transformation are performed by the hardware coordinate transformation module to generate the direct axis feedback current value and quadrature axis feedback current value in the rotating coordinate system.

[0164] The first step of the hardware current loop is to acquire the feedback current, which reads the sampled and converted three-phase actual current values ​​Ia, Ib, and Ic from the analog-to-digital converter interface. Simultaneously, it obtains the current absolute position count from the encoder signal acquisition unit and converts it into an electrical angle θ. Then, the hardware coordinate transformation module performs the following purely hardware calculations:

[0165] First, a Clarke transformation is performed: the three-phase stationary coordinate system (Ia, Ib, Ic) is transformed into a two-phase stationary coordinate system (Iα, Iβ). The calculation formulas, implemented by the hardware circuit, are: Iα = Ia, Iβ = (Ia + 2 * Ib) / 3 0.5 However, in actual hardware, this is achieved through scaling and addition.

[0166] Next, the Parker transformation is performed: the two-phase stationary coordinate system (Iα, Iβ) is transformed into a coordinate system (Id, Iq) that rotates with the rotor. The calculation formulas are implemented by hardware circuitry as follows: Id = Iα*cosθ + Iβ*sinθ, Iq = -Iα*sinθ + Iβ*cosθ. The sine and cosine values ​​are generated using a lookup table or a coordinate rotation digital computer algorithm. The calculated Id_fb and Iq_fb are the feedback current values ​​for the direct axis and quadrature axis, respectively.

[0167] Step S313: Read the axis control command block issued by the digital signal processor platform in the current control cycle from the dual-port block random access memory, and extract the direct axis current command value and quadrature axis current command value contained in the axis control command block.

[0168] The hardware current loop operation unit reads the latest axis control instruction block for the current axis written by the digital signal processor platform from the dual-port block random access memory through a dedicated read port, and extracts the direct axis current instruction value Id_ref and the quadrature axis current instruction value Iq_ref from it.

[0169] Step S314: Input the direct-axis feedback current value and the direct-axis current command value into the first hardware proportional-integral regulator for parallel comparison and accumulation to generate the direct-axis voltage command value. At the same time, input the quadrature-axis feedback current value and the quadrature-axis current command value into the second hardware proportional-integral regulator for parallel comparison and accumulation to generate the quadrature-axis voltage command value.

[0170] Two parallel hardware proportional-integral (PI) controllers operate simultaneously. Each PI controller is a finite state machine described by a hardware description language, executing the following logic:

[0171] Calculate the errors e_d = Id_ref - Id_fb (for the direct axis) and e_q = Iq_ref - Iq_fb (for the quadrature axis).

[0172] The scaling term P_d = e_d * Kp_current, where Kp_current is the current loop scaling gain coefficient, read from a dedicated hardware register.

[0173] The integral term I_d = I_d_previous + e_d * Ki_current * T_current, where I_d_previous is the accumulated integral value of the previous cycle, Ki_current is the current loop integral gain coefficient, and T_current is the control period of the current loop (usually very short, synchronized with the pulse width modulation period). The above multiplication and addition are completed by hardware multipliers and adders within one clock cycle.

[0174] The final output voltage command values ​​are Vd_ref = P_d + I_d and Vq_ref = P_q + I_q. After the calculation is complete, the accumulated integral value is updated and stored back in the register.

[0175] Step S315: Input the direct-axis voltage command value and the quadrature-axis voltage command value into the hardware Parker inverse transformation module and Clark inverse transformation module for coordinate inverse transformation processing to generate three-phase voltage command values ​​in the stationary coordinate system.

[0176] The hardware current loop arithmetic unit then performs the inverse transformation. First, the Parker inverse transformation is performed: transforming Vd_ref and Vq_ref in the rotating coordinate system to Vα_ref and Vβ_ref in the two-phase stationary coordinate system. The formulas, implemented in hardware, are: Vα_ref = Vd_ref * cosθ - Vq_ref * sinθ, Vβ_ref = Vd_ref * sinθ + Vq_ref * cosθ.

[0177] Then, the inverse Clarke transformation is performed: transforming Vα_ref and Vβ_ref in the two-phase stationary coordinate system to Va_ref, Vb_ref, and Vc_ref in the three-phase stationary coordinate system. The formula, implemented in hardware, is Va_ref = Vα_ref, Vb_ref ​​= (-Vα_ref + 3). 0.5 *Vβ_ref) / 2,Vc_ref=(-Vα_ref-3 0.5 *Vβ_ref) / 2. Similarly, these operations are all performed by hardware combinational logic within one clock cycle.

[0178] Step S316: The three-phase voltage command value is directly used as the input of the high-speed signal generation unit to replace the current loop setpoint sequence originally calculated by the digital signal processor platform in the shaft control command block set, thereby realizing the full hardware parallel processing of the current loop.

[0179] The Va_ref, Vb_ref, and Vc_ref outputs from the hardware current loop arithmetic unit are directly injected into the reference value register group of the high-speed signal generation unit via the internal high-speed bus as bypass signals. In this way, the current loop setpoint originally calculated by the digital signal processor platform software is overridden by the value calculated in real time by the hardware. This reduces the current loop response time from microseconds in software calculations to nanoseconds in hardware logic, significantly improving the dynamic response performance of the current loop. The digital signal processor platform can then focus on higher-level control such as the position and velocity loops, while completely delegating the lowest-level, fastest current control to the field-programmable gate array (FPGA) hardware.

[0180] Step S317: Instantiate the overcurrent comparator array in the field programmable gate array platform, and collect the actual three-phase current values ​​output by the power drive module in real time through the analog-to-digital conversion interface. Compare the actual three-phase current values ​​with the hardware overcurrent protection threshold read from the parameter storage module in real time.

[0181] In parallel with the current loop, a hardware overcurrent protection module is also instantiated in the field-programmable gate array platform. This module acquires the actual three-phase current values ​​Ia, Ib, and Ic output by the intelligent power module in real time via a high-speed analog-to-digital converter interface (these values ​​may have already been converted into voltage signals by sensors and conditioning circuits). These digitized current values ​​are simultaneously fed into three parallel hardware comparators. Another input to each comparator is a fixed hardware overcurrent protection threshold I_oc read from the parameter storage module.

[0182] Step S318: When the actual current value of any phase exceeds the hardware overcurrent protection threshold, the overcurrent comparator array immediately outputs a hardware overcurrent trigger signal. This hardware overcurrent trigger signal is directly input to the enable control terminal of the dead time insertion unit without any software processing.

[0183] In any clock cycle, if the comparator detects that Ia > I_oc, it can immediately set the output to a logic high level. This high-level signal is a purely hardware signal, directly connected to an emergency shutdown enable pin of the dead-time insertion unit without any software polling or interrupt handling.

[0184] Step S319: After receiving the hardware overcurrent trigger signal, the dead time insertion unit forces the output of all complementary pulse width modulation waveform pairs to be set to invalid level and latches the corresponding state at the hardware level until a special fault reset signal is received.

[0185] The logic within the dead-time insertion unit has the highest priority for responding to this enable signal. Once a high signal is detected, it immediately forces all six currently outputting pulse-width modulation signals (three high-side and three low-side) to a low level (off state). Simultaneously, it sets a fault latch register to record overcurrent events. Afterward, regardless of input changes, the output remains locked in the off state until a dedicated external hardware fault reset signal arrives, clearing the latch and restoring normal output. This ensures that in the event of an overcurrent fault, the power transistors can be safely turned off as quickly as possible, preventing device damage.

[0186] Step S3110: Simultaneously, the hardware overcurrent trigger signal is used as a write enable to write the current fault type identifier, the fault occurrence time, and the actual three-phase current value at the fault occurrence time into the fault record register file inside the field programmable gate array platform.

[0187] The rising edge of the hardware overcurrent trigger signal is simultaneously used as a trigger signal and connected to a fault logging module. Upon receiving the trigger signal, the fault logging module immediately latches the current timestamp from the global clock tree, latches the current three-phase current values ​​Ia, Ib, and Ic from the analog-to-digital converter interface, and combines a preset fault type identifier (e.g., overcurrent fault code 0xOC) to form a fault log entry, which is then automatically written to a dedicated, non-volatile fault log register file.

[0188] Step S3111: Output a fault indication signal to the digital signal processor platform and the ARM processor platform through a dedicated hardware status register to notify the upper-level processor platform that a hardware-level overcurrent fault has occurred and that a pulse blocking operation has been performed.

[0189] Simultaneously, a specific bit in a dedicated status register is set to 1. The output of this status register is directly connected to the general-purpose input / output interrupt line connecting the digital signal processor platform and the ARM processor platform. When this bit is set to 1, a hardware interrupt is triggered simultaneously on both processor platforms. The interrupt service routines on both processor platforms can read the status register and the fault log file to obtain detailed fault information and execute the upper-level fault handling logic (such as steps S217 and S218). However, by this time, the most dangerous overcurrent situation has already been handled by the field-programmable gate array hardware within nanoseconds.

[0190] Step S410: Implementing advanced motion control algorithms and parameter self-tuning steps in a digital signal processor platform.

[0191] In addition to performing regular periodic task scheduling, digital signal processor platforms can also utilize idle time to perform advanced functions, such as automatic tuning of servo parameters.

[0192] For example, in step S411: In the core control algorithm execution unit of the digital signal processor platform, in addition to the preemptible task scheduler, a parameter self-tuning coprocessor runs in parallel. The parameter self-tuning coprocessor is woken up and executed during the idle period of the servo drive system.

[0193] In the core of the digital signal processor platform, besides the main core running the real-time task scheduler, there is also a separate coprocessor or a low-priority background task specifically responsible for parameter self-tuning. This background task is set to extremely low priority and will only be scheduled for execution when there are no tasks for any axis in the real-time task scheduler (i.e., all instruction queues are empty, and the motor is stationary or running at a constant speed).

[0194] Step S412: Read the historical raw feedback signal set from the field programmable gate array platform through the high-speed data communication link. The historical raw feedback signal set includes the actual speed feedback value sequence and the absolute position feedback value sequence recorded in multiple consecutive servo drive control cycles.

[0195] When the self-tuning task is awakened, it reads historical feedback data over a continuous period of time from the memory of the field-programmable gate array platform in batches via direct memory access. For example, it may read 8,000 actual speed feedback values ​​N_fb[t] and corresponding position feedback values ​​P_fb[t] recorded at 125 microsecond intervals within the most recent second. The above data constitutes a time series.

[0196] Step S413: Compare and analyze the actual speed feedback value sequence in the historical original feedback signal set with the speed command value sequence issued in the corresponding time period, and calculate the root mean square value of speed tracking error and the maximum overshoot.

[0197] The self-tuning task first extracts the sequence of velocity command values ​​N_ref[t] corresponding to the time period of the aforementioned feedback data from the historical command log. Then, it calculates the tracking error e[t] = N_ref[t] - N_fb[t] at each moment.

[0198] Next, the root mean square error is calculated, which is the sum of squares of e[t], divided by the number of data points N, and then the square root is taken to obtain RMSE = ((∑e[t]). 2 ) / N) 0.5 .

[0199] Simultaneously, it scans the e[t] sequence to find the maximum positive value, i.e., the maximum overshoot, Overshoot_max = max(e[t]). These two indicators quantify the performance of the current speed loop control.

[0200] Step S414: Based on the root mean square value and maximum overshoot of the speed tracking error, call the lookup instruction in the instruction set of the digital signal processor platform to find the initial proportional gain adjustment and initial integral gain adjustment that match the current tracking error characteristics from the self-tuning parameter mapping table stored in the internal flash memory of the digital signal processor platform.

[0201] The self-tuning task uses the calculated RMSE and Overshoot_max as a two-dimensional index. It executes a lookup instruction to access a lookup table pre-stored in flash memory. This lookup table is a two-dimensional array, where each row corresponds to an RMSE range and each column corresponds to an Overshoot_max range. Each entry stores a pair of adjustment values ​​(ΔKp, ΔKi). For example, if the current RMSE is high and the overshoot is large, the adjustment value obtained from the lookup table might be (+10, -5), meaning that the proportional gain needs to be increased to reduce the error, while the integral gain needs to be decreased to suppress the overshoot.

[0202] Step S415: Add the initial proportional gain adjustment and the initial integral gain adjustment to the speed loop proportional gain coefficient and speed loop integral gain coefficient currently in use in the control cycle, respectively, to generate updated speed loop proportional gain coefficient and speed loop integral gain coefficient.

[0203] The self-tuning task reads the currently used speed loop proportional gain coefficient Kp_spd_current and speed loop integral gain coefficient Ki_spd_current from the system global variable area. Then, it performs a simple addition: Kp_spd_new = Kp_spd_current + ΔKp, Ki_spd_new = Ki_spd_current + ΔKi, to obtain a set of updated gain coefficients.

[0204] Step S416: Construct a system transfer function model in the digital signal processor platform, substitute the updated velocity loop proportional gain coefficient and velocity loop integral gain coefficient into the system transfer function model to perform stability simulation analysis, and calculate the gain margin and phase margin.

[0205] Before actually applying the new parameters, the self-tuning task performs offline simulation using a simplified mathematical model of the controlled object (motor + load) pre-built and stored in memory (e.g., a second-order transfer function G(s)). This constructs the transfer function of the closed-loop system, where the controller part uses Kp_spd_new and Ki_spd_new. Then, it estimates the gain margin Gm_new and phase margin Pm_new of the new system through mathematical calculations (e.g., solving for the crossover frequency and phase of the open-loop transfer function in the frequency domain).

[0206] Step S417: Determine whether the calculated gain margin is greater than the preset lower limit threshold for gain margin and whether the phase margin is greater than the preset lower limit threshold for phase margin. If both are greater than the corresponding thresholds, then the updated velocity loop proportional gain coefficient and velocity loop integral gain coefficient are calibrated as valid new parameters.

[0207] The self-tuning task compares the calculated Gm_new with a preset lower limit threshold Gm_min (e.g., 6 dB) and Pm_new with a lower limit threshold Pm_min (e.g., 45 degrees). The new set of parameters is considered stable and valid only if Gm_new > Gm_min and Pm_new > Pm_min.

[0208] Step S418: The speed loop proportional gain coefficient and speed loop integral gain coefficient, which have been calibrated as valid new parameters, are sent to the parameter storage module of the field programmable gate array platform through the high-speed data communication link, so that the hardware current loop calculation unit in the subsequent control cycle can use them in coordinate transformation and regulator calculation.

[0209] If the parameters are calibrated to be valid, the self-tuning task writes Kp_spd_new and Ki_spd_new to the parameter storage module related to the current loop in the field-programmable gate array platform via a high-speed communication link. In this way, in the next control cycle, the hardware current loop arithmetic unit will automatically use these new gain coefficients to perform proportional-integral calculations on the current loop, thereby optimizing control performance online.

[0210] Step S419: Simultaneously, the new parameters calibrated as valid are written into the parameter backup area of ​​the non-volatile memory inside the digital signal processor platform as the default startup parameters when the system is powered on next time.

[0211] This new set of parameters will also be written to a backup area in the flash memory inside the digital signal processor platform. The next time the system is powered on, the bootloader will first load these parameters from this backup area as default values, thus solidifying the parameters.

[0212] Step S4110: If either the gain margin or the phase margin does not meet the corresponding threshold requirement, the updated gain coefficient is discarded, the parameter search step size is increased, and a new adjustment amount is searched from the self-tuning parameter mapping table for another attempt.

[0213] If the simulation results show that the stability does not meet the requirements, the self-tuning task will abandon this set of parameters. It can adjust the search strategy, such as increasing or decreasing the step size when looking up the table, or select another set of different adjustment values ​​(ΔKp', ΔKi') from the lookup table, and then repeat steps S415 to S417 to make a new round of attempts.

[0214] Step S4111: During the parameter self-tuning process, monitor the operating status of the servo motor in real time. If any abnormal vibration or overshoot is detected, immediately stop the self-tuning process and roll back all control parameters to the backup values ​​before the start of self-tuning.

[0215] Throughout the self-tuning process, a parallel monitoring task runs continuously, analyzing the fluctuations in the actual speed feedback value N_fb[t]. If a sustained, excessively severe oscillation is detected, or a sudden, large overshoot occurs, the monitoring task immediately sends a stop signal to the self-tuning task and triggers a parameter rollback operation. The self-tuning task has already backed up the original parameters Kp_spd_backup and Ki_spd_backup before starting; it immediately writes these backup values ​​back to the controller and notifies the operator that the self-tuning has failed.

[0216] Step S510: Multi-core collaborative initialization and self-test steps during servo drive control system startup.

[0217] System power-on startup is a critical process involving the collaborative work of multiple processor cores, requiring precise timing coordination.

[0218] For example, in step S511: after the servo drive control system is powered on, the ARM processor platform starts up first, executes the bootloader program embedded in the internal flash memory of the ARM processor platform, and initializes the core clock, memory controller and external storage interface of the ARM processor platform.

[0219] After the system powers on, according to the hardware design, the ARM processor platform is configured to boot first. The bootloader in its internal read-only memory begins execution. This bootloader first configures the ARM core's phase-locked loop, enabling it to operate at full clock speed. Then, it initializes the memory controller, setting the timing parameters of the dynamic random access memory (DRAM) to make the external DRAM available. Next, it initializes external storage interfaces, such as the four-wire serial peripheral interface controller for connecting flash memory.

[0220] Step S512: The ARM processor platform bootloader loads the embedded real-time operating system kernel and starts running. The embedded real-time operating system initializes the network protocol stack, file system, and general input / output interface driver.

[0221] The bootloader loads the embedded real-time operating system kernel image from external flash memory into dynamic random access memory and transfers execution control to the kernel. After the kernel starts, it initializes its core services and loads drivers. It initializes the network protocol stack to prepare for Ethernet communication; mounts a flash-based file system for storing configuration files; and initializes general-purpose input / output interface drivers, setting their pins to default states.

[0222] Step S513: After the embedded real-time operating system runs, it sends a hardware reset release signal to the digital signal processor platform and the field programmable gate array platform through the general-purpose input / output interface, allowing the digital signal processor platform and the field programmable gate array platform to exit the reset state.

[0223] Once the operating system is running, a startup script is executed. This startup script releases the two slave processors from their reset states by manipulating the registers of the general-purpose input / output interface (GPIO) to pull the two GPIO lines connected to the digital signal processor platform reset pin and the field-programmable gate array platform configuration reset pin from low (reset) to high (run).

[0224] Step S514: After receiving the reset signal, the digital signal processor platform loads the startup code from its internal read-only memory and initializes the core clock, internal cache and high-speed bus interface of the digital signal processor platform.

[0225] After the digital signal processor platform hardware detects the reset pin going high, it begins executing the Level 1 bootloader in its internal read-only memory. This Level 1 bootloader configures the digital signal processor core's phase-locked loop and internal cache. It then initializes critical peripherals, particularly the high-speed bus interface controllers (such as PCIeRC mode) used for communication with ARM and field-programmable gate arrays.

[0226] Step S515: After receiving the reset signal, the field-programmable gate array platform reads the configuration bitstream file from the external serial configuration flash memory, completes the instantiation and connection of all logic units inside the field-programmable gate array, and establishes the instruction preprocessing logic unit, the high-speed signal generation unit, and the encoder signal acquisition unit.

[0227] When the configuration pin of the Field-Programmable Gate Array (FPGA) platform is pulled high, its internal configuration controller begins operation. It reads a bitstream file from an external dedicated configuration flash memory via a serial peripheral interface. This bitstream contains a description of all hardware logic. The configuration controller loads the bitstream into the FPGA's internal configuration memory, thus completing the "wiring" and "connection" of all instantiated logic units. This allows hardware modules such as the instruction preprocessing logic unit, high-speed signal generation unit, and encoder signal acquisition unit to be physically constructed within the chip.

[0228] Step S516: After the field programmable gate array platform completes the configuration, it sends a configuration completion flag to the ARM processor platform and the digital signal processor platform via a dedicated handshake signal line.

[0229] Once configured, a flag register inside the field-programmable gate array is set. The output of this register is connected to a dedicated general-purpose input / output line that connects to the ARM and digital signal processor platforms, sending a high-level pulse to both processors to indicate that they are ready.

[0230] Step S517: After the digital signal processor platform detects the configuration completion flag, it loads the executable code of the core control algorithm execution unit, initializes the preemptible task scheduler and each software task control block, and enters the instruction waiting state.

[0231] Upon detecting the flag, the digital signal processor platform loads the executable code of the core control algorithm from its external flash memory into its internal static random access memory. Then, it calls the real-time operating system's initialization function to create multiple task control blocks corresponding to the number of axes, initialize the task stack, and start the preemptive task scheduler. After initialization, all tasks enter a suspended state, awaiting instruction events from the field-programmable gate array platform.

[0232] Step S518: After the ARM processor platform detects the configuration completion flag, it reads the device identification register and status register of the power drive module through the integrated circuit bus to verify whether the model of the power drive module is correct and whether it is in normal working condition.

[0233] After detecting the configuration completion flag, the ARM processor platform executes its self-test procedure. It sends a command to the power drive module via the integrated circuit bus to read the device ID and compares the read value (e.g., a 16-bit manufacturer ID and device model) with the value pre-stored in the configuration file. Simultaneously, it reads the status register to check for undervoltage, overtemperature, or fault reports.

[0234] Step S519: The ARM processor platform reads the initial values ​​of each peripheral sensor connected to the system through the serial peripheral interface bus, determines whether the sensor readings are within the preset normal range, and completes the peripheral sensor self-test.

[0235] Next, the ARM processor platform sequentially reads the initial values ​​from all peripheral sensors (such as ambient temperature, power module temperature, and bus voltage) via the serial peripheral interface bus. For example, it reads the 16-bit digital value returned by the ambient temperature sensor, converts it into a temperature value, and determines whether it is within the normal range of -10 degrees Celsius to 50 degrees Celsius. If the reading of any sensor exceeds the preset reasonable range, it will record a self-test error.

[0236] Step S5110: The ARM processor platform will send the initialization configuration parameters received from the upper-level factory information system via Ethernet communication connection to the digital signal processor platform and the field programmable gate array platform through the high-speed bus interface, respectively, to complete the unified configuration of the operating parameters of each processing platform.

[0237] After obtaining the initialization configuration file from the manufacturing execution system (or, if offline, reading the default configuration from the local file system), the ARM processor platform decomposes the configuration parameters. It packages the parameters belonging to the digital signal processor platform (such as the initial gain of the position loop and velocity loop, and task priority mapping) and writes them to a designated memory area of ​​the digital signal processor platform via a high-speed bus. It packages the parameters belonging to the field-programmable gate array (FPGA) platform (such as carrier frequency, dead time, and overcurrent threshold) and writes them to a designated address in the FPGA platform's parameter storage module via a high-speed bus.

[0238] Step S5111: After receiving the initialization configuration parameters, the digital signal processor platform and the field programmable gate array platform write the initialization configuration parameters into their respective parameter storage modules and return a parameter writing success confirmation frame to the ARM processor platform.

[0239] Upon detecting a parameter write event, a management task on a digital signal processor platform copies the parameters from the shared memory area to the global variable area used by its core control algorithm and returns a simple acknowledgment data packet to the ARM processor. Similarly, the logic of a field-programmable gate array (FPGA) platform automatically updates the corresponding operating parameters (such as the dead-time register value) after detecting a write operation at a specific address of its parameter storage module, and indicates to the ARM processor that the write is complete via a bit in a status register.

[0240] Step S5112: After receiving all confirmation frames, the ARM processor platform illuminates the system's normal operating status indicator via the general-purpose input / output interface and sends a start command to the digital signal processor platform to allow task scheduling to begin, so that the servo drive control system enters normal operating mode.

[0241] After receiving confirmation messages from both the digital signal processor (DSP) platform and the field-programmable gate array (FPGA) platform, the ARM processor platform confirms that all initialization steps have been successfully completed. It then sets a general-purpose input / output pin connected to the "Run" indicator on the panel to a high level, illuminating the green light. Next, it writes a specific "Start" command word to the DSP platform via a dedicated inter-core communication register. Upon detecting this command word, the DSP platform switches its real-time task scheduler from "Suspended" to "Run," beginning to respond to instruction queue events from the FPGA platform. The entire multi-platform servo drive control system thus officially enters closed-loop operation mode.

[0242] In one exemplary embodiment, a multi-platform architecture servo drive control system is provided. This multi-platform architecture servo drive control system can be a terminal, server, etc., and its internal structure diagram can be as follows: Figure 2 As shown, this multi-platform architecture servo drive control system includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, near-field communication, or other technologies. When the computer program is executed by the processor, it implements a multi-platform architecture servo drive control method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device can be a touch layer covering the display screen, or a button, trackball, or touchpad set on the housing of a multi-platform architecture servo drive control system, or an external keyboard, touchpad, or mouse, etc.

[0243] It should be noted that, in order to simplify the description of the present invention and thus help to understand one or more embodiments of the invention, multiple features may sometimes be grouped into one embodiment, drawing or description thereof in the foregoing description of the embodiments of the present invention.

Claims

1. A servo drive control method with a multi-platform architecture, characterized in that, The method includes: The system receives a set of instructions sent by a multi-axis motion control system, performs instruction type parsing on the instruction set, and obtains the instruction type identifier, instruction priority parameter, and instruction target execution axis number corresponding to each instruction unit in the instruction set. The instruction set includes position instructions, speed instructions, and torque instructions. The instruction preprocessing logic unit of the field-programmable gate array platform is invoked to perform instruction stream classification and reorganization processing on the instruction type identifier, the instruction priority parameter, and the instruction target execution axis number to generate an axis instruction queue set. Each axis instruction queue in the axis instruction queue set is bound to a unique instruction target execution axis number. The set of axis command queues is transmitted to the core control algorithm execution unit of the digital signal processor platform. Based on the command priority parameters and servo drive control cycle parameters in the set of axis command queues, task preemptive scheduling is performed to generate a set of axis control command blocks. The set of axis control command blocks is fed back to the high-speed signal generation unit of the field programmable gate array platform, and the set of axis control command blocks is processed to generate pulse width modulation waveforms to obtain a set of multiphase pulse width modulation drive signals. The multiphase pulse width modulation drive signal set is sent to the power drive module to trigger the servo motor to perform position adjustment, speed adjustment or torque adjustment actions. At the same time, the encoder signal acquisition unit of the field programmable gate array platform captures the original feedback signal set returned by the servo motor in real time. The core control algorithm execution unit that transmits the axis command queue set to the digital signal processor platform performs preemptive scheduling processing based on the instruction priority parameters and servo drive control cycle parameters in the axis command queue set to generate an axis control instruction block set, including: In the core control algorithm execution unit of the digital signal processor platform, a priority-based real-time task scheduling kernel is maintained. The real-time task scheduling kernel manages multiple software task control blocks that correspond one-to-one with the instruction target execution axis number. The set of axis command queues is received through a high-speed data communication link, and after parsing the set of axis command queues, they are classified according to the axis number to be executed by the command target and stored in the task private data buffer associated with each software task control block. Each of the software task control blocks maintains a local task ready flag and a task priority attribute. The local task ready flag is set according to whether its corresponding task private data buffer is empty. The task priority attribute is obtained directly from the instruction priority parameter of the received instruction entry. At the beginning of each servo drive control cycle, the real-time task scheduling kernel scans the local task ready flags of all software task control blocks and adds all software task control blocks with valid local task ready flags to the competitive task set of the current cycle. Extract the task priority attribute of each software task control block from the set of competing tasks, and simultaneously extract the instruction timeout deadline of the instruction queue corresponding to each software task control block; sort all tasks in the set of competing tasks in descending order according to the task priority attribute; for tasks with the same task priority attribute, calculate the urgency factor based on their instruction timeout deadline, and sort the corresponding part of the tasks in secondary order according to the urgency factor, and finally generate the set of competing tasks in descending order. The real-time task scheduling kernel selects the top-ranked task from the set of competing tasks in descending order as the first task to be executed in the current cycle, saves the context of the current task, and jumps to the entry point of the core control algorithm program corresponding to the first task to be executed in the current cycle. The core control algorithm program is executed, and the instruction type identifier and related parameters of the first instruction entry are read from the task private data buffer corresponding to the task. The position loop, speed loop and current loop control algorithm calculations are performed to generate a preliminary axis control instruction block. The initial axis control instruction block is stored in the task's private data output buffer, and it is checked whether the current servo drive control cycle deadline has been reached. If it has not been reached and there are still unexecuted tasks in the competing task set, the current task state is saved, the real-time task scheduling kernel execution is resumed, and the next ranked task is selected for execution. The task selection and execution process is repeated until the current servo drive control cycle deadline is reached. The real-time task scheduling kernel stops starting new tasks and collects and packages the preliminary axis control instruction blocks generated in the private data output buffers of all tasks to generate the axis control instruction block set for the current cycle.

2. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The system receives a set of instructions from a multi-axis motion control system, performs instruction type parsing on the instruction set, and obtains the instruction type identifier, instruction priority parameter, and instruction target execution axis number corresponding to each instruction unit in the instruction set, including: A physical interface for communication with the multi-axis motion control system is constructed in the field programmable gate array platform. The original instruction data frame sent by the multi-axis motion control system in broadcast form is received through the physical interface. The original instruction data frame includes a frame header identifier field, a frame length field, multiple consecutively arranged instruction units, and a frame check field. The hardware parser of the field-programmable gate array platform is invoked to perform frame boundary recognition processing on the original instruction data frame. The start position of the original instruction data frame is located according to the frame header identifier field, and the end position of the original instruction data frame is determined according to the frame length field, thereby generating a complete instruction data frame unit. The complete instruction data frame unit is subjected to serial-to-parallel conversion processing to convert the serially transmitted bit stream data into a set of instruction words in parallel data bus format, wherein each instruction word in the instruction word set corresponds to an instruction unit. The instruction word set is input into the instruction type decoder of the field programmable gate array platform. The instruction type decoder extracts bit segment information at a predefined position in each instruction word and compares and matches the bit segment information with a preset instruction type encoding table to obtain the instruction type identifier corresponding to each instruction unit. Synchronously extract the bit segment information of another predefined position in each instruction word as the original instruction priority code of the instruction unit, perform numerical mapping processing on the original instruction priority code, and convert it into instruction priority parameters for subsequent scheduling comparison; Extract the instruction target execution axis number field from each instruction word. The instruction target execution axis number field contains a binary code value that identifies the target servo drive axis. The binary code value is directly used as the instruction target execution axis number of the instruction unit. For each instruction unit that has been parsed, an integrity check is performed, and the instruction type identifier, the instruction priority parameter, and the instruction target execution axis number are associated and combined to form a structured instruction entry containing the three elements of information. The structured instruction entries are written into the input buffer queue of the field-programmable gate array platform in the order of their reception time, and each structured instruction entry in the input buffer queue maintains its original arrival order; The structured instruction entries are read one by one from the input buffer queue, and an arrival timestamp obtained from the global clock tree of the field programmable gate array platform is appended to each structured instruction entry to generate instruction entries to be classified with timestamps. The instruction entries to be classified with time tags are transmitted to the instruction preprocessing logic unit as the input data source for subsequent instruction stream classification and reorganization processing.

3. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The high-speed signal generation unit that feeds back the set of axis control command blocks to the field-programmable gate array platform performs pulse width modulation waveform generation processing on the set of axis control command blocks to obtain a set of multiphase pulse width modulation drive signals, including: The set of axis control command blocks is sent to the high-speed input port of the field programmable gate array platform in parallel data burst transmission mode through a pre-established high-speed data communication link between the digital signal processor platform and the field programmable gate array platform. The direct memory access controller instantiated inside the field programmable gate array platform automatically transfers the set of axis control command blocks received by the high-speed input port to a dedicated dual-port block random access memory, completing zero-overhead data transmission. The set of axis control instruction blocks is continuously read from one read port of the dual-port block random access memory, the current loop setpoint sequence in each axis control instruction block is parsed, and the current loop setpoint sequence is loaded into the reference value register group of the waveform generator inside the high-speed signal generation unit; The high-speed signal generation unit calls the digital triangular wave generator instantiated inside, which generates a digital triangular carrier signal with stable periodicity and amplitude in real time based on the carrier frequency setting value and carrier amplitude setting value read from the parameter storage module. The current loop setpoint sequence stored in the reference value register group of the waveform generator is synchronously input to multiple parallel hardware comparators along with the digital triangular carrier signal. Each hardware comparator compares one current loop setpoint with the instantaneous value of the digital triangular carrier signal point by point. Each of the hardware comparators outputs a pulse signal in real time based on the comparison result. When the current loop setpoint is greater than the instantaneous value of the digital triangular carrier signal, it outputs a high level; otherwise, it outputs a low level, thereby generating an original pulse width modulation waveform sequence corresponding to the current loop setpoint sequence. The original pulse width modulation waveform sequence is input into the dead time insertion unit. The dead time insertion unit delays the output by a preset dead time parameter at each rising edge of the original pulse width modulation waveform sequence before allowing the output to rise, and terminates the output at each falling edge by a preset dead time parameter in advance, thereby generating a complementary pulse width modulation waveform pair with a dead time interval. The complementary pulse width modulation waveform is assigned to the input pulse allocation matrix. The pulse allocation matrix routes the complementary pulse width modulation waveform to a specific output channel group corresponding to the target axis number of the instruction carried in each axis control instruction block. An output drive buffer is instantiated at the end of each output channel group. The output drive buffer converts the level standard of the complementary pulse width modulation waveform pair from the core logic level to a level standard that can directly drive external power modules, and performs current amplification. The complementary pulse width modulation waveforms of all output channel groups after level conversion and current amplification are collected to form a complete set of drive signals containing multiphase pulse width modulation drive signals, and sent to the power drive module through the parallel output pin of the field programmable gate array platform.

4. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The set of raw feedback signals returned by the servo motor that is captured in real time by the encoder signal acquisition unit of the field-programmable gate array platform includes: The multiple input pins of the field-programmable gate array platform are configured to receive differential signals, and each input pin is physically connected to the differential signal lines A positive, A negative, B positive, B negative, Z positive, and Z negative of the incremental encoder of the servo motor in a one-to-one correspondence. A differential signal decoder is instantiated after each differential input pin pair. The differential signal decoder performs subtraction and shaping operations on the received positive and negative A signals to restore the standard single-ended A-phase signal. The same processing is performed on the B-phase signal and the Z-phase signal. The restored single-ended A-phase signal and single-ended B-phase signal are input into the quadrature decoding module. The quadrature decoding module performs phase detection processing on the phase relationship between the A-phase signal and the B-phase signal. When the A-phase leads the B-phase signal, it determines that the motor is rotating in the forward direction and generates a forward direction indicator. When the B-phase leads the A-phase signal, it determines that the motor is rotating in the reverse direction and generates a reverse direction indicator. The quadrature decoding module simultaneously performs quadruple frequency counting on the rising and falling edges of the A-phase and B-phase signals, and accumulates the change in the count value within each servo drive control cycle to generate a high-resolution position increment count value. The position increment count value is input into the increment accumulator. The increment accumulator sums the position increment count values ​​obtained in each control cycle based on the motor power-on time to generate a relative position accumulation value starting from the starting position. The restored single-ended Z-phase signal is input to the zero-position capture module. The zero-position capture module detects the rising edge of the Z-phase signal. When the rising edge is detected, a zero-position pulse flag is generated, and the current accumulated value of the incremental accumulator is locked as the zero-position offset of the servo motor. The relative position accumulated value is corrected according to the zero position offset, and the zero position offset is subtracted from the relative position accumulated value to generate an absolute position count value with the encoder zero position as the reference point. The absolute position count value and the cycle duration in the servo drive control cycle parameter are input into the speed calculation unit. The speed calculation unit calculates the difference between the absolute position count values ​​of two adjacent control cycles and divides the difference by the cycle duration to obtain the actual speed feedback value of the servo motor. The actual rotational speed feedback value and the absolute position count value are bound to the current time information obtained from the global clock tree to generate a rotational speed feedback data unit and a position feedback data unit with a precise timestamp. The speed feedback data units and position feedback data units with precise timestamps are classified and stored according to the corresponding instruction target axis number, thus constructing the original feedback signal set for each servo drive axis.

5. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The method further includes: communication management and peripheral device control steps performed in the ARM processor platform. An embedded real-time operating system runs on the ARM processor platform. An Ethernet communication connection with the upper-level factory information system is established through the network protocol stack of the embedded real-time operating system. Production task configuration files are received from the upper-level factory information system. The production task configuration file is parsed to extract the multi-axis motion trajectory planning parameters, the operating mode setting parameters of each axis servo drive, and the fault protection threshold parameters contained in the production task configuration file. The multi-axis motion trajectory planning parameters are transmitted to the trajectory planning algorithm module running on the ARM processor platform through the internal process communication mechanism of the embedded real-time operating system. The trajectory planning algorithm module performs motion trajectory interpolation calculations based on the multi-axis motion trajectory planning parameters to generate a continuous instruction sequence containing position, speed, and torque instructions. The generated instruction sequence is sent to the digital signal processor platform in the form of data packets through the high-speed bus interface between the ARM processor platform and the digital signal processor platform, so that the core control algorithm execution unit can perform preemptive scheduling processing of tasks. The system reads the set of raw feedback signals captured in real time from the field-programmable gate array platform through a high-speed data communication link, performs data parsing and format conversion on the set of raw feedback signals, and generates unified format feedback data suitable for processing in the ARM processor platform. The unified format feedback data is compared and monitored with the operation mode setting parameters set in the production task configuration file. When the deviation between the actual speed feedback value or position feedback value in the unified format feedback data and the set value exceeds the preset monitoring threshold, an abnormal operation status event is generated. The fault handling thread in the ARM processor platform is invoked. The fault handling thread queries the corresponding fault response action code from the fault handling strategy table stored in non-volatile memory according to the type of the abnormal running state event. According to the fault response action code, an alarm trigger signal is sent to an external audible and visual alarm device through a general input / output interface, and at the same time, fault alarm information including the fault type and the time of fault occurrence is reported to the upper-level factory information system through an Ethernet communication connection. Data from multiple peripheral sensors connected to the ARM processor platform are read via an integrated circuit bus interface or a serial peripheral interface bus. The peripheral sensors include an ambient temperature sensor, a power module temperature sensor, and a bus voltage sensor. The data from multiple peripheral sensors are correlated and analyzed with the set of raw feedback signals obtained from the field programmable gate array platform to generate a comprehensive status monitoring report containing all aspects of the system's operating status information. The comprehensive status monitoring report is then periodically reported via the Ethernet communication connection.

6. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The method further includes: hardware-level fault protection and fast current loop processing steps implemented in the field-programmable gate array platform. A parallel hardware current loop operation unit is instantiated in the field programmable gate array platform. The parallel hardware current loop operation unit runs in parallel with the high-speed signal generation unit and is independent of the core control algorithm execution unit of the digital signal processor platform. The absolute position count value contained in the set of raw feedback signals captured in real time by the encoder signal acquisition unit, combined with the initial angle of the motor magnetic pole position read from the parameter storage module, is processed by the hardware coordinate transformation module to perform Clark transformation and Park transformation to generate the direct axis feedback current value and quadrature axis feedback current value in the rotating coordinate system. Read the axis control command block issued by the digital signal processor platform within the current control cycle from the dual-port block random access memory, and extract the direct axis current command value and quadrature axis current command value contained in the axis control command block; The direct-axis feedback current value and the direct-axis current command value are input into the first hardware proportional-integral regulator for parallel comparison and accumulation to generate the direct-axis voltage command value. At the same time, the quadrature-axis feedback current value and the quadrature-axis current command value are input into the second hardware proportional-integral regulator for parallel comparison and accumulation to generate the quadrature-axis voltage command value. The direct-axis voltage command value and the quadrature-axis voltage command value are input into the hardware Parker inverse transformation module and the Clark inverse transformation module for coordinate inverse transformation processing to generate three-phase voltage command values ​​in the stationary coordinate system. The three-phase voltage command value is directly used as the input of the high-speed signal generation unit, replacing the current loop setpoint sequence originally calculated by the digital signal processor platform in the shaft control command block set, thereby realizing the full hardware parallel processing of the current loop. An overcurrent comparator array is instantiated in the field programmable gate array platform. The actual three-phase current values ​​output by the power drive module are acquired in real time through the analog-to-digital conversion interface. The actual three-phase current values ​​are compared in real time with the hardware overcurrent protection threshold read from the parameter storage module. When the actual current value of any phase exceeds the hardware overcurrent protection threshold, the overcurrent comparator array immediately outputs a hardware overcurrent trigger signal. This hardware overcurrent trigger signal is directly input to the enable control terminal of the dead time insertion unit without any software processing. After receiving the hardware overcurrent trigger signal, the dead time insertion unit forces the output of all complementary pulse width modulation waveform pairs to be set to an invalid level and latches the corresponding state at the hardware level until a dedicated fault reset signal is received. Simultaneously, the hardware overcurrent trigger signal is used as a write enable to write the current fault type identifier, the fault occurrence time, and the actual three-phase current value at the fault occurrence time into the fault record register file inside the field programmable gate array platform. A fault indication signal is output to the digital signal processor platform and the ARM processor platform through a dedicated hardware status register, notifying the upper-level processor platform that a hardware-level overcurrent fault has occurred and that a pulse blocking operation has been performed.

7. The servo drive control method for a multi-platform architecture according to claim 1, characterized in that, The step of sending the multiphase pulse width modulation drive signal set to the power drive module to trigger the servo motor to perform position adjustment, speed adjustment, or torque adjustment actions includes: The set of multiphase pulse width modulation drive signals output from the parallel output pin of the field programmable gate array platform is transmitted to the power drive module at a remote end through optical fiber or differential cable. The power drive module includes an intelligent power module and a drive optocoupler. The drive optocoupler in the power drive module receives the set of multiphase pulse width modulation drive signals, isolates and amplifies the received optical or electrical signals, and generates a high-voltage drive signal that can drive the gate of the insulated gate bipolar transistor inside the intelligent power module. The three-phase inverter bridge arm inside the intelligent power module controls the conduction and cutoff of the upper bridge arm insulated gate bipolar transistor and the lower bridge arm insulated gate bipolar transistor according to the logic level of the high voltage drive signal, so as to convert the external DC bus power supply into a three-phase AC power supply with controlled frequency and amplitude. The three-phase AC power supply is applied to the three-phase stator windings of the servo motor, and a rotating magnetic field is generated inside the servo motor according to the principle of electromagnetic induction. The rotation direction of the rotating magnetic field is determined by the phase sequence of the multi-phase pulse width modulation drive signal set, and the rotation speed is determined by the fundamental frequency of the multi-phase pulse width modulation drive signal set. The rotor of the servo motor is subjected to electromagnetic torque under the action of the rotating magnetic field, and begins to rotate along the direction of the rotating magnetic field to realize position adjustment or speed adjustment. The rotation angle is determined by the pulse width and number of the multiphase pulse width modulation drive signal set. When the instruction type identifier in the set of axis control instruction blocks is a torque instruction, the axis control instruction block output by the core control algorithm execution unit contains a torque current instruction value. By controlling the amplitude and phase of the stator current, the magnitude of the electromagnetic torque is directly controlled to achieve torque adjustment. During the servo motor's operation, the encoder signal acquisition unit continuously captures changes in rotor position and speed, forming feedback for closed-loop control. The digital signal processor platform recalculates the axis control instruction block in the next servo drive control cycle based on the received feedback, and adjusts the pulse width and frequency of the multiphase pulse width modulation drive signal set so that the actual operating state of the servo motor is infinitely close to the target value given in the instruction set. When the servo motor reaches the target position specified in the instruction set or reaches the target speed, it maintains the output state of the corresponding multi-phase pulse width modulation drive signal set, so that the servo motor remains in the target state or enters the stationary holding state.

8. A servo drive control system with a multi-platform architecture, characterized in that, include: processor; A machine-readable storage medium for storing machine-executable instructions of the processor; The processor is configured to execute the servo drive control method of any one of claims 1 to 7 via executing the machine-executable instructions.

9. A computer program product, characterized in that, The computer program product includes machine-executable instructions stored in a computer-readable storage medium. The processor of the multi-platform servo drive control system reads the machine-executable instructions from the computer-readable storage medium and executes the machine-executable instructions, causing the multi-platform servo drive control system to perform the multi-platform servo drive control method as described in any one of claims 1 to 7.

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