Floating-point multiply-add fused operation unit and processor

Abstract

The application provides a floating-point multiplication-addition fusion operation unit and a processor, the floating-point multiplication-addition fusion operation unit comprising a precision-keeping multiplication subunit, an exponent bit extraction subunit, a carry-keeping addition tree subunit and a floating-point number merging output subunit. The operation unit fuses multiplication and addition into one high-efficiency data channel, optimizes the mantissa operation structure inside the multiplication operation unit, reduces the number of rounding and normalization, overcomes the precision loss and delay problem caused by the two-stage independent rounding of the prior art, reduces the hardware complexity of the multiplication unit, is conducive to realizing high working frequency, realizes higher operation speed and precision under the premise of meeting the existing calculation standard.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and in particular to a floating-point multiply-accumulate fusion arithmetic unit and processor. Background Technology

[0002] In core areas such as high-performance computing and artificial intelligence acceleration, the operating speed, latency, and accuracy of integrated circuits directly determine device performance. Floating-point multiplication and addition, as a fundamental high-frequency operation, requires crucial hardware implementation. High-performance processors and AI accelerators need to implement floating-point multiplication and addition operations (Fa×Fb+Fc) compliant with the IEEE 754 standard at the hardware level to improve operating speed, reduce latency, and meet the demands of high-precision real-time computing. This standard is the core basis for ensuring operational accuracy and compatibility.

[0003] like Figure 1 As shown, existing floating-point multiply-accumulate units (100+) employ a two-stage serial processing scheme. The two input floating-point numbers Fa and Fb first pass through... Figure 2 The standard floating-point multiplier 200 shown internally performs mantissa multiplication, exponent addition, rounding, and normalization to obtain the multiplication result. Then, this result is fed into a standard floating-point adder with a third floating-point number Fc for addition, followed by rounding and normalization again, finally outputting the result. This structure is logically clear, easy to implement, and widely used in early processors and low-to-medium performance scenarios.

[0004] However, as Figure 1 The floating-point multiply-add unit 100 shown completely separates multiplication and addition into two standard modules, and performs rounding and normalization once in each step of the multiplication and addition calculation, resulting in a large loss of accuracy in intermediate results and additional latency overhead. Furthermore, the standard floating-point multiplier is a large-bit-width mantissa multiplier, which includes modules such as floating-point unpacking, special value processor, exponent XOR gate, mantissa multiplier, shifter and leading zero detection, making the overall implementation logic complex and the critical path latency high.

[0005] With the development of artificial intelligence and high-performance computing, higher requirements have been placed on the speed and accuracy of multiply-accumulate fusion operations. The traditional two-level independent rounding structure and large bit width mantissa multiplier design have become performance bottlenecks. Therefore, a new multiply-accumulate operation design is needed to achieve the goal of high-performance computing. Summary of the Invention

[0006] This invention provides a floating-point multiply-accumulate fusion arithmetic unit and processor, aiming to solve the technical problems of precision loss and high latency in existing multiply-accumulate fusion arithmetic units during the calculation process.

[0007] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a floating-point multiplication-addition fusion operation unit for performing a floating-point multiplication-addition fusion operation Fa×Fb+Fc based on a first floating-point number Fa, a second floating-point number Fb, and a third floating-point number Fc. The floating-point multiplication-addition fusion operation unit includes a precision-preserving multiplication subunit, an exponent extraction subunit, a carry-preserving addition tree subunit, and a floating-point number merging and output subunit, wherein:

[0008] The precision-preserving multiplication subunit is used to perform sign bit generation, mantissa segmented multiplication, exponent addition, denormalized number leading zero detection and shifting based on the first floating-point number Fa and the second floating-point number Fb, and obtain the multiplication result;

[0009] The exponent extraction subunit is used to obtain the exponent shift amount m corresponding to the third floating-point number Fc based on the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc, and to shift the third floating-point number Fc according to the exponent shift amount m to obtain the shifted third floating-point number Fc. m ;

[0010] The carry-preserving addition tree subunit is used to perform the multiplication result and the shifted third floating-point number Fc. m Perform floating-point addition, and then round and normalize the result to obtain the addition result;

[0011] The floating-point number merging and output subunit is used to reorganize and arrange the sign bit, exponent bit, and mantissa bit of the addition result, and output the final floating-point multiplication and addition result.

[0012] Furthermore, the precision-preserving multiplication subunit includes an unpacking module, a special value processing module, an XOR gate module, an addition module, a piecewise multiplication module, a shift module, a selection module, a leader calculation module, and a shift module, wherein:

[0013] The unpacking module is used to unpack the first floating-point number Fa and the second floating-point number Fb, and separate the first floating-point number Fa and the second floating-point number Fb into a sign bit, an exponent bit, a mantissa, and a special value identifier;

[0014] The special value processing module is used to perform unconventional multiplication operations based on the special value identifier;

[0015] The XOR gate module is used to perform operations based on the sign bit to obtain the sign bit operation result;

[0016] The addition module is used to perform operations based on the exponent to obtain the exponent operation result;

[0017] The segmented multiplication module is used to perform operations based on the mantissa to obtain the mantissa operation result;

[0018] The selection module is used to identify whether there is a denormalized number in the first floating-point number Fa and the second floating-point number Fb. If so, the mantissa corresponding to the denormalized number is output.

[0019] The leading calculation module is used to obtain the number of adjustment bits in the mantissa that need to be led by 0;

[0020] The shift module is used to shift the result of the exponent operation and the result of the mantissa operation according to the number of adjustment bits;

[0021] The result of the sign bit operation, the result of the exponent bit operation, and the result of the mantissa bit operation are integrated and used as the multiplication result output by the precision-preserving multiplication subunit.

[0022] Furthermore, the segmented multiplication module includes a mantissa splitting submodule, a parallel multiplication submodule, a shifting submodule, and an adder tree submodule, wherein:

[0023] The mantissa bits of the first floating-point number Fa and the second floating-point number Fb are defined as A and B, respectively. The mantissa splitting submodule is used to split A and B into a first high-order mantissa A0, a first low-order mantissa A1, a second high-order mantissa B0, and a second low-order mantissa B1, respectively, according to half the original number of mantissa bits.

[0024] The parallel multiplication submodule is used to calculate the first partial product P1 of the first low-order mantissa A1 and the second low-order mantissa B1, the second partial product P2 of the first high-order mantissa A0 and the second low-order mantissa B1, the third partial product P3 of the first low-order mantissa A1 and the second high-order mantissa B0, and the fourth partial product P4 of the first high-order mantissa A0 and the second high-order mantissa B0, that is:

[0025] P1=A1×B1, P2=A0×B1, P3=A1×B0, P4=A0×B0;

[0026] The shifting submodule is used to shift the fourth partial product P4 to the left according to the original number of digits in the mantissa; at the same time, it shifts the third partial product P3 and the second partial product P2 to the left according to half the original number of digits in the mantissa.

[0027] The adder tree submodule is used to accumulate the shifted fourth partial product P4, the third partial product P3, the second partial product P2, and the unshifted first partial product P1 to obtain the mantissa operation result.

[0028] Furthermore, the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc are defined as Ea, Eb, and Ec, respectively, and the exponent shift amount m obtained by the exponent bit extraction subunit satisfies the following relationship:

[0029] m = Ea + Eb Ec.

[0030] Secondly, the present invention also provides a processor, the processor including the floating-point multiply-accumulate fusion arithmetic unit as described above.

[0031] The beneficial effects achieved by this invention are that it proposes a floating-point multiplication-addition fusion operation unit, which integrates multiplication and addition into a single efficient data path, optimizes the mantissa operation structure inside the multiplication operation unit, reduces the number of rounding and normalization operations, overcomes the precision loss and latency problems caused by the two-level independent rounding in the prior art, and reduces the hardware complexity of the multiplication unit, which is conducive to achieving a high operating frequency. Under the premise of complying with existing computing standards, it achieves higher operation speed and accuracy. Attached Figure Description

[0032] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0033] Figure 1 This is a schematic diagram of the structure of a floating-point multiply-accumulate unit in existing technology;

[0034] Figure 2 This is a schematic diagram of the structure of a standard floating-point multiplier in the existing technology;

[0035] Figure 3 This is a schematic diagram of the structure of the floating-point multiplication-accumulation fusion operation unit provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the precision-preserving multiplication subunit of the floating-point multiplication-accumulation fusion operation unit provided in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the segmented multiplication module of the floating-point multiplication-addition fusion operation unit provided in an embodiment of the present invention. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0039] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0040] Example 1

[0041] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the floating-point multiplication-addition fusion operation unit provided in an embodiment of the present invention. The floating-point multiplication-addition fusion operation unit 300 is used to perform a floating-point multiplication-addition fusion operation Fa×Fb+Fc based on a first floating-point number Fa, a second floating-point number Fb, and a third floating-point number Fc, to comply with the existing IEEE 754 standard. The floating-point multiplication-addition fusion operation unit 300 includes a precision-preserving multiplication subunit 301, an exponent extraction subunit 302, a carry-preserving addition tree subunit 303, and a floating-point number merging and output subunit 304, wherein:

[0042] The precision-preserving multiplication subunit 301 is used to perform sign bit generation, mantissa segmented multiplication, exponent addition, denormalized number leading zero detection and shifting based on the first floating-point number Fa and the second floating-point number Fb, and obtain the multiplication result;

[0043] The exponent extraction subunit 302 is used to obtain the exponent shift amount m corresponding to the third floating-point number Fc based on the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc, and to shift the third floating-point number Fc according to the exponent shift amount m to obtain the shifted third floating-point number Fc. m ;

[0044] The carry-preserving addition tree subunit 303 is used to perform the multiplication based on the multiplication result and the shifted third floating-point number Fc. m Perform floating-point addition, and then round and normalize the result to obtain the addition result;

[0045] The floating-point number merging and output subunit 304 is used to reorganize and arrange the sign bit, exponent bit, and mantissa bit of the addition result, and output the final floating-point multiplication and addition result.

[0046] Specifically, the precision-preserving multiplication subunit 301 is the core design of the floating-point multiplication-addition fusion operation unit 300 proposed in this embodiment of the invention. It aims to complete the multiplication operation of Fa × Fb without performing any rounding operations, fully preserving the precision of the intermediate multiplication results. To achieve this, please refer to... Figure 4 The schematic diagram shown is of the structure of the precision-preserving multiplication subunit. The precision-preserving multiplication subunit 301 includes an unpacking module 3011, a special value processing module 3012, an XOR gate module 3013, an addition module 3014, a piecewise multiplication module 3015, a selection module 3016, a leader calculation module 3017, and a shift module 3018, wherein:

[0047] The unpacking module 3011 is used to unpack the first floating-point number Fa and the second floating-point number Fb, and separate the first floating-point number Fa and the second floating-point number Fb into a sign bit, an exponent bit, a mantissa bit, and a special value identifier. The unpacking process of the unpacking module 3011 is based on the IEEE 754 standard, and the obtained sign bit, exponent bit, mantissa bit, and special value identifier are all standardized data.

[0048] The special value processing module 3012 is used to perform unconventional multiplication operations based on the special value identifier. Special value identifiers, such as NaN (all exponent bits are 1, mantissa bits are not 0), Inf (all exponent bits are 1, mantissa bits are 0), and 0 (all exponent bits are 0, mantissa bits are 0), are special floating-point numbers defined by the IEEE 754 standard. Floating-point multiplication related to special values ​​has special rules; for example, Inf × Inf outputs Inf, 0 × Inf outputs NaN, etc. Existing multiply-accumulate units based on the IEEE 754 standard have corresponding designs. In this embodiment of the invention, floating-point multiplication calculations with special values ​​are handled independently by the special value processing module 3012, and this processing is not within the scope of improvement of this embodiment of the invention.

[0049] The XOR gate module 3013 is used to perform operations based on the sign bit to obtain the sign bit operation result; the XOR gate module 3013 follows the rule that the same sign results in a positive result and the opposite sign results in a negative result to complete the sign bit operation of floating-point multiplication;

[0050] The addition module 3014 is used to perform operations based on the exponent bits to obtain the exponent bit operation result; the addition module 3014 directly performs the addition operation of the exponent bits of Fa and Fb to obtain the preliminary exponent result of the multiplication.

[0051] The segmented multiplication module 3015 is used to perform operations based on the mantissa to obtain the mantissa operation result; this is the core design of the embodiment of the present invention, used to replace the existing large bit width multiplier, to perform segmented parallel multiplication on the mantissa, to fully retain all product bits, and to eliminate the rounding step, thereby shortening the critical path and increasing the operation frequency.

[0052] The selection module 3016 is used to identify whether there is a denormalized number in the first floating-point number Fa and the second floating-point number Fb. If so, it outputs the mantissa corresponding to the denormalized number to be adjusted.

[0053] The leader calculation module 3017 is used to obtain the number of adjustment bits in the mantissa to be adjusted that need to be led by 0;

[0054] The shift module 3018 is used to shift the result of the exponent operation and the result of the mantissa operation according to the number of adjustment bits;

[0055] The selection module 3016, the preamble calculation module 3017, and the shift module 3018 are a modular structure designed for denormalized floating-point numbers. They are used to coordinate the adjustment of the mantissa and exponent of denormalized numbers so that the results of denormalized number operations conform to the IEEE 754 bit weighting rule while maintaining accuracy.

[0056] The result of the sign bit operation, the result of the exponent bit operation, and the result of the mantissa bit operation are integrated and used as the multiplication result output by the precision-preserving multiplication subunit 301.

[0057] Furthermore, the segmented multiplication module 3015 includes a mantissa splitting submodule 30151, a parallel multiplication submodule 30152, a shifting submodule 30153, and an adder tree submodule 30154, wherein:

[0058] The mantissa bits of the first floating-point number Fa and the second floating-point number Fb are defined as A and B, respectively. The mantissa splitting submodule 30151 is used to split A and B into a first high-order mantissa A0, a first low-order mantissa A1, a second high-order mantissa B0, and a second low-order mantissa B1, respectively, according to half the original number of mantissa bits.

[0059] The parallel multiplication submodule 30152 is used to calculate the first partial product P1 of the first low-order mantissa A1 and the second low-order mantissa B1, the second partial product P2 of the first high-order mantissa A0 and the second low-order mantissa B1, the third partial product P3 of the first low-order mantissa A1 and the second high-order mantissa B0, and the fourth partial product P4 of the first high-order mantissa A0 and the second high-order mantissa B0, that is:

[0060] P1=A1×B1, P2=A0×B1, P3=A1×B0, P4=A0×B0;

[0061] The shift submodule 30153 is used to shift the fourth partial product P4 to the left according to the original number of digits of the mantissa; at the same time, it shifts the third partial product P3 and the second partial product P2 to the left according to half the original number of digits of the mantissa.

[0062] The adder tree submodule 30154 is used to accumulate the shifted fourth partial product P4, the third partial product P3, and the second partial product P2 with the unshifted first partial product P1 to obtain the mantissa operation result. Specifically, when the special value identifier is valid, the precision-preserving multiplication subunit 301 directly outputs the multiplication result obtained by the special value processing module 3012.

[0063] In this embodiment of the invention, unlike the prior art, the precision-preserving multiplication subunit 301 implements segmented parallel computation of multiplication based on the segmented multiplication module 3015. It decomposes the multiplication of the high-order mantissa into four groups of low-order mantissa multiplications. Without losing any mantissa precision, it replaces a single large-bit-width mantissa multiplier through the process of mantissa splitting, parallel operation, shift alignment, and accumulation synthesis. It decomposes the high-bit-width mantissa multiplication into multiple groups of low-bit-width parallel multiplications, which significantly shortens the critical path of operation, reduces the hardware logic complexity, and improves the operation frequency, thus providing support for the high-speed and high-precision performance of the entire floating-point multiplication-addition fusion operation unit.

[0064] For example, such as Figure 5 The schematic diagram of the segmented multiplication module shown illustrates a floating-point calculation with an original mantissa W of 24 bits. The mantissa splitting submodule 30151 equally splits the high-width mantissa bits A and B of Fa and Fb by half the original mantissa bit width W / 2, resulting in two sets of low-width mantissa bits. For example, if the 24-bit binary number of A is 101100111000110100101100, then A0 = 101100111000 (high 12 bits) and A1 = 110100101100 (low 12 bits). It can be seen that this splitting process only involves dividing the binary bits and does not involve any calculations, thus avoiding any loss of precision.

[0065] The parallel multiplication submodule 30152 employs four independent low-width multipliers (each multiplier is 12×12 bits in size when the original mantissa is 24 bits) to calculate the product of the four sets of low-width mantissas (A0, A1, B0, B1) output by the mantissa splitting submodule in parallel, generating four partial products. This replaces the serial operation of the existing single high-width multiplier, significantly reducing the computation time. For example, the first multiplier calculates the product of the first low-width mantissa A1 and the second low-width mantissa B1, obtaining the first partial product P1, i.e., P1 = A1 × B1. Since the result of a 12×12-bit multiplication is at most 24 bits, P1 is a 24-bit binary number.

[0066] During the computation of the parallel multiplication submodule 30152, four multipliers work synchronously, with an operation time equivalent to that of a single 12×12-bit multiplier. Compared to the operation time using a 24×24-bit multiplier, the computation time is reduced to one-quarter, significantly shortening the critical path length. Furthermore, each multiplier retains all bits of the product without any rounding or truncation, ensuring that the subsequent summation result is consistent with the full-precision result of a 24×24-bit multiplier. In addition, the logical complexity of a 12×12-bit multiplier is much lower than that of a 24×24-bit multiplier, requiring fewer circuit components and lower signal transmission latency. This reduces hardware design difficulty and increases the operation frequency, making it suitable for high-performance computing needs.

[0067] The shift submodule 30153 performs a targeted left shift operation on the four sets of partial products (P1, P2, P3, P4) output by the parallel multiplication submodule to ensure that the bit weights of all partial products are consistent, laying the foundation for the subsequent accumulation operation of the adder tree submodule 30154. Since the four sets of partial products correspond to the products of different high-order and low-order mantissas, their original bit weights differ. Direct accumulation would lead to incorrect results; therefore, shift alignment is a crucial step to ensure the accuracy of mantissa multiplication. In this embodiment of the invention, different processing is performed on partial products with different bit lengths, wherein:

[0068] For the fourth part product P4 (A0×B0): A0 is the high 12 bits of A and B0 is the high 12 bits of B. The product of the two has the highest bit weight, so it needs to be shifted left by W bits (i.e. 24 bits). After the shift, the bit weight of P4 is consistent with the bit weight of the high 24 bits of the original 24-bit mantissa A×B.

[0069] For the third part product P3 (A1×B0): A1 is the lower 12 bits of A and B0 is the higher 12 bits of B. The place value of the product is in the middle, so it needs to be shifted to the left by W / 2 bits (i.e. 12 bits). After the shift, the place value of P3 is consistent with the place value of the middle 12-24 bits of the original 24-bit mantissa A×B.

[0070] For the second part product P2 (A0×B1): A0 is the high 12 bits of A and B1 is the low 12 bits of B. Its bit weight is exactly the same as that of P3. Therefore, the same shift rule as P3 is used to shift it to the left by W / 2 bits (12 bits) to ensure that it is aligned with the bit weight of P3.

[0071] For the first partial product P1 (A1×B1): A1 is the lower 12 bits of A and B1 is the lower 12 bits of B. The bit weight of the product is the lowest, so no shifting operation is needed. Its bit weight is the same as the bit weight of the lower 24 bits of the original 24-bit mantissa A×B.

[0072] Finally, the adder tree submodule 30154 accumulates the four shifted partial products in the order of P4, P3, P2, and P1 to generate a full-precision mantissa product of A×B, which is the final output of the piecewise multiplication module 3015.

[0073] The exponent extraction subunit 302, the carry-preserving addition tree subunit 303, and the floating-point number merging and output subunit 304, together with the precision-preserving multiplication subunit 301, constitute the complete chain of the floating-point multiplication-addition fusion operation unit 300. Among them, the exponent extraction subunit 302 provides the shift basis for mantissa alignment, the carry-preserving addition tree subunit 303 performs high-speed addition operation, and the floating-point number merging and output subunit 304 realizes standardized encoding output. The three have clear division of labor and are closely connected.

[0074] Specifically, the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc are defined as Ea, Eb, and Ec, respectively. The exponent shift amount m obtained by the exponent bit extraction subunit 302 satisfies the following relationship:

[0075] m = Ea + Eb Ec.

[0076] The m value is essentially a prediction of the exponential difference between Fa×Fb and Fc, controlling the mantissa shift alignment of Fc to ensure accurate addition. The m value is directly fed into the mantissa shift logic of Fc and connected to the carry-preserving addition tree subunit 303.

[0077] The carry-retaining addition tree subunit 303 is the core of the addition process, used to receive the multiplication result from the segmented multiplication module 3015 and the shifted third floating-point number Fc after being shifted by the m-value. m It includes a carry initialization signal, efficiently performs addition, and outputs the sum and carry vector.

[0078] The floating-point number merging output subunit 304 is the final output module of the arithmetic link. It is used to receive the rounded and normalized sign bit, exponent bit, and mantissa bit. It first verifies the validity of each part, and then reassembles the sign bit, exponent bit, and mantissa bit in a fixed order according to the corresponding floating-point format. The mantissa is truncated and adapted, and the encoding is reassembled according to the IEEE 754 standard to output the final floating-point multiplication and addition result that conforms to the standard.

[0079] The implementation of the carry-preserving addition tree subunit 303 and the floating-point number merging output subunit 304 can be implemented according to the existing addition processing structure and floating-point number recombination structure. The implementation of these two subunits does not directly affect the calculation logic of the precision-preserving multiplication subunit 301, and the present invention does not impose any restrictions on this.

[0080] The beneficial effects achieved by this invention are that it proposes a floating-point multiplication-addition fusion operation unit, which integrates multiplication and addition into a single efficient data path, optimizes the mantissa operation structure inside the multiplication operation unit, reduces the number of rounding and normalization operations, overcomes the precision loss and latency problems caused by the two-level independent rounding in the prior art, and reduces the hardware complexity of the multiplication unit, which is conducive to achieving a high operating frequency. Under the premise of complying with existing computing standards, it achieves higher operation speed and accuracy.

[0081] Example 2

[0082] This invention also provides a processor, which includes the floating-point multiply-accumulate fusion arithmetic unit 300 as described in Embodiment 1 above. It is understood that, based on the specific structure of the floating-point multiply-accumulate fusion arithmetic unit 300, the processor can achieve higher computational speed and accuracy compared to existing technologies when performing floating-point multiply-accumulate fusion calculations. Referring to the descriptions in the above embodiments, further details are omitted here.

[0083] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0084] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A floating-point multiply-add fusion operation unit, used to perform a floating-point multiply-add fusion operation Fa×Fb+Fc based on a first floating-point number Fa, a second floating-point number Fb, and a third floating-point number Fc, characterized in that, The floating-point multiplication-addition fusion operation unit includes a precision-preserving multiplication subunit, an exponent extraction subunit, a carry-preserving addition tree subunit, and a floating-point number merging and output subunit, wherein: The precision-preserving multiplication subunit is used to perform sign bit generation, mantissa segmented multiplication, exponent addition, denormalized number leading zero detection and shifting based on the first floating-point number Fa and the second floating-point number Fb, and obtain the multiplication result; The exponent extraction subunit is used to obtain the exponent shift amount m corresponding to the third floating-point number Fc based on the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc, and to shift the third floating-point number Fc according to the exponent shift amount m to obtain the shifted third floating-point number Fc. m ; The carry-preserving addition tree subunit is used to perform the multiplication result and the shifted third floating-point number Fc. m Perform floating-point addition, and then round and normalize the result to obtain the addition result; The floating-point number merging and output subunit is used to reorganize and arrange the sign bit, exponent bit, and mantissa bit of the addition result, and output the final floating-point multiplication and addition result; The precision-preserving multiplication subunit includes an unpacking module, a special value processing module, an XOR gate module, an addition module, a piecewise multiplication module, a selection module, a leader calculation module, and a shift module, wherein: The unpacking module is used to unpack the first floating-point number Fa and the second floating-point number Fb, and separate the first floating-point number Fa and the second floating-point number Fb into a sign bit, an exponent bit, a mantissa, and a special value identifier; The special value processing module is used to perform unconventional multiplication operations based on the special value identifier; The XOR gate module is used to perform operations based on the sign bit to obtain the sign bit operation result; The addition module is used to perform operations based on the exponent to obtain the exponent operation result; The segmented multiplication module is used to perform operations based on the mantissa to obtain the mantissa operation result; The selection module is used to identify whether there is a denormalized number in the first floating-point number Fa and the second floating-point number Fb. If so, the mantissa corresponding to the denormalized number is output. The leading calculation module is used to obtain the number of adjustment bits in the mantissa that need to be led by 0; The shift module is used to shift the result of the exponent operation and the result of the mantissa operation according to the number of adjustment bits; The result of the sign bit operation, the result of the exponent bit operation, and the result of the mantissa bit operation are integrated and used as the multiplication result output by the precision-preserving multiplication subunit. The segmented multiplication module includes a mantissa splitting submodule, a parallel multiplication submodule, a shifting submodule, and an adder tree submodule, wherein: The mantissa bits of the first floating-point number Fa and the second floating-point number Fb are defined as A and B, respectively. The mantissa splitting submodule is used to split A and B into a first high-order mantissa A0, a first low-order mantissa A1, a second high-order mantissa B0, and a second low-order mantissa B1, respectively, according to half the original number of mantissa bits. The parallel multiplication submodule is used to calculate the first partial product P1 of the first low-order mantissa A1 and the second low-order mantissa B1, the second partial product P2 of the first high-order mantissa A0 and the second low-order mantissa B1, the third partial product P3 of the first low-order mantissa A1 and the second high-order mantissa B0, and the fourth partial product P4 of the first high-order mantissa A0 and the second high-order mantissa B0, that is: P1=A1×B1, P2=A0×B1, P3=A1×B0, P4=A0×B0; The shifting submodule is used to shift the fourth partial product P4 to the left according to the original number of digits in the mantissa; at the same time, it shifts the third partial product P3 and the second partial product P2 to the left according to half the original number of digits in the mantissa. The adder tree submodule is used to accumulate the shifted fourth partial product P4, the third partial product P3, the second partial product P2, and the unshifted first partial product P1 to obtain the mantissa operation result.

2. The floating-point multiply-accumulate fusion arithmetic unit according to claim 1, characterized in that, Let the exponent bits corresponding to the first floating-point number Fa, the second floating-point number Fb, and the third floating-point number Fc be Ea, Eb, and Ec, respectively. The exponent shift amount m obtained by the exponent bit extraction subunit satisfies the following relationship: m = Ea + Eb - Ec.

3. A processor, characterized in that, The processor includes a floating-point multiply-accumulate fusion arithmetic unit as described in any one of claims 1-2.

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