An end-side processor debugging system and a debugging method

Abstract

The application provides an end-side processor debugging system and a debugging method, the debugging system comprising a JTAG interface, an input-output function selector, a debugging transmission module (DTM), an advanced peripheral bus (APB) and a plurality of cores in the end-side processor. The application designs the input-output function selector on the side of the JTAG interface, selects three different JTAG links according to the value of the JTAG link selection (SEL) signal, wherein two JTAG links can be directly connected with the cores in the end-side processor, and the other JTAG link is connected with the advanced peripheral bus (APB) through the debugging transmission module (DTM) and then connected with the cores in the end-side processor, which not only enhances the debugging independence but also can debug a plurality of cores according to different addresses, has strong expansibility and high universality. Meanwhile, in the debugging transmission module (DTM), a two-wire JTAG interface coexisting with a five-wire JTAG is defined, which saves the external pin resources and simplifies the communication mode.

Description

Technical Field

[0001] This invention relates to the field of chip debugging technology, and more specifically, to an edge processor debugging system and debugging method. Background Technology

[0002] With the rapid development of semiconductor technology, edge processors are becoming increasingly integrated, larger in scale, and more functional. Besides the basic Microcontroller Unit (MCU), edge processors also integrate modules such as the Central Processing Unit (CPU) and Neural Processing Unit (NPU), which increases the difficulty of troubleshooting during actual testing and debugging. Comprehensive debugging capabilities help designers quickly locate program faults, which is especially important in complex projects. Furthermore, edge processors primarily operate in embedded application environments, and their hardware platforms are diverse, with varying specifications and types. Given this trend, the design of edge processor debugging capabilities is crucial for promoting the widespread adoption and application of edge processors. The Joint Test Action Group (JTAG) boundary scan technology, initially applied to integrated circuit testing, has become widely used in processor debugging due to its flexible and efficient technical characteristics.

[0003] In current technological implementations, processors commonly use the JTAG interface as a means to access their internal circuit logic, thereby completing the processor debugging process. The standard (IEEE 1149.1) JTAG five-wire interface includes Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test Mode Select (TMS), and Test Reset (TRST) ports. The basic principle of using JTAG to debug a processor is based on the Test Access Port (TAP) state machine, which interconnects with the debugger through the standard five-wire port. It incorporates various registers and shift register chains, as well as serial-to-parallel conversion mechanisms. Through a dedicated register link, it completes the conversion between serial and parallel data and interacts with the debug bus, enabling debug access to the processor's internal logic.

[0004] In an existing JTAG debugging system compatible with the Advanced Peripheral Bus (APB) protocol, the object debugged through the JTAG interface is an embedded processor. The basic method of this scheme to debug a single embedded processor through the APB bus is as follows: use the five-wire JTAG interface to test the instructions of the access port controller, and use extended instructions to achieve conversion with the APB protocol, thereby debugging a single embedded processor.

[0005] However, for edge processors, since they include multiple single-core or multi-core sub-processors such as microcontrollers, central processing units or neural network processing units, as well as some peripheral modules, some sub-processors are equipped with their own debug access ports for debugging. Debugging methods that only target a single processor core cannot debug multiple sub-processors. Furthermore, edge processors have a variety of application scenarios, and although the area and power consumption indicators are different in each scenario, they are all important factors affecting whether edge processors can be successfully applied. Summary of the Invention

[0006] To address the limitations of existing processor debugging technologies, this invention provides an edge processor debugging system and method.

[0007] According to a first aspect of the present invention, a terminal processor debugging system is provided, comprising a JTAG interface, an input / output function selector, a debug transmission module (DTM), an advanced peripheral bus (APB), and multiple cores in the terminal processor. The multiple cores include at least a microcontroller unit, a central processing unit, a neural network processing unit, a vector processing extension unit, and a high-speed peripheral component interconnect unit. The JTAG interface is connected to the input / output function selector, which is connected to the debug transmission module (DTM), the vector processing extension unit, and the high-speed peripheral component interconnect unit, respectively. The debug transmission module (DTM) is connected to the advanced peripheral bus (APB), and the multiple cores of the terminal processor are connected to the APB. The input / output function selector includes a JTAG interface multiplexing function. The I / O function selector selects the JTAG interface to be connected to the debug transmission module (DTM), the vector processing extension unit, or the high-speed peripheral component interconnect unit via a JTAG link selection signal, so as to achieve debugging of different cores in the terminal processor through different links.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Optionally, the input / output function selector selects the JTAG interface via the JTAG link selection SEL signal to connect it to the debug transmission module DTM, the vector processing extension unit, or the high-speed peripheral component interconnection unit, respectively, so as to enable debugging of different cores in the edge processor through different links, including:

[0010] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b01, the JTAG interface is a five-wire JTAG interface, and the JTAG interface is switched to the JTAG interface of the high-speed peripheral component interconnection unit, and connected to the high-speed peripheral component interconnection unit to realize the debugging of the high-speed peripheral component interconnection unit.

[0011] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b10, the JTAG interface is a five-wire JTAG interface, and the JTAG interface is switched to the JTAG interface of the vector processing extension unit and connected to the vector processing extension unit to realize the debugging of the vector processing extension unit.

[0012] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM. The debugging transmission module DTM converts the JTAG signal into the Advanced Peripheral Bus (APB) signal, and the debugging of multiple cores of the edge processor is realized through the APB.

[0013] Optionally, the debug transmission module DTM selects whether to use a five-wire JTAG interface or a two-wire JTAG interface to debug the end-side processor via a two-wire / five-wire JTAG mode selection signal;

[0014] When the JTAG link selection SEL signal value of the debugging system is set to 2'b00, the JTAG interface is configured through the two-wire / five-wire JTAG mode selection signal of the debugging transmission module DTM. If the two-wire / five-wire JTAG mode selection signal value is set to 1'b1, the JTAG interface is a two-wire JTAG interface. The debugging transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. The debugging of multiple cores of the end-side processor is realized through the APB.

[0015] Keep the JTAG link selection SEL signal value of the debugging system unchanged. If the dual-wire / five-wire JTAG mode selection signal value is set to 1'b0, the JTAG interface is a five-wire JTAG interface. The debugging transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. The debugging of multiple cores of the end-side processor is realized through the APB.

[0016] Optionally, the input / output function selector includes multiple input / output units and a multiplexer. The five signals of the JTAG interface and the JTAG link selection SEL signal are all connected to the multiplexer through the corresponding input / output units. The five signals of the JTAG interface include test clock TCLK, test reset TRST, test data input TDI, test mode selection TMS, and test data output TDO. The input / output direction of the access signals is controlled by controlling the input enable IE signal and the output enable OEN signal of each input / output unit. Among them, TCLK, TRST, TDI, and SEL signals are set as input signals, and the input / output direction of TMS and TDO signals is determined according to the specific situation. Optionally, one side of the debug transmission module DTM contains JTAG signals, including pad_tclk, pad_trst_b, pad_tms, pad_tdi, pad_tdo, pad_jtag2_sel, pad_tdo_oe, pad_tms_o, and pad_tms_oe; the other side contains an Advanced Peripheral Bus (APB) interface, which is connected to the Advanced Peripheral Bus (APB). The debug transmission module DTM includes a serial-to-parallel data conversion submodule, a two-wire / five-wire JTAG status control submodule, an instruction data processing submodule, an I / O control submodule, and a JTAG-APB protocol conversion submodule.

[0017] Among them, pad_jtag2_sel is the two-wire / five-wire JTAG mode selection signal, pad_tclk is the JTAG clock signal, pad_trst_b is the JTAG reset signal, pad_tdi is the JTAG serial input port, pad_tdo is the JTAG serial data output port, pad_tms is the JTAG test mode selection signal, pad_tms_o is the two-wire JTAG serial data output signal, and pad_tms_oe is the pad_tms_o output enable signal;

[0018] The input / output control submodule is used to control the input and output of the JTAG interface side in the debug transmission module DTM, and selects the pad_tms signal or the pad_tdi signal as the input of serial data according to the pad_jtag2_sel signal;

[0019] The serial-to-parallel data conversion submodule is used to store the input serial data bit by bit into the instruction or data register, or to serially output the parallel read data from the Advanced Peripheral Bus (APB) via TDO.

[0020] The dual-wire / five-wire JTAG status control submodule is the TAP status control module for JTAG. It is used to select the TAP of the dual-wire JTAG interface or the five-wire JTAG interface according to the pad_jtag2_sel signal to complete the timing control of the serial-to-parallel conversion process.

[0021] The instruction data processing submodule is used to filter the parallel data information after the serial-to-parallel data conversion submodule has completed the conversion based on the control signals generated by the two-wire / five-wire JTAG status control submodule, receive the request and response with the Advanced Peripheral Bus (APB) interface, generate the address, data and control signals required by the JTAG-APB protocol conversion submodule, and receive data from the JTAG-APB protocol conversion submodule.

[0022] The JTAG-APB protocol conversion submodule is used to organize the address, write data and control identifiers extracted from the two-wire / five-wire JTAG status control submodule into the corresponding Advanced Peripheral Bus (APB) timing sequence, and at the same time, return the APB transmission acknowledgment signal and read data to the two-wire / five-wire JTAG status control submodule.

[0023] Optionally, the debug transmission module (DTM) defines a two-wire JTAG interface that can coexist with the five-wire JTAG interface.

[0024] The dual-wire JTAG interface defines two interface signals, including a clock TCK signal and a data TDATA signal. The TDATA signal is a bidirectional signal. The TCK signal and TDATA signal in the dual-wire JTAG interface are multiplexed from the TCLK signal and TMS signal of the five-wire JTAG interface, respectively.

[0025] In the communication protocol of the two-wire JTAG interface, data is sampled on the rising edge of the clock, and the sampled data is transmitted in the form of data packets. The format of a data packet includes: start bit, read / write indicator bit rw, register group select bit rs[1:0], data signal direction inversion bit inv, data synchronization bit sync, data bit data, and data parity bit par.

[0026] The start bit is a low level on the TDATA signal line for one cycle.

[0027] A high read / write indicator bit rw indicates a read operation from the DTM register, while a low read operation indicates a write operation from the DTM register.

[0028] rs[1:0] indicates register group selection, where 00 indicates selection of the DTM external debug register; 01 indicates selection of the DTM internal instruction register; and 11 indicates selection of the DTM internal data register.

[0029] The data signal direction reversal bit inv indicates that the direction of the tdata data signal will be reversed;

[0030] The data synchronization bit sync is low for one cycle and only exists during DTM register read operations. This bit is used to determine the time to start reading data returned by DTM.

[0031] The data bit indicates that the data segment is fixed at 5 bits when rs is 01, and the bit width is set differently depending on the register when rs is 11 or 00.

[0032] The parity bit 'par' is the odd parity bit for the 'data' data segment.

[0033] Optionally, during the process of reading and writing the DTM internal registers through the two-wire JTAG interface, when rs[1:0]=2'b10, in the first data signal direction reversal state, an instruction register capture signal in the five-wire JTAG protocol is generated; in the data transmission state, an instruction register shift signal in the five-wire JTAG protocol is generated; and in the second data signal direction reversal state, an instruction register update signal in the five-wire JTAG protocol is generated. The whole process is called the instruction register stage. When rs[1:0]=2'b11 or rs[1:0]=2'b00, in the first data signal direction reversal state, a data register capture signal in the five-wire JTAG protocol is generated; in the data transmission state, a data register shift signal in the five-wire JTAG protocol is generated; and in the second data signal direction reversal state, a data register update signal in the five-wire JTAG protocol is generated. The whole process is called the data register stage.

[0034] Specifically, during the instruction register stage, the debug module interface (DMI) register within the debug transfer module (DTM) is selected; during the data register stage, the address and operation type are written to the address and operation type fields of the debug module interface (DMI) register, where the operation type is either a read operation or a write operation.

[0035] Specifically, writing an address to the debug module interface DMI register during the data register phase includes:

[0036] When a debug module DM exists in the core of the edge processor, write the edge processor's on-chip offset address into the debug module interface DMI register.

[0037] When the debug module DM is not present in the core of the edge processor, the address is the on-chip offset address of the edge processor that writes to the core register of the debug module interface DMI register;

[0038] During the data register phase, data is also read from or written to the data segment of the debug module interface DMI register, including:

[0039] When the operation type is a write operation, data also needs to be written to the data segment of the DMI register of the debug module interface; when the operation type is a read operation, data is read out from the data segment of the DMI register of the debug module interface.

[0040] Specifically, the debug transmission module DTM transmits debug control commands to the core of the end-side processor that has a debug module DM through the debug module interface DMI, or transmits register read / write commands to the core of the end-side processor that does not have a debug module DM.

[0041] According to a second aspect of the present invention, a terminal-side processor debugging method is provided, applied to a terminal-side processor debugging system, comprising:

[0042] Set the SEL signal value of the JTAG link selection of the debugging system to 2'b01, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the high-speed peripheral component interconnection unit, connect it to the high-speed peripheral component interconnection unit, and realize the debugging of the high-speed peripheral component interconnection unit.

[0043] Set the SEL signal value of the JTAG link selection of the debugging system to 2'b10, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the vector processing extension unit, connect it to the vector processing extension unit, and realize the debugging of the vector processing extension unit.

[0044] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM. The debugging transmission module DTM converts the JTAG signal into the Advanced Peripheral Bus (APB) signal, and the debugging of multiple cores of the edge processor is realized through the APB.

[0045] Optional, also includes:

[0046] When the JTAG link selection SEL signal value of the debugging system is set to 2'b00, the JTAG interface is configured through the two-wire / five-wire JTAG mode selection signal pad_jtag2_sel of the debugging transmission module DTM. If the pad_jtag2_sel value is set to 1'b1, the JTAG interface is a two-wire JTAG interface. The debugging transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. The debugging of multiple cores of the end-side processor is realized through the APB.

[0047] Keeping the JTAG link selection SEL signal value of the debugging system unchanged, if the pad_jtag2_sel value is set to 1'b0, the JTAG interface is a five-wire JTAG interface. The debug transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. The debugging of multiple cores of the end-side processor is realized through the APB.

[0048] This invention provides a debugging system and method for a terminal processor. The debugging system includes a JTAG interface, an input / output function selector, a debug transmission module (DTM), an Advanced Peripheral Bus (APB), and multiple cores in the terminal processor. The input / output function selector selects the JTAG interface via the JTAG link selection SEL signal and connects it to the debug transmission module (DTM), a vector processing expansion unit, or a high-speed peripheral component interconnection unit, respectively, to debug different cores in the terminal processor through different links. This invention designs an input / output function selector on the JTAG interface side, selecting three different JTAG links based on the JTAG link selection SEL signal value. Two of these JTAG links can be directly connected to the cores in the terminal processor, while the other JTAG link connects to the Advanced Peripheral Bus (APB) and then to the cores in the terminal processor. This enhances debugging independence and allows debugging of multiple cores based on different addresses, offering strong scalability and high versatility. Furthermore, the debug transmission module (DTM) defines a two-wire JTAG interface that can coexist with the five-wire JTAG, saving external pin resources and simplifying communication. Attached Figure Description

[0049] Figure 1 A structural block diagram of an edge processor debugging system provided in one embodiment of the present invention;

[0050] Figure 2 A block diagram of an input / output function selector;

[0051] Figure 3 A block diagram for debugging the transmission module DTM;

[0052] Figure 4This is a schematic diagram of the data packet format for read register operations in the two-wire JTAG communication protocol;

[0053] Figure 5 A schematic diagram of the data packet format for write register operations in the two-wire JTAG communication protocol;

[0054] Figure 6 This is a schematic diagram of the state transitions of the control state machine for a two-wire JTAG interface communication.

[0055] Figure 7 Timing diagram for reading DTM registers using a two-wire JTAG;

[0056] Figure 8 Timing diagram for writing to the DTM register for a two-wire JTAG;

[0057] Figure 9 This is a block diagram of the JTAG-APB protocol conversion submodule. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0059] Existing debugging systems primarily convert the JTAG interface to an APB interface and then connect to the processor core via the APB bus. This lack of direct core connection results in weak debugging independence and reliance on bus stability during debugging. While improvements to the data signals on the five-wire JTAG interface increase debugging speed, they are incompatible with applications where pin resources are insufficient. This can impact debugging on the edge processor. Fewer pin resources required for debugging allow for more pins to be allocated to other modules, which is beneficial for edge processor applications.

[0060] To address the shortcomings of existing debugging systems, this invention provides an edge processor debugging system capable of debugging multiple sub-processors of the edge processor. It maintains both stability and scalability, directly connecting to vector processing expansion units and high-speed peripheral component interconnect units, while also connecting to other cores (microcontroller units, central processing units, etc.) via the APB bus. Furthermore, by multiplexing the TCLK and TMS signals of the five-wire JTAG interface, communication is simplified, debugging pins are saved, and a two-wire JTAG interface, coexisting with the five-wire JTAG interface, allows debugging of multiple sub-processors in the edge processor via the APB bus or direct connection to the core.

[0061] Figure 1 This illustration shows an edge processor debugging system according to an embodiment of the present invention, including a JTAG interface, an input / output function selector, a debug transport module (DTM), an APB bus, and multiple cores (sub-processors) in the edge processor, such as a Reduced Instruction Set Computer (RISC-V) microcontroller, a RISC-V central processing unit, a neural network processing unit, a vector processing extension unit, and a high-speed peripheral component interconnect unit. The JTAG interface is connected to the input / output function selector, which is connected to the debug transport module, as well as the vector processing extension unit and the high-speed peripheral component interconnect unit. The input / output function selector includes a JTAG interface multiplexing function. The selector selects whether the JTAG interface is connected to the debug transport module (DTM), the vector processing extension unit, or the high-speed peripheral component interconnect unit via the SEL signal selected by the JTAG link. The debug transport module (DTM) is connected to the APB bus, which connects multiple cores, such as the microcontroller, the central processing unit, the neural network processing unit, the vector processing extension unit, and the high-speed peripheral component interconnect unit.

[0062] The input / output function selector enables direct connection between the JTAG interface and the cores in the edge processor, or it enables the JTAG interface to connect to the cores in the edge processor through the debug transmission module DTM and the APB bus. This allows for debugging of each core in the edge processor through different debug links, thus achieving debugging flexibility.

[0063] See Figure 2The diagram illustrates the internal structure of an input / output function selector. In this selector, the five signals of the JTAG interface are connected to five input / output units, which in turn connect to a multiplexer. The JTAG link selection signal (SEL) of the selector is also connected to the multiplexer via an input / output unit. The five JTAG interface signals include Test Clock (TCLK), Test Reset (TRST), Test Data Input (TDI), Test Mode Selection (TMS), and Test Data Output (TDO). The input / output direction of the signals can be controlled by adjusting the input enable (IE) and output enable (OEN) signals of the input / output units. TCLK, TRST, TDI, and SEL signals are set as input signals, while the input / output directions of TMS and TDO signals are determined based on specific circumstances.

[0064] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b01, the JTAG interface is a five-wire JTAG interface, and the JTAG interface is switched to the JTAG interface of the high-speed peripheral component interconnection unit, which is connected to the high-speed peripheral component interconnection unit to realize the debugging of the high-speed peripheral component interconnection unit.

[0065] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b10, the JTAG interface is a five-wire JTAG interface. The JTAG interface is switched to the JTAG interface of the vector processing extension unit and connected to the vector processing extension unit to realize the debugging of the vector processing extension unit.

[0066] When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM, which converts the JTAG signal into an APB signal and realizes the debugging of multiple cores of the edge processor through the APB bus.

[0067] External debugging tools connect to the Debug Transmission Module (DTM) via the JTAG interface. The DTM communicates with the RISC-V processor cores. The DTM transmits debugging control commands to the debug module (DM) in the core of the edge processor via the Debug Module Interface (DMI) to enable debugging of each core of the edge processor. The DM is the main unit in the RISC-V debugging architecture, providing various RISC-V debugging functions to the outside world.

[0068] The Debug Transport Module (DTM) provides external debugging tools with access to internal debugging resources, allowing them to communicate with the target platform via different transport protocols, such as two-wire or five-wire JTAG interfaces. The DTM implements access control to the Debug Module (DM) within the edge processor core through the JTAG TAP mechanism.

[0069] The DMI is the communication interface between the DTM and DM. It controls the DM by accessing the DM's registers in the DMI address space. As the interface between the DTM and DM, the DMI enables a one-to-many connection through the APB bus.

[0070] The Debug Transmission Module (DTM) also defines a dual-wire JTAG interface that can coexist with the five-wire JTAG interface. The DTM uses the pad_jtag2_sel signal to select between the five-wire and dual-wire JTAG interfaces for debugging the edge processor. Specifically:

[0071] When the JTAG link selection SEL signal value of the debugging system is set to 2'b00, the JTAG interface is configured through the pad_jtag2_sel signal of the debug transmission module DTM. If the pad_jtag2_sel value is set to 1'b1, the JTAG interface is a two-wire JTAG interface. The debug transmission module DTM converts the JTAG signal into an APB signal and connects it to the APB bus. The debugging of multiple cores of the end-side processor is realized through the APB bus.

[0072] Keep the JTAG link selection SEL signal value of the debugging system unchanged. If the pad_jtag2_sel value is set to 1'b0, the JTAG interface is a five-wire JTAG interface. The debug transmission module DTM converts the JTAG signal into an APB signal and connects it to the APB bus. The debugging of multiple cores of the end-side processor is realized through the APB bus.

[0073] In the Debug Transmission Module (DTM), one side contains JTAG signals, including pad_tclk, pad_trst_b, pad_tms, pad_tdi, pad_tdo, pad_jtag2_sel, pad_tdo_oe, pad_tms_o, and pad_tms_oe; the other side is an APB interface connected to the APB bus. The DTM includes a serial-to-parallel data conversion submodule, a two-wire / five-wire JTAG status control submodule, an instruction data processing submodule, an input / output control submodule, and a JTAG-APB protocol conversion submodule, such as... Figure 3 As shown, in Figure 3The diagram briefly shows the block diagram of the DTM (Diagram of the Debug Transmission Module) and its main signals.

[0074] The specific descriptions of the JTAG interface side signals are as follows:

[0075] ①The pad_jtag2_sel signal is a two-wire / five-wire JTAG mode selection signal. A high level indicates a two-wire signal, and a low level indicates a five-wire signal.

[0076] ②pad_tclk is the JTAG clock signal;

[0077] ③pad_trst_b is the JTAG reset signal;

[0078] ④pad_tdi is the JTAG serial input port, which includes control commands and data. The input order is from low bit to high bit. The DTM terminal samples it on the rising edge of the JTAG clock signal, while the external debugger sets the signal on the falling edge of the JTAG clock.

[0079] ⑤pad_tdo is the JTAG serial data output port. The output order is from low bit to high bit. The DTM terminal is set on the falling edge of the JTAG clock signal, while the external debugger samples it on the rising edge of the JTAG clock.

[0080] ⑥tdo_oe is the tdo output enable signal;

[0081] ⑦pad_tms is the JTAG test mode selection signal, which controls the operation of the TAP state machine; in two-wire JTAG, it is used as a serial data input signal. The DTM samples it on the rising edge of the JTAG clock signal, and the external debugger sets the signal on the falling edge of the JTAG clock.

[0082] ⑧pad_tms_o is a two-wire JTAG serial data output signal. DTM sets it on the falling edge of the JTAG clock signal, while the external debugger samples it on the rising edge of the JTAG clock.

[0083] ⑨pad_tms_oe is the output enable signal for pad_tms_o. In the input / output function selector, this signal is used to combine pad_tms and pad_tms_o into a bidirectional port signal.

[0084] The debug transmission module (DTM) includes a serial-to-parallel data conversion submodule, a two-wire / five-wire JTAG status control submodule, an instruction data processing submodule, an input / output control submodule, and a JTAG-APB protocol conversion submodule. The debug transmission module selects whether to use two-wire or five-wire JTAG to debug the processor based on the pad_jtag2_sel signal.

[0085] The input / output control submodule controls the input and output of the JTAG interface in the debug transmission module (DTM). It primarily selects between the pad_tms and pad_tdi signals as the serial data input based on the pad_jtag2_sel signal. The serial-to-parallel data conversion submodule includes various registers, including the debug module interface access register DMI_ACC, the debug module interface register DMI, the debug transmission module control and status register DTMCS, and the device identification code register IDCODE. This submodule mainly shifts data through serial input into the instruction or data register, or serially outputs parallel read data from the APB host via pad_tdo. The two-wire / five-wire JTAG status control submodule is the JTAG TAP status control module. It selects between two-wire and five-wire JTAG TAP based on the pad_jtag2_sel signal to complete the timing control of the serial-to-parallel conversion process. The instruction data processing submodule filters the parallel data information converted by the serial-to-parallel data conversion submodule based on the timing control signals generated by the two-wire / five-wire JTAG status control submodule. It receives the acknowledgment signal (read / write completion flag wr_ready) from the APB bus interface, generates the address, data (wdata), and control signals (read / write valid flag wr_vld and read / write flag wr_flg) required by the JTAG-APB protocol conversion submodule, and receives data (read data rdata) from the JTAG-APB protocol conversion submodule. The JTAG-APB protocol conversion submodule organizes the address, write data, and control flags extracted from the two-wire / five-wire JTAG status control submodule into corresponding APB timing sequences, and simultaneously returns the APB bus transmission acknowledgment signal and read data to the two-wire / five-wire JTAG status control submodule.

[0086] The two-wire / five-wire JTAG state control submodule includes a standard (IEEE 1149.1) five-wire JTAG TAP state machine (which will not be detailed here). The TAP state machine changes once per pad_tclk cycle under the control of the pad_tms signal. By controlling the pad_tms transition, the TAP state machine is controlled, achieving the purpose of debugging. The two-wire / five-wire JTAG state control submodule also includes two-wire JTAG control logic.

[0087] To save external pin resources and simplify communication, a two-wire JTAG interface that can coexist with the five-wire JTAG interface is defined in the Debug Transmission Module (DTM).

[0088] The dual-wire JTAG interface defines two interface signals: clock signal TCK and data signal TDATA. TDATA is a bidirectional signal. In this invention, the TCK and TDATA signals of the dual-wire JTAG are multiplexed from the TCLK and TMS signals of the five-wire JTAG, respectively.

[0089] In the two-wire JTAG communication protocol, data is always sampled on the rising edge of the clock. Data is transmitted in the form of data packets. A data packet has the following format: start bit, read / write indicator bit (rw), register group select bits (rs[1:0]), data signal direction inversion bit (inv), data synchronization bit (sync), data bits (data), and data parity bit (par). The read / write data packet formats are as follows: Figure 4 and Figure 5 As shown.

[0090] The meanings of each data bit in the data packet of the two-wire JTAG interface communication protocol are as follows:

[0091] The start bit is a low level on the TDATA signal line for one cycle;

[0092] A high read / write indicator bit rw indicates a read operation from the DTM register, while a low read operation indicates a write operation from the DTM register.

[0093] rs[1:0] indicates register group selection, where 00 indicates selection of the DTM external debug register; 01 indicates selection of the DTM internal instruction register; and 11 indicates selection of the DTM internal data register.

[0094] The data signal direction reversal bit inv indicates that the direction of the tdata data signal will be reversed;

[0095] The data synchronization bit sync is low for one cycle and only exists during DTM register read operations. This bit is used to determine the time to start reading data returned by DTM.

[0096] The data bit indicates that the data segment is fixed at 5 bits when rs is 01, and the bit width is set differently depending on the register when rs is 11 or 00.

[0097] The parity bit 'par' is the odd parity bit for the 'data' data segment.

[0098] Specifically, a state machine was designed in the Debug Transmission Module (DTM) to control the behavior of the DTM in communicating with external logic via a two-wire JTAG interface. The state machine is as follows: Figure 6 As shown. The timing diagrams for reading and writing DTM internal registers via the two-wire JTAG interface are as follows. Figure 7 and Figure 8 As shown.

[0099] Specifically, when rs[1:0]=2'b10, a five-wire JTAG protocol instruction register capture signal is generated during the first data signal direction reversal state, a five-wire JTAG protocol instruction register shift signal is generated during data transmission, and a five-wire JTAG protocol instruction register update signal is generated during the second data signal direction reversal state. This entire process is called the instruction register stage. When rs[1:0]=2'b11 or rs[1:0]=2'b00, a five-wire JTAG protocol data register capture signal is generated during the first data signal direction reversal state, a five-wire JTAG protocol data register shift signal is generated during data transmission, and a five-wire JTAG protocol data register update signal is generated during the second data signal direction reversal state. This entire process is called the data register stage. The instruction register stage selects registers in the DTM, and the data register stage transmits the read and write data.

[0100] When communicating with the DM via the two-wire JTAG interface, the DMI register within the DTM is selected through the instruction register stage. The address of the DM register to be accessed, the data, and the operation type are written to the DMI through the data register stage. Operation types include read and write operations; for write operations, data must also be written. For example, when writing to a DM register via the two-wire JTAG interface, it involves two steps: First, selecting the DMI register: writing 0 to the rw bit, 2'b01 to the rs bit, and 5'h11 to the data bit; second, writing to the DMI register: writing 0 to the rw bit, 2'b11 to the rs bit, and the data bit format is {address, data, op}, where address is the address of the DM register in the SoC (System on Chip), data is the data to be written, and op is the value of the write operation, 2'b10.

[0101] For example, when reading the DM register via the two-wire JTAG interface, the process involves four steps: First, select the DMI register: write 0 to the rw bit, 2'b01 to the rs bit, and 5'h11 to the data bit. Second, write to the DMI register: write 0 to the rw bit, 2'b00 to the rs bit, and the data bit format is {address, data, op}, where address is the address of the DM register in the SoC, data can be any value (the DTM internal logic will ignore this data value and will not transmit it to the DM register), and op is the read operation value 2'b01. The value of the DM register is then read from the DM and stored in the data register. Third, repeat the first step. Fourth, read the value of the DMI register: write 1 to the rw bit, 2'b11 to the rs bit, and the data bit format is {address, data, op}, where address is the address of the DM register in the SoC, data is the output value and equal to the DM register value, and op is the read operation value 2'b01.

[0102] The JTAG-APB protocol conversion submodule within the Debug Transmission Module (DTM) is the core module for generating APB bus signals. This module receives signals from the APB bus and JTAG input signals, and generates corresponding APB bus signals. Its main function is to convert between JTAG and APB signals. Figure 9 The main input and output signals of the JTAG-APB protocol conversion submodule are shown.

[0103] The JTAG-APB protocol conversion submodule contains the data, address, and control signals (wdata, address, wr_flg, wr_vld) required by the APB slave device input from the JTAG side, and generates APB bus signals (psel, penable, pwrite, paddr, pwdata) based on signals (pclk, preset_b, preply, prdata, psilverr) fed back from the APB slave device and the end-side processor on the APB bus side. This module also generates the internal JTAG-side signals rdata and apb_wr_ready based on the preply, prdata, and penable signals.

[0104] Figure 9 The diagram shows the block diagram of the JTAG-APB protocol conversion submodule. Its core function is to enable JTAG debugging tools to access and control peripherals on the APB (Advanced Peripheral Bus) through the standard JTAG interface.

[0105] in, Figure 9The JTAG-APB protocol conversion submodule mainly includes:

[0106] APB state machine: includes the idle state IDLE, the ready state SETUP, and the transmission state ACCESS. It receives the trans_req signal and the preready signal from the APB interface side, drives the state machine changes, and generates the APB control signals penable and psel signals required by the APB protocol timing.

[0107] Register configuration and signal synchronization logic block: Synchronizes the input signals wdata, address, wr_flg, and wr_vld on the JTAG side across clock domains, generates the source signal of the control signal trans_req for the APB state machine, generates the output signals pwrite, paddr, and pwdata on the APB interface side, and receives the preready and prdata signals from the APB interface side and the penable signal from the APB state machine to control the generation of the rdata and wr_ready signals on the JTAG side.

[0108] Its core workflow is as follows: When an APB transmission operation is triggered, the JTAG-APB protocol conversion submodule, acting as the APB master, sends valid information containing the specified address to the APB slave interface and receives 32-bit data from the APB slave. When wr_vld is 1'b1 and wr_flg is 2'b01, and the address is a valid address, the wr_vld and wr_flg signals, after cross-clock domain synchronization, generate the APB state machine transition signal trans_req, causing the APB state machine to transition from the idle state (IDLE) to the ready state (SETUP). trans_req is maintained at 0 for one APB clock cycle, after which the APB state machine transitions to the transmission state (ACCESS), where it waits for the prepared signal from the APB slave. The `psel` signal is set to 1 when `trans_req` is 1'b1 and in the `IDLE` state, and to 0 when receiving the `preready` signal, `trans_req` is 1'b0, and in the `ACCESS` state. The `penable` signal is set to 1 in the `SETUP` state, and to 0 when receiving the `preready` signal and in the `ACCESS` state. When `trans_req` is 1'b1, the `pwrite` signal is set to 1 or 0 depending on the value of `wr_flg` after cross-clock domain synchronization, the `paddr` signal value is equal to the value of `address` after cross-clock domain synchronization, and the `pwdata` signal value is equal to the value of `wdata` after cross-clock domain synchronization. When `wr_flg` is 2'b10, an APB write operation occurs; when `wr_flg` is 2'b01, an APB read operation occurs. When the JTAG-APB protocol conversion submodule receives the `preready` signal from the APB slave, the current APB transmission operation ends normally. Simultaneously, the preprey signal and the penable signal are ANDed, and then output to the JTAG side after cross-clock domain synchronization and together with the prdata signal.

[0109] Corresponding to the edge processor debugging system provided above, the present invention also provides an edge processor debugging method, which includes the following:

[0110] Step 1: Set the SEL signal value of the JTAG link selection of the debugging system to 2'b01, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the high-speed peripheral component interconnection unit, connect it to the high-speed peripheral component interconnection unit, and the other two JTAG interfaces have no data transmission. The external debugger can directly debug the high-speed peripheral component interconnection unit.

[0111] Step 2: Set the SEL signal value of the JTAG link selection of the debugging system to 2'b10, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the vector processing extension unit. The other two JTAG interfaces do not transmit data, and the external debugger can directly debug with the vector processing extension unit.

[0112] Step 3: When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM. The debugging transmission module DTM converts the JTAG signal into an APB signal and realizes the debugging of multiple cores of the edge processor through the APB bus.

[0113] Understandably, by selecting whether the JTAG interface is directly connected to the vector processing extension unit and the high-speed peripheral component interconnect unit through the SEL signal value of the debugging system, or connected to the core in the edge processor through the debugging transmission module DTM and the APB bus, the present invention can achieve debugging of multiple cores in the edge processor through a variety of different debugging links.

[0114] When the JTAG link selection SEL value of the debugging system is set to 2'b00, the JTAG interface can be configured via the internal two-wire / five-wire JTAG mode selection pad_jtag2_sel signal. Setting the pad_jtag2_sel value to 1'b1 activates a two-wire JTAG interface. The DTM module converts the JTAG signal to an APB signal and connects it to the APB bus. No data transmission occurs on the JTAG interfaces of the high-speed peripheral interconnect unit and the vector processing expansion unit; only the DTM's JTAG interface transmits data in two-wire JTAG mode. In this configuration, different modules, such as the microcontroller unit, central processing unit, and neural network processing unit, can be debugged via the two-wire JTAG interface by simply inputting the address of the register of the module to be debugged. Furthermore, when debugging other modules in this system, simply connecting the module to the bus allows for register read / write access, providing high scalability.

[0115] Keeping the JTAG link selection SEL value unchanged, and setting the pad_jtag2_sel value to 1'b0, the JTAG interface is now a five-wire JTAG interface. The DTM module converts the JTAG signal to an APB signal and connects it to the APB bus. There is no data transmission on the JTAG interfaces of the high-speed peripheral component interconnect unit and the vector processing expansion unit; only the DTM's JTAG interface transmits data in five-wire JTAG mode. Except for the two-wire / five-wire JTAG status control submodule and the input / output signals on the JTAG side, the signal variations and design of the other modules are the same as in two-wire JTAG.

[0116] Based on the edge processor debugging system provided by this invention, the JTAG interface can be directly connected to the cores of the edge processor, enhancing debugging independence. It can also be converted into an APB interface via the Debug Transmission Module (DTM) and connected to the APB bus. This allows for debugging of multiple cores in the edge processor based on different addresses, offering strong scalability and high versatility. Furthermore, the DTM allows selection between a two-wire and a five-wire JTAG interface, accommodating the needs of the edge processor in different application scenarios and saving pin resources.

[0117] The present invention provides a terminal-side processor debugging system and debugging method, which have the following advantages:

[0118] 1. By using the input / output function selector, different JTAG links can be selected according to the SEL value of the JTAG link. It can be directly connected to the internal sub-modules of the edge processor or connected to the APB bus through the debug transmission module DTM conversion. This enhances the independence of debugging and allows debugging of multiple cores according to different addresses. It has strong scalability and high versatility.

[0119] 2. By debugging the transmission module DTM, different JTAG modes are selected based on the pad_jtag2_sel signal value according to the two-wire / five-wire JTAG mode. Both standard five-wire and two-wire JTAG interfaces are available, converting JTAG signals into APB signals for interaction with different cores. This caters to the needs of the edge processor in different application scenarios, saves pin resources, and provides another debugging option. Before packaging, the edge processor is packaged using a two-wire JTAG interface when pin resources are limited, and a five-wire JTAG interface when pin resources are sufficient, depending on the specific scenario.

[0120] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0121] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0122] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0123] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0124] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0125] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0126] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A terminal-side processor debugging system, characterized in that, The device includes a JTAG interface, an input / output function selector, a debug transfer module (DTM), an advanced peripheral bus (APB), and multiple cores in an edge processor. These multiple cores include at least a microcontroller unit, a central processing unit, a neural network processing unit, a vector processing extension unit, and a high-speed peripheral component interconnect unit. The JTAG interface is connected to the input / output function selector, which is connected to the DTM, the vector processing extension unit, and the high-speed peripheral component interconnect unit, respectively. The DTM is connected to the APB, and the APB connects to the multiple cores of the edge processor. The input / output function selector includes a JTAG interface multiplexing function. The selector uses a JTAG link selection (SEL) signal to select whether the JTAG interface is connected to the DTM, the vector processing extension unit, or the high-speed peripheral component interconnect unit, allowing debugging of different cores in the edge processor through different links. The debug transmission module DTM selects whether to use a five-wire JTAG interface or a two-wire JTAG interface to debug the end-side processor via a JTAG mode selection signal; When the JTAG link selection SEL signal value of the debugging system is set to 2'b00, the JTAG interface is configured through the two-wire / five-wire JTAG mode selection signal of the debugging transmission module DTM. If the two-wire / five-wire JTAG mode selection signal value is set to 1'b1, the JTAG interface is a two-wire JTAG interface. The debugging transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. The debugging of multiple cores in the end-side processor is achieved through the APB. Keeping the JTAG link selection SEL signal value of the debugging system unchanged, if the dual-wire / five-wire JTAG mode selection value is set to 1'b0, the JTAG interface is a five-wire JTAG interface. The debugging transmission module DTM converts the JTAG signal into an Advanced Peripheral Bus (APB) signal and connects it to the APB. Debugging of multiple cores in the end-side processor is achieved through the APB.

2. The edge processor debugging system according to claim 1, characterized in that, The input / output function selector selects the JTAG interface via the JTAG link selection SEL signal to connect to the debug transmission module DTM, the vector processing extension unit, or the high-speed peripheral component interconnection unit, respectively, so as to enable debugging of different cores in the edge processor through different links, including: When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b01, the JTAG interface is a five-wire JTAG interface, and the JTAG interface is switched to the JTAG interface of the high-speed peripheral component interconnection unit, and connected to the high-speed peripheral component interconnection unit to realize the debugging of the high-speed peripheral component interconnection unit. When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b10, the JTAG interface is a five-wire JTAG interface, and the JTAG interface is switched to the JTAG interface of the vector processing extension unit and connected to the vector processing extension unit to realize the debugging of the vector processing extension unit. When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM. The debugging transmission module DTM converts the JTAG signal into the Advanced Peripheral Bus (APB) signal, and the debugging of multiple cores of the end-side processor is realized through the APB.

3. The edge processor debugging system according to claim 1, characterized in that, The input / output function selector includes multiple input / output units and a multiplexer. The five signals of the JTAG interface and the JTAG link selection SEL signal are all connected to the multiplexer through the corresponding input / output units. The five signals of the JTAG interface include test clock TCLK, test reset TRST, test data input TDI, test mode selection TMS, and test data output TDO. The input / output direction of the input signals is controlled by controlling the input enable IE signal and the output enable OEN signal of each input / output unit. Among them, the test clock TCLK, test reset TRST, test data input TDI, and JTAG link selection SEL signal are set as input signals, and the input / output direction of the test mode selection TMS and test data output TDO signals is determined according to the specific situation.

4. The edge processor debugging system according to claim 1, characterized in that, One side of the debug transmission module DTM contains JTAG signals, including pad_tclk, pad_trst_b, pad_tms, pad_tdi, pad_tdo, pad_jtag2_sel, pad_tdo_oe, pad_tms_o, and pad_tms_oe; the other side contains an Advanced Peripheral Bus (APB) interface, which is connected to the Advanced Peripheral Bus (APB). The debug transmission module DTM includes a serial-to-parallel data conversion submodule, a two-wire / five-wire JTAG status control submodule, an instruction data processing submodule, an input / output control submodule, and a JTAG-APB protocol conversion submodule. Among them, pad_jtag2_sel is the two-wire / five-wire JTAG mode selection signal, pad_tclk is the JTAG clock signal, pad_trst_b is the JTAG reset signal, pad_tdi is the JTAG serial input port, pad_tdo is the JTAG serial data output port, pad_tms is the JTAG test mode selection signal, pad_tms_o is the two-wire JTAG serial data output signal, and pad_tms_oe is the pad_tms_o output enable signal; The input / output control submodule is used to control the input and output of the JTAG interface side in the debug transmission module DTM, and selects the pad_tms signal or the pad_tdi signal as the input of serial data according to the pad_jtag2_sel signal value. The serial-to-parallel data conversion submodule is used to store the input serial data bit by bit into the instruction or data register, or to serially output the parallel read data from the Advanced Peripheral Bus (APB) via tdo. The dual-line / five-line JTAG status control submodule is the JTAG test access port status control module. It is used to select the dual-line JTAG interface or the five-line JTAG interface test access port control logic according to the pad_jtag2_sel signal value to complete the timing control of the serial-to-parallel conversion process. The instruction data processing submodule is used to filter the parallel data information after the serial-to-parallel data conversion submodule has completed the conversion based on the control signals generated by the two-wire / five-wire JTAG status control submodule, receive the request and response with the Advanced Peripheral Bus (APB) interface, generate the address, data and control signals required by the JTAG-APB protocol conversion submodule, and receive data from the JTAG-APB protocol conversion submodule. The JTAG-APB protocol conversion submodule is used to organize the address, write data and control flags extracted from the two-wire / five-wire JTAG status control submodule into the corresponding Advanced Peripheral Bus (APB) timing sequence, and at the same time, return the APB transmission acknowledgment signal and read data to the instruction data processing submodule.

5. The edge processor debugging system according to claim 1, characterized in that, The debug transmission module (DTM) defines a two-wire JTAG interface that can coexist with the five-wire JTAG interface. The dual-wire JTAG interface defines two interface signals, including a clock TCK signal and a data TDATA signal. The data TDATA signal is a bidirectional signal. The TCK signal and the data TDATA signal in the dual-wire JTAG interface reuse the test clock TCLK signal and the test mode selection TMS signal of the five-wire JTAG interface, respectively. In the communication protocol of the two-wire JTAG interface, data is sampled on the rising edge of the clock, and the sampled data is transmitted in the form of data packets. The format of a data packet includes: start bit, read / write indicator bit rw, register group select bit rs[1:0], data signal direction inversion bit inv, data synchronization bit sync, data bit data, and data parity bit par. The start bit is a low level on the TDATA signal line for one cycle. A high read / write indicator bit rw indicates a read operation from the DTM register, while a low read operation indicates a write operation to the debug transmission module's DTM register. rs[1:0] indicates register group selection, where 00 indicates selection of the external debug register of the debug transfer module (DTM); 01 indicates selection of the internal instruction register of the debug transfer module (DTM); and 11 indicates selection of the internal data register of the debug transfer module (DTM). The data signal direction reversal bit inv indicates that the direction of the tdata data signal will be reversed; The data synchronization bit sync is low for one cycle and only exists during DTM register read operations. This bit is used to determine the time to start reading data returned by DTM. The data bit indicates that the data segment is fixed at 5 bits when rs is 01, and the bit width is set differently depending on the register when rs is 11 or 00. The parity bit 'par' is the odd parity bit for the 'data' data segment.

6. The edge processor debugging system according to claim 5, characterized in that, During the process of reading and writing the internal registers of the debugging transmission module DTM through the two-wire JTAG interface, when rs[1:0]=2'b10, in the first data signal direction reversal state, the instruction register capture signal in the five-wire JTAG protocol is generated; in the data transmission state, the instruction register shift signal in the five-wire JTAG protocol is generated; and in the second data signal direction reversal state, the instruction register update signal in the five-wire JTAG protocol is generated. The whole process is called the instruction register stage. When rs[1:0]=2'b11 or rs[1:0]=2'b00, in the first data signal direction reversal state, the data register capture signal in the five-wire JTAG protocol is generated; in the data transmission state, the data register shift signal in the five-wire JTAG protocol is generated; and in the second data signal direction reversal state, the data register update signal in the five-wire JTAG protocol is generated. The whole process is called the data register stage. Specifically, during the instruction register stage, the debug module interface (DMI) register within the debug transfer module (DTM) is selected; during the data register stage, the address field and operation type are written to the address field and operation type field of the debug module interface (DMI) register, wherein the operation type is a read operation or a write operation. Specifically, writing an address to the debug module interface DMI register during the data register phase includes: When a debug module DM exists in the core of the edge processor, write the edge processor's on-chip offset address into the debug module interface DMI register. When the debug module DM is not present in the core of the edge processor, write the edge processor's on-chip offset address in the register of the core to the debug module interface DMI register; During the data register phase, data is also read from or written to the data segment of the debug module interface DMI register, including: When the operation type is a write operation, data also needs to be written to the data segment of the DMI register of the debug module interface; when the operation type is a read operation, data is read out from the data segment of the DMI register of the debug module interface. The debug transmission module DTM transmits debug control commands and register read / write commands to the core of the end-side processor that has a debug module DM through the debug module interface DMI, or transmits register read / write commands to the core of the end-side processor that does not have a debug module DM. The transmission of debug control commands or register read / write commands is achieved by converting JTAG signals into Advanced Peripheral Bus (APB) signals.

7. A method for debugging a terminal-side processor, applied to the terminal-side processor debugging system of claim 1, characterized in that, The debugging method includes: Step 1: Set the SEL signal value of the JTAG link selection of the debugging system to 2'b01, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the high-speed peripheral component interconnection unit, connect it to the high-speed peripheral component interconnection unit, and the other two JTAG interfaces have no data transmission. The external debugger can directly debug the high-speed peripheral component interconnection unit. Step 2: Set the SEL signal value of the JTAG link selection of the debugging system to 2'b10, the JTAG interface to a five-wire JTAG interface, and switch the JTAG interface to the JTAG interface of the vector processing extension unit. The other two JTAG interfaces do not transmit data, and the external debugger can directly debug with the vector processing extension unit. Step 3: When the SEL signal value of the JTAG link selection of the debugging system is set to 2'b00, the JTAG interface is switched to the JTAG interface of the debugging transmission module DTM. The JTAG interface is connected to the debugging transmission module DTM. The debugging transmission module DTM converts the JTAG signal into the Advanced Peripheral Bus (APB) signal, and the debugging of multiple cores in the edge processor is realized through the APB.

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