Performance evaluation method of quantum computer, electronic device, chip, and storage medium

Abstract

This application provides a method, electronic device, chip, and storage medium for evaluating the performance of a quantum computer. The method includes: obtaining the total number of qubits of the quantum computer to be evaluated; constructing multiple sets of quantum circuits of different scales based on different fundamental quantum algorithms; for each quantum algorithm, increasing the circuit width from a preset minimum value to the total number of qubits, and increasing the circuit depth according to a predetermined mathematical relationship as the circuit width increases; inputting each quantum circuit into at least one noise-free quantum simulator for computation to obtain an ideal result probability distribution; running each generated quantum circuit a predetermined number of measurements to obtain an actual result probability distribution; calculating the similarity between the actual result probability distribution and the ideal result probability distribution as the fidelity of the circuit running on the quantum computer, and generating a performance heatmap.

Description

Technical Field

[0001] This application relates to the field of quantum computing technology, and in particular to a method for evaluating the performance of a quantum computer, an electronic device, a chip, and a storage medium. Background Technology

[0002] Quantum computers are a new type of computing system based on the principles of quantum coherent superposition and entanglement. Unlike classical computers, which use classical bits (which can only be in a 0 or 1 state), quantum computers use qubits to represent information. Qubits can be in a superposition of 0 and 1 simultaneously. Therefore, for specific problems, such as prime factorization, optimization problems, and simulating quantum systems, quantum computers can achieve parallel computing, significantly improving computing speed.

[0003] Depending on the physical system used to realize qubits, quantum computers currently employ various technological approaches, including superconductivity, ion traps, neutral atoms, photonics, and silicon spin. These different approaches result in different qubit implementation methods and varying development progress. Currently, quantum computers have between tens and hundreds of qubits, and the operable qubits are still unstable with significant noise; therefore, they are generally still in the noisy medium-scale quantum (NISQ) stage. At this stage, quantum computers can only provide higher computing power than classical computers in specific fields and cannot yet solve large-scale practical application problems. Therefore, objective performance evaluation and comparison of quantum computers using different technological approaches in the NISQ stage has become a hot research topic in the industry.

[0004] Currently, the commonly used quantum benchmarking methods mainly include random benchmarking (RB) and quantum volume (QV). However, RB testing is limited to Clifford gate sets and cannot characterize the performance of general-purpose gate sets in quantum computing; QV testing can only verify the ability of a quantum computer to run square circuits (i.e., the circuit width is equal to the circuit depth), and cannot fully reflect the performance of a quantum computer in solving practical algorithmic problems. Summary of the Invention

[0005] This application provides a method for evaluating the performance of a quantum computer, as well as an electronic device, a chip, a storage medium, and a program product. By selecting various fundamental algorithms in the quantum field to generate quantum circuits of different scales, and combining them with noiseless simulator comparison and heatmap visualization, a comprehensive and intuitive evaluation of the quantum computer's performance can be achieved.

[0006] The technical solution of this application embodiment is implemented as follows: This application provides a method for evaluating the performance of a quantum computer, including: The total number of qubits of the quantum computer to be evaluated is obtained, and multiple sets of quantum circuits of different scales with different basic quantum algorithms are constructed. The circuit scale is defined by the circuit width and the circuit depth, where the circuit width is the number of qubits in the circuit and the circuit depth is the number of layers in which the circuit performs gate operations. For each quantum algorithm, the range of the circuit width is increased from a preset minimum value to the total number of qubits; the circuit depth is increased according to a predetermined mathematical relationship as the circuit width increases, based on the inherent circuit structure of the algorithm. Each quantum circuit is input into at least one noise-free quantum simulator for computation to obtain an ideal result probability distribution; each generated quantum circuit is then run on the quantum computer to be evaluated for a predetermined number of measurements to obtain the corresponding actual result probability distribution. For each quantum circuit, the similarity between its actual result probability distribution and its ideal result probability distribution is calculated, which serves as the fidelity for the circuit to run on the quantum computer. Based on all the obtained fidelity, a performance heatmap is generated; wherein the horizontal axis of the heatmap represents the circuit width and the vertical axis represents the circuit depth, and each coordinate point corresponds to a quantum circuit with a specific width and depth.

[0007] As one implementation method, the construction of multiple sets of quantum circuits of different scales based on different quantum algorithms includes: For the Bernstein-Vazirani algorithm, if the given circuit width is n, then the corresponding Bernstein-Vazirani quantum circuit is constructed; wherein the depth of the circuit is n+1. For the quantum Fourier transform algorithm, if the given circuit width is n, a forward quantum Fourier transform circuit and a subsequent inverse quantum Fourier transform circuit are constructed to form a complete test circuit; wherein, the depth of the test circuit is O(n²). For a given circuit width of n, construct a Grover search iteration circuit containing an Oracle operator and a Diffuser operator; wherein the quantum circuit depth of the Oracle operator and the Diffuser operator are both preset values, and the total depth of the test circuit is O(√(2^n)).

[0008] As one implementation method, after obtaining the ideal probability distribution, the method further includes: Based on the actual result probability distribution P and the ideal result probability distribution Q, the fidelity F between them is calculated using the following formula: ; in, and These represent the probabilities of probability distributions P and Q in the i-th measurement ground state, respectively. The fidelity F is calculated using the following formula: F = 1 - ².

[0009] As one implementation, generating a performance heatmap based on all obtained fidelity includes: The fidelity values ​​calculated by combining all different circuit widths and depths are mapped to a two-dimensional coordinate system; the X-axis of the two-dimensional coordinate system is the circuit width, and the Y-axis is the circuit depth. The color gradient is used to visualize the fidelity value corresponding to each coordinate point. The higher the fidelity, the darker the corresponding color or the closer it is to the preset high-performance hue.

[0010] As one implementation, before inputting each quantum circuit into at least one noise-free quantum simulator for computation, the method further includes: The constructed quantum circuits are converted into circuit description files that conform to the OpenQASM specification of the open quantum assembly language to ensure compatibility with different quantum computing platforms.

[0011] As one implementation, the method further includes: For the Grover search iterative circuit, the number of Grover iterations k is set to ensure that the total circuit depth D can cover the preset target depth range, thereby forming a dense and comprehensive (W, D) test grid together with other algorithms, where W is the circuit width.

[0012] As one implementation, the method further includes: Based on the nearby measured fidelity F values, an interpolation algorithm is used to interpolate and calculate the fidelity F values ​​of (W,D) coordinate points in the circuit that have not been directly tested, in order to generate a smooth and continuous fidelity distribution heatmap.

[0013] The electronic device provided in this application includes a processor and a memory. The memory is used to store computer programs, and the processor is used to call and run the computer programs stored in the memory to execute the above-described quantum computer performance evaluation method.

[0014] The chip provided in this application includes a processor for calling and running a computer program from a memory, so that a device equipped with the chip performs the above-described quantum computer performance evaluation method.

[0015] The computer-readable storage medium provided in this application embodiment is used to store a computer program that causes a computer to execute the above-described quantum computer performance evaluation method.

[0016] The computer program product provided in this application includes computer program instructions that cause a computer to execute the above-described quantum computer performance evaluation method.

[0017] The embodiments of this application have the following beneficial effects: They employ multiple fundamental quantum algorithms, such as Bernstein-Vazirani, quantum Fourier transform, and Grover search. As the number of qubits increases, the rate of change in circuit depth varies, covering performance testing scenarios under different combinations of circuit width and depth, thus comprehensively evaluating the performance of quantum computers on circuits of various scales. Ideal results are obtained through a noiseless simulator as a benchmark, avoiding the complex statistical classification and fitting processes of existing technologies. The fidelity is calculated using the Hellinger distance formula, making the calculation process simple and efficient. The results are visualized through heatmaps, making them intuitive and easy to read. The constructed quantum circuit is converted to Open Quantum Assembly Language (OpenQASM) 2.0 format, which is supported by mainstream quantum computing platforms, solving compatibility issues between different types of quantum computers and facilitating cross-platform performance comparison. Running the same circuit on both a real quantum machine and a noiseless simulator, and calculating fidelity by comparing probability distributions, eliminates calculation errors caused by circuit differences, resulting in objective and accurate results. The fidelity data is displayed in the form of a heatmap, with the horizontal axis representing circuit width and the vertical axis representing circuit depth. The color intensity indicates the fidelity value, allowing for a direct observation of the performance distribution of quantum computers at different circuit scales, facilitating performance comparisons between different quantum computers. The technical solution of this application can be directly applied to the performance evaluation of quantum computers using various technical routes in the Noisy Intermediate-Scale Quantum (NISQ) stage, providing important reference for the research, optimization, and selection of quantum computers. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the performance evaluation method for a quantum computer provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the implementation process of the quantum computer performance evaluation method provided in this application embodiment; Figure 3 This is a schematic diagram of the Bernstein-Vazirani quantum circuit structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of the QFT quantum circuit structure provided in the embodiments of this application; Figure 5This is a schematic diagram of the Grover search quantum circuit structure provided in an embodiment of this application; Figure 6 This is a heatmap generated based on random data, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the composition structure of the quantum computer performance evaluation device provided in the embodiments of this application; Figure 8 This is a schematic structural diagram of an electronic device provided in an embodiment of this application; Figure 9 This is a schematic structural diagram of the chip according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.

[0020] Figure 1 This is a flowchart illustrating the performance evaluation method for quantum computers provided in this application embodiment, as shown below. Figure 1 As shown, the performance evaluation method for quantum computers in this application specifically includes the following processing steps: Step 101: Obtain the total number of qubits of the quantum computer to be evaluated, and construct multiple sets of quantum circuits of different scales based on different fundamental quantum algorithms.

[0021] In this embodiment, the maximum number of usable qubits that can be fully connected or effectively connected via a SWAP network is obtained by consulting the official documentation or API interface of the NISQ quantum computer under test, denoted as max_qubits. This value is the upper limit of the scale of the subsequent test circuit construction.

[0022] The size of a circuit is defined by its width and depth. The width is the number of qubits in the circuit, and the depth is the number of layers in which the circuit performs gate operations.

[0023] For the Bernstein-Vazirani algorithm, if the given circuit width is n, then the corresponding Bernstein-Vazirani quantum circuit is constructed; where the circuit depth is n+1. For the quantum Fourier transform algorithm, if the given circuit width is n, construct a forward quantum Fourier transform circuit and a subsequent inverse quantum Fourier transform circuit to form a complete test circuit; where the depth of the test circuit is O(n²). For a given circuit width of n, construct a Grover search iterative circuit containing Oracle and Diffuser operators; where the quantum circuit depths of the Oracle and Diffuser operators are preset values, and the total depth of the test circuit is O(√(2^n)).

[0024] As an example, the Qiskit open-source software development kit (SDK) can be used to build Bernstein-Vazirani circuits. Cirq can also be used with the open-source SDK; both software packages have comprehensive quantum circuit editing, generation, and export capabilities, meeting the needs of building quantum circuits of different scales. For a circuit width n (i.e., the number of qubits), the circuit structure is as follows: Layer 1: Apply Hadamard gates to all qubits; Layers 2 to n: Apply CNOT gates (control qubits are auxiliary qubits, target qubits are the corresponding data qubits) or pass them directly to each bit of the secret string s; Layer n+1: Apply Hadamard gates again; finally, measure the data qubits. The circuit depth is n+1. For example, when n=3, the circuit depth is 4. This embodiment can generate 8 Bernstein-Vazirani circuits for n=3, 4, 5, ..., 10.

[0025] QFT algorithm circuit generation: Construct a test circuit by cascading forward and reverse QFT circuits. The forward QFT circuit includes: applying a Hadamard gate for each qubit, applying a controlled rotation gate (Rk gate) according to the qubit position, and finally performing a qubit swap (SWAP gate).

[0026] The inverse QFT circuit is the reverse implementation of the forward QFT. The depth of a complete test circuit is approximately n(n+1) / 2. For example, when n=3, the depth is approximately 6. As an example, eight QFT test circuits can be generated for n=3, 4, 5, ..., 10.

[0027] The Grover search test circuit is constructed, consisting of three parts: initial state preparation, k Grover iterations, and measurement. Initial state preparation involves applying a Hadamard gate of depth 1 to all qubits. Grover iterations include both an Oracle operator and a Diffuser operator in each iteration. For example, the Oracle operator depth d_Oracle = 3, and the Diffuser operator depth d_Diffuser = 7. The optimal number of iterations k is calculated using the formula k = floor(π / 4 × √(2^n)). For instance, when n=3, k=2; when n=4, k=3; when n=5, k=4; when n=6, k=5; when n=7, k=7; when n=8, k=10; when n=9, k=14; and when n=10, k=20.

[0028] The measurement operation depth is 1, and the total circuit depth D_total = k × (3 + 7) + 1 + 1 = 10k + 2. This can generate 8 Grover test circuits with n = 3, 4, 5, ..., 10.

[0029] Step 102: For each quantum algorithm, the circuit width ranges from a preset minimum value to the total number of qubits, and the circuit depth increases according to a predetermined mathematical relationship as the circuit width increases, based on the inherent circuit structure of the algorithm.

[0030] In this embodiment, all the multiple quantum circuits generated for each algorithm are converted into text files in OpenQASM 2.0 format for running on different platforms.

[0031] Step 103: Input each quantum circuit into at least one noise-free quantum simulator for computation to obtain the ideal result probability distribution; run each generated quantum circuit on the quantum computer to be evaluated for a predetermined number of measurements to obtain the corresponding actual result probability distribution.

[0032] In this embodiment, each OpenQASM file is input into a noise-free quantum simulator (such as Qiskit's Aer simulator, set to noise-free mode) and run. Each circuit runs for 8192 times (shots), and the output probability distribution is recorded as the ideal result Q.

[0033] The same OpenQASM file was submitted to the superconducting quantum computer to be tested and run. Each circuit ran the quantum simulator the same number of times, such as 8192 times, and the probability distribution of the output was recorded as the actual result P.

[0034] For the Grover search iterative circuit, the number of Grover iterations k is set to ensure that the total circuit depth D can cover the preset target depth range, thereby forming a dense and comprehensive (W, D) test grid together with other algorithms, where W is the circuit width.

[0035] Step 104: For each quantum circuit, calculate the similarity between its actual result probability distribution and its ideal result probability distribution, as the fidelity of the circuit running on the quantum computer.

[0036] In this embodiment of the application, the fidelity F between the actual result probability distribution P and the ideal result probability distribution Q is calculated using the following formula: ; in, and These represent the probabilities of probability distributions P and Q in the i-th measurement ground state, respectively; the fidelity F is calculated using the following formula: F = 1 - ².

[0037] Taking the Bernstein-Vazirani circuit with n=3 as an example, assuming that in the ideal result Q |000 The probability is 0.125, |001 The actual result P is 0.125, ..., where |000 The probability is 0.110, |001 The values ​​are 0.120, ..., which are then substituted into the formula to calculate the fidelity value. This embodiment calculates 24 fidelity data points, each corresponding to a specific combination of (algorithm, circuit width, circuit depth). Since different algorithms have different circuit depths, the same width may correspond to multiple depth values.

[0038] In this embodiment of the application, a quantum circuit is run on the NISQ quantum computer under test, and no less than 1,000 sampling measurements are performed.

[0039] Step 105: Generate a performance heatmap based on all the obtained fidelity values.

[0040] In this embodiment of the application, the fidelity values ​​calculated by combining all different circuit widths and depths are mapped to a two-dimensional coordinate system; the X-axis of the two-dimensional coordinate system is the circuit width, and the Y-axis is the circuit depth; a color gradient is used to visualize and render the fidelity value corresponding to each coordinate point, wherein the higher the fidelity, the darker the corresponding color or the more it is biased towards the preset high-performance hue.

[0041] The horizontal axis of the heatmap represents the circuit width, and the vertical axis represents the circuit depth. Each coordinate point corresponds to a quantum circuit with a specific width and depth.

[0042] The calculated fidelity data is mapped onto a two-dimensional coordinate system, with the horizontal axis representing the circuit width (3-10) and the vertical axis representing the circuit depth, determined according to the actual circuit depth values, such as Bernstein-Vazirani depth 4-11, QFT depth 6-55, and Grover depth 22-202. Color mapping is used, with fidelity values ​​from 0 to 1 corresponding to a gradient from blue to red; for example, 0 is dark blue, 0.5 is white, and 1 is dark red. The color of each coordinate point (width, depth) represents the fidelity of the corresponding circuit. For coordinate points without data (e.g., certain depth combinations do not exist), an interpolation algorithm is used to calculate the fidelity F value of the (W,D) coordinate points in the circuit that were not directly tested, based on the neighboring measured fidelity F values, to generate a smooth and continuous fidelity distribution heatmap. Alternatively, as an implementation method, coordinate points without data can be left blank.

[0043] The following specific examples further illustrate the essence of the technical solutions in the embodiments of this application.

[0044] Figure 2 This is a schematic diagram illustrating the implementation flow of the quantum computer performance evaluation method provided in this application embodiment, as shown below. Figure 2 As shown, the technical solution of this application uses at least three algorithms, such as Bernstein-Vazirani, Quantum Fourier Transform, and Grover search, for performance testing to generate quantum circuits of different scales. The fidelity is obtained by comparing the calculation results of the corresponding algorithms running on the quantum computer with the calculation results of the noise-free simulator. Finally, the fidelity data is processed by heatmap to obtain the fidelity distribution of the quantum computer as the circuit width and circuit depth change, and the performance benchmark of the quantum computer is obtained. Therefore, this solution can verify the ability of the quantum computer to solve quantum algorithms of different circuit scales, and is not affected by the above solution, and is superior to the above solution.

[0045] like Figure 2 As shown, the specific implementation method of the quantum computer performance evaluation method in this application embodiment is as follows: The quantum computer is operating normally. The number of quantum computer bits is obtained according to the machine manual, etc. Bernstein-Vazirani, Quantum Fourier Transform, and Grover search algorithms were selected for performance testing. Quantum circuits of different sizes were generated based on the number of qubits. The fidelity was further obtained by running the computation results of these three algorithms on a real quantum computer and the computation results of a noise-free simulator using the Hellinger distance formula. Finally, by processing the fidelity data into a heatmap, with the horizontal axis representing the circuit width and the vertical axis representing the circuit depth, and the fidelity represented by the color intensity at a specific coordinate position, the fidelity distribution of the quantum computer as the circuit width and circuit depth change was obtained, thus providing a performance benchmark for the quantum computer.

[0046] Figure 3 This is a schematic diagram of the Bernstein-Vazirani quantum circuit structure provided in an embodiment of this application, as shown below. Figure 3 As shown, Bernstein-Vazirani circuit building modules can be implemented using open-source SDKs such as Qiskit and Cirq. A schematic diagram of a Bernstein-Vazirani quantum circuit is shown below, generating quantum circuits based on different numbers of qubits. Taking solving the Bernstein-Vazirani problem with n=3 as an example, 4 qubits are required. The following example quantum circuit is constructed with a circuit width of 4 and a circuit depth of 5. As the problem size increases, the depth and width of the generated quantum circuit also increase. When the number of qubits is n, the circuit width is n and the circuit depth is n+1, continuously increasing the circuit width until the maximum number of qubits in the quantum computer is reached. The probability distribution P of each quantum computer circuit run and the probability distribution Q of the ideal result obtained from the noise-free simulator are then compared using the following Hellinger distance formula. ,in, and Given the probability distributions P and Q on sample i, calculate the fidelity.

[0047] Figure 4 This is a schematic diagram of the QFT quantum circuit structure provided in the embodiments of this application, such as... Figure 4 As shown, the Quantum Fourier Transform is a quantum realization of the discrete Fourier transform on the amplitude of the wave function. If simultaneously... The Fourier transform is performed on each element. The classic algorithm uses the Fast Fourier Transform (FFT) algorithm, which has a time complexity of O(n log n). The time complexity of using the QFT algorithm is O(n log n). .

[0048] The input sequence is passed through a QFT circuit to obtain Fourier states. A reverse QFT circuit is then run during quantum computer operation. By comparing the input sequence with the reversed QFT state using the Hellinger distance formula, the fidelity of the quantum computer's QFT algorithm can be determined. The quantum computer's operating circuit is as follows: Figure 4 As shown, when the number of qubits is n, the width of the quantum circuit is n, and the circuit depth is n. .

[0049] Figure 5 This is a schematic diagram of the Grover search quantum circuit structure provided in an embodiment of this application, as shown below. Figure 5 As shown, Grover's search algorithm is used to search for a specified target item in an unsorted database, and its time complexity is O(log n). In comparison, Grover's algorithm has a time complexity of O(n). In Grover's algorithm, the quantum circuit depth of the oracle and diffuser is 10. Therefore, when the number of qubits is n, the quantum circuit width is n and the circuit depth is... The fidelity was obtained by using the Hellinger distance formula from the results of the quantum computer operation and the results obtained from the noise-free simulator.

[0050] By running the Bernstein-Vazirani, Quantum Fourier Transform, and Grover search algorithm quantum circuits respectively, increasing the number of qubits in the quantum circuit from 3 up to the maximum number of qubits in the quantum computer, and running the circuit at least 1000 times in a single run, the fidelity values ​​for different line widths and depths can be obtained because the circuit depth of these three algorithms changes at different rates with the number of qubits. By visualizing the fidelity values ​​using heatmaps, the performance of the quantum computer can be evaluated intuitively.

[0051] Figure 6 This is a heatmap generated based on random data, as provided in the embodiments of this application. Figure 6 As shown, based on random data simulation, the performance of this quantum computer under different circuit widths and depths can be visually observed. For example, it can be found that the fidelity is generally higher when the circuit depth is smaller, and the fidelity gradually decreases as the depth increases; at certain widths, the fidelity appears to be abnormally low, which may indicate that the qubit has poor quality or crosstalk.

[0052] Collect all (W, D, F) data points and visualize them in a two-dimensional coordinate system. The horizontal axis (X-axis) represents the circuit width W, and the vertical axis (Y-axis) represents the circuit depth D. Since the test points are discrete, to obtain a smooth and continuous performance view, algorithms such as bilinear interpolation or radial basis function (RBF) interpolation can be used to estimate the fidelity values ​​of untested areas. Finally, based on the F value corresponding to each (W, D) coordinate point, a performance heatmap is plotted using color depth, as shown below. Figure 6 As shown, dark blue represents high fidelity and red represents low fidelity. By analyzing this heatmap, users can intuitively determine the performance boundaries of the NISQ device under test. For example, it can be clearly seen at what number of qubits and circuit depths the device's fidelity will drastically drop below a certain threshold (such as 0.5). Figure 6 The performance map shown provides researchers with direct, quantitative data for selecting appropriate algorithms, developers for optimizing quantum programs, and hardware engineers for pinpointing performance bottlenecks.

[0053] Figure 7 This is a schematic diagram of the composition structure of the quantum computer performance evaluation device provided in the embodiments of this application, as shown below. Figure 7 As shown, the performance evaluation device for a quantum computer according to an embodiment of this application includes: The construction unit 70 is used to obtain the total number of qubits of the quantum computer to be evaluated and to construct multiple sets of quantum circuits of different scales with different basic quantum algorithms; wherein, the circuit scale is defined by the circuit width and the circuit depth, the circuit width being the number of qubits in the circuit and the circuit depth being the number of layers in which the circuit performs gate operations. The triggering unit 71 is used to, for each quantum algorithm, increase the range of the circuit width from a preset minimum value to the total number of qubits; and to increase the circuit depth according to a predetermined mathematical relationship as the circuit width increases, based on the inherent circuit structure of the algorithm. The computation unit 72 is used to input each quantum circuit into at least one noise-free quantum simulator for computation to obtain an ideal result probability distribution; and to run each generated quantum circuit on the quantum computer to be evaluated a predetermined number of measurements to obtain the corresponding actual result probability distribution. The computing unit 73 is used to calculate the similarity between the actual result probability distribution and the ideal result probability distribution for each quantum circuit, as the fidelity of the circuit running on the quantum computer. The generation unit 74 is used to generate a performance heatmap based on all the obtained fidelity; wherein the horizontal axis of the heatmap represents the circuit width and the vertical axis represents the circuit depth, and each coordinate point corresponds to a quantum circuit with a specific width and depth.

[0054] As one implementation, the building unit 70 is further used for: For the Bernstein-Vazirani algorithm, if the given circuit width is n, then the corresponding Bernstein-Vazirani quantum circuit is constructed; wherein the depth of the circuit is n+1. For the quantum Fourier transform algorithm, if the given circuit width is n, a forward quantum Fourier transform circuit and a subsequent inverse quantum Fourier transform circuit are constructed to form a complete test circuit; wherein, the depth of the test circuit is O(n²). For a given circuit width of n, construct a Grover search iteration circuit containing an Oracle operator and a Diffuser operator; wherein the quantum circuit depth of the Oracle operator and the Diffuser operator are both preset values, and the total depth of the test circuit is O(√(2^n)).

[0055] As one implementation, after obtaining the probability distribution of the ideal result, the calculation unit 73 is further used for: Based on the actual result probability distribution P and the ideal result probability distribution Q, the fidelity F between them is calculated using the following formula: ; in, and These represent the probabilities of probability distributions P and Q in the i-th measurement ground state, respectively. The fidelity F is calculated using the following formula: F = 1 - ².

[0056] In one implementation, the generation unit 74 is further configured to: The fidelity values ​​calculated by combining all different circuit widths and depths are mapped to a two-dimensional coordinate system; the X-axis of the two-dimensional coordinate system is the circuit width, and the Y-axis is the circuit depth. The color gradient is used to visualize the fidelity value corresponding to each coordinate point. The higher the fidelity, the darker the corresponding color or the closer it is to the preset high-performance hue.

[0057] As one implementation, the building unit 70 is also used to convert the built quantum circuit into a circuit description file conforming to the OpenQASM specification before inputting each quantum circuit into at least one noise-free quantum simulator for computation, so as to ensure compatibility with different quantum computing platforms.

[0058] As one implementation, for the Grover search iterative circuit, the number of Grover iterations k is set to ensure that the total circuit depth D can cover the preset target depth range, thereby forming a dense and comprehensive (W, D) test grid together with other algorithms, where W is the circuit width.

[0059] In one implementation, the computing unit 73 is further configured to: Based on the nearby measured fidelity F values, an interpolation algorithm is used to interpolate and calculate the fidelity F values ​​of (W,D) coordinate points in the circuit that have not been directly tested, in order to generate a smooth and continuous fidelity distribution heatmap.

[0060] In an exemplary embodiment, each processing module in the quantum computer performance evaluation device of this application embodiment can be implemented by one or more central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components.

[0061] Regarding the apparatus in the above embodiments, the specific manner in which each module and unit performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0062] Figure 8 This is a schematic structural diagram of an electronic device 800 provided in an embodiment of this application. The electronic device may be a personal computer or a server. Figure 8 The illustrated electronic device 800 includes a processor 810, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0063] Optionally, such as Figure 8 As shown, the electronic device 800 may further include a memory 820. The processor 810 can retrieve and run computer programs from the memory 820 to implement the methods described in the embodiments of this application.

[0064] The memory 820 can be a separate device independent of the processor 810, or it can be integrated into the processor 810.

[0065] Optionally, such as Figure 8 As shown, the electronic device 800 may also include a transceiver 830, which the processor 810 can control to communicate with other devices. Specifically, it can send information or data to other devices or receive information or data sent by other devices.

[0066] The transceiver 830 may include a transmitter and a receiver. The transceiver 830 may further include an antenna, and the number of antennas may be one or more.

[0067] The electronic device 800 can implement the corresponding processes of the various methods implemented in the embodiments of this application, which will not be described in detail here for the sake of brevity. That is to say, the electronic device in the embodiments of this application can be implemented as a server or as a client. For the sake of simplicity, they will not be presented separately. The main difference lies in the different methods corresponding to the programs they run, while their hardware structures are exactly the same.

[0068] Figure 9 This is a schematic structural diagram of the chip according to an embodiment of this application. Figure 9 The chip 900 shown includes a processor 910, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0069] Optionally, such as Figure 9 As shown, chip 900 may further include memory 920. Processor 910 can retrieve and run computer programs from memory 920 to implement the methods described in this embodiment.

[0070] The memory 920 can be a separate device independent of the processor 910, or it can be integrated into the processor 910.

[0071] Optionally, the chip 900 may also include an input interface 930. The processor 910 can control the input interface 930 to communicate with other devices or chips; specifically, it can acquire information or data sent by other devices or chips.

[0072] Optionally, the chip 900 may also include an output interface 940. The processor 910 can control the output interface 940 to communicate with other devices or chips, specifically, to output information or data to other devices or chips.

[0073] The chip can implement the corresponding processes of the various methods in the embodiments of this application, which will not be described in detail here for the sake of brevity.

[0074] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0075] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. The functionality of a chip can be implemented using different processing methods depending on the program running in its memory.

[0076] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0077] It should be understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM), etc. That is to say, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0078] This application also provides a computer-readable storage medium for storing a computer program. This computer program causes a computer to execute the corresponding processes implemented by the various methods of this application embodiment; for brevity, these will not be elaborated upon here.

[0079] This application also provides a computer program product, including computer program instructions. These computer program instructions cause a computer to execute the corresponding processes implemented by the various methods of this application embodiment; for brevity, they will not be described in detail here.

[0080] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method of performance evaluation of a quantum computer, characterized by, The method includes: The total number of qubits of the quantum computer to be evaluated is obtained, and multiple sets of quantum circuits of different scales with different basic quantum algorithms are constructed. The circuit scale is defined by the circuit width and the circuit depth, where the circuit width is the number of qubits in the circuit and the circuit depth is the number of layers in which the circuit performs gate operations. For each quantum algorithm, the range of the circuit width is increased from a preset minimum value to the total number of qubits, and the circuit depth is increased according to a predetermined mathematical relationship as the circuit width increases, based on the inherent circuit structure of the algorithm. Each quantum circuit is input into at least one noise-free quantum simulator for computation to obtain an ideal result probability distribution; each generated quantum circuit is then run on the quantum computer to be evaluated for a predetermined number of measurements to obtain the corresponding actual result probability distribution. For each quantum circuit, the similarity between its actual result probability distribution and its ideal result probability distribution is calculated, which serves as the fidelity for the circuit to run on the quantum computer. Based on all the obtained fidelity, a performance heatmap is generated; wherein the horizontal axis of the heatmap represents the circuit width and the vertical axis represents the circuit depth, and each coordinate point corresponds to a quantum circuit with a specific width and depth.

2. The method of claim 1, wherein, The construction of multiple sets of quantum circuits of different scales based on different fundamental quantum algorithms includes: For the Bernstein-Vazirani algorithm, if the given circuit width is n, then the corresponding Bernstein-Vazirani quantum circuit is constructed; wherein the depth of the circuit is n+1. For the quantum Fourier transform algorithm, if the given circuit width is n, a forward quantum Fourier transform circuit and a subsequent inverse quantum Fourier transform circuit are constructed to form a complete test circuit; wherein, the depth of the test circuit is O(n²). For a given circuit width of n, construct a Grover search iteration circuit containing an Oracle operator and a Diffuser operator; wherein the quantum circuit depth of the Oracle operator and the Diffuser operator are both preset values, and the total depth of the test circuit is O(√(2^n)).

3. The method according to claim 2, characterized in that, After obtaining the probability distribution of the ideal result, the method further includes: Based on the actual result probability distribution P and the ideal result probability distribution Q, the fidelity F between them is calculated using the following formula: ； in, and These represent the probabilities of probability distributions P and Q in the i-th measurement ground state, respectively. The fidelity F is calculated using the following formula: F = 1 - ².

4. The method according to claim 3, characterized in that, The generation of a performance heatmap based on all obtained fidelity values ​​includes: The fidelity values ​​calculated by combining all different circuit widths and depths are mapped to a two-dimensional coordinate system; the X-axis of the two-dimensional coordinate system is the circuit width, and the Y-axis is the circuit depth. The color gradient is used to visualize the fidelity value corresponding to each coordinate point. The higher the fidelity, the darker the corresponding color or the closer it is to the preset high-performance hue.

5. The method according to any one of claims 1 to 4, characterized in that, Before inputting each quantum circuit into at least one noise-free quantum simulator for computation, the method further includes: The constructed quantum circuits are converted into circuit description files that conform to the OpenQASM specification of the open quantum assembly language to ensure compatibility with different quantum computing platforms.

6. The method according to claim 2, characterized in that, The method further includes: For the Grover search iterative circuit, the number of Grover iterations k is set to ensure that the total circuit depth D can cover the preset target depth range, thereby forming a dense and comprehensive (W, D) test grid together with other algorithms, where W is the circuit width.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Based on the nearby measured fidelity F values, an interpolation algorithm is used to interpolate and calculate the fidelity F values ​​of (W,D) coordinate points in the circuit that have not been directly tested, in order to generate a smooth and continuous fidelity distribution heatmap.

8. An electronic device, characterized in that, include: A processor and a memory for storing a computer program, the processor for calling and running the computer program stored in the memory to perform the method as described in any one of claims 1 to 7.

9. A chip, comprising: A processor for retrieving and running a computer program from memory, causing a device on which the chip is mounted to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program that causes a computer to perform the method as described in any one of claims 1 to 7.

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