一种系统级芯片管脚分配方法、装置、电子设备及存储介质
By performing directional decomposition and intersection calculation on the module sequence based on the physical path topology in SoC physical design, a common boundary is generated, which solves the problem of traditional pin assignment relying on manual experience, realizes efficient and automated pin assignment, reduces maintenance costs and improves design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CIX TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-03-23
- Publication Date
- 2026-07-17
AI Technical Summary
In system-on-chip (SoC) physical design, traditional pin assignment relies on manual experience or local heuristic rules, resulting in low efficiency, long cycles, and inconsistent results, making it difficult to maintain consistency and reusability in large-scale designs.
By performing directional decomposition on the module sequence based on physical path topology, calculating the intersection of the allocatable regions of the module boundaries, generating common boundaries, and achieving consistent pin mapping between reused modules under physical constraints, the common boundaries of reused modules are processed using logical AND operations, and manual intervention is reduced by combining iterative allocation processes.
It improves the success rate and automation of pin assignment, reduces subsequent maintenance and ECO costs, and enhances the overall efficiency and feasibility of SoC physical design.
Smart Images
Figure CN121881966B_ABST