A locally sensitive amplifier circuit and memory

Abstract

This disclosure provides a local sensitive amplifier circuit and a memory. The control terminal of a readout transistor is connected to a local data line, and its first terminal is connected to the second terminal of a first switching transistor. The first terminal of the first switching transistor is connected to a global data line. The control terminal of a complementary readout transistor is connected to a complementary local data line, and its first terminal is connected to the second terminal of a second switching transistor. The first terminal of the second switching transistor is connected to a complementary global data line. The second terminals of the readout transistor, the complementary readout transistor, the first terminal of the first ground transistor, and the first terminal of the second ground transistor are connected. The control terminal of the first ground transistor receives a first read enable signal, and the control terminal of the second ground transistor receives a second read enable signal. The second terminals of both the first and second ground transistors are grounded. The control terminals of the first and second switching transistors receive a third read enable signal. This disclosure achieves a balance between speed and power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a local sensitive amplifier circuit and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many identical storage cells. During data retrieval, the data stored in each storage cell is read out sequentially via bit lines, local data lines, global data lines, and the data bus.

[0003] In this system, data transmitted via the local data line is amplified by a local sense amplifier (LSA) before being transmitted to the global data line. In silicon wafer testing, speed and power consumption can be balanced by adjusting the pulse width of the read enable signal or column strobe signal. However, with the increasing demands for high speed and low power consumption as chip performance improves, traditional pulse width adjustment methods face greater challenges in achieving speed and power optimization.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a local sensitivity amplifier circuit and a memory.

[0006] In a first aspect, embodiments of this disclosure provide a local sensitive amplifier circuit, including: a readout transistor, a complementary readout transistor, a first ground transistor, a second ground transistor, a first switching transistor, and a second switching transistor; The control terminal of the readout transistor is connected to the local data line, the first terminal of the readout transistor is connected to the second terminal of the first switching transistor, and the first terminal of the first switching transistor is connected to the global data line. The control terminal of the complementary readout transistor is connected to the complementary local data line, the first terminal of the complementary readout transistor is connected to the second terminal of the second switching transistor, and the first terminal of the second switching transistor is connected to the complementary global data line. The second terminal of the readout transistor, the second terminal of the complementary readout transistor, the first terminal of the first ground transistor, and the first terminal of the second ground transistor are connected; The control terminal of the first grounding transistor receives the first read enable signal, and the second terminal of the first grounding transistor is grounded; The control terminal of the second grounding transistor receives the second read enable signal, and the second terminal of the second grounding transistor is grounded; Both the control terminals of the first and second switching transistors receive a third read enable signal.

[0007] In some embodiments, the first grounding transistor, the second grounding transistor, the first switching transistor, and the second switching transistor are all NMOS transistors; During the preset working phase, the first read enable signal, the second read enable signal, and the third read enable signal are all in a disabled state, and the voltage of the third read enable signal is higher than that of the first read enable signal and the second read enable signal. During the preset working phase, the first grounding transistor, the second grounding transistor, the first switching transistor, and the second switching transistor are all in the off state.

[0008] In some embodiments, the preset working phase includes at least one of the following: pre-charge power-down mode phase, activation + pre-charge phase, and refresh mode phase.

[0009] In some embodiments, both the first grounding transistor and the second grounding transistor are MOS transistors, and the size of the first grounding transistor is smaller than that of the second grounding transistor.

[0010] In some embodiments, the size ratio of the first ground transistor, the second ground transistor, and the preset ground transistor is 0.25:0.75:1; the preset ground transistor is a MOS transistor used for grounding in the memory to which the local sensitive amplifier circuit belongs.

[0011] In some embodiments, whether the first read enable signal is enabled is related to the interval between the row activation signal and the read signal; wherein, if the interval is less than a first time interval, the first read enable signal is in an enabled state, and if the interval is greater than or equal to the first time interval, the first read enable signal is in a disabled state. And / or, the voltage value when the second read enable signal is in the enabled state is related to the process angle.

[0012] In some embodiments, the voltage value of the second read enable signal when it is in the enabled state is related to the process voltage and temperature conditions; Specifically, the voltage value of the second read enable signal when it is enabled under high temperature conditions is lower than the voltage value of the second read enable signal when it is enabled under low temperature conditions.

[0013] In some embodiments, the local sensitivity amplifier circuit further includes a first drive adjustment circuit and / or a second drive adjustment circuit; wherein: The first drive adjustment circuit has its output terminal connected to the control terminal of the first grounded transistor. It is used to receive a row activation signal and a read signal, and generate a pulse signal based on the row activation signal. If the read signal is within the pulse time period of the pulse signal, it outputs the first read enable signal in the enabled state; otherwise, it outputs the first read enable signal in the disabled state. The second drive adjustment circuit has its output terminal connected to the control terminal of the second grounded transistor. It is used to detect the process voltage and temperature conditions and output a first drive voltage based on the detected process voltage and temperature conditions. The first drive voltage is used to drive the initial read enable signal to generate the second read enable signal.

[0014] In some embodiments, the first drive adjustment circuit includes: A pulse generation circuit is used to receive the row activation signal and generate a pulse signal based on the row activation signal, wherein the pulse width of the pulse signal is greater than that of the row activation signal. An enable signal output circuit is used to receive the pulse signal and the read signal; if the read signal is within the pulse time period of the pulse signal, the first read enable signal in the enabled state is output; otherwise, the first read enable signal in the disabled state is output.

[0015] In some embodiments, the second drive adjustment circuit includes: A condition detection circuit is used to detect the process voltage and temperature conditions and generate a control signal characterizing the process voltage and temperature conditions. A voltage adjustment circuit is used to receive the control signal and generate the corresponding first driving voltage based on the control signal; The first driving circuit has an input terminal for receiving the initial read enable signal, a driving terminal for receiving the first driving voltage, and an output terminal for outputting the second read enable signal.

[0016] In some embodiments, the condition detection circuit includes: An oscillator circuit is used to generate an oscillator signal; the frequency of the oscillator signal is related to the process voltage and temperature conditions. A frequency detection circuit is used to detect the frequency of the oscillator signal; A voltage control circuit is used to generate a control signal based on the frequency of the oscillator signal; the control signal is used to control the voltage value of the first driving voltage.

[0017] In some embodiments, the voltage adjustment circuit includes: a selection circuit, a comparator, a first transistor, and a resistor string; The first end of the resistor string is connected to the second end of the first transistor, and the second end of the resistor string is grounded; the resistor string includes multiple resistors connected in series, and the connection nodes of some or all of the resistors serve as voltage nodes. The control terminal of the selection circuit is connected to the voltage control circuit to receive the control signal; the multiple input terminals of the selection circuit are respectively connected to the multiple voltage nodes; the output terminal of the selection circuit is connected to the second input terminal of the comparator. The first input terminal of the comparator receives a reference voltage, and the output terminal of the comparator is connected to the control terminal of the first transistor. The first terminal of the first transistor is connected to a power supply.

[0018] In a second aspect, embodiments of this disclosure provide a memory including the local sensitive amplifier circuit described in the first aspect.

[0019] This disclosure provides a local sensitive amplifier circuit and a memory. The transistor used for grounding in the local sensitive amplifier circuit is split into a first grounding transistor and a second grounding transistor. Furthermore, the read enable signal used to control the read operation is split into a first read enable signal, a second read enable signal, and a third read enable signal. This allows the first grounding transistor, the second grounding transistor, and the switching transistors (including the first and second switching transistors) to be controlled independently. Moreover, at different operating stages, the first, second, and third read enable signals can be set to be enabled and their specific voltage values ​​can be configured according to actual needs. This allows for faster response times when speed is required, and effectively reduced power consumption when power consumption is a concern, achieving a balance between speed and power consumption to meet different needs in various application scenarios. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the signal transmission process for a read operation in DRAM provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of the circuit structure of a local sensitivity amplifier provided for an embodiment of this disclosure; Figure 3 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ; Figure 4 A schematic diagram of the structure of a local sensitivity amplifier provided in this disclosure embodiment. Figure 1 ; Figure 5 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ; Figure 6 A schematic diagram of the structure of a local sensitivity amplifier provided in this disclosure embodiment. Figure 2 ; Figure 7 A signal timing diagram provided for an embodiment of this disclosure Figure 3 ; Figure 8 This is a schematic diagram of the structure of a second drive adjustment circuit provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure of a first drive adjustment circuit provided in an embodiment of the present disclosure; Figure 10 This is a schematic diagram of a comparison circuit provided in an embodiment of the present disclosure; Figure 11 A schematic diagram of the structure of a local sensitivity amplifier provided in this disclosure embodiment. Figure 3 ; Figure 12 This is a schematic diagram comparing the data separation of a global data line and a complementary global data line, provided as an embodiment of this disclosure. Detailed Implementation

[0021] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0023] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0025] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows: Dynamic Random Access Memory (DRAM) Sense Amplifier (SA); Offset Cancel SA (OCSA) sensitive amplifier; The second-stage sensing amplifier (the Second SA, DSA); Local Sensitive Amplifier (Local SA, LSA); Column Select Signal (CSL); Global data line (YIO); Local data cable (LIO); Metal-oxide-semiconductor field-effect transistor (MOS transistor); P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor); N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor); Word line (WL); Bit Line (BL); Double Data Rate (DDR); Low-power DDR (LPDDR); Process Voltage Temperature (PVT); Burst Read Operating Current (IDD4R); The delay time from row address to column address (tRCD); Column address to column address delay time (tCCD).

[0026] DRAM is a commonly used semiconductor memory device in computers. Its memory array contains multiple memory cells arranged in an array. The control terminals of the memory cells are connected to the word lines, and the input / output terminals of the memory cells are connected to the bit lines. See also... Figure 1 This illustrates the signal transmission process for a read operation in DRAM.

[0027] like Figure 1 As shown, for a read operation, the data signal output from the memory cell is amplified for the first time on the bit line BL by an offset-canceling sensitive amplifier OCSA (also known as the primary amplifier, denoted as the First SA). The amplified data signal is then transmitted to the local data line LIO via the column select signal. The data signal on the local data line LIO is amplified by the local sensitive amplifier LSA, and then transmitted to the global data line YIO. The data signal on the global data line YIO is amplified by the second-stage sense amplifier DSA (also known as the secondary amplifier, denoted as the Second SA), and then transmitted to the data bus. For a write operation, the local amplifier LSA transmits the data from the global data line YIO to the local data line LIO.

[0028] Figure 2 A schematic diagram of the circuit structure of a local sensitivity amplifier (LSA) is shown. Figure 3 The corresponding timing diagram is shown. For example... Figure 2 As shown, the local sensitive amplifier (LSA) includes: a ground transistor M1, a sense transistor M2, a complementary sense transistor M3, a first switching transistor M4, and a second switching transistor M5. The gates of the ground transistor M1, the first switching transistor M4, and the second switching transistor M5 are connected together and all receive the read enable signal RdEn. The first terminal of the ground transistor M1, the second terminal of the sense transistor M2, and the second terminal of the complementary sense transistor M3 are connected together, with the second terminal of the ground transistor M1 grounded. The gate of the sense transistor M2 is connected to the local data line LIO, and the first terminal of the sense transistor M2 is connected to the second terminal of the first switching transistor M4. The gate of the complementary sense transistor M3 is connected to the complementary local data line LION, and the first terminal of the complementary sense transistor M3 is connected to the second terminal of the second switching transistor M5. The first terminal of the first switching transistor M4 is connected to the global data line YIO, and the first terminal of the second switching transistor M5 is connected to the complementary global data line YION. Figure 2 As shown, each transistor can be an NMOS transistor.

[0029] During data transmission, the global data line YIO and the complementary global data line YION are first precharged to a high potential. Then, the read enable signal RdEn becomes high, turning on the ground transistor M1, the first switching transistor M4, and the second switching transistor M5. The local data line LIO and the complementary local data line LION transmit a pair of inverted data, i.e., one high and one low. This results in one end of the global data line YIO and the complementary global data line YION having a constant voltage while the other end begins to discharge, transmitting "0" and "1" respectively.

[0030] like Figure 3 As shown, in silicon testing, speed and IDD4R can be balanced by adjusting the pulse of the read enable signal RdEn or the column strobe signal CSL, where IDD4R represents the current consumption during a read operation. The adjustment step size is typically set to 200ps. With the improvement of chip performance, the requirements for high speed and low power consumption are also increasing, and traditional pulse adjustment methods face greater challenges in achieving speed and power consumption optimization.

[0031] Based on this, embodiments of this disclosure provide a local sensitive amplifier circuit, including: a readout transistor, a complementary readout transistor, a first ground transistor, a second ground transistor, a first switching transistor, and a second switching transistor; the control terminal of the readout transistor is connected to a local data line, the first terminal of the readout transistor is connected to the second terminal of the first switching transistor, and the first terminal of the first switching transistor is connected to a global data line; the control terminal of the complementary readout transistor is connected to a complementary local data line, the first terminal of the complementary readout transistor is connected to the second terminal of the second switching transistor, and the first terminal of the second switching transistor is connected to a complementary global data line; the second terminal of the readout transistor, the second terminal of the complementary readout transistor, the first terminal of the first ground transistor, and the first terminal of the second ground transistor are connected; the control terminal of the first ground transistor receives a first read enable signal, and the second terminal of the first ground transistor is grounded; the control terminal of the second ground transistor receives a second read enable signal, and the second terminal of the second ground transistor is grounded; the control terminals of both the first and second switching transistors receive a third read enable signal.

[0032] In this embodiment, the transistor used for grounding in the local sensitive amplifier circuit is split into a first grounding transistor and a second grounding transistor, and the read enable signal used to control the read operation is split into a first read enable signal, a second read enable signal, and a third read enable signal. Thus, the first grounding transistor, the second grounding transistor, and the switching transistors (including the first and second switching transistors) can be controlled independently. Furthermore, in different operating stages, the first read enable signal, the second read enable signal, and the third read enable signal can be set according to actual needs to accelerate the response speed while pursuing speed, and effectively reduce power consumption when there is a power consumption requirement, thereby achieving a balance between speed and power consumption and meeting different needs in various application scenarios.

[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0034] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 This illustration shows a schematic diagram of a local sensitive amplifier circuit provided in an embodiment of this disclosure. Figure 4 As shown, the local sensitive amplifier circuit 10 includes a readout transistor M2, a complementary readout transistor M3, a first ground transistor M1_1, a second ground transistor M1_2, a first switching transistor M4, and a second switching transistor M5; The control terminal of the read transistor M2 is connected to the local data line LIO, the first terminal of the read transistor M2 is connected to the second terminal of the first switching transistor M4, and the first terminal of the first switching transistor M4 is connected to the global data line YIO. The control terminal of the complementary readout transistor M3 is connected to the complementary local data line LION, the first terminal of the complementary readout transistor M3 is connected to the second terminal of the second switching transistor M5, and the first terminal of the second switching transistor M5 is connected to the complementary global data line YION. The second terminal of readout transistor M2, the second terminal of complementary readout transistor M3, the first terminal of first ground transistor M1_1, and the first terminal of second ground transistor M1_2 are connected; The control terminal of the first grounding transistor M1_1 receives the first read enable signal RdEn1, and the second terminal of the first grounding transistor M1_1 is grounded to Vss. The control terminal of the second grounding transistor M1_2 receives the second read enable signal RdEn2, and the second terminal of the second grounding transistor M1_2 is grounded to Vss. The control terminals of the first switching transistor M4 and the second switching transistor M5 both receive the third read enable signal RdEn3.

[0035] It should be noted that, as Figure 4As shown, each transistor in the local sensitive amplifier circuit 10 can be a MOS transistor, specifically an NMOS transistor.

[0036] like Figure 4 As shown, with Figure 2 Compared to the local sensitive amplifier circuit shown, the grounding transistor M1 is split into a first grounding transistor M1_1 and a second grounding transistor M1_2, and the read enable signal RdEn is split into a first read enable signal RdEn1, a second read enable signal RdEn2 and a third read enable signal RdEn3.

[0037] Thus, this embodiment of the present disclosure allows for the independent control of the first grounding transistor M1_1, the second grounding transistor M1_2, and the switching transistors (i.e., the first switching transistor M4 and the second switching transistor M5) by setting whether the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3 are enabled, based on actual needs. Furthermore, the specific voltage values ​​of the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3 in enabled and disabled states can be set according to actual needs. Therefore, by controlling the timing and voltage values ​​of the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3, the actual speed or power consumption requirements of the memory at different operating stages can be met, achieving comprehensive optimization of speed and power consumption.

[0038] For example, during a read operation, under conditions where latency requirements are not high, only one of the first read enable signal RdEn1 and the second read enable signal RdEn2 is enabled, while the other is disabled. One of the first ground transistor M1_1 and the second ground transistor M1_2 is turned on, pulling the second terminals of the read transistor M2 and the complementary read transistor M3 to ground, while simultaneously saving power. Alternatively, under conditions where latency requirements are high, both the first read enable signal RdEn1 and the second read enable signal RdEn2 are enabled, and both the first ground transistor M1_1 and the second ground transistor M1_2 are turned on. This quickly pulls the second terminals of the read transistor M2 and the complementary read transistor M3 to ground, enhancing drive capability and ensuring that the global data line YIO and the complementary global data line YION complete signal transmission in a short time, avoiding signal distortion or excessive delay.

[0039] For example, in operating conditions with high power consumption requirements, the specific voltage values ​​of the first read enable signal RdEn1 and / or the second read enable signal RdEn2 and / or the third read enable signal RdEn3 in the disabled or enabled state can be set to reduce the leakage current of the transistor and thus save power consumption.

[0040] Thus, by splitting the grounding transistor and the read enable signal, the embodiments of this disclosure can reasonably set the state and voltage value of the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3, thereby flexibly adapting to different speed and power consumption requirements and achieving performance optimization of the memory.

[0041] It should also be noted that, in this embodiment, the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3 can all be adjusted, or only one or two of them can be adjusted, while the others remain the same as the original read enable signal RdEn.

[0042] In some embodiments, during a preset working phase, the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3 are all in an disabled state, and the voltage of the third read enable signal RdEn3 is higher than that of the first read enable signal RdEn1 and the second read enable signal RdEn2. During the preset working phase, the first grounding transistor M1_1, the second grounding transistor M1_2, the first switching transistor M4, and the second switching transistor M5 are all in the off state.

[0043] It should be noted that, in the embodiments disclosed herein, the preset working stage refers to certain working stages when the first grounding transistor M1_1, the second grounding transistor M1_2, the first switching transistor M4, and the second switching transistor M5 are all in the off state. However, not all periods when these transistors are in the off state are preset working stages.

[0044] For example, the preset work stages may include, but are not limited to, one or more of the following work stages: The stages are: Precharge Power-Down Mode, Active / Precharged, and Refresh.

[0045] It should be noted that during the precharge power-down mode, the DRAM is in an idle state, and all its banks are in a precharged standby or idle state, meaning no word lines are activated, and the clock enable signal (CKE) is set to a low level (i.e., disabled). At this time, unnecessary modules within the DRAM, such as the clock and input buffers, are either turned off or enter a low-power state to minimize power consumption. The static leakage current of the DRAM in this deep power-saving mode and the current required to maintain its basic state are denoted as IDD2P; correspondingly, this operating phase can be called the IDD2P phase.

[0046] During the activation + precharge phase (or active operation phase), the activation command (ACT) and precharge command (PRE) switch frequently. The main current consumption in this phase is dynamic switching power consumption, which mainly comes from address line switching, row decoder driving, and the charging and discharging of the precharge circuit. The average current in this phase is denoted as IDD0, and this operating phase can be called the IDD0 phase.

[0047] During the refresh mode phase, to compensate for the inherent leakage current of the storage cell capacitors, a refresh operation is performed on all storage repositories. The current consumed is denoted as IDD5, and this working phase can be called the IDD5 phase.

[0048] For example, see Figure 5 As shown, (a) is the corresponding Figure 2 The signal timing diagram, (b) is the corresponding Figure 4 The signal timing diagram shows that the stage before the dashed line can be the preset working stage. In the preset working stage, the first read enable signal RdEn1, the second read enable signal RdEn2, and the third read enable signal RdEn3 are all in a disabled state (i.e., a low-level logic 0 state) to turn off the first ground transistor M1_1, the second ground transistor M1_2, the first switching transistor M4, and the second switching transistor M5. (See diagram below.) Figure 5 As shown in (b), during the preset working phase, although the first read enable signal RdEn1, the second read enable signal RdEn2 and the third read enable signal RdEn3 are all at low levels, the voltage of the third read enable signal RdEn3 is higher than that of the first read enable signal RdEn1 and the second read enable signal RdEn2.

[0049] Specifically, during the preset working phase, the low level of the third read enable signal RdEn3 can be set to 0V, and the low level of the first read enable signal RdEn1 and the second read enable signal RdEn2 can both be set to -0.2V (the same as the original unsplit read enable signal RdEn). In this way, during the IDD2P phase, the junction leakage current of the first switching transistor M4 and the second switching transistor M5 can be reduced. This is because: For an NMOS transistor, when the gate voltage is 0V, it is far below its threshold voltage. At this point, the channel is completely depleted, no conductive path is formed, and the source and drain are in a high-resistance state. During this period, it is in an ideal off-state, and the leakage current is mainly the intrinsic junction leakage current inherent to the manufacturing process and independent of the gate voltage. However, when the gate voltage is -0.2V, it may enter the subthreshold region. In this region, although a complete conductive channel is not formed, there is an exponentially decaying carrier concentration gradient in the semiconductor, resulting in a subthreshold current flowing from the drain to the source. This subthreshold current is much larger than the intrinsic junction leakage current when it is completely off. It is a non-ideal leakage current in the off-state caused by the gate electric field partially adjusting the channel. Therefore, when using a 0V gate voltage to turn off the NMOS transistor, the device is in a completely depleted off-state, and the leakage current is only a very small intrinsic junction leakage current. When using a -0.2V gate voltage, the NMOS transistor enters the subthreshold conduction region, generating a larger subthreshold leakage current.

[0050] During the IDD0 and IDD5 stages, the gate loading of the third read enable signal RdEn3 during signal toggling can be reduced, thereby reducing leakage current. This is because, for the third read enable signal RdEn3, during signal toggling, it only needs to toggle from 0V to a high level, instead of toggle from -0.2V to a high level, resulting in a smaller voltage swing, thus lower power consumption and leakage current.

[0051] It should be noted that the above settings of 0V and -0.2V for the low level are only examples and are not limited to in practice.

[0052] In this embodiment, the first grounding transistor M1_1 and the second grounding transistor M1_2 can have the same or different dimensions, both of which enable flexible control of grounding. Furthermore, for the purpose of balancing speed and power consumption, the first grounding transistor M1_1 is smaller than the second grounding transistor M1_2.

[0053] It should be noted that when grounding is required, if high power consumption is a concern, only the second read enable signal RdEn2 can be enabled to control the second grounding transistor M1_2 to conduct and ground, while the first read enable signal RdEn1 is disabled to control the first grounding transistor M1_1 to turn off. In this way, since the second grounding transistor M1_2 is larger, it can meet the grounding requirements, while turning off the first grounding transistor M1_1 saves power. If high speed is required, both the first read enable signal RdEn1 and the second read enable signal RdEn2 can be enabled to control both the first grounding transistor M1_1 and the second grounding transistor M1_2 to conduct, achieving rapid grounding and ensuring the circuit's operating speed.

[0054] It should also be noted that, as mentioned above, the first grounding transistor M1_1 and the second grounding transistor M1_2 can be considered as... Figure 2 The grounding transistor M1 is split into two transistors. The sum of the dimensions of the first grounding transistor M1_1 and the second grounding transistor M1_2 is the same as that of the grounding transistor M1. Alternatively, the remaining MOS transistors used for grounding in the memory to which the local sensitive amplifier circuit 10 belongs can be defined as preset grounding transistors. The dimensions of the preset grounding transistors are the same as those of the grounding transistor M1.

[0055] The size ratio of the first grounding transistor M1_1, the second grounding transistor M1_2, and the grounding transistor M1 is a1:a2:1, and satisfies: a1+a2=1, where a1 is the size ratio of the first grounding transistor M1_1, and a2 is the size ratio of the second grounding transistor M1_2. Here, size can refer to the length, width, thickness, etc. of components such as the gate and channel of the transistor.

[0056] Specifically, the size ratio of the first grounding transistor M1_1, the second grounding transistor M1_2, and the preset grounding transistor can be 0.25:0.75:1, thereby achieving a balance between speed and power consumption by controlling the state and voltage value of the first read enable signal RdEn1 and the second read enable signal RdEn2.

[0057] In some embodiments, the voltage value of the second read enable signal RdEn2 when it is in the enabled state is related to the process corner.

[0058] It should be noted that in this embodiment, the second grounding transistor M1_2 is larger than the first grounding transistor M1_1. The second grounding transistor M1_2 is the main transistor for grounding the control circuit, while the first grounding transistor M1_1 serves as a supplement to the grounding capability and speed when necessary.

[0059] For the first grounding transistor M1_1, when the circuit needs to be grounded, its activation or deactivation can be determined based on the actual speed requirements.

[0060] For the second grounding transistor M1_2, when the circuit needs to be grounded, its gate voltage when it is turned on can be set according to the actual process corner conditions, that is, the specific voltage value when the second read enable signal RdEn2 is in the enabled state.

[0061] Here, the second grounding transistor M1_2 under different process corners can be tested or simulated in advance. The performance of the transistor is different under different process corners. For example, the driving current of the transistor under the FF process corner will be larger, so the voltage requirements of the FF process corner and the SS process corner will be different. The voltage value of the enable state of the second read enable signal RdEn2 is set according to the actual voltage requirements of the transistor under the corresponding process corner, that is, the specific voltage value when it is high.

[0062] In this context, the FF process corner (Fast-Fast) refers to the situation where both NMOS and PMOS transistors are in a "fast" state. In this case, the transistors have lower threshold voltages, higher carrier mobility, and the fastest switching speed, but also higher leakage current and power consumption. The SS process corner (Slow-Slow) refers to the situation where both NMOS and PMOS transistors are in a "slow" state. In this case, the transistors have higher threshold voltages, lower mobility, slower switching speeds, and increased delay, but also lower leakage current and lower static power consumption.

[0063] For example, during testing, the voltage value of the second read enable signal RdEn2 in the enable state can be dynamically adjusted according to the actual process corner conditions of different chips, thereby dynamically adjusting IDD4R and reducing power consumption.

[0064] Based on this, such as Figure 6 As shown, the local sensitive amplifier circuit 10 may further include a first drive adjustment circuit 101 and / or a second drive adjustment circuit 102, wherein: The first drive adjustment circuit 101 is used to receive the read enable signal RdEn and the first control signal (not shown in the figure). When the first control signal is in the enabled state, the read enable signal RdEn is output as the first read enable signal RdEn1. When the first control signal is in the disabled state, the first read enable signal RdEn1 in the disabled state is output. The second drive adjustment circuit 102 is used to receive the read enable signal RdEn, drive the read enable signal RdEn based on the drive voltage Vtrim, and output the second read enable signal RdEn2. The voltage value of the drive voltage Vtrim is the voltage value when the second read enable signal RdEn2 is in the enabled state, and the voltage value of the drive voltage Vtrim is related to the process corner.

[0065] It should be noted that when high-speed operation is required, the first control signal is enabled, allowing the first drive adjustment circuit 101 to output the read enable signal RdEn as the first read enable signal RdEn1, which controls the first grounding transistor M1_1 to turn on, thus accelerating the circuit's data processing speed. When high-speed operation is not required, the first control signal is disabled, and the first drive adjustment circuit 101 always outputs the disabled first read enable signal RdEn1, turning off the first grounding transistor M1_1. Furthermore, during non-preset operating phases, the voltage value of the disabled state (i.e., low-level state) of the first read enable signal RdEn1 is the same as the original read enable signal RdEn, for example, both being 0V.

[0066] It should also be noted that the input terminal of the second drive adjustment circuit 102 receives the read enable signal RdEn, the power supply terminal receives the drive voltage Vtrim, and the output terminal outputs the second read enable signal RdEn2. The drive voltage Vtrim provides a high level for the second read enable signal RdEn2, and its specific voltage value is related to the process corner and can be dynamically adjusted.

[0067] See Figure 7 , where (a) is the corresponding Figure 2 The timing diagram is shown in (b), which is the corresponding... Figure 6 The timing diagram.

[0068] and Figure 4 compared to, Figure 6 Dynamic drive voltage control for the second read enable signal RdEn2 has been added, while the first read enable signal RdEn1 can control whether the first grounding transistor M1_1 is turned on. For example... Figure 7 As shown in (a) above, for Figure 2 The circuit shown adjusts the pulses of the read enable signal RdEn and the column select signal CSL. Adjusting the pulse of the read enable signal RdEn requires adjusting the timing of other signals, resulting in numerous combinations and leading to long testing times and high testing costs. This embodiment dynamically adjusts the high-level voltage value of the second read enable signal RdEn2 based on the process corner of different chips (dies), thereby dynamically adjusting IDD4R and reducing power consumption. This method of dynamically adjusting the voltage of the second read enable signal RdEn2 not only improves efficiency and accuracy and reduces testing costs, but also facilitates mass production.

[0069] And / or, embodiments of this disclosure can also control whether to use the first read enable signal RdEn1 to turn on the first ground transistor M1_1 based on power consumption and speed requirements, which can also save power.

[0070] In some embodiments, whether the first read enable signal RdEn1 is enabled is related to the interval between the row activation signal and the read signal; wherein, if the interval is less than the first time interval, the first read enable signal RdEn1 is in an enabled state, and if the interval is greater than the first time interval, the first read enable signal RdEn1 is in an disabled state.

[0071] It should be noted that when performing a read operation, a specific row needs to be activated first, and then a specific column needs to be selected. The row activation signal is the signal used to activate the row, and the read signal is the command signal to execute the read operation. The read signal can be the preceding signal of the read enable signal RdEn, which is the signal obtained by decoding the read-related command signals sent by the DDR controller (or other controllers, test equipment, etc.).

[0072] Therefore, in this embodiment, the interval between the row activation signal and the read signal can be used to characterize the tRCD. The interval between the row activation signal and the read signal is compared with a first time interval. Based on the comparison result, it is determined whether the tRCD is a short tRCD or a regular tRCD. The first time interval is a critical value for determining whether it is a short tRCD, and can be set according to actual conditions. If the interval between the row activation signal and the read signal is less than the first time interval, it is considered a short tRCD, and the first read enable signal RdEn1 needs to be turned on to conduct the first ground transistor M1_1 to enhance the driving capability. If the interval between the row activation signal and the read signal is greater than or equal to the first time interval, it is considered a regular tRCD, and the first read enable signal RdEn1 is turned off to turn off the first ground transistor M1_1 to achieve power saving.

[0073] In this way, compared to Figure 4 The example shown is in Figure 6 In the example, dynamic voltage control can be added to the second read enable signal RdEn2, allowing for dynamic adjustment of its high-level voltage value. This enables adjustment of IDD4R based on the process corner of different chips, reducing power consumption. This not only improves efficiency and accuracy and reduces testing costs but also facilitates mass production. Furthermore, by determining whether a short tRCD condition occurs, the system can decide whether to enable the first read enable signal RdEn1 to enhance drive capability, ensuring that the signals of the global data line YIO and the complementary global data line YION are transmitted within a short time, avoiding signal distortion or delay. In other cases, the first read enable signal RdEn1 is disabled to save power.

[0074] In some embodiments, the voltage value of the second read enable signal RdEn2 when it is in the enabled state is related to the PVT condition; Specifically, the voltage value of the second read enable signal RdEn2 when it is enabled under high temperature conditions is lower than the voltage value of the second read enable signal RdEn2 when it is enabled under low temperature conditions.

[0075] It should be noted that the PVT conditions include operating conditions in three dimensions: process voltage and temperature. The process angle can be regarded as a model of the "process" dimension. In the embodiments of this disclosure, the high-level voltage value of the second read enable signal RdEn2 can be controlled based solely on the process angle, or it can be controlled based on one, two, or all of the PVT conditions.

[0076] Temperature has a significant impact on the threshold voltage of an NMOS transistor, with the main trend being that the threshold voltage decreases as temperature increases. That is, with increasing temperature, a lower gate voltage can be used to turn on the NMOS transistor compared to a lower temperature. Therefore, in this embodiment, the high-level voltage of the second read enable signal RdEn2 under high-temperature conditions can be set lower than that under low-temperature conditions. It is understood that high and low temperatures are relative terms. This ensures that the second ground transistor M1_2 is turned on with the most suitable gate voltage under different temperature conditions, thereby saving power.

[0077] To achieve dynamic adjustment of the second read enable signal RdEn2 based on PVT conditions, in some other embodiments of this disclosure, the output terminal of the second drive adjustment circuit 102 is connected to the control terminal of the second ground transistor M1_2, and is used to detect PVT conditions and output a first drive voltage based on the detected PVT conditions; the first drive voltage is used to drive the initial read enable signal to generate the second read enable signal RdEn2.

[0078] It should be noted that the second drive adjustment circuit 102 can internally include a circuit module capable of detecting PVT conditions, converting the detected PVT conditions into corresponding signals to characterize the corresponding PVT conditions, and then outputting a first drive voltage matching the PVT conditions to drive the initial read enable signal, thereby obtaining the second read enable signal RdEn2. Here, the initial read enable signal can be the aforementioned read enable signal RdEn. Specifically, "the first drive voltage drives the initial read enable signal to generate the second read enable signal RdEn2" means that the second drive adjustment circuit 102 can also internally include a circuit module with buffer drive functions, capable of outputting the initial read enable signal in the same logic state (1 or 0) as the second read enable signal RdEn2, and the specific voltage value of the high-level state of the second read enable signal RdEn2 is the first drive voltage, thereby achieving dynamic control of the voltage value of the high-level state of the second read enable signal RdEn2.

[0079] Specifically, such as Figure 8 As shown, the second drive adjustment circuit 102 may include: The condition detection circuit 1021 is used to detect the PVT condition and generate a control signal characterizing the PVT condition; The voltage adjustment circuit 1022 is used to receive control signals and generate a corresponding first driving voltage based on the control signals. The first driving circuit 1023 is used to receive the initial read enable signal and the first driving voltage, drive and enhance the initial read enable signal based on the first driving voltage, and output the second read enable signal RdEn2.

[0080] It should be noted that, as Figure 8 As shown, the condition detection circuit 1021 is connected to the voltage adjustment circuit 1022. The condition detection circuit 1021 is used to detect the PVT condition and output a control signal to characterize the detected PVT condition. Then, the voltage adjustment circuit 1022 generates a first driving voltage corresponding to the PVT condition based on the control signal and sends the first driving voltage to the first driving circuit 1023 to drive the initial read enable signal RdEn to generate the second read enable signal RdEn2.

[0081] Among them, the LSA main circuit refers to, for example, Figure 4 A circuit structure consisting of multiple transistors.

[0082] In some embodiments, such as Figure 8 As shown, the condition detection circuit 1021 may include: Condition detection sub-circuit 201 is used to generate a PVT signal based on PVT conditions; The decoding circuit 202 is used to decode the PVT signal and generate a control signal.

[0083] It should be noted that the condition detection sub-circuit 201 can be referred to as a PVT detector (PVT monitor), which is a circuit module for detecting process, voltage, and temperature. To facilitate the control of the voltage adjustment circuit 1022, a decoding circuit 202 can also be set to decode the PVT signal and convert it into a control signal to control the voltage adjustment circuit 1022 to generate the corresponding first driving voltage.

[0084] To enable the first grounding transistor M1_1 to be turned on or off based on whether it is short tRCD, in some embodiments of this disclosure, the first drive adjustment circuit 101 has its output terminal connected to the control terminal of the first grounding transistor M1_1, and is used to receive the row activation signal and the read signal, and generate a pulse signal based on the row activation signal; if the read signal is within the pulse time period of the pulse signal, the first read enable signal RdEn1 in the enabled state is output, otherwise, the first read enable signal RdEn1 in the disabled state is output.

[0085] It should be noted that the time interval between the row activation signal and the read signal can characterize the length of tRCD. In this embodiment, the determination of whether to enable the first grounding transistor M1_1 is made by judging whether it is a short tRCD. The judgment method can be as follows: process the row activation signal to obtain a pulse signal, the pulse width of which can be the first time interval; then judge whether the read signal arrives within the pulse time period of the pulse signal. If it arrives, it means that the read signal was received after the row activation signal without the first time interval, that is, the time interval between the row activation signal and the read signal is less than the first time interval, and it is determined to be a short tRCD, and the first read enable signal RdEn in the enabled state is output; if the read signal fails to arrive within the pulse time period of the pulse signal, it means that the time interval between the row activation signal and the read signal is greater than or equal to the first time interval, and it is determined to be a normal tRCD, and the first read enable signal RdEn1 in the disabled state is output. The first time interval can be set based on the expected tRCD value according to the specific application scenario such as product type and product working state.

[0086] For example, such as Figure 9 As shown, the first drive adjustment circuit 101 may include: The comparator circuit 1011 is used to receive the row activation signal and the read signal, determine whether the time interval between the row activation signal and the read signal is greater than a first time interval, and output the first read enable signal RdEn1 corresponding to the state based on the comparison result.

[0087] It may also include: an amplifier control circuit 1012, used to receive the first read enable signal RdEn1, and output it after driving enhancement.

[0088] It should be noted that, as Figure 9 As shown, the comparator circuit 1011 is the main circuit in the first drive adjustment circuit 101 that generates the first read enable signal RdEn1, as follows: Figure 10 As shown, the comparator circuit 1011 may specifically include: The pulse generation circuit 301 is used to receive the row activation signal and generate a pulse signal based on the row activation signal. The pulse width of the pulse signal is greater than that of the row activation signal. The enable signal output circuit 302 is used to receive pulse signals and read signals; if the read signal is within the pulse time period of the pulse signal, it outputs the first read enable signal in the enabled state; otherwise, it outputs the first read enable signal in the disabled state.

[0089] Thus, in this embodiment of the present disclosure, the pulse generation circuit 301 is first used to convert the row activation signal into a pulse signal, and then the enable signal output circuit determines whether the read signal is within the pulse time period of the pulse signal, so as to output the first read enable signal of the enable state during short tRCD.

[0090] Furthermore, in Figure 4 , Figures 8-10 Based on this, see Figure 11 This illustrates a detailed structural diagram of a local sensitive amplifier circuit 10 provided in an embodiment of this disclosure. For example... Figure 11 As shown, the pulse generation circuit 301 may specifically include a delay circuit 3011 and an OR gate 3012; the enable signal output circuit 302 is an AND gate 3021; The delay circuit 3011 is used to receive the row activation signal, perform delay processing, and then send the delayed signal to the OR gate 3012. OR gate 3012 is used to receive the row activation signal and the delay signal, perform OR logic processing, and obtain a pulse signal; The first input terminal of AND gate 3021 is connected to the output terminal of OR gate 3012 to receive pulse signals. The second input terminal of AND gate 3021 receives read signals, and the output terminal of AND gate 3021 outputs the first read enable signal RdEn1.

[0091] It should be noted that the delay circuit 3011 is a dynamic delay circuit with an adjustable delay time. The specific delay time can be controlled by a relevant delay control signal (not shown in the figure), thereby adjusting the size of the first time interval. Figure 11 The arrows in the delay circuit 3011 indicate that the delay time of the delay circuit 3011 is adjustable. Figure 11 In this example, an OR gate 3012 is used to generate the pulse signal. Therefore, the delay time of the delay circuit 3011 typically does not exceed the pulse width of the row activation signal to ensure the generation of the pulse signal. In other examples, the pulse generation circuit 301 can also use other circuit structures, which are not specifically limited here.

[0092] If the read signal falls within the pulse time period of the pulse signal, then AND gate 3021 will output the read signal as the first read enable signal RdEn1. For example, see... Figure 7 The timing diagram shown in (b) indicates that when the first read signal is detected after the row activation signal is detected, the first read enable signal RdEn1 is enabled to enhance the driving capability.

[0093] It should also be noted that the amplifier control circuit 1012 can be a buffer, with its input terminal connected to the output terminal of AND gate 3021 and its output terminal connected to the control terminal of the first ground transistor M1_1, used to drive and enhance the first read enable signal RdEn1 and send it to the first ground transistor M1_1.

[0094] like Figure 11As shown, the condition detection sub-circuit 201 can specifically be an oscillator circuit 2011. In this case, the PVT signal is denoted as the oscillator signal. The decoding circuit 202 can specifically include a frequency detection circuit 2021 and a voltage control circuit 2022. Therefore, the condition detection circuit 1021 can specifically include: Oscillator circuit 2011 is used to generate oscillator signals; the frequency of the oscillator signals is related to process voltage and temperature conditions. Frequency detection circuit 2021 is used to detect the frequency of the oscillator signal; The voltage control circuit 2022 is used to generate a control signal based on the frequency of the oscillator signal; the control signal is used to control the voltage value of the first drive voltage Vtrim.

[0095] It should be noted that the oscillator circuit 2011 can specifically be a ring oscillator, composed of multiple stages of inverters connected end-to-end. The number of inverters is typically an odd number, such as 11 stages. After being enabled, the oscillator circuit 2011 begins to oscillate. The oscillation frequency is related to the PVT (Programmable Voltage Transformation). Generally, the higher the temperature and the faster the process time, the higher the oscillation frequency. The oscillation frequency is the frequency of the oscillator signal output by the oscillator circuit 2011. Thus, the frequency of the oscillator signal can be used to characterize the effect of the PVT. The output terminal of any one of the inverters can be used as the output terminal of the oscillator circuit 2011 to output the oscillator signal.

[0096] The frequency detection circuit 2021 can specifically use a counter to determine the frequency of the oscillator signal. The frequency can be determined by recording the number of pulses of the oscillator signal within a fixed time period, and a frequency indication signal is generated to characterize the frequency of the oscillator signal.

[0097] The voltage control circuit 2022 is connected to the frequency detection circuit 2021 and is used to receive the frequency indication signal. It generates a corresponding control signal through logic decoding, digital conversion and other methods. The control signal is used to control the voltage value of the first driving voltage Vtrim so that the voltage value of the first driving voltage Vtrim meets the current PVT conditions and adjusts the high-level voltage value of the second read enable signal RdEn2 to the optimal state.

[0098] It should also be noted that the control signal can be a control code (which can be denoted as Secsor code). Different control codes correspond to different first drive voltage values. The voltage adjustment circuit 1022 outputs the corresponding first drive voltage Vtrim according to the received control signal.

[0099] like Figure 11 As shown, the voltage adjustment circuit 1022 may include: a selection circuit 401, a comparator 402, a first transistor 403, and a resistor string 404; The first end of the resistor string 404 is connected to the second end of the first transistor 403, and the second end of the resistor string 404 is grounded; the resistor string 404 includes multiple resistors connected in series, and the connection nodes of some or all of the resistors serve as voltage nodes. The control terminal of the selection circuit 401 is connected to the voltage control circuit 2022 to receive control signals; the multiple input terminals of the selection circuit 401 are respectively connected to multiple voltage nodes; the output terminal of the selection circuit 401 is connected to the second input terminal of the comparator 402. The first input terminal of comparator 402 receives the reference voltage Vref, and the output terminal of comparator 402 is connected to the control terminal of the first transistor 403. The first terminal of the first transistor 403 is connected to the power supply.

[0100] It should be noted that, in Figure 11 In this example, the connection node between the second terminal of the first transistor 403 and the first terminal of the resistor string 404 is used as the voltage output node to output the first driving voltage Vtrim. In other examples, the connection node between two adjacent resistors in the resistor string 404 can also be used as the voltage output node for outputting the first driving voltage Vtrim; no specific limitation is made here.

[0101] The first transistor can be an NMOS transistor, or in other examples, a PMOS transistor.

[0102] The selection circuit 401 can be a multiplexer. Its control terminal (also called the selection terminal) receives a control signal and selects which voltage node to output based on the control signal, thereby determining the voltage division at the output terminal of the selection circuit 401.

[0103] One end of comparator 402 is connected to the reference signal Vref, and the other end receives the resistor voltage divider selected by the selection circuit 401. After comparison, it outputs a comparison signal to the control terminal (i.e., gate) of the first transistor 403 to control the conduction level of the first transistor 403, thereby determining the appropriate first driving voltage Vtrim. The entire control process is a dynamic adjustment process.

[0104] The first driving circuit 1023 may include one or more buffer circuits. The power supply terminal of the final buffer circuit (i.e. the buffer circuit used to output the second read enable signal RdEn2) is connected to the voltage output node mentioned above. It is used to receive the first driving voltage Vtrim and control the high level state of the second read enable signal RdEn2 to be the first driving voltage Vtrim, thereby realizing dynamic adjustment.

[0105] exist Figure 11 In the first driving circuit 1023, it is a first-stage buffer circuit, such as... Figure 11As shown, the first driving circuit 1023 has an input terminal for receiving the initial read enable signal RdEn, a driving terminal for receiving the first driving voltage Vtrim, and an output terminal for outputting the second read enable signal RdEn2.

[0106] like Figure 11 As shown, in this embodiment of the disclosure, the condition detection circuit 1021 can generate control signals under different PVT conditions to change the driving voltage of the second read enable signal RdEn2, thereby achieving automatic adjustment of the driving capability of the second ground transistor M1_2. And / or, a pulse width-adjustable pulse signal is generated by the row activation signal to detect whether the read signal arrives within the pulse. If so, the first read enable signal RdEn1 is output through the AND gate 3021, driving the first ground transistor M1_1 to conduct, enhancing the driving capability, and ensuring signal integrity under short RCD conditions.

[0107] Thus, this embodiment of the present disclosure can utilize the condition detection circuit 1021 to control the high-level voltage of the second read enable signal RdEn2 based on PVT conditions, thereby achieving on-chip automatic adjustment of tCCD and compensation for tCCD at different temperatures, ensuring that tCCD remains stable even under the worst temperature conditions. For example, during the testing phase, under low-temperature conditions, increasing the high-level voltage of the second read enable signal RdEn2 accelerates the discharge speed of the global data line YIO, thereby reducing tCCD and increasing speed; under high-temperature conditions, the high-level voltage of the second read enable signal RdEn2 can be lowered, even lowered to -0.2V, i.e., turned off, thereby slowing down the discharge speed of the global data line YIO, increasing tCCD, and slowing down speed; thus, tCCD is kept within a stable range under different temperatures, and the discharge speed of the global data line YIO tends to stabilize, achieving a compromise between tCCD and IDD4R.

[0108] In other words, the second drive adjustment circuit 102 can control the voltage value of the first drive voltage Vtrim to have a negative correlation with the temperature, so as to adjust tCCD to maintain it in a stable range.

[0109] See Figure 12 This illustration shows a comparative diagram of data separation between a global data line YIO and a complementary global data line YION, provided in an embodiment of this disclosure. Specifically, (a) and... Figure 2 Correspondingly, (b) and Figure 11 Correspondingly, it can be seen that without dynamic adjustment of the gate voltage, as shown in (a), there is a significant difference in the separation states of low temperature LT and high temperature HT. As shown in (b), with dynamic adjustment of the gate voltage, the separation states of low temperature LT and high temperature HT remain consistent, thus making the overall circuit work smoothly and avoiding significant differences under different environmental conditions.

[0110] It should also be noted that, in the embodiments disclosed herein, the adjustment control of the first read enable signal RdEn1 and the second read enable signal RdEn2 can be performed simultaneously or selectively, without any specific limitation.

[0111] In summary, the embodiments of this disclosure provide a local sensitive amplifier circuit that solves the key problem of how to flexibly adjust speed and power consumption in the design, thereby meeting the high-speed and low-power requirements of DRAM. By improving the circuit structure of the local sensitive amplifier, speed and power consumption can be flexibly adjusted during the testing phase, thereby optimizing performance.

[0112] Specifically, this disclosure proposes a scheme to split the grounding transistor in a local sensitive amplifier into two transistors. Compared with traditional local sensitive amplifiers, this allows for dynamic adjustment of the second read enable signal RdEn2 according to different operating conditions. Furthermore, this disclosure also proposes a dynamic adjustment scheme. In the case of short tRCD, a high-speed control mode is used to enable the first read enable signal RdEn1 to turn on the first grounding transistor M1_1, improving the relevant core timing. This allows for adjustment of IDD4R to achieve a low-power design. Simultaneously, it supports dynamic test analysis during the testing phase, thereby achieving controllable power consumption on the silicon die and optimizing LPDDR performance through single-chip (by-die) adjustments.

[0113] In another embodiment of this disclosure, a memory is provided, including the local sensitivity amplifier circuit 10 of the foregoing embodiments.

[0114] It should be noted that the memory can be DRAM. For DRAM, it can not only conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6. No restrictions are imposed here.

[0115] It should also be noted that, due to the addition of a condition detection circuit 1021 and a voltage adjustment circuit 1022 to the local sensitive amplifier circuit 10, and the improvement of the main circuit of the local sensitive amplifier, the voltage value of the second read enable signal RdEn2 can be flexibly adjusted under different PVT conditions, thereby better achieving a balance between speed and power consumption optimization.

[0116] And / or, the speed and power consumption of the memory can be optimized by dynamically adjusting the current capability of the local sensitive amplifier based on the actual tRCD and the characteristics of the memory architecture. This solution is applicable to various types of DRAM memory and can improve memory performance and energy efficiency.

[0117] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0118] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0119] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0120] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0121] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0122] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A locally sensitive amplifier circuit, characterized by include: Readout transistor, complementary readout transistor, first ground transistor, second ground transistor, first switching transistor, and second switching transistor; The control terminal of the readout transistor is connected to the local data line, the first terminal of the readout transistor is connected to the second terminal of the first switching transistor, and the first terminal of the first switching transistor is connected to the global data line. The control terminal of the complementary readout transistor is connected to the complementary local data line, the first terminal of the complementary readout transistor is connected to the second terminal of the second switching transistor, and the first terminal of the second switching transistor is connected to the complementary global data line. The second terminal of the readout transistor, the second terminal of the complementary readout transistor, the first terminal of the first ground transistor, and the first terminal of the second ground transistor are connected; The control terminal of the first grounding transistor receives the first read enable signal, and the second terminal of the first grounding transistor is grounded; The control terminal of the second grounding transistor receives the second read enable signal, and the second terminal of the second grounding transistor is grounded; Both the control terminals of the first and second switching transistors receive the third read enable signal; The first read enable signal, the second read enable signal, and the third read enable signal are independent of each other.

2. The locally sensitive amplifier circuit of claim 1, wherein, The first grounding transistor, the second grounding transistor, the first switching transistor, and the second switching transistor are all NMOS transistors; During the preset working phase, the first read enable signal, the second read enable signal, and the third read enable signal are all in a disabled state, and the voltage of the third read enable signal is higher than that of the first read enable signal and the second read enable signal. During the preset working phase, the first grounding transistor, the second grounding transistor, the first switching transistor, and the second switching transistor are all in the off state.

3. The locally sensitive amplifier circuit of claim 2, wherein, The preset working stages include at least one of the following: pre-charge power-off mode stage, activation + pre-charge stage, and refresh mode stage.

4. The locally sensitive amplifier circuit of claim 1, wherein, Both the first grounding transistor and the second grounding transistor are MOS transistors, and the size of the first grounding transistor is smaller than that of the second grounding transistor.

5. The locally sensitive amplifier circuit of claim 4, wherein, The size ratio of the first grounding transistor, the second grounding transistor, and the preset grounding transistor is 0.25:0.75:1; the preset grounding transistor is a MOS transistor used for grounding in the memory to which the local sensitive amplifier circuit belongs.

6. The locally sensitive amplifier circuit of claim 1, wherein, Whether the first read enable signal is enabled is related to the interval between the row activation signal and the read signal; wherein, if the interval is less than the first time interval, the first read enable signal is in an enabled state, and if the interval is greater than or equal to the first time interval, the first read enable signal is in a disabled state. And / or, the voltage value when the second read enable signal is in the enabled state is related to the process angle.

7. The locally sensitive amplifier circuit of claim 1, wherein, The voltage value of the second read enable signal when it is in the enabled state is related to the process voltage and temperature conditions; Specifically, the voltage value of the second read enable signal when it is enabled under high temperature conditions is lower than the voltage value of the second read enable signal when it is enabled under low temperature conditions.

8. A locally sensitive amplifier circuit according to any one of claims 1-7, characterized in that, The local sensitivity amplifier circuit further includes a first drive adjustment circuit and / or a second drive adjustment circuit; wherein: The first drive adjustment circuit has its output terminal connected to the control terminal of the first grounded transistor. It is used to receive a row activation signal and a read signal, and generate a pulse signal based on the row activation signal. If the read signal is within the pulse time period of the pulse signal, it outputs the first read enable signal in the enabled state; otherwise, it outputs the first read enable signal in the disabled state. The second drive adjustment circuit has its output terminal connected to the control terminal of the second grounded transistor. It is used to detect the process voltage and temperature conditions and output a first drive voltage based on the detected process voltage and temperature conditions. The first drive voltage is used to drive the initial read enable signal to generate the second read enable signal.

9. The locally sensitive amplifier circuit of claim 8, wherein, The first drive adjustment circuit includes: A pulse generation circuit is used to receive the row activation signal and generate a pulse signal based on the row activation signal, wherein the pulse width of the pulse signal is greater than that of the row activation signal. An enable signal output circuit is used to receive the pulse signal and the read signal; if the read signal is within the pulse time period of the pulse signal, the first read enable signal in the enabled state is output; otherwise, the first read enable signal in the disabled state is output.

10. The locally sensitive amplifier circuit of claim 8, wherein, The second drive adjustment circuit includes: A condition detection circuit is used to detect the process voltage and temperature conditions and generate a control signal characterizing the process voltage and temperature conditions. A voltage adjustment circuit is used to receive the control signal and generate the corresponding first driving voltage based on the control signal; The first driving circuit has an input terminal for receiving the initial read enable signal, a driving terminal for receiving the first driving voltage, and an output terminal for outputting the second read enable signal.

11. The locally sensitive amplifier circuit of claim 10, wherein, The condition detection circuit includes: An oscillator circuit is used to generate an oscillator signal; the frequency of the oscillator signal is related to the process voltage and temperature conditions. A frequency detection circuit is used to detect the frequency of the oscillator signal; A voltage control circuit is used to generate a control signal based on the frequency of the oscillator signal; the control signal is used to control the voltage value of the first driving voltage.

12. The locally sensitive amplifier circuit of claim 11, wherein, The voltage adjustment circuit includes: a selection circuit, a comparator, a first transistor, and a resistor string; The first end of the resistor string is connected to the second end of the first transistor, and the second end of the resistor string is grounded; the resistor string includes multiple resistors connected in series, and the connection nodes of some or all of the resistors serve as voltage nodes. The control terminal of the selection circuit is connected to the voltage control circuit to receive the control signal; the multiple input terminals of the selection circuit are respectively connected to the multiple voltage nodes; the output terminal of the selection circuit is connected to the second input terminal of the comparator. The first input terminal of the comparator receives a reference voltage, and the output terminal of the comparator is connected to the control terminal of the first transistor. The first terminal of the first transistor is connected to a power supply.

13. A memory, comprising: Includes the local sensitive amplifier circuit as described in any one of claims 1-12.

Images