Semiconductor device lower electrode compatible with multiple wafer sizes

Abstract

The application provides a lower electrode for semiconductor equipment compatible with wafers of different sizes, which comprises an electrode body, an annular groove is formed in the upper surface of the electrode body, the annular groove is symmetrically arranged about the central axis of the electrode body, and a cover ring is matched with the annular groove, the upper surface of the cover ring is not higher than the upper surface of the annular groove, wherein the inner diameter of the annular groove is less than 100 mm, and the outer diameter of the annular groove is greater than or equal to 104 mm; when the electrode body supports a wafer, the wafer is symmetrically placed about the central axis. The application is compatible with 8-inch wafers and 12-inch wafers, and can avoid plasma bombardment on the lower electrode.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor equipment technology, and particularly relates to a lower electrode for semiconductor equipment that is compatible with multi-size wafers. Background Technology

[0002] Existing lower electrode structures such as Figures 1-2 As shown, because the bottom electrode design must be compatible with the largest wafer size (12 inches), such as Figures 5-6 Therefore, when processing small-sized wafers (8-inch wafers), such as Figures 3-4 As shown, there will be a portion of the lower electrode ( Figure 3 When the brown area in the image is exposed to plasma, two consequences will occur: 1) The plasma will continuously bombard the exposed electrode surface, causing damage or penetration; 2) Deposits will continuously accumulate on the exposed surface, resulting in particulate pollution, etc. Summary of the Invention

[0003] The purpose of this invention is to provide a lower electrode for semiconductor devices that is compatible with multiple wafer sizes, including 8-inch and 12-inch wafers, and avoids plasma bombardment of the lower electrode. The technical solution adopted is as follows: A lower electrode for a semiconductor device compatible with multiple wafer sizes, comprising: The electrode body 1 has an annular groove 2 on its upper surface; the annular groove 2 is symmetrically arranged about the central axis of the electrode body 1. and a cover ring 3, which is adapted to the annular groove 2, and whose upper surface is not higher than the upper surface of the annular groove 2; Wherein, the annular groove 2 has an inner diameter r < 100 mm and an outer diameter R ≥ 104 mm; When the electrode body 1 receives the wafer 4, the wafer 4 is placed symmetrically about the central axis.

[0004] Preferably, the depth H of the annular groove 2 is ≥ 2 mm.

[0005] Preferably, the cover ring 3 is embedded in the annular groove 2.

[0006] Preferably, the cover ring 3 is made of insulating material.

[0007] Preferably, when the wafer 4 received by the electrode body 1 is an 8-inch wafer, the first limiting ring 5 covers the outer edge of the annular groove 2.

[0008] Preferably, when the wafer 4 supported by the electrode body 1 is a 16-inch wafer, the wafer 4 covers the annular groove 2.

[0009] Compared with the prior art, the advantages of the present invention are: It is compatible with 8-inch and 12-inch wafers and avoids electrodes under plasma bombardment. Attached Figure Description

[0010] Figure 1 This is a top view of the lower electrode in the prior art; Figure 2 This is a cross-sectional view of the lower electrode in the prior art; Figures 3-4 This is a schematic diagram of an 8-inch wafer placed in the prior art; Figures 5-6 This is a schematic diagram of a 12-inch wafer placed in the prior art; Figures 7-8 A structural diagram of the lower electrode for semiconductor devices compatible with multiple wafer sizes; Figure 9 This is a structural diagram of the annular groove; Figures 10-11 This is a schematic diagram showing the placement of an 8-inch wafer in this embodiment; Figures 12-13 This is a schematic diagram showing the placement of a 12-inch wafer in this embodiment.

[0011] Among them, 1-electrode body, 2-annular groove, 3-cap ring, 4-wafer, 5-first limiting ring, 6-second limiting ring. Detailed Implementation

[0012] The lower electrode for a semiconductor device compatible with multiple wafer sizes according to the present invention will now be described in more detail with reference to the schematic diagrams, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0013] like Figures 7-13 A lower electrode for semiconductor devices compatible with multiple wafer sizes includes: an electrode body 1, an annular groove 2, and a cover ring 3.

[0014] The electrode body 1 has an annular groove 2 on its upper surface; the annular groove 2 is symmetrically arranged about the central axis A of the electrode body 1. The cover ring 3 is adapted to the annular groove 2, and its upper surface is not higher than the upper surface of the annular groove 2; specifically, the cover ring 3 is embedded in the annular groove 2.

[0015] Among them, the annular groove 2 has an inner diameter r < 100 mm and an outer diameter R ≥ 104 mm; When the electrode body 1 receives the wafer 4, the wafer 4 is placed symmetrically about the central axis.

[0016] This semiconductor equipment can be used for semiconductor etching, resist removal, surface treatment, deposition, etc.

[0017] In this embodiment, as Figure 1 , Figure 7 As shown, the projection point A of the "central axis of electrode body 1" on electrode body 1 is the center point of electrode body 1.

[0018] The depth H of the annular groove 2 is ≥ 2 mm.

[0019] The cap ring 3 is made of ceramic or quartz.

[0020] like Figures 10-11 As shown, when the wafer 4 supported by the electrode body 1 is an 8-inch wafer, the first limiting ring 5 covers the outer edge of the annular groove 2.

[0021] When the outer diameter R of the annular groove 2 is greater than or equal to 104 mm, the first limiting ring 5 covers the outer edge of the annular groove 2. That is, the radial distance between the first limiting ring 5 and the 8-inch wafer is less than 4 mm.

[0022] In this embodiment, the "outer" direction is the direction away from the center point of the electrode body 1.

[0023] like Figures 12-13 As shown, when the wafer 4 held by the electrode body 1 is a 16-inch wafer, the wafer 4 covers the annular groove 2. The second limiting ring 6 surrounds the wafer.

[0024] The installation method between the first limiting ring 5, the second limiting ring 6 and the electrode body 1 is existing technology; The material composition of the first limiting ring 5 and the second limiting ring 6 is existing technology; The structure and material composition of electrode body 1 are also existing technologies.

[0025] In summary, the design principle of this invention is as follows: Based on existing technology: the diameter of an 8-inch wafer is 200mm.

[0026] Therefore, in this embodiment, a groove (annular groove 2) is dug in the 200 mm diameter area of ​​the electrode body, for example, 4 mm wide and 2 mm deep. Then, a pair of rings of the same shape are designed, with the height of the rings being equal to or slightly lower than the depth of the groove. The material can be ceramic, quartz, etc. Then, the rings are embedded in the groove of the electrode. In this way, when running an 8-inch wafer, the bombardment of the electrode body 1 by plasma is avoided.

[0027] Using the same design principle, if it is necessary to be compatible with 6-inch wafers, a groove needs to be cut in the electrode area with a diameter of 150 mm to place an insulating ring.

[0028] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A lower electrode for a semiconductor device compatible with multiple wafer sizes, characterized in that, include: The electrode body (1) has an annular groove (2) on its upper surface; the annular groove (2) is symmetrical about the central axis of the electrode body (1); and a cover ring (3), which is adapted to the annular groove (2), and its upper surface is not higher than the upper surface of the annular groove (2); The annular groove (2) has an inner diameter r < 100 mm and an outer diameter R ≥ 104 mm. When the electrode body (1) receives the wafer (4), the wafer (4) is placed symmetrically about the central axis; When the wafer (4) held by the electrode body (1) is an 8-inch wafer, the first limiting ring (5) covers the outer edge of the annular groove (2).

2. The lower electrode for a semiconductor device compatible with multiple wafer sizes according to claim 1, characterized in that, The depth H of the annular groove (2) is ≥2mm.

3. The lower electrode for a semiconductor device compatible with multiple wafer sizes according to claim 1, characterized in that, The cover ring (3) is embedded in the annular groove (2).

4. The lower electrode for a semiconductor device compatible with multiple wafer sizes according to claim 1, characterized in that, The cover ring (3) is made of insulating material.

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