Intelligent drive management method, system and device for power electronic converters

Abstract

The application provides a power electronic converter intelligent driving management method, system and device, the method comprising: receiving a control instruction, generating a PWM modulation strategy matched with a converter topology based on a preset multi-topology PWM modulation algorithm library; collecting the electrical and thermal parameters of a power device, calculating the junction temperature of the power device based on a preset junction temperature model; iteratively adjusting the gate resistance based on the PWM modulation strategy and the life loss model, and outputting an optimal gate resistance; generating a PWM driving signal and predicting the life of the converter based on the optimal gate resistance, the PWM modulation strategy and the junction temperature; the application can not only be directly called to reduce cross-platform transplantation costs, but also realize modulation and control oriented to the life constraints of each power device, reduce the life cycle cost of each power device, and achieve the balance between minimizing total power loss and maximizing safety.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology and relates to a method, system and device for intelligent drive management of power electronic converters. Background Technology

[0002] In fields such as industrial drives, new energy power generation, rail transit, and data center power distribution, power electronic converters based on power devices such as insulated-gate bipolar transistors (IGBTs), SiC MOSFETs, and gallium nitride (GaN) widely adopt a hierarchical system architecture. This hierarchical system architecture includes an upper-level controller layer and a discrete gate driver layer. The upper-level controller layer is responsible for control algorithm calculations and PWM duty cycle generation; the discrete gate driver layer is used to implement level conversion, isolation amplification, and basic protection functions. However, this hierarchical system architecture often suffers from the following technical defects in practical applications:

[0003] First, developers need to repeatedly design hardware circuits and customize modulation algorithms for different power topologies or application scenarios, which leads to a longer development cycle. In addition, mastering multi-scenario modulation strategies, protection mechanisms and thermal management technologies requires cross-domain professional knowledge, which increases the threshold for system development.

[0004] Secondly, existing solutions mostly rely on offline simulation calculations or NTC thermistors to estimate the average chip temperature, which cannot reflect the local hot spot temperature of the device in real time; life assessment is based on offline load model prediction, which is difficult to dynamically adapt to changes in actual operating conditions; over-reliance on safety margins leads to increased costs; insufficient margins may cause early device failure and affect system reliability.

[0005] Furthermore, PWM modulation, drive control, junction temperature assessment, lifespan management, and fault protection are distributed among the controller and discrete drive circuits, which increases the difficulty of software and hardware debugging due to the multi-module collaborative design, affects the protection response speed due to cross-level data transmission delay, and requires multi-stage linkage adjustment for fault diagnosis and parameter optimization. Summary of the Invention

[0006] The purpose of this application is to provide a method, system and device for intelligent drive management of power electronic converters, which can solve the problems of high system development cost, difficulty in dynamically adapting to changes in actual operating conditions and lack of multi-module collaborative control and parameter optimization in the prior art.

[0007] In a first aspect, this application provides a smart drive management method for a power electronic converter, the method comprising:

[0008] Receive control commands and generate a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library;

[0009] The electrothermal parameters of the power device are collected, and the junction temperature of the power device is calculated based on the preset junction temperature model and the lifetime loss model.

[0010] Based on the PWM modulation strategy and the lifetime loss model, the gate resistance is iteratively adjusted to output the optimal gate resistance;

[0011] A PWM drive signal is generated based on the optimal gate resistor, the PWM modulation strategy, and the junction temperature.

[0012] In one embodiment, the formula for calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model is as follows: ,in, For ambient temperature, This represents the total power loss of the power devices. For thermal resistance, This is the junction temperature.

[0013] In one embodiment, after calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model, the method further includes:

[0014] Based on the junction temperature, the PWM carrier frequency is dynamically adjusted or switched to a low-loss modulation mode.

[0015] In one embodiment, after collecting the electrothermal parameters of the power device and calculating the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model, the method further includes:

[0016] The remaining lifetime factor of the power device is calculated based on the junction temperature fluctuation data.

[0017] Predictive maintenance is performed based on the remaining lifetime coefficient.

[0018] In one embodiment, calculating the remaining lifetime factor of the power device based on junction temperature fluctuation data includes:

[0019] Obtain real data on the junction temperature change over time to form a continuous temperature fluctuation curve;

[0020] The temperature fluctuation curve is decomposed into independent thermal cycles using the rainflow counting method;

[0021] Obtain the fatigue life of the power device under the fluctuation amplitude of each thermal cycle;

[0022] The total damage to the power device from all thermal cycles is calculated using the linear cumulative loss method.

[0023] The remaining lifetime factor of the power device is calculated based on the total damage.

[0024] In one implementation, the receiving control command, based on a pre-set multi-topology PWM modulation algorithm library, generates a PWM modulation strategy that matches the converter topology, including:

[0025] The topology identifier in the control command is parsed, and the PWM modulation algorithm of the corresponding topology is called within a single carrier cycle according to the topology identifier to generate a PWM modulation strategy that matches the converter topology.

[0026] When the control command is a topology switching command, the PWM modulation algorithm switching is completed at the end of each carrier cycle or the current zero-crossing point.

[0027] In one implementation, the step of iteratively adjusting the gate resistor based on the PWM modulation strategy and the lifetime loss model to output the optimal gate resistor includes:

[0028] Obtain the modulation ratio and switching frequency of the PWM modulation strategy, and determine the initial gate resistor based on the mapping relationship between the modulation ratio and the switching frequency;

[0029] Based on the operating stage type of the power device, the initial gate resistance is adjusted using a differentiated resistance optimization method to obtain the gate optimized resistance for each operating stage.

[0030] The gate optimization resistors for each operating stage are input into the lifetime loss model to verify whether the lifetime loss rate of the power device is within the safe range, and the gate optimization resistors for each operating stage of the power device with a lifetime loss rate within the safe range are output as the optimal gate resistors.

[0031] Continue iteratively adjusting the gate optimization resistor for each operating stage where the lifetime decay rate is outside the safe range.

[0032] In one embodiment, adjusting the initial gate resistance using a differentiated resistance optimization method based on the operating stage type of the power device to obtain the gate-optimized resistance for each operating stage includes:

[0033] When the operating phase type of the power device is a loss-sensitive phase, the first gate resistor is used as the gate optimization resistor for the operating phase type.

[0034] When the operating phase type of the power device is the safe and stable phase, the second gate resistor is used as the gate optimization resistor for the operating phase type.

[0035] When the power device is in standby or off mode, a third gate resistor is used as the gate optimization resistor for the operating mode.

[0036] The resistance values ​​of the third gate resistor, the second gate resistor, and the first gate resistor decrease sequentially.

[0037] Secondly, this application provides an intelligent drive management system for a power electronic converter, the system comprising:

[0038] The PWM modulation strategy generation module is configured to receive control commands and generate a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library.

[0039] The junction temperature prediction module is configured to collect the electrothermal parameters of the power device and calculate the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model.

[0040] The gate resistance optimization module is electrically connected to the PWM modulation strategy generation module and the junction temperature prediction module, respectively, and is configured to iteratively adjust the gate resistance based on the PWM modulation strategy and the lifetime loss model, and output the optimal gate resistance.

[0041] The PWM drive signal generation module is electrically connected to the gate resistor optimization module and is configured to generate a PWM drive signal based on the optimal gate resistor, the PWM modulation strategy, and the junction temperature.

[0042] Thirdly, this application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.

[0043] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0044] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0045] As described above, the intelligent drive management method, system, and device for power electronic converters described in this application have the following beneficial effects:

[0046] One of the beneficial effects of this application is that it integrates various mature PWM algorithms such as SPWM, SVPWM, random PWM, and various DPWM into the chip, and allows for online switching between different topologies and modulation methods through parameter configuration, adapting to different application scenarios. This eliminates the need for the host computer to redevelop the underlying PWM algorithm, allowing for direct calls, reducing cross-platform porting costs, and enabling rapid product family development.

[0047] One of the beneficial effects of this application is that it integrates a pre-set junction temperature model and a lifetime loss model inside the chip, enabling the system to evaluate the lifetime loss and junction temperature changes of each power device online based on real-time information such as voltage, current, temperature, and gate resistance during operation. This achieves modulation and control of lifetime constraints for each power device, reduces the total life cycle cost of each power device, and solves the technical problem that existing technologies that rely solely on offline calculations or rough estimations cannot accurately grasp the lifetime loss and junction temperature changes of each power device.

[0048] One of the beneficial effects of this application is that it achieves a balance between minimizing total power loss and maximizing safety by adjusting and optimizing the gate resistors. Attached Figure Description

[0049] Figure 1 The diagram shown is a flowchart of an intelligent drive management method for a power electronic converter provided in an embodiment of this application.

[0050] Figure 2 The flowchart shows the method for collecting the electrothermal parameters of the power device provided in the embodiments of this application, and calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model.

[0051] Figure 3 The flowchart shown is a method for calculating the remaining lifetime factor of a power device based on junction temperature fluctuation data, as provided in an embodiment of this application.

[0052] Figure 4 The flowchart shown is a method for iteratively adjusting the gate resistor and outputting the optimal gate resistor based on a PWM modulation strategy and lifetime loss model, as provided in an embodiment of this application.

[0053] Figure 5 The diagram shows the voltage waveforms over time corresponding to different operating stages of the IGBT provided in this application embodiment.

[0054] Figure 6 The diagram shown is a structural block diagram of an intelligent drive management system for a power electronic converter provided in an embodiment of this application.

[0055] Figure 7 The electronic device shown is an embodiment of the present application.

[0056] Explanation of reference numerals in the accompanying drawings: 1. PWM modulation strategy generation module; 2. Junction temperature prediction module; 3. Gate resistance optimization module; 4. PWM drive signal generation module; 20. Electronic equipment; 21. Processor; 22. Memory; 23. Output interface; 24. Communication interface; 25. Antenna. Detailed Implementation

[0057] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0058] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] It should be noted that different application scenarios include motor drives, photovoltaic grid connection, energy storage converters, etc.

[0060] This embodiment is applicable to the gate drive control and status management of power devices in three-phase inverters, motor drive devices, photovoltaic grid-connected inverters, energy storage converters, and other types of AC / DC power conversion equipment.

[0061] To address the aforementioned technical challenges, this application proposes an intelligent drive management method, system, and device for power electronic converters. By integrating multiple mature PWM algorithms within the chip and enabling online switching between different topologies and modulation methods through parameter configuration, the system's adaptability to various application scenarios is improved. Simultaneously, a preset junction temperature model and lifetime loss model are integrated within the chip to online evaluate the lifetime loss and junction temperature changes of each power device, achieving modulation and control tailored to the lifetime constraints of each power device and reducing the total lifecycle cost of each device. Furthermore, by adjusting and optimizing the gate resistors, a balance is achieved between minimizing total power loss and maximizing safety.

[0062] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0063] like Figure 1 As shown in the figure, this embodiment provides a smart drive management method for power electronic converters, the method including:

[0064] Step 100: Receive control commands and generate a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library.

[0065] Specifically, the received control command generates a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library, including: parsing the topology identifier in the control command, calling the PWM modulation algorithm of the corresponding topology in a single carrier cycle according to the topology identifier, and generating a PWM modulation strategy that matches the converter topology.

[0066] When the control command is a topology switching command, the PWM modulation algorithm switching is completed at the end of each carrier cycle or the current zero-crossing point.

[0067] In some embodiments, the end point of the carrier cycle is the time when the PWM counter returns to zero, and the current zero-crossing point is the three-phase current zero-crossing point estimated by the Kalman filter with an error of <1μs.

[0068] In some embodiments, the topology identifier is a two-level, three-level NPC, a T-type NPC, or an active NPC.

[0069] In some embodiments, the PWM modulation algorithm includes SPWM, SVPWM, DPWM, RPWM, etc.

[0070] This embodiment solves the problem of redundant development of modulation algorithms for multiple scenarios by pre-installing a configurable PWM modulation algorithm library in the chip, supporting dynamic switching. This embodiment can also use a unified hardware interface to adapt to multi-level topologies, resolving the problem of repetitive hardware design across topologies.

[0071] In another exemplary embodiment, before generating a PWM modulation strategy that matches the converter topology, the method further includes: determining whether a system fault exists, such as overcurrent, overvoltage, overheating, or gate drive failure. If a fault is detected, the system enters a fault protection procedure, such as blocking the PWM output, cutting off the power supply, or issuing an alarm signal. If no fault is detected, the process continues to the next step.

[0072] Step 200: Collect the electrothermal parameters of the power device, and calculate the junction temperature of the power device based on the preset junction temperature model and lifetime loss model.

[0073] In some embodiments, the electrothermal parameters are the on-state voltage drop, off-state current, and case temperature of the power device.

[0074] In some embodiments, the electrothermal parameters are the converter AC voltage, converter AC current, switching frequency, ambient temperature, gate-on resistance value, and gate-off resistance value.

[0075] Specifically, the formula for calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model is as follows: ,in, For ambient temperature, This represents the total power loss of the power devices. For thermal resistance, This is the junction temperature.

[0076] In some embodiments, the lifetime loss model is as follows: = + .

[0077] For example, the formula for calculating the junction temperature of an IGBT is: ,in, This refers to the real-time junction temperature of the IGBT, specifically the temperature of the PN junction inside the IGBT chip, which directly affects the lifespan and reliability of the IGBT device. The ambient temperature is typically measured using a temperature sensor. This represents the total power loss of the IGBT, including turn-on losses. ), shutdown loss ( ) and conduction loss ( ); This indicates the overall heat dissipation capacity from the internal PN junction of the IGBT chip to the ambient air, i.e., the thermal resistance from the internal PN junction of the chip to the environment.

[0078] The formulas for the turn-on loss energy and power of IGBT are as follows: , ,in, This is a temperature correction factor. , The switching loss temperature interpolation factor is used. This refers to the junction temperature of the IGBT. For reference temperature; The activation energy under reference conditions; This is the gate resistance correction factor. , The gate resistor interpolation factor is used for turning on the gate. The actual gate resistance for activation. For reference gate resistance; The switching frequency; This is the interpolation factor for the gate resistance. Power loss during IGBT turn-on. Energy lost during IGBT turn-on.

[0079] The formula for the energy and power of IGBT turn-off losses is as follows: , ,in, The turn-off energy under reference conditions. This is a temperature correction factor. , The temperature interpolation factor for turn-off loss; This is the gate resistance correction factor. , The interpolation coefficient for the turn-off gate resistance is... This is the actual gate resistance for shutting off. The gate resistor is used as a reference for shutdown.

[0080] The conduction loss of IGBT is ,in, This refers to the collector-emitter voltage when the IGBT is turned on. This refers to the current when the IGBT is turned on. This refers to the IGBT's duty cycle, which is the ratio of the on-time to the switching cycle. Integration interval. This refers to the IGBT conduction time. Since the IGBT and diode conduct in a complementary manner, when the upper IGBT is on, the lower diode is off, and the conduction time is half a switching cycle.

[0081] In summary, the total power loss of the IGBT is .

[0082] For example, the formula for calculating the junction temperature of a diode is: ,in, This refers to the real-time junction temperature of the diode, specifically the temperature of the PN junction of the diode chip. For ambient temperature, and in the IGBT formula same; This represents the total power loss of the diode, including reverse recovery loss and conduction loss. The definition is the same as the IGBT formula, but it should be noted that in practical applications, the IGBT and diode... It may vary depending on the package location or heat dissipation path.

[0083] The calculation process for the reverse recovery loss of the diode is as follows:

[0084] First, the initial switching loss model of the diode is as follows: , The power loss of the diode switch is the energy consumed per second during the reverse recovery process. The switching cycle is the time it takes for the diode to turn on and off once. To indicate the summation sign, sum the reverse recovery energy over each switching cycle; The reverse recovery energy under reference conditions refers to the energy of a diode when the reference current is reached. Reference DC voltage The reverse recovery energy is generally obtained from a data table; For the reference current in the datasheet, measure The forward current condition at that time. For the reference DC voltage in the datasheet, measure... The DC voltage across the diode at that time. This is the actual operating forward current, the forward current when the diode is turned on; This is the actual operating DC voltage, the DC voltage across the diode when it is turned off.

[0085] Due to reference conditions It is a fixed value, but the actual operating current is... May not equal For example, when the load changes. The reverse recovery energy under the actual current can be corrected using the following formula:

[0086] ,in, Actual operating current The reverse recovery energy below, Actual operating current The correction factor reflects the nonlinear relationship between the reverse recovery energy and the increase of the actual operating current.

[0087] In summary, the reverse recovery loss of a diode ,in, This is the average current correction factor. For switching frequency, Number of times per second to switch on / off For reference, reverse recovery energy, This is the voltage correction factor.

[0088] For example, suppose the parameters of a diode are: , , ; , , The actual operating current is then... The correction factor is The voltage correction factor is The average current correction factor is The reverse recovery loss of the diode = .

[0089] Wherein, the conduction loss of the diode is , This refers to the conduction loss power of a diode, which is the energy consumed per second when the diode is forward-biased. This is the forward voltage of the diode. This is the forward current of the diode, that is, the current flowing through the diode when it is turned on. This refers to the diode's duty cycle. I is the diode's forward threshold voltage, and I is the diode's effective forward current. This is the forward resistance of the diode. The modulation ratio is the ratio of the fundamental amplitude of the output voltage to the DC bus voltage in PWM modulation. The power factor is the cosine of the phase difference between the fundamental output voltage and the fundamental current.

[0090] In summary, the diode conduction loss is = + .

[0091] For example, if the conduction loss The total loss is .

[0092] This embodiment integrates a pre-set junction temperature model and a lifetime loss model within the chip, enabling the system to evaluate the lifetime loss and junction temperature changes of each power device online based on real-time information such as voltage, current, temperature, and gate resistance during operation. This achieves modulation and control of lifetime constraints for each power device, reduces the total life cycle cost of each power device, and solves the technical problem that existing technologies that rely solely on offline calculations or rough estimations cannot accurately grasp the lifetime loss and junction temperature changes of each power device.

[0093] In some embodiments, after calculating the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model, the method further includes: dynamically adjusting the PWM carrier frequency or switching to a low-loss modulation mode based on the junction temperature.

[0094] Specifically, a pre-set warning threshold and a critical threshold are defined. When the junction temperature is between the warning threshold and the critical threshold, the PWM carrier frequency is reduced or the system is switched to a low-power modulation mode. When the junction temperature exceeds the critical threshold, the system is switched to a low-power modulation mode. The warning threshold is less than the critical threshold.

[0095] In some embodiments, the warning threshold and the critical threshold can be set according to the actual needs of those skilled in the art.

[0096] For example, this embodiment selects a three-phase motor drive device using a three-level NPC topology as the application scenario. The three-phase bridge arms use IGBT power modules, each phase containing four main switching transistors and two clamping diodes, the DC bus voltage is approximately 1100V, and the load is a medium-voltage induction motor. The three-phase bridge arms are driven by the gate drive logic signal output by the chip of this invention, which is amplified by an isolation driver. Assuming the warning threshold is 110℃, the critical threshold is 130℃, the thermal resistance is 0.25℃ / W, and the initial modulation mode is SVPWM.

[0097] Assuming the IGBT junction temperature is 118℃, which is greater than 110℃ but less than 130℃, the PWM carrier frequency is reduced. Assuming the junction temperature is 114℃ after reducing the PWM carrier frequency, which is greater than 110℃ but less than 130℃, the system is switched to low-power modulation mode, i.e., SVPWM is disabled and three-level DPWM mode is enabled.

[0098] This embodiment solves the problem of shortened system lifespan caused by excessive junction temperature under traditional fixed PWM carrier frequency by dynamically adjusting the PWM carrier frequency.

[0099] In another exemplary embodiment, such as Figure 2 As shown, the electrothermal parameters of the power device are collected. After calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model, the following steps are also included:

[0100] Step 210: Calculate the remaining lifetime factor of the power device based on the junction temperature fluctuation data.

[0101] Specifically, such as Figure 3 As shown, the remaining lifetime factor of the power device is calculated based on junction temperature fluctuation data, including:

[0102] Step 211: Obtain the actual data of the junction temperature change over time to form a continuous temperature fluctuation curve.

[0103] In some embodiments, this real data can be obtained through a temperature sensor.

[0104] In some embodiments, the sampling rate can be set to be greater than or equal to 10 Hz to ensure that details of temperature fluctuations, such as temperature changes corresponding to switching frequencies, are captured.

[0105] Step 212: Decompose the temperature fluctuation curve into independent thermal cycles using the rain flow counting method.

[0106] Specifically: Arrange the temperature fluctuation curves in chronological order, marking all peaks and troughs, where peaks are local maxima and troughs are local minima. Using rainflow counting, start from the first peak and stop when a higher peak is encountered, forming a closed loop. Record the fluctuation amplitude, peak value, and number of loops for each closed loop. Remove the counted loops and repeat the above process until all closed loops are extracted. For the unclosed portions of the curve, the beginning and end of the curve are usually connected to form a virtual loop. For example, if the temperature curve is "100℃→120℃→110℃→130℃→120℃", rainflow counting will extract two loops: 100→120→110, ΔT=20℃, and 110→130→120, ΔT=20℃, where ΔT is the fluctuation amplitude.

[0107] Step 213: Obtain the fatigue life of the power device under the fluctuation range of each thermal cycle.

[0108] In some embodiments, the fatigue life can be obtained by looking up a table or manual.

[0109] In some embodiments, the fatigue life can be obtained by thermal cycling test, which involves placing the power device in a temperature chamber, repeatedly heating and cooling it, and recording the number of cycles at failure. For example, the fluctuation range of an IGBT module is ΔT=50℃, the peak value is Tj,mean=100℃, and the number of cycles is Nf=1e5.

[0110] Step 214: Calculate the total damage to the power device from all thermal cycles using the linear cumulative loss method.

[0111] Specifically, the damage of each thermal cycle is the ratio of the number of cycles to the fatigue life under the fluctuation range. Therefore, the formula for calculating the total damage of all thermal cycles to the power device is: Where D is the total damage, 0≤D≤1, and when D=1, the power device fails; m is the number of thermal cycle types, i.e., thermal cycles under different fluctuation amplitudes; Let be the number of the i-th type of thermal cycle; Let be the fatigue life corresponding to the i-th thermal cycle.

[0112] For example, if there are two thermal cycles, i.e. ΔT = 20℃, n1 = 1e4 times, N f1 =1e5 times, ΔT=30℃, n2=5e3 times, N f2 =5e4 times, then the total damage D=(1e4 / 1e5)+(5e3 / 5e4)=0.1+0.1=0.2 (that is, 20% damage).

[0113] Step 215: Calculate the remaining lifetime factor of the power device based on the total damage.

[0114] Specifically, the remaining lifetime factor of this power device is expressed as L. rem =1-D, where when D≤1, L rem This represents the remaining lifespan factor.

[0115] For example, when the total damage D=0.2, L rem =0.8, meaning 80% of the lifespan remains.

[0116] This embodiment predicts the remaining lifetime coefficient of power devices by using thermal fatigue cumulative damage, thus solving the problems of poor accuracy and low real-time performance of existing lifetime prediction methods.

[0117] Step 220: Perform predictive maintenance based on the remaining lifetime coefficient.

[0118] In some embodiments, this predictive maintenance can be setting an over-temperature protection threshold and a soft shutdown rate.

[0119] Specifically, the over-temperature protection threshold is set smaller as the remaining lifetime coefficient decreases, and the soft shutdown rate is slowed down as the remaining lifetime coefficient decreases, in order to reduce thermal stress.

[0120] The mathematical expression for the over-temperature protection threshold is: , Let be the initial maximum temperature of the power device. The mathematical expression for the soft turn-off rate is: .

[0121] For example, suppose a three-phase motor drive device with a certain three-level NPC topology is a brand new device, i.e. =1, =150℃, at this time =150℃ =50A / μs. Assuming a three-phase motor drive with a certain three-level NPC topology uses a micro-aging device, i.e. =0.8, at this time, =144℃ =45A / μs.

[0122] This embodiment converts junction temperature fluctuation data into a remaining lifetime coefficient and uses this to dynamically reconstruct the protection system, enabling power electronic devices to upgrade from fixed protection to lifetime adaptive protection. This solves the core contradiction in traditional solutions where new devices are overprotected and aging devices are underprotected.

[0123] Step 300: Based on the PWM modulation strategy and the junction temperature, iteratively adjust the gate resistance and output the optimal gate resistance.

[0124] Specifically, such as Figure 4 As shown, based on the PWM modulation strategy and the lifetime loss model, the gate resistor is iteratively adjusted to output the optimal gate resistor, including:

[0125] Step 301: Obtain the modulation ratio and switching frequency of the PWM modulation strategy, and determine the initial gate resistor based on the mapping relationship between the modulation ratio and the switching frequency.

[0126] Specifically, the modulation ratio is the ratio of the effective value of the output AC voltage to the DC bus voltage. The switching frequency is the reciprocal of the PWM waveform period. This mapping relationship can be obtained by looking up the mapping rule table.

[0127] In some embodiments, the modulation ratio can be obtained by directly reading the modulation ratio register of the PWM controller; the switching frequency can be obtained by directly reading the switching frequency register of the PWM controller or by measuring the period of the PWM waveform with an oscilloscope and calculating the reciprocal.

[0128] Step 302: Based on the operating stage type of the power device, the initial gate resistor is adjusted using a differentiated resistance optimization method to obtain the gate optimized resistance for each operating stage.

[0129] Specifically, based on the operating stage type of the power device, a differentiated resistance optimization method is used to adjust the initial gate resistor to obtain the gate-optimized resistor for each operating stage, including: when the operating stage type of the power device is a loss-sensitive stage, a first gate resistor is used as the gate-optimized resistor for that operating stage type; when the operating stage type of the power device is a safe and stable stage, a second gate resistor is used as the gate-optimized resistor for that operating stage type; when the operating stage type of the power device is a standby or shutdown stage, a third gate resistor is used as the gate-optimized resistor for that operating stage type.

[0130] The resistance values ​​of the third gate resistor, the second gate resistor, and the first gate resistor decrease sequentially.

[0131] Among them, the loss-sensitive stage is the turn-on transition period when the gate voltage is at the threshold voltage to the Miller plateau, or the turn-off transition period after receiving a turn-off command; the safe and stable stage is the voltage rise period after the turn-on command is issued or the stable period when the power device enters saturation conduction; the standby or turn-off stage is the standby state after the system is powered on without operation, the power device is completely turned off, or after a fault reset.

[0132] Step 303: Input the gate optimization resistors for each operating stage into the lifetime loss model.

[0133] Step 304: Determine whether the lifespan loss rate of the power device is within a safe range.

[0134] Step 305: Output the gate optimization resistors for each operating stage of the power device with a lifetime wear rate within a safe range as the optimal gate resistors.

[0135] Step 306: Continue iteratively adjusting the gate optimization resistor for each operating stage where the lifetime decay rate is outside the safe range.

[0136] This embodiment, by linking with lifetime loss and junction temperature estimation results, can achieve a real-time trade-off between efficiency, overshoot, electromagnetic interference, and device safety, thereby improving system efficiency and reducing electromagnetic interference.

[0137] For example, the gate resistance optimization strategy for the entire life cycle of an IGBT switch:

[0138] Stage E: When the system is powered on or without a switching command, the maximum gate resistance RgE is selected. At this time, the gate voltage can be set to 0V-15V to ensure reliable IGBT turn-off and prevent accidental turn-on.

[0139] Phase A: When the system receives the turn-on command, a medium gate resistor RgA is selected; at this time, the gate voltage Vge rises rapidly to the IGBT threshold voltage Vth to control the gate current rise rate and avoid excessive gate current damaging the gate oxide layer; at the same time, the turn-on delay is kept within a reasonable range.

[0140] Stage B: When the gate voltage Vge is greater than or equal to the IGBT threshold voltage Vth, the minimum gate resistor RgB is selected, and the gate voltage Vge stagnates at the Miller plateau voltage. At this time, the IGBT enters the voltage-to-current conversion region. Through the minimum gate resistor RgB, the gate charging speed is accelerated, and the turn-on loss is minimized.

[0141] Stage C: When the gate voltage Vge is less than or equal to the IGBT's saturation state, i.e., the voltage between the collector and emitter drops to the saturation voltage drop Vce_sat, a medium gate resistor RgC is selected. The gate voltage Vge rises to +15V and remains stable. Selecting a medium gate resistor RgC can balance the gate's anti-interference capability and conduction margin, avoid false turn-off due to gate noise, and maintain the IGBT in the saturation region with low conduction losses.

[0142] Stage D: Upon receiving the shutdown command, the minimum gate resistance RgD is selected. As the gate voltage Vge rapidly drops to the Miller plateau voltage, the IGBT enters the current-to-voltage transition region, meaning the collector current Ic drops from the load current to 0, and Vce rises from the saturation voltage drop Vce_sat to the bus voltage. By reducing RgD, the gate discharge speed is accelerated, minimizing shutdown losses.

[0143] Stage E: When the gate voltage Vge drops to the DC bus voltage Vdc, the IGBT is completely turned off. A larger gate resistor RgE is selected, causing the gate voltage Vge to drop from the Miller plateau to -15V (negative bias) and remain stable. Setting a larger gate resistor RgE slows down the gate discharge rate, preventing false turn-on due to gate voltage Vge fluctuations. Simultaneously, the negative bias ensures the IGBT's anti-interference capability in the off-state.

[0144] In another exemplary embodiment, when overcurrent or overvoltage is detected in stage B or stage D, the system immediately switches to the ultra-large turn-off resistor Rg_soft to achieve soft turn-off, slowing down the gate discharge rate and reducing the rate of Ic decline, thereby preventing IGBT breakdown. After the soft turn-off is completed, the system enters stage E and locks the fault state until an external reset command is received.

[0145] This application optimizes turn-on and turn-off losses by using minimum resistance in loss-sensitive areas such as stages B and D of the IGBT switching process, and uses medium or large resistance to ensure stability in safety-sensitive areas such as stages A, C and E. At the same time, it achieves the driving goals of low loss, high safety and high reliability through fault soft turn-off.

[0146] For example, RgE can be selected as 10~22Ω, RgA can be selected as 10~15Ω, Vth can be selected as 5~6V, the minimum turn-on resistance RgB can be selected as 1~5Ω, the medium gate resistance RgC can be selected as 15~22Ω, the Miller plateau voltage is 7~9V, and the larger gate resistance RgE is 10~22Ω.

[0147] The waveforms of the voltage changes over time for the corresponding stages A to E of the IGBT in the above embodiments are as follows: Figure 5 As shown.

[0148] This embodiment breaks down the IGBT's turn-on, turn-on, and turn-off processes into five key stages, dynamically switching the gate resistor in each stage to achieve a balance between minimizing total power loss and maximizing safety.

[0149] Step 400: Generate a PWM drive signal based on the optimal gate resistor, the PWM modulation strategy, and the junction temperature.

[0150] This embodiment solves the problem of response delay caused by the dispersion of protection functions through closed-loop control of junction temperature prediction, gate resistance optimization, loss reduction, and junction temperature drop.

[0151] The scope of protection of the intelligent drive management method for power electronic converters described in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, deleting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0152] This application also provides an intelligent drive management system for power electronic converters. The intelligent drive management system for power electronic converters can implement the intelligent drive management method for power electronic converters described in this application. However, the implementation device of the intelligent drive management method for power electronic converters described in this application includes, but is not limited to, the structure of the intelligent drive management system for power electronic converters listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principles of this application are included within the protection scope of this application.

[0153] like Figure 6As shown, this embodiment provides an intelligent drive management system for a power electronic converter. The system includes: a PWM modulation strategy generation module 1, configured to receive control commands and generate a PWM modulation strategy matching the converter topology based on a preset multi-topology PWM modulation algorithm library; a junction temperature prediction module 2, configured to collect the electrothermal parameters of the power device and calculate the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model; a gate resistance optimization module 3, electrically connected to the PWM modulation strategy generation module 1 and the junction temperature prediction module 2 respectively, configured to iteratively adjust the gate resistance based on the PWM modulation strategy and the lifetime loss model, and output the optimal gate resistance; and a PWM drive signal generation module 4, electrically connected to the gate resistance optimization module 3, configured to generate a PWM drive signal based on the optimal gate resistance, the PWM modulation strategy, and the junction temperature.

[0154] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0155] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0156] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] In one exemplary embodiment, this embodiment also provides an electronic device, including a memory and a processor, wherein the memory stores a program that can run on the processor, and when the program is executed by the processor, the electronic device performs any of the methods described in the above embodiments.

[0158] In one possible embodiment, such as Figure 7 As shown, the electronic device 20 also includes: an output interface 23 for outputting results; a communication interface 24 for transmitting communication signals; and an antenna 25 for transmitting or receiving signals.

[0159] It should be noted that the processor 21 in this embodiment can be an image processing chip or an integrated circuit chip, capable of processing image signals. In implementation, each step of the above method embodiment can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices. It can implement or execute the methods, steps, and logic block diagrams disclosed in this embodiment. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this embodiment can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0160] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0161] In one exemplary embodiment, this embodiment also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.

[0162] In one exemplary embodiment, this embodiment also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0163] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0164] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0165] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for intelligent drive management of a power electronic converter, characterized in that, The method includes: Receive control commands and generate a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library; The electrothermal parameters of the power device are collected, and the junction temperature of the power device is calculated based on the preset junction temperature model and the lifetime loss model. Based on the PWM modulation strategy and the lifetime loss model, the gate resistance is iteratively adjusted to output the optimal gate resistance; Based on the optimal gate resistance, the PWM modulation strategy, and the junction temperature, a PWM drive signal is generated. The step of iteratively adjusting the gate resistor based on the PWM modulation strategy and the lifetime loss model to output the optimal gate resistor includes: Obtain the modulation ratio and switching frequency of the PWM modulation strategy, and determine the initial gate resistor based on the mapping relationship between the modulation ratio and the switching frequency; Based on the operating stage type of the power device, the initial gate resistance is adjusted using a differentiated resistance optimization method to obtain the gate optimized resistance for each operating stage. The gate optimization resistors for each operating stage are input into the lifetime loss model to verify whether the lifetime loss rate of the power device is within the safe range, and the gate optimization resistors for each operating stage of the power device with a lifetime loss rate within the safe range are output as the optimal gate resistors. Continue iteratively adjusting the gate optimization resistor for each operating stage where the lifetime decay rate is outside the safe range.

2. The method according to claim 1, characterized in that, The formula for calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model is as follows: ,in, For ambient temperature, This represents the total power loss of the power devices. For thermal resistance, This is the junction temperature.

3. The method according to claim 2, characterized in that, After calculating the junction temperature of the power device based on the preset junction temperature model and the lifetime loss model, the method further includes: Based on the junction temperature, the PWM carrier frequency is dynamically adjusted or switched to a low-loss modulation mode.

4. The method according to claim 2, characterized in that, After collecting the electrothermal parameters of the power device and calculating the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model, the method further includes: The remaining lifetime factor of the power device is calculated based on the junction temperature fluctuation data. Based on the remaining lifetime coefficient, the over-temperature protection threshold and soft shutdown rate are adaptively adjusted.

5. The method according to claim 4, characterized in that, The step of calculating the remaining lifetime factor of the power device based on junction temperature fluctuation data includes: Obtain real data on the junction temperature change over time to form a continuous temperature fluctuation curve; The temperature fluctuation curve is decomposed into independent thermal cycles using the rainflow counting method; Obtain the fatigue life of the power device under the fluctuation amplitude of each thermal cycle; The total damage to the power device from all thermal cycles is calculated using the linear cumulative loss method. The remaining lifetime factor of the power device is calculated based on the total damage.

6. The method according to claim 1, characterized in that, The received control command, based on a pre-set multi-topology PWM modulation algorithm library, generates a PWM modulation strategy that matches the converter topology, including: The topology identifier in the control command is parsed, and the PWM modulation algorithm of the corresponding topology is called within a single carrier cycle according to the topology identifier to generate a PWM modulation strategy that matches the converter topology. When the control command is a topology switching command, the PWM modulation algorithm switching is completed at the end of each carrier cycle or the current zero-crossing point.

7. The method according to claim 1, characterized in that, The initial gate resistance is adjusted using a differentiated resistance optimization method based on the operating stage type of the power device to obtain the gate optimized resistance for each operating stage, including: When the operating phase type of the power device is a loss-sensitive phase, the first gate resistor is used as the gate optimization resistor for the operating phase type. When the operating phase type of the power device is the safe and stable phase, the second gate resistor is used as the gate optimization resistor for the operating phase type. When the power device is in standby or off mode, a third gate resistor is used as the gate optimization resistor for the operating mode. The resistance values ​​of the third gate resistor, the second gate resistor, and the first gate resistor decrease sequentially.

8. A smart drive management system for a power electronic converter, characterized in that, The system includes: The PWM modulation strategy generation module is configured to receive control commands and generate a PWM modulation strategy that matches the converter topology based on a pre-set multi-topology PWM modulation algorithm library. The junction temperature prediction module is configured to collect the electrothermal parameters of the power device and calculate the junction temperature of the power device based on a preset junction temperature model and a lifetime loss model. The gate resistance optimization module, electrically connected to both the PWM modulation strategy generation module and the junction temperature prediction module, is configured to iteratively adjust the gate resistance based on the PWM modulation strategy and the lifetime loss model, and output an optimal gate resistance. This iterative adjustment includes: obtaining the modulation ratio and switching frequency of the PWM modulation strategy; determining an initial gate resistance based on the mapping relationship between the modulation ratio and the switching frequency; adjusting the initial gate resistance using a differentiated resistance optimization method according to the operating stage type of the power device to obtain the optimized gate resistance for each operating stage; inputting the optimized gate resistance for each operating stage into the lifetime loss model to verify whether the lifetime loss rate of the power device is within a safe range, and outputting the optimized gate resistance for each operating stage corresponding to power devices with lifetime loss rates within a safe range as the optimal gate resistance; and continuing to iteratively adjust the optimized gate resistance for each operating stage where the lifetime loss rate is not within a safe range. The PWM drive signal generation module is electrically connected to the gate resistor optimization module and is configured to generate a PWM drive signal based on the optimal gate resistor, the PWM modulation strategy, and the junction temperature.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

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