Low-overhead three-node flip-tolerant latch circuit and memory chip thereof

Abstract

This invention relates to the field of integrated circuits, and in particular to a low-overhead three-node flip-tolerant latch circuit and its memory chip. The latch circuit includes a memory circuit, an error isolation circuit, an input circuit, and an output circuit. The memory circuit has a dual-node flip-to-recovery function and includes three sets of redundant memory nodes reinforced with polarity. Two of the positive and negative memory nodes share pull-up PMOS transistors. The error isolation circuit includes a dual-input C-cell and a clocked dual-input C-cell. The former takes two positive memory nodes as inputs, and its output and any one of the negative memory nodes serve as the inputs to the latter, which is used to output stored data. The input circuit is used to set the memory nodes; the output circuit is used to achieve data pass-through when the error isolation circuit is turned off. This invention solves the problem that radiation-hardened memories struggle to improve flip-to-recovery performance while maintaining circuit power consumption and speed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a low-overhead three-node flip-tolerant latch circuit and its memory chip. Background Technology

[0002] In the space environment, high-energy particles and radiation can bombard integrated circuits, causing them to malfunction and affecting the normal operation of electronic devices. Damage to electronic devices and systems caused by space radiation has become a significant challenge in the aerospace field. Currently, latch circuits are widely used in integrated circuits, but they are susceptible to single-event effects, particularly single-event flips that cause memory node flips, thus affecting the reliability of memory chips. Engineers have conducted extensive research on the radiation resistance of latch circuits, exploring solutions and new technologies to improve their reliability in the space radiation environment. Existing technologies for latch designs to resist two-node or three-node flips mainly include the following typical solutions: In 2020, Watkins and Tragoudas proposed a three-node flip-tolerant latch (TNU-latch) based on C cells, such as... Figure 1 As shown, this latch comprises five four-input C cells interconnected end-to-end to form a core storage ring. The input of each C cell is taken from the outputs of the other four nodes within the ring, forming an internal interlock. The output employs a two-stage C cell structure for error isolation. The four-input interlock mechanism ensures that the flipping of any three nodes does not affect the state of the internal C cells. The two-stage output structure ensures correct final output through redundant paths, achieving complete tolerance for three-node flipping. However, this design uses a redundant structure of twelve C cells, significantly increasing the number of circuit nodes and interconnection complexity, resulting in large area overhead and higher power consumption and latency. Furthermore, after multiple node flips, some nodes cannot recover, causing internal nodes to enter a high-impedance state.

[0003] In 2023, Chen et al. proposed a three-node flip-flop tolerating latch (TTLL) for a dual-ring interlock and output recovery module, such as... Figure 2 As shown, the structure includes two interlocking loops (each containing two dual-input C units and two clock-controlled dual-input C units) and a two-stage error isolation module, storing input signals through four parallel transmission gates. In the event of a multi-node flip, the interlocking loops ensure that at least one C unit input is correct, and the output module blocks fault propagation through two stages of C units (CE5, CE6). Output node flips can be quickly recovered, achieving complete three-node flip tolerance. Clock gating is used to achieve lower latency, but this structure uses 16 C units, increasing area overhead and design complexity while improving reliability.

[0004] In 2023, Liu et al. proposed a three-node flip-tolerant latch (KOBE) based on critical node flip-blocking, such as... Figure 3 As shown, this circuit employs clock-gated input inverter pairs (CG-IP) and clock-gated input split inverters (CG-IINV), achieving TNU tolerance through a non-redundant single feedback loop. The mechanism is as follows: in hold mode, the CG-IP activates a single path, combined with the output of the CG-IINV. When multiple node flips occur, the affected nodes recover through complementary nodes and the single feedback loop, outputting a high-impedance state to block error propagation. This design uses 32 transistors, achieving full TNU fault tolerance while reducing area, power consumption, and delay. However, the non-redundant structure is unstable under extreme process and voltage conditions, and the node layout is susceptible to charge-sharing effects.

[0005] In 2023, Bai Na et al. proposed a dual-node flip-flop self-recovery latch (DRLW) based on a clock-gated recovery array, such as... Figure 4 As shown, this latch uses an interconnect array of 4×2 C-cells (CE) and clock-gated C-cells (CG-CE), achieving full-node DNU self-recovery through complete inter-column interlocking and input / output node combination. When a DNU occurs in different columns, the error isolation function of the C-cells ensures that the flipped node does not affect other nodes and is recovered; self-recovery is also achieved when a DNU occurs at the same CE input. This structure employs a large number of redundant C-cells, resulting in a large area overhead due to the high number of transistors.

[0006] It is evident that resisting two-node or three-node flip-flops often requires complex circuit structure design, which leads to increased circuit area, power consumption, and delay. Therefore, how to provide a latch circuit with stronger anti-flip performance and more balanced performance has become a technical problem that urgently needs to be solved in the aerospace field. Summary of the Invention

[0007] To address the challenge of achieving a balance between anti-flip performance, power consumption, and speed in radiation-resistant memories, this invention provides a low-overhead three-node flip-tolerant latch circuit and its memory chip.

[0008] The technical solution provided by this invention is as follows: A low-overhead three-node flip-tolerant latch circuit includes: a storage circuit, an error isolation circuit, an input circuit, and an output circuit.

[0009] The storage circuit features a dual-node flip-over self-recovery function, comprising three redundant sets of positive-phase storage nodes S0, S2, and S4, all reinforced with N-polarity, and three redundant sets of negative-phase storage nodes S1, S3, and S5. In a typical scheme, each N-polarity reinforced storage node consists of a pull-up PMOS transistor, a pull-up NMOS transistor, and a pull-down NMOS transistor. However, in this invention, any two positive-phase storage nodes share the same pull-up PMOS transistor, while the other uses an independent pull-up PMOS transistor; similarly, any two negative-phase storage nodes also share the same pull-up PMOS transistor, while the other uses an independent pull-up PMOS transistor.

[0010] The error isolation circuit includes one dual-input C unit CE1 and one clock-controlled dual-input C unit CG-CE1. Two inputs of CE1 are connected to any two non-inverting storage nodes, and the output of CE1 is connected to one of the inputs of CG-CE1. The other input of CG-CE1 is connected to any one of the inverting storage nodes. For example, when the stored data is 1 / 0, storage nodes S0, S2, and S4 are non-inverting storage nodes, storing 1 / 0 data, and the two inputs of CE1 are connected to any two of these three storage nodes; storage nodes S1, S3, and S5 are inverting storage nodes, storing 0 / 1 data, and one of the inputs of CG-CE1 is connected to any one of these three storage nodes. The control terminal of CG-CE1 is connected to the clock signal CLK, and the output of CG-CE1 is used to output the stored data.

[0011] The input circuit is used to set the storage nodes S0~S5 in the storage circuit according to the input signal; the output circuit is connected in parallel between the input terminal of the input circuit and the output terminal of the error isolation circuit to realize data pass-through when CG-CE1 is turned off.

[0012] As a further improvement of the present invention, the storage circuit includes four PMOS transistors P1~P4 and twelve NMOS transistors N1~N12; the circuit connection is as follows: The sources of P1~P4 are connected to the power supply; the drain of P1 is connected to the drains of N1 and N3; the source of N1 is connected to the drain of N2 and serves as storage node S0; the source of N3 is connected to the drain of N4 and serves as storage node S2; the drain of P2 is connected to the drains of N5 and N7; the source of N5 is connected to the drain of N6 and serves as storage node S1; the source of N7 is connected to the drain of N8 and serves as storage node S3; the drain of P3 is connected to the drain of N9; the source of N9 is connected to the drain of N10. P4 is connected to the drain of N11; the source of N11 is connected to the drain of N12 and serves as storage node S5; the sources of N2, N4, N6, N8, N10, and N12 are grounded; the gates of P2, P4, and N3 are connected to S0; the gates of N2, N7, and N10 are connected to S1; the gates of N6, N9, and N12 are connected to S2; the gates of P1, P3, and N11 are connected to S3; the gates of N1 and N8 are connected to S4; and the gates of N4 and N5 are connected to S5.

[0013] As a further improvement of the present invention, the dual-input C unit CE1 includes two PMOS transistors P5 and P6 and two NMOS transistors N19 and N20. The source of P5 is connected to the power supply; the drain of P5 is connected to the source of P6; the drain of P6 is connected to the drain of N19 and serves as the output terminal of CE1; the source of N19 is connected to the drain of N20; the source of N20 is grounded; the gates of P5 and N19 are connected and serve as one of the input terminals of CE1; the gates of P6 and N20 are connected and serve as the other input terminal of CE1.

[0014] As a further improvement of the present invention, the clock-controlled dual-input C unit CG-CE1 includes three PMOS transistors P7~P9 and three NMOS transistors N21~N23. The source of P7 is connected to the power supply; the drain of P7 is connected to the source of P8; the drain of P8 is connected to the source of P9; the drain of P9 is connected to the drain of N21 and serves as the output terminal of CG-CE1; the source of N21 is connected to the drain of N22; the source of N22 is connected to the drain of N23; the drain of N23 is grounded; the gates of P7 and N22 are connected and serve as one input terminal of CG-CE1; the gates of P8 and N23 are connected and serve as the other input terminal of CG-CE1; the gate of P9 is connected to the clock signal CLK; the gate of N21 is connected to the inverted signal NCK of CLK.

[0015] As a further improvement of the present invention, the input circuit includes six NMOS transistors N13~N18 and an inverter INV1; the drains of N13~N18 are connected to S0~S5 respectively; the gates of N13~N18 are connected to CLK; the sources of N13~N15 are connected to the input terminal of the inverter and serve as the input terminal for receiving the input signal D; the sources of N16~N18 are connected to the output terminal of INV1 to receive the inverted signal DN of D.

[0016] As a further improvement of the present invention, the output circuit includes a transmission gate TG1, the input terminal of which is connected to the input terminal of the input circuit; the output terminal of TG1 is connected to the output terminal of the error isolation circuit.

[0017] As a further improvement of the present invention, the transmission gate TG1 is composed of an NMOS transistor N26 and a PMOS transistor P12; the drains of N26 and P12 are connected to the input terminals of the input circuit. The sources of N26 and P12 are connected to the output terminals of CG-CE1. The gate of N26 is connected to CLK; the gate of P12 is connected to the inverted signal NCK of CLK.

[0018] As a further improvement of the present invention, the low-overhead three-node flip-tolerance latch circuit also includes an inverter INV2, which is used to generate its inverted signal NCK based on the clock signal CLK, so as to achieve coordinated adjustment of the operating modes of the error isolation circuit, the input circuit and the output circuit.

[0019] As a further improvement of the present invention, in the low-overhead three-node flip-tolerant latch circuit, when CLK = 1 and NCK = 0, the latch circuit is in transparent mode. At this time, TG1 and N13~N18 are turned on, and CG-CE1 is turned off; the input signal D and its inverted signal DN respectively rewrite the level state of the corresponding storage node through N13~N18; and TG1 directly transmits the input signal D and uses it as the output signal Q.

[0020] When CLK = 0 and NCK = 1, the latch circuit is in hold mode. At this time, TG1 and N13~N18 are turned off, and CG-CE1 is turned on; TG1 is turned off; the transmission path between each storage node of the latch circuit and the input signal is disconnected; the stored data of each storage node of the storage circuit is processed by error isolation to obtain the output signal Q.

[0021] The present invention also includes a memory chip that uses the aforementioned low-overhead three-node flip-tolerant latch circuit as a memory cell.

[0022] The present invention has the following beneficial effects: The low-overhead three-node flip-tolerant latch circuit provided by this invention employs polarity hardening technology in the storage circuit to design a special circuit structure with dual-node flip-tolerance self-recovery function. This storage circuit has three sets of mutually locked and redundant positive and negative storage nodes, and the storage circuit shares pull-up PMOS transistors in some storage nodes. This circuit structure reduces the number of sensitive nodes and improves the circuit's radiation resistance. Furthermore, it can be used in conjunction with the two-stage C-cell in the error isolation circuit to isolate storage nodes, thereby enabling the latch circuit to tolerate three-node flip-tolerance. In addition, the latch circuit designed in this invention has significant advantages in power consumption, delay, and power-delay-area product (PDAP), and exhibits low sensitivity to voltage and temperature fluctuations.

[0023] The circuit design provided by this invention can achieve the most comprehensive circuit performance with fewer transistors, effectively reducing the circuit area. Furthermore, the overall circuit exhibits improvements over existing circuits in terms of area, power consumption, delay, PDAP, and overall radiation resistance. This memory circuit can be applied to memory chips with stronger radiation resistance and has broad application prospects in the aerospace field. Attached Figure Description

[0024] Figure 1 This is the schematic diagram of the TNU-latch circuit mentioned in the background section of this invention.

[0025] Figure 2 This is the schematic diagram of the TTLL circuit mentioned in the background section of this invention.

[0026] Figure 3 This is the schematic diagram of the KOBE circuit mentioned in the background section of this invention.

[0027] Figure 4 The schematic diagram of the DRLW circuit mentioned in the background art of this invention.

[0028] Figure 5 This is a circuit diagram of the low-overhead three-node flip-tolerant latch circuit provided in Embodiment 1 of the present invention.

[0029] Figure 6 for Figure 5 The diagram shows one of the typical circuit diagrams of a latching circuit.

[0030] Figure 7 The circuit diagram shows the dual-input C unit CE1 and the clock-controlled dual-input C unit CG-CE1 used in the latch circuit of Embodiment 1 of the present invention.

[0031] Figure 8 For performance testing experiments, Figure 6 The circuit shown is illustrated in the signal timing diagram during normal operation.

[0032] Figure 9 For performance testing experiments, Figure 6 The circuit shown is a signal timing diagram for testing single-node and dual-node bombardment.

[0033] Figure 10 For performance testing experiments, Figure 6 The circuit shown is a signal timing diagram when tested with three-node bombardment. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] Example 1

[0037] This embodiment provides a low-overhead three-node flip-tolerant latch circuit, such as... Figure 5 As shown, it includes a storage circuit, an error isolation circuit, an input circuit, and an output circuit. The storage circuit has a dual-node flip-over self-recovery function, comprising three sets of redundant positive storage nodes S0, S2, and S4, all hardened with N-polarity, and three sets of redundant negative storage nodes S1, S3, and S5. In a typical scheme, each N-polarity hardened storage node consists of a pull-up PMOS transistor, a pull-up NMOS transistor, and a pull-down NMOS transistor; the source of the pull-up PMOS transistor is connected to the power supply VDD; the drain of the pull-up PMOS transistor is connected to the drain of the pull-up NMOS transistor; the source of the pull-up NMOS transistor is connected to the drain of the pull-down NMOS transistor and serves as the storage node; the source of the pull-down NMOS transistor is grounded to VSS. Specifically, in the storage circuit provided by this invention, any two positive storage nodes share the same pull-up PMOS transistor, while the other uses an independent pull-up PMOS transistor; any two negative storage nodes also share the same pull-up PMOS transistor, while the other uses an independent pull-up PMOS transistor.

[0038] In a typical embodiment, the storage circuit includes four PMOS transistors P1-P4 and twelve NMOS transistors N1-N12. For example... Figure 6 As shown, the circuit connections of the storage circuit are as follows: The sources of P1~P4 are connected to the power supply; the drain of P1 is connected to the drains of N1 and N3; the source of N1 is connected to the drain of N2 and serves as storage node S0; the source of N3 is connected to the drain of N4 and serves as storage node S2; the drain of P2 is connected to the drains of N5 and N7; the source of N5 is connected to the drain of N6 and serves as storage node S1; the source of N7 is connected to the drain of N8 and serves as storage node S3; the drain of P3 is connected to the drain of N9; the source of N9 is connected to the drain of N10. P4 is connected to the drain of N11; the source of N11 is connected to the drain of N12 and serves as storage node S5; the sources of N2, N4, N6, N8, N10, and N12 are grounded; the gates of P2, P4, and N3 are connected to S0; the gates of N2, N7, and N10 are connected to S1; the gates of N6, N9, and N12 are connected to S2; the gates of P1, P3, and N11 are connected to S3; the gates of N1 and N8 are connected to S4; and the gates of N4 and N5 are connected to S5.

[0039] It should be noted that, in Figure 6 In the typical scheme shown, the positive-phase memory nodes S0 and S2, which employ an N-polarity hardened structure, share a pull-up PMOS transistor P1; the negative-phase memory nodes S1 and S3, which also employ an N-polarity hardened structure, share a pull-up PMOS transistor P2; memory nodes S2 and S3 each employ independent pull-up PMOS transistors. In other embodiments, within each positive-phase memory node, the same circuit design principle can be followed to allow S0 and S4, or S2 and S4, to share the same pull-up PMOS transistor. Similarly, within each negative-phase memory node, the same circuit design principle can be followed to allow S1 and S5, or S3 and S5, to share the same pull-up PMOS transistor.

[0040] Based on the polarity hardening principle, when a SEU occurs in the six storage nodes of the storage circuit, only "1→0" and "0→0" voltage pulses are generated, meaning only negative voltage pulses are produced. Therefore, when the data stored in these six nodes is "0", S1, S3, and S5 are sensitive nodes; when the data stored in these six nodes is "1", S0, S2, and S4 are sensitive nodes. It has a dual-node flip-over self-recovery function.

[0041] The error isolation circuit includes one dual-input C unit CE1 and one clock-controlled dual-input C unit CG-CE1. The two inputs of CE1 are connected to any two non-inverting input nodes. The output of C1 is denoted as the intermediate node X1, which is connected to one of the inputs of CG-CE1. The other input of CG-CE1 is connected to any one of the inverting input nodes. The control terminal of CG-CE1 is connected to the clock signal CLK, and the output of CG-CE1 is used to output stored data.

[0042] In the error isolation circuit provided in this embodiment, the two input terminals of CE1 are connected to any two non-inverting storage nodes, and one input terminal of CG-CE1 is connected to any one inverting storage node. The two input terminals of CE1 can be connected to S0+S2, or S2+S4, or S0+S4 respectively, while one input terminal of CG-CE1 is connected to the output terminal of CE1, and the other input terminal is connected to any one of S1, S3, and S5.

[0043] In practical applications, such as Figure 7 As shown, the dual-input C unit CE1 includes two PMOS transistors P5 and P6 and two NMOS transistors N19 and N20. The source of P5 is connected to the power supply; the drain of P5 is connected to the source of P6; the drain of P6 is connected to the drain of N19 and serves as the output terminal OUT of CE1; the source of N19 is connected to the drain of N20; the source of N20 is grounded; the gates of P5 and N19 are connected and serve as one of the input terminals IN1 of CE1; the gates of P6 and N20 are connected and serve as the other input terminal IN2 of CE1.

[0044] Accordingly, the clock-controlled dual-input C unit CG-CE1 includes three PMOS transistors P7~P9 and three NMOS transistors N21~N23. The source of P7 is connected to the power supply; the drain of P7 is connected to the source of P8; the drain of P8 is connected to the source of P9; the drain of P9 is connected to the drain of N21 and serves as the output terminal OUT of CG-CE1; the source of N21 is connected to the drain of N22; the source of N22 is connected to the drain of N23; the drain of N23 is grounded; the gates of P7 and N22 are connected and serve as one of the input terminals IN1 of CG-CE1; the gates of P8 and N23 are connected and serve as the other input terminal IN2 of CG-CE1; the gate of P9 is connected to the clock signal CLK; the gate of N21 is connected to the inverted signal NCK of CLK.

[0045] In the error isolation circuit, the state of the two positive storage nodes connected to the input of CE1 jointly determines the level state of X1, while the state of X1 and another negative storage node jointly determines the level state of the output signal of CG-CE1.

[0046] Taking the input terminals of CE1 connected to S0 and S4, and the input terminals of CG-CE1 connected to X1 and S1 as an example, for the above dual-input C unit, when the two input values ​​are the same, the output value is the opposite of the input value. When the two input values ​​are different, the C unit enters a high-impedance state, and the output value will remain the same as the previous value. The clock-controlled dual-input C unit differs from the basic dual-input C unit in that it adds one NMOS transistor and one PMOS transistor, and is controlled by the clock signal CLK and the inverted clock signal NCK. When CLK is low and NCK is high, the C unit is in the off state, and the output value is not controlled by the input value; when CLK is low and NCK is high, it functions the same as the basic dual-input C unit, which means that the C unit can isolate error signals. When the storage circuit stores data as "1", that is, S0=S2=S4=Q="1", S1=S3=S5=X1="0", S0, S4, X1, and Q in the error isolation circuit are sensitive nodes.

[0047] The input circuit is used to set the storage nodes S0~S5 in the storage circuit according to the input signal. Considering that each storage node in the storage circuit of this embodiment adopts an N-polarity hardened structure, an NMOS transistor should be used to write the input signal to ensure the polarity hardening design of these nodes. Specifically, in practical applications, the input circuit in this embodiment can adopt the following... Figure 6 The circuit design shown includes six NMOS transistors N13-N18 and an inverter INV1. The drains of N13-N18 are connected to S0-S5 respectively; the gates of N13-N18 are connected to CLK; the sources of N13-N15 are connected to the input terminals of the inverter and serve as the input terminals for receiving the input signal D; the sources of N16-N18 are connected to the output terminal of INV1 to receive the inverted signal DN of D. The inverter INV1 is used to generate the inverted signal DN based on the input signal D, thereby enabling the independent write transistors N13-N18 to write different level states to different types of memory nodes.

[0048] The inverter INV1 is composed of a PMOS transistor P10 and an NMOS transistor N24; the source of P10 is connected to VDD; the gates of P10 and N24 are connected as the input terminal of INV1 and are used to receive the input signal D; the drains of P10 and N24 are connected as the output terminal of INV1 and are used to output the inverted signal DN of D; the source of N24 is grounded.

[0049] The output circuit is connected in parallel between the input terminal of the input circuit and the output terminal of the error isolation circuit to enable data pass-through when CG-CE1 is turned off. In this embodiment, the output circuit includes a transmission gate TG1, the input terminal of which is connected to the input terminal of the input circuit; the output terminal of TG1 is connected to the output terminal of the error isolation circuit. The transmission gate TG1 is composed of an NMOS transistor N26 and a PMOS transistor P12; the drains of N26 and P12 are connected to the input terminal of the input circuit. The sources of N26 and P12 are connected to the output terminal of CG-CE1. The gate of N26 is connected to CLK; the gate of P12 is connected to the inverted signal NCK of CLK. This embodiment uses a transmission gate as the output circuit so that the latch circuit can achieve full-swing output.

[0050] In the input circuit, memory circuit, and error isolation circuit, a set of inverted clock signals CLK and NCK are needed to coordinate the operating modes of each circuit. In practical applications, the low-overhead three-node flip-tolerant latch circuit also includes an inverter INV2, which generates its inverted signal NCK based on the clock signal CLK, to achieve coordinated adjustment of the operating modes of the error isolation circuit, input circuit, and output circuit. Specifically, INV2 is composed of a PMOS transistor P11 and an NMOS transistor N25; the source of P11 is connected to VDD; the gates of P11 and N25 are connected as the input terminal of INV2, and are used to receive the input clock signal CLK; the drains of P11 and N25 are connected as the output terminal of INV2, and are used to output the inverted signal DCK of CLK; the source of N25 is grounded.

[0051] In summary, in such Figure 6 In the typical circuit shown, this invention designs a latch circuit capable of tolerating three-node switching using only 38 MOS transistors (including 26 NMOS transistors and 12 PMOS transistors). In practical applications, all transistor dimensions can be minimized, such as a width-to-length ratio (W / L) of 100 nm / 30 nm.

[0052] The embodiment provided is as follows: Figure 6 The latch circuit uses a set of clock signals CLK and NCK to switch its operating mode. When CLK = 1 and NCK = 0, the latch is in transparent mode. In this mode, the latch circuit directly transmits the input signal D transparently, the storage node of the storage circuit does not change with the input signal D, and the output signal Q changes dynamically with the input signal D.

[0053] Specifically, in transparent mode, transmission gate TG1 and NMOS transmission transistors N13~N18 are turned on, and the input signal D and the inverted input signal DN drive the storage nodes of the circuit through the transmission transistors, thereby enabling the writing of input data to rewrite the level state of each storage node according to the input signal. At the same time, in transparent mode, the clock control unit CG-CE1 is turned off, and transmission gate TG1 directly generates the corresponding output signal Q according to the input signal D, without being affected by nodes S1 and X1.

[0054] When CLK = 0 and NCK = 1, the latch is in hold mode. In this mode, transmission gate TG1 and all NMOS transmission transistors are turned off. The transmission path between each storage node in the storage circuit and the input circuit is disconnected, so the storage circuit no longer supports data rewriting, and the level state of each storage node is unaffected by the input signal D. At the same time, the clock control C unit CG-CE1 is turned on; the intermediate node X1 is driven by the storage nodes S0 and S4 of the storage circuit through the dual-input C unit CE1; the intermediate node X1 and the storage node S1 jointly drive the level state of the output signal Q through the clock control C unit, thus enabling the correct storage data to be output even when the three nodes are flipped.

[0055] The following are provided in this embodiment: Figure 6 In the latch circuit shown, the error isolation circuit is mainly driven by the individual storage nodes in the storage circuit with dual-node flip-to-recovery functionality. The storage circuit has good symmetry, and the fault tolerance principle of the latch circuit is basically the same whether storing 1 or 0. It is worth noting that the fault tolerance of the latch circuit is only considered when a single-event upset (SEU) occurs in hold mode; if an SEU occurs in transparent mode, the input signal D can immediately recover the stored data, preventing data erroneous flipping.

[0056] To make the radiation resistance (flip resistance) performance and advantages of the latch circuit provided in this embodiment clearer, the latch circuit will be explained below from the perspective of the implementation principle of the full SNU, DNU flip self-recovery and the tolerance of three-node flip (TNU) functions.

[0057] I. SNU Self-Recovery In this embodiment, all six storage nodes in the latch circuit employ polarity hardening technology. Therefore, when the stored data is 1 (i.e., S0=S2=S4=Q=1, S1=S3=S5=X1=0), there are five sensitive nodes: S0, S2, S4, X1, and Q. Since the latch circuit has five sensitive nodes, there are five possible SNU scenarios. Furthermore, the SNU scenarios occurring in the latch circuit can be categorized into three types: SNU Type 1: SNU occurs in the storage circuit, including three cases, namely, SNU occurs in storage nodes S0, S2, and S4.

[0058] SNU Type 2: SNU occurs at intermediate node X1 in the error isolation circuit.

[0059] SNU Type 3: SNU occurs on output signal Q.

[0060] The following is a detailed analysis of the recovery mechanism of each SEU: 1. SNU occurs in S0 (type 1) When storage node S0 undergoes a 1→0 level transition, NMOS transistors P2 and P4 are turned on, while NMOS transistor N3 is turned off. At this time, the pull-up PMOS transistors controlling nodes S1, S3, and S5 are turned on, but the switching states of the corresponding pull-up NMOS transistors N5, N7, and N11 remain unchanged, resulting in these three nodes being in a high-impedance state. Therefore, the SNU of S0 does not affect the voltage values ​​of other storage nodes in the storage circuit. Since only S0 among the two input nodes of CE1 changes, X1 enters a high-impedance state, keeping the output signal Q unchanged. Because S1 and S3 are low and S4 is high, S0 is restored to a high level, simultaneously restoring the high-impedance nodes to the correct state, ultimately successfully achieving SNU self-recovery.

[0061] 2. SNU occurs in S2 (type 1). When storage node S2 undergoes a 1→0 level transition, NMOS transistors N6, N9, and N12 are turned off. At this time, nodes S0 and S3 remain in their original states, causing nodes S1, S4, and S5 to enter a high-impedance state. During this process, the SNU of S2 fails to cause voltage changes in other nodes in the storage circuit. Since S3 and S5 are low and S0 is high, S2 recovers to a high level, simultaneously restoring the high-impedance nodes to their correct state. The operating states of CE1 and CG-CE1 are unaffected by the S2 level transition, ultimately achieving SNU self-recovery.

[0062] 3. SNU occurs in S4 (Type 1). When storage node S2 undergoes a 1→0 level transition, NMOS transistors N8 and N11 are turned off. At this time, nodes S1, S2, and S3 maintain their original levels, while nodes S0 and S3 exhibit a high-impedance state. During this process, the SNU self-recovery at S2 does not affect the voltages of other storage nodes in the storage circuit. Since only the input node S4 of CE1 changes level, node X1 enters a high-impedance state, and the output signal Q remains unchanged. Because S1 and S3 are low and S2 is high, S4 is restored to a high level, simultaneously restoring the high-impedance node to the correct state, ultimately successfully achieving SNU self-recovery.

[0063] 4. SNU occurs in X1 (type 2). When the intermediate node X1 undergoes a 0→1 level transition, since this node only serves as a secondary input of CG-CE1, the state of the stored node in the storage circuit remains unchanged. At this time, due to the voltage change of a single input node, the output signal Q of CG-CE1 enters a high-impedance state. Nodes S0 and S4 remain at a low level, driving CE1 to restore the intermediate node X1 to its normal operating state, and simultaneously restoring the output signal Q to its normal operating state, ultimately achieving SNU self-recovery.

[0064] 5. SNU occurs in Q (type 3). The output signal Q is not used as a control signal for other nodes. Therefore, when the output signal Q experiences a SEU, the remaining nodes in the circuit maintain their original states. After the output signal Q undergoes a level flip, nodes S1 and X1 immediately restore it to the correct level.

[0065] In summary, the latch circuit of this embodiment can achieve complete SNU self-recovery.

[0066] II. DNU Self-Recovery In the latch circuit of this embodiment, there are 10 possible scenarios when a DNU occurs. These can be categorized into 3 types: DNU Type 1: DNU occurs within the memory circuitry, i.e.<S0,S2> ,<S0,S4> ,<S2,S4> These are the three scenarios.

[0067] DNU Type 2: One SNU occurs within the storage circuitry, and one SNU occurs within the error isolation circuitry.<S0,X1> ,<S2,X1> ,<S4,X1> ,<S0,Q> ,<S2,Q> ,<S4,Q> These are the 6 situations.

[0068] DNU Type 3: DNU occurs within an error isolation circuit, i.e.<X1,Q> This is the only situation.

[0069] The recovery mechanism of the latch circuit in this embodiment under various DNU conditions is analyzed in detail below: 1. DNU occurs<S0,S2> (Type 1) When storage nodes S0 and S2 simultaneously undergo a 1→0 level transition, PMOS transistors P2 and P4 are turned on, while NMOS transistors N3, N6, N9, and N12 are turned off. This state change of the six transistors causes nodes S1, S3, S4, and S5 to enter a high-impedance state. Since only S0 at the CE1 input changes level, the intermediate node X1 enters a high-impedance state, and the output signal Q remains unchanged. S0 recovers its level through S1, S3, and S4, further turning on N3, and ultimately restoring S2 to the correct level. During this process, the voltages of the remaining nodes in the storage circuit and the output signal Q are unaffected by DNU.

[0070] 2. DNU occurs<S0,S4> (Type 1) When storage nodes S0 and S4 simultaneously undergo a 1→0 level transition, PMOS transistors P2 and P4 turn on, while NMOS transistors N1, N3, and N8 turn off. At this time, nodes S1, S2, and S3 remain in a high-impedance state. In the error isolation circuit, the change in the state of input nodes S0 and S4 via CE1 causes intermediate node X1 to change from 0 to 1. Since the level of S1 remains unchanged, the output signal Q remains in a high-impedance state. Considering that the voltages of nodes S1, S2, and S3 remain unchanged, the pull-up and pull-down transistors of S4 maintain their initial switching state, thus restoring S4 to its normal operating state. The restored S4 then turns on transistor N1 again, restoring S0 to its normal level. This process restores the high-impedance nodes in the storage circuit to normal. When X1 returns to its normal operating state through CE1, the output signal Q returns from a high-impedance state to normal. Finally, all circuit nodes return to their original operating states.

[0071] 3. DNU occurs<S2,S4> (Type 1) When storage nodes S0 and S4 simultaneously undergo a 1→0 level transition, NMOS transistors N6, N8, N9, and N12 enter the off state, making nodes S0, S1, S3, and S5 high-impedance nodes. In the error isolation circuit, the CE1 input node S4 undergoes a level transition, and the intermediate node X1 presents a high-impedance state. Since the pull-up / pull-down control signals of node S2 remain unchanged, S2 returns to its normal operating state. As the pull-up NMOS transistor N9 of S4 turns on again, node S4 returns to its normal operating state. After recovery, S2 and S4 restore S0, S1, S3, S5, and X1, which were in a high-impedance state, to their normal operating state, ultimately achieving a complete DNU self-recovery function.

[0072] 4. DNU occurs<S0,X1> ,<S2,X1> ,<S4,X1> ,<S0,Q> ,<S2,Q> ,<S4,Q> (Type 2) Based on the analysis of the SNU situation at intermediate node X1 and output signal Q described earlier, it can be concluded that changes in the node voltage in the error isolation circuit will not affect the storage node voltage value in the storage circuit.<S0,X1> ,<S2,X1> ,<S4,X1> ,<S0,Q> ,<S2,Q> and<S4,Q> When the DNU occurs in these 6 pairs of nodes, the storage circuit will further restore the state of nodes X1 and Q after the storage node flips and recovers, ultimately achieving complete DNU self-recovery.

[0073] 5. DNU occurs<X1,Q> (Type 3) when<X1,Q> When a DNU occurs in a node pair, since neither node feeds back to the storage circuit, the internal storage node state will not change. Nodes S0 and S4 drive CE1 to restore node X1 to its normal working state. After restoration, X1 and node S1 drive CG-CE1 to restore Q, thus achieving complete DNU self-recovery.

[0074] In summary, the latch circuit in this example can achieve complete DNU self-recovery.

[0075] III. TNU Tolerance In the latch circuit provided in this embodiment, there are 10 possible scenarios when a TNU occurs. These can be categorized into three types based on the location of the TNU: TNU Type 1: All three SNUs occur within the memory circuit, meaning the node pair where the TNU occurs is...<S0,S2,S4> .

[0076] TNU Type 2: Two SEUs occur within the storage circuitry, and another SEU occurs within the error isolation circuitry, including...<S0,S2,X1> ,<S0,S2,Q> ,<S0,S4,X1> ,<S0,S4,Q> ,<S2,S4,X1> ,<S2,S4,Q> These are the 6 situations.

[0077] TNU Type 3: One SEU occurs within the storage circuit, and two occur within the error isolation circuit, including...<S0,X1,Q> ,<S2,X1,Q> ,<S4,X1,Q> These are the three scenarios.

[0078] The tolerance and self-recovery mechanisms of various TNUs are analyzed in detail below: 1. TNU occurs<S0,S2,S4> (Type 1) The TNU occurs entirely within the storage circuit. When storage nodes S0, S2, and S4 toggle to 0, the pull-up PMOS transistors of nodes S1, S3, and S5 are turned on. Since the gates of control transistors N7, N11, and N5 remain off during the toggle, the node voltage remains 0. In the error isolation circuit, S0 and S4 toggle to 0 simultaneously, driving CE1 to toggle X1 to 1. The S1 node voltage remains unchanged, and the output signal Q remains high impedance and is consistently high. Therefore, LDRATL can fully tolerate this worst-case TNU.

[0079] 2. TNU occurs<S0,S2,X1> ,<S0,S2,Q> ,<S0,S4,X1> ,<S0,S4,Q> ,<S2,S4,X1> ,<S2,S4,Q> (Type 2) Changes in the fault isolation circuit nodes do not affect the storage nodes in the storage circuit. The fault-tolerance mechanism for this type of TNU can be analyzed starting with the nodes that flip within the storage circuit. As discussed in the previous analysis of DNU type 1, DNUs within the storage circuit can self-recover. After recovery, the storage nodes in the storage circuit further drive CE1 and CG-CE1 to restore the intermediate node X1 and the output signal Q, ultimately achieving complete TNU self-recovery.

[0080] 3. TNU occurs<S0,X1,Q> ,<S2,X1,Q> ,<S4,X1,Q> (Type 3) This type of TNU is similar to DNU type 3. When an SNU recovery occurs in the storage node inside the storage circuit, nodes S0 and S4 drive CE1 to restore X1. After the recovery, X1 and S1 drive CG-CE1 to restore Q, thus achieving complete TNU self-recovery.

[0081] In summary, the latch circuit provided in this embodiment can tolerate TNU. Except for one type which can only achieve TNU tolerance, the other nine types can achieve TNU self-recovery, and the TNU self-recovery rate can reach 90%.

[0082] Example 2

[0083] Based on the three-node flip-flop tolerant latch circuit provided in Embodiment 1, this embodiment further provides a memory chip that uses the low-overhead three-node flip-flop tolerant latch circuit as described in Embodiment 1 as the memory cell. Since the storage power supply in this memory chip has complete SNU and DNU self-recovery functions and is TNU tolerant, it can be used as a radiation-resistant memory chip with stronger flip-flop resistance, and has broad application prospects in the aerospace field.

[0084] Performance testing To verify the advantages of the present invention, technicians used... Figure 6 Taking the latch circuit scheme with 38 transistors as an example, the circuit performance of this scheme is simulated and tested: 1. Normal operation timing diagram This experiment first tested the timing of the latch circuit in hold mode and transparent mode. The operating states of each signal during this process are as follows: Figure 8 As shown.

[0085] according to Figure 8 It can be seen that the latching circuit of the present invention has normal data writing and data holding functions in both holding mode and transparent mode, and can work normally.

[0086] 2. SNU simulation verification This experiment verifies the data recovery performance of the latch circuit in a single-node switching state (SNU). In hold mode, nodes S0, S2, S4, X1, and Q are bombarded, simulating the transition from 1 to 0 for each node. The final simulation data is shown in Table 1, and the corresponding timing waveforms are as follows. Figure 9 As shown.

[0087] Table 1: SNU Simulation Verification Table

[0088] Based on the above data, it can be seen that the latching circuit of the present invention can correctly achieve data recovery in all five SNU states.

[0089] 3. DNU simulation verification This experiment verifies the data recovery performance of the latch circuit under dual-node flip-north (SNU) conditions. Due to the strictly symmetrical structure of the storage circuit and the fact that its storage nodes drive the error isolation circuit, only 5 node pairs need to be selected for the bombardment verification:<S0,S2> ,<S0,S4> ,<S2,S4> ,<S0,X1> ,<S0,Q> In hold mode, the two nodes within each node pair are simultaneously bombarded from 1 to 0 in the simulation. The final simulation data is shown in Table 2, and the corresponding timing waveforms are as follows. Figure 9 As shown.

[0090] Table 2: DNU Simulation Verification Table

[0091] Based on the above data, it can be seen that the circuit of the present invention can correctly achieve data recovery in all 10 DNU states.

[0092] 4. TNU simulation verification This experiment verifies the data recovery performance of the latch circuit under the three-node flip-north (TNU) state by bombarding node pairs in hold mode.<S0,S2,S4> ,<S0,S2,X1> ,<S0,S2,Q> ,<S0,S4,X1> ,<S0,S4,Q> ,<S2,S4,X1> ,<S2,S4,Q> ,<S2,X1,Q> ,<S4,X1,Q> Since the SNU can continue to drive X1 and Q recovery after recovery within the storage circuit, for TNU type 3, it is only necessary to verify any two of the three cases, which are ignored here.<S0,X1,Q> Node pairs. During simulation verification, all three nodes in each node pair were simultaneously bombarded from 1 to 0. The final simulation data is shown in Table 3, and the corresponding timing waveforms are as follows. Figure 10 As shown.

[0093] Table 3: TNU Simulation Verification Table

[0094] Based on the above data, it can be concluded that the circuit TNU of this invention occurs...<S0,S2,S4> It can be tolerated under certain conditions, and data recovery can be achieved in the other 9 TNU conditions.

[0095] 5. Circuit performance comparison This experiment uses the four latch circuits (TNU-latch circuit, TTLL circuit, KOBE circuit, and DRLW circuit) introduced in the background technology as control groups, and compares them with the latch circuit of this invention (denoted as LDRATL). The five circuit schemes are tested in terms of DNU recovery capability, TNU tolerance capability, area, power consumption, Tdq delay (transmission delay from D to Q in transparent mode), Tcq delay (transmission delay from CLK to Q in transparent mode), and PDAP. The performance comparison table is shown in Table 4. Table 4: Performance Comparison Table of the Invention Circuit and the Control Circuit

[0096] Analysis of the data in the table above shows that, in terms of radiation resistance, only the LDRATL circuit can achieve both DNU recovery and TNU tolerance, while other latching circuits can only achieve one of the functions: DNU recovery or TNU tolerance.

[0097] In terms of delay, TTLL, KOBE, DRLW, and the latch circuit have a direct path from D to Q, and the output signal Q does not control the internal transistors, resulting in smaller DQ and CLK-Q delays. The TNU-latch circuit has the largest delay. The Tdq and Teq delays of the LDRATL circuit are reduced by an average of 42.41% and 38.22% compared to the KOBE, TTLL, DRLW, and TNU-latch circuits, respectively.

[0098] In terms of area and power consumption, the KOBE circuit has a simple structure, fewer transistors, and the smallest layout area, but it can only tolerate a portion of the TNUs and has relatively high power consumption. TNU-latch, TTLL, and DRLW circuits use a large number of C cells to improve radiation immunity, resulting in higher area and power consumption overhead. As shown in Table 4, the LDRATL circuit reduces area and power consumption by an average of 29.77% and 57.22% compared to other latch circuits, respectively.

[0099] Regarding the power-delay-area product (PDAP), the above analysis shows that the LDRATL circuit has lower area, power consumption, and delay, thus exhibiting a superior overall performance in terms of PDAP. Table 4 shows that compared to these latching circuits, the PDAP of the LDRATL circuit is reduced by 99.96%, 86.69%, 67.74%, and 80.46%, respectively, with an average reduction of 83.71%.

[0100] Furthermore, by measuring the power consumption and delay of these latching circuits and their sensitivity to voltage and temperature fluctuations, it can be seen that the LDRATL circuit has the lowest sensitivity to voltage and temperature fluctuations.

[0101] In summary, the latch circuit of this invention uses fewer transistors, but its power consumption, delay, and PDAP are all at a low level. It is also less sensitive to voltage and temperature fluctuations and has the best overall radiation resistance performance.

[0102] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A low-overhead three-node flip-tolerant latch circuit, comprising: It includes: The storage circuit features a dual-node flip-over self-recovery function. It comprises three redundant sets of positive-phase storage nodes S0, S2, and S4, and inverted-phase storage nodes S1, S3, and S5, all reinforced with N-polarity. The circuit includes four PMOS transistors P1-P4 and twelve NMOS transistors N1-N12. The circuit connections are as follows: the sources of P1-P4 are connected to the power supply; the drain of P1 is connected to the drains of N1 and N3; the source of N1 is connected to the drain of N2 and serves as storage node S0; the source of N3 is connected to the drain of N4 and serves as storage node S2; the drain of P2 is connected to the drains of N5 and N7; and the source of N5 is connected to the drain of N6 and serves as storage node S1. Storage node S1; the source of N7 is connected to the drain of N8 and forms storage node S3; the drain of P3 is connected to the drain of N9; the source of N9 is connected to the drain of N10 and forms storage node S4; the drain of P4 is connected to the drain of N11; the source of N11 is connected to the drain of N12 and forms storage node S5; the sources of N2, N4, N6, N8, N10, and N12 are grounded; the gates of P2, P4, and N3 are connected to S0; the gates of N2, N7, and N10 are connected to S1; the gates of N6, N9, and N12 are connected to S2; the gates of P1, P3, and N11 are connected to S3; the gates of N1 and N8 are connected to S4; the gates of N4 and N5 are connected to S5. The error isolation circuit includes a dual-input C unit CE1 and a clock-controlled dual-input C unit CG-CE1; the two inputs of CE1 are connected to any two non-inverting storage nodes, and the output of CE1 is connected to one of the inputs of CG-CE1; the other input of CG-CE1 is connected to any one inverting storage node; the control terminal of CG-CE1 is connected to the clock signal CLK, and the output of CG-CE1 is used to output the stored data. The input circuit is used to set S0~S5 in the storage circuit according to the input signal; The output circuit is connected in parallel between the input terminal of the input circuit and the output terminal of the error isolation circuit to enable data pass-through when CG-CE1 is turned off.

2. The low-overhead three-node toggle-tolerant latch circuit of claim 1, wherein: The dual-input C unit CE1 is composed of two PMOS transistors P5 and P6 and two NMOS transistors N19 and N20; The source of P5 is connected to the power supply; the drain of P5 is connected to the source of P6; the drain of P6 is connected to the drain of N19 and serves as the output of CE1; the source of N19 is connected to the drain of N20; the source of N20 is grounded; the gates of P5 and N19 are connected and serve as one of the inputs of CE1; the gates of P6 and N20 are connected and serve as the other input of CE1.

3. The low-overhead three-node flip-tolerant latch circuit according to claim 1, characterized in that: The clock-controlled dual-input C unit CG-CE1 is composed of three PMOS transistors P7~P9 and three NMOS transistors N21~N23; The source of P7 is connected to the power supply; the drain of P7 is connected to the source of P8; the drain of P8 is connected to the source of P9; the drain of P9 is connected to the drain of N21 and serves as the output of CG-CE1; the source of N21 is connected to the drain of N22; the source of N22 is connected to the drain of N23; the drain of N23 is grounded; the gates of P7 and N22 are connected and serve as one of the inputs of CG-CE1; the gates of P8 and N23 are connected and serve as the other input of CG-CE1; the gate of P9 is connected to the clock signal CLK; the gate of N21 is connected to the inverted signal NCK of CLK.

4. The low-overhead three-node flip-tolerant latch circuit according to claim 1, characterized in that: The input circuit includes six NMOS transistors N13 to N18 and an inverter INV1; the drains of N13 to N18 are connected to S0 to S5 respectively; the gates of N13 to N18 are connected to CLK; the sources of N13 to N15 are connected to the input terminals of the inverter and serve as the input terminals for receiving the input signal D; the sources of N16 to N18 are connected to the output terminals of INV1 to receive the inverted signal DN of D.

5. The low-overhead three-node flip-tolerant latch circuit according to claim 4, characterized in that: The output circuit includes a transmission gate TG1, the input of which is connected to the input of the input circuit; the output of TG1 is connected to the output of the error isolation circuit.

6. The low-overhead three-node flip-tolerant latch circuit according to claim 5, characterized in that: The transmission gate TG1 is composed of an NMOS transistor N26 and a PMOS transistor P12; the drains of N26 and P12 are connected to the input terminals of the input circuit; the sources of N26 and P12 are connected to the output terminals of CG-CE1; the gate of N26 is connected to CLK; and the gate of P12 is connected to the inverted signal NCK of CLK.

7. The low-overhead three-node flip-tolerant latch circuit according to claim 6, characterized in that: It also includes an inverter INV2, which generates its inverted signal NCK based on the clock signal CLK, in order to coordinate the operating modes of the error isolation circuit, input circuit and output circuit.

8. The low-overhead three-node flip-tolerant latch circuit according to claim 7, characterized in that: When CLK = 1 and NCK = 0, the latch circuit is in transparent mode; at this time, TG1 and N13~N18 are turned on, and CG-CE1 is turned off; the input signal D and its inverted signal DN are respectively rewritten by N13~N18 to modify the level state of the corresponding storage node; TG1 directly transmits the input signal D and uses it as the output signal Q; When CLK = 0 and NCK = 1, the latch circuit is in hold mode; at this time, TG1 and N13~N18 are turned off, and CG-CE1 is turned on; TG1 is turned off; the transmission path between each storage node of the latch circuit and the input signal is disconnected; the stored data of each storage node of the storage circuit is processed by error isolation to obtain the output signal Q.

9. A memory chip, characterized in that, It uses a low-overhead three-node flip-tolerant latch circuit as described in any one of claims 1-8 as the storage unit.

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