A GaN HEMT device structure comprising a depletion mode and an enhancement mode

Abstract

The application relates to the technical field of gallium nitride semiconductor, and discloses a kind of including depletion type and enhanced GaN HEMT device structure, by substrate layer, GaN device, MOS device is constituted, the GaN device includes buffer layer, gallium nitride channel layer, aluminum gallium nitride channel layer, dielectric layer and GaN gate from below to above in sequence, the two sides of the dielectric layer also include GaN drain and GaN source.The application effectively avoids the problems of switch speed reduction, on-resistance increase and threshold voltage instability of traditional enhanced GaN HEMT caused by introducing P-GaN layer by monolithic integration of depletion type GaN HEMT and silicon-based MOSFET on the same substrate, so that the overall device has consistent positive threshold voltage and reliable always-off operating characteristics while maintaining the high-frequency and high-efficiency characteristics of gallium nitride material, significantly improving the comprehensive performance of the device in high-frequency applications.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride semiconductor technology, and more particularly to a GaN HEMT device structure comprising depletion-mode and enhancement-mode. Background Technology

[0002] With the development of microelectronics technology, gallium nitride high electron mobility transistors (HEMTs), as representatives of power semiconductor devices, have huge market potential in high-frequency applications. GaN, a wide-bandgap semiconductor material, possesses an ultra-high critical breakdown electric field, nearly 10 times higher than that of silicon (Si), and heterojunctions composed of AlGaN and GaN exhibit a strong two-dimensional electron gas.

[0003] Therefore, under the same voltage withstand conditions, GaN power devices have an on-resistance nearly three orders of magnitude lower than Si devices, significantly reducing chip area and the weight of the drive circuit. Furthermore, gallium nitride (GaN) material has excellent thermal conductivity, making it highly valuable for applications in high-temperature power electronic devices. In the future, GaN-based power electronics are very likely to become a replacement for Si-based power devices and play a crucial role in emerging industries such as smart grids, hybrid vehicles, aerospace, and high-speed rail.

[0004] An existing patent discloses a monolithic integrated chip based on a GaN double heterojunction (publication number CN114759025A). The all-GaN monolithic integration scheme disclosed in the existing patent faces limitations in enhancement-mode GaN HEMTs due to their reliance on P-type GaN layers or complex polarization junction structures, resulting in limited switching speed, increased on-resistance, poor threshold voltage stability, high process complexity, and significant integration difficulty. Summary of the Invention

[0005] This invention provides a GaN HEMT device structure that includes depletion-mode and enhancement-mode features to address existing technical problems. It solves the problems of reduced switching speed, increased on-resistance, and unstable threshold voltage caused by the introduction of a P-GaN layer in traditional enhancement-mode GaN HEMTs.

[0006] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a GaN HEMT device structure comprising depletion-mode and enhancement-mode GaN, comprising a substrate layer, a GaN device, and a MOS device, wherein the GaN device comprises, from bottom to top, a buffer layer, a gallium nitride channel layer, an aluminum gallium nitride channel layer, a dielectric layer, and a GaN gate, and the dielectric layer further comprises a GaN drain and a GaN source on both sides;

[0007] The MOS device includes an N-well layer, a P-well layer, a MOS drain, a MOS gate, and a MOS source;

[0008] A first connecting metal layer is provided between the GaN source and the MOS drain; a second connecting metal layer is provided between the GaN gate and the MOS source.

[0009] Furthermore, the GaN source and the MOS drain are electrically connected via a connecting metal layer;

[0010] The GaN gate and the MOS source are electrically connected through a connecting metal layer.

[0011] Furthermore, the MOS source serves as the source of the GaN HEMT device structure comprising depletion-mode and enhancement-mode modes;

[0012] The GaN drain serves as the drain of the GaN HEMT device structure comprising depletion-type and enhancement-type GaN;

[0013] The MOS gate serves as the gate of the GaN HEMT device structure, which includes depletion-type and enhancement-type modes.

[0014] Furthermore, a covering medium is deposited beneath both the first connecting metal layer and the second connecting metal layer.

[0015] Furthermore, both the covering medium and the dielectric layer are made of silicon dioxide.

[0016] Furthermore, the GaN gate is located near the GaN source; both the GaN drain and the GaN gate are in ohmic contact with the aluminum gallium nitride channel layer.

[0017] Furthermore, both the P-well layer and the MOS drain are located inside the N-well layer, and the MOS drain does not directly contact the P-well layer.

[0018] Furthermore, both the MOS gate and the MOS source are located inside the P-well layer, with the MOS gate located between the MOS drain and the MOS source.

[0019] The present invention provides a GaN HEMT device structure comprising depletion-mode and enhancement-mode technologies. Compared with existing technologies, the advantages achieved by this method are as follows:

[0020] 1. This invention effectively avoids the problems of reduced switching speed, increased on-resistance, and unstable threshold voltage caused by the introduction of a P-GaN layer in traditional enhancement-mode GaN HEMTs by monolithically integrating a depletion-mode GaN HEMT and a silicon-based MOSFET on the same substrate. This allows the overall device to maintain the high-frequency and high-efficiency characteristics of gallium nitride material while possessing the same positive threshold voltage and reliable normally-off operation characteristics as conventional MOSFETs, significantly improving the overall performance of the device in high-frequency applications.

[0021] 2. The connection structure of the present invention connects the GaN source to the MOS drain and the GaN gate to the MOS source, and uses the MOS gate as the overall control terminal to achieve fast turn-on and turn-off under a single signal control. By utilizing the gate voltage bootstrap mechanism of the MOSFET, the source potential of the GaN HEMT is rapidly raised when turned off, thereby achieving efficient and stable switching operation without the need for complex driving circuits, while retaining the high-frequency and low-loss advantages of depletion-type GaN HEMTs.

[0022] 3. By setting up the covering medium and the hierarchical isolation design of N-well and P-well, this invention significantly improves the internal insulation withstand voltage and anti-interference capability of the device, and reduces the risk of leakage and breakdown. The integrated structure avoids the parasitic inductance, resistance and welding reliability problems introduced by the connection of discrete devices, thereby improving the overall device's working stability, yield and service life, and is particularly suitable for high frequency and high power density working environments.

[0023] 4. This invention achieves monolithic integration of GaN HEMT and Si MOSFET on the same silicon substrate, which not only simplifies the process and reduces manufacturing costs, but also facilitates the miniaturization and modularization of devices, providing a compact, high-performance, and easy-to-manufacture solution for power semiconductor devices in high-frequency, high-voltage, and high-temperature applications. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the present invention;

[0025] Figure 2 This is a top view of the present invention.

[0026] In the figure: 1. Substrate layer; 2. GaN device; 3. Cover dielectric; 4. Connecting metal layer one; 5. MOS device; 6. Connecting metal layer two; 201. Buffer layer; 202. Gallium nitride channel layer; 203. AlGaN channel layer; 204. Dielectric layer; 205. GaN drain; 206. GaN gate; 207. GaN source; 501. N-well layer; 502. P-well layer; 503. MOS drain; 504. MOS gate; 505. MOS source. Detailed Implementation

[0027] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] like Figure 1 , Figure 2As shown, according to one aspect of the present invention, a GaNHEMT device structure including depletion-mode and enhancement-mode is provided, comprising a substrate layer 1, a GaN device 2, and a MOS device 5. The GaN device 2 includes, from bottom to top, a buffer layer 201, a gallium nitride channel layer 202, an aluminum gallium nitride channel layer 203, a dielectric layer 204, and a GaN gate 206. The dielectric layer 204 also includes a GaN drain 205 and a GaN source 207 on both sides. The GaN gate 206 is located near the GaN source 207. Both the GaN drain 205 and the GaN gate 206 are in ohmic contact with the aluminum gallium nitride channel layer 203.

[0029] The MOS device 5 includes an N-well layer 501, a P-well layer 502, a MOS drain 503, a MOS gate 504, and a MOS source 505; wherein, a first connecting metal layer 4 is connected between the GaN source 207 and the MOS drain 503; and a second connecting metal layer 6 is connected between the GaN gate 206 and the MOS source 505.

[0030] By monolithically integrating depletion-mode GaN HEMT and silicon-based MOSFET on the same substrate, the problems of reduced switching speed, increased on-resistance, and poor threshold stability caused by the introduction of P-GaN layer in traditional enhancement-mode GaN HEMT are avoided. At the same time, the gate control characteristics of MOSFET are used to achieve normally-off operation of the overall device, which combines high-frequency performance and reliable drive.

[0031] In this embodiment, the GaN source 207 and the MOS drain 503 are electrically connected through a connecting metal layer 4; the GaN gate 206 and the MOS source 505 are electrically connected through a connecting metal layer 6; the MOS source 505 serves as the source of a GaN HEMT device structure that includes both depletion-type and enhancement-type GaN HEMT devices; the GaN drain 205 serves as the drain of a GaN HEMT device structure that includes both depletion-type and enhancement-type GaN HEMT devices; and the MOS gate 504 serves as the gate of a GaN HEMT device structure that includes both depletion-type and enhancement-type GaN HEMT devices.

[0032] By connecting the GaN source 207 to the MOS drain 503 and the GaN gate 206 to the MOS source 505, and using the MOS gate 504 as the overall gate, this structure achieves single-channel signal control. This allows the entire GaN HEMT to be turned on when the MOS gate voltage is higher than the threshold, and to be quickly turned off when it is lower than the threshold through a potential bootstrap mechanism. This achieves stable positive threshold voltage and good switching characteristics while maintaining the high-frequency advantages of depletion-mode GaN.

[0033] In this embodiment, a covering dielectric 3 is deposited below both the first connecting metal layer 4 and the second connecting metal layer 6; the covering dielectric 3 and the dielectric layer 204 are both made of silicon dioxide; the P-well layer 502 and the MOS drain 503 are both located inside the N-well layer 501, and the MOS drain 503 is not in direct contact with the P-well layer 502; the MOS gate 504 and the MOS source 505 are both located inside the P-well layer 502, and the MOS gate 504 is located between the MOS drain 503 and the MOS source 505.

[0034] The inclusion of dielectric 3 improves the insulation and reliability between metal layers, preventing leakage and breakdown. The hierarchical layout of N-wells and P-wells and the electrode isolation design in the MOS device enhance the device's withstand voltage and anti-interference capabilities. The overall structure can be manufactured as a single unit, reducing parasitic parameters and failure risks caused by external connections, and improving device yield and high-frequency stability.

[0035] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A GaN HEMT device structure comprising depletion-mode and enhancement-mode GaN, comprising a substrate (1), a GaN device (2), and a MOS device (5), characterized in that: The GaN device (2) includes, from bottom to top, a buffer layer (201), a gallium nitride channel layer (202), an aluminum gallium nitride channel layer (203), a dielectric layer (204), and a GaN gate (206). The dielectric layer (204) also includes a GaN drain (205) and a GaN source (207) on both sides. The MOS device (5) includes an N-well layer (501), a P-well layer (502), a MOS drain (503), a MOS gate (504), and a MOS source (505). A first connecting metal layer (4) is connected between the GaN source (207) and the MOS drain (503); a second connecting metal layer (6) is connected between the GaN gate (206) and the MOS source (505). The P-well layer (502) and the MOS drain (503) are both located inside the N-well layer (501), and the MOS drain (503) is not in direct contact with the P-well layer (502); The MOS gate (504) and MOS source (505) are both located inside the P-well layer (502), and the MOS gate (504) is located between the MOS drain (503) and the MOS source (505); A covering medium (3) is deposited below both the first connecting metal layer (4) and the second connecting metal layer (6); the material of both the covering medium (3) and the dielectric layer (204) is silicon dioxide.

2. The GaN HEMT device structure comprising depletion-mode and enhancement-mode according to claim 1, characterized in that: The GaN source (207) and the MOS drain (503) are electrically connected through a connecting metal layer (4); The GaN gate (206) and the MOS source (505) are electrically connected through a second connecting metal layer (6).

3. The GaN HEMT device structure comprising depletion-mode and enhancement-mode according to claim 2, characterized in that: The MOS source (505) serves as the source of the GaN HEMT device structure containing depletion-type and enhancement-type modes; The GaN drain (205) serves as the drain of the GaN HEMT device structure comprising depletion-mode and enhancement-mode. The MOS gate (504) serves as the gate of the GaN HEMT device structure comprising depletion-type and enhancement-type.

4. The GaN HEMT device structure comprising depletion-mode and enhancement-mode according to claim 1, characterized in that: The GaN gate (206) is located on the side close to the GaN source (207); both the GaN drain (205) and the GaN gate (206) are in ohmic contact with the aluminum gallium nitride channel layer (203).

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